Datasheet RF1S70N03SM, RFP70N03 Datasheet (Intersil)

RFP70N03, RF1S70N03SM

Data Sheet July 1999 File Number

70A, 30V, 0.010 Ohm, N-Channel Power
MOSFETs

These N-Channel power MOSFETs are manufacturedusing
the MegaFET process. This process, which uses feature
sizes approaching those of LSI integrated circuits gives
optimum utilization of silicon, resulting in outstanding
performance. They were designed for use in applications
such as switching regulators, switching converters, motor
drivers, and relaydrivers. These transistors can be operated
directly from integrated circuits.

Formerly developmental type TA49025.

Ordering Information

PART NUMBER PACKAGE BRAND

RFP70N03 TO-220AB RFP70N03
RF1S70N03SM TO-263AB F1S70N03

NOTE: When ordering,usethe entire part number.Add the suffix 9Ato
obtain the TO-263AB variant in tape and reel, e.g., RF1S70N03SM9A

Features

• 70A, 30V

DS(ON)

= 0.010Ω

®

Model

•r

• Temperature Compensating PSPICE

• Peak Current vs Pulse Width Curve

• UIS Rating Curve (Single Pulse)

o

C Operating Temperature

• 175

• Related Literature

- TB334 “Guidelines for Soldering Surface Mount
Components to PC Boards”

Symbol

D

G

S

3404.4

Packaging

DRAIN

(FLANGE)

JEDEC TO-220AB JEDEC TO-263AB

SOURCE

DRAIN

GATE

GATE
SOURCE

DRAIN

(FLANGE)

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.

PSPICE® is a registered trademark of MicroSim Corporation.

http://www.intersil.com or 407-727-9207

| Copyright © Intersil Corporation 1999

RFP70N03, RF1S70N03SM

Absolute Maximum Ratings T

= 25oC, Unless Otherwise Specified

C

UNITS

Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

DSS

DGR

GS

30 V
30 V

±20 V

Drain Current

Continuous (Figure 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I

Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I

Pulsed Avalanche Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P

D

DM

AS

D

Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, T

STG

Maximum Temperature for Soldering

Leads at 0.063in (1.6mm) from case for 10s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .T

Package Body for 10s, see Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationofthe
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

L

pkg

70

200

Figures 5, 13, 14

150

1.0

-55 to 175

300
260

A
A

W

W/oC

o

C

o

C

o

C

NOTE:

1. TJ = 25oC to 150oC.

Electrical Specifications T

= 25oC, Unless Otherwise Specified

C

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Drain to Source Breakdown Voltage BV
Gate to Source Threshold Voltage V
Zero Gate Voltage Drain Current I

DSSID

GS(TH)VGS

DSS

= 250µA, VGS = 0V (Figure 10) 30 - - V

= VDS, ID = 250µA (Figure 9) 2 - 4 V
VDS = 30V, VGS = 0V - - 1 µA
VDS = 30V, VGS = 0V, TC = 150oC--50µA

Gate to Source Leakage Current I
Drain to Source On Resistance r

DS(ON)ID

Turn-On Time t
Turn-On Delay Time t

d(ON)

Rise Time t
Turn-Off Delay Time t

d(OFF)

Fall Time t
Turn-Off Time t
Total Gate Charge Q

g(TOT)VGS

Gate Charge at 10V Q
Threshold Gate Charge Q
Input Capacitance C
Output Capacitance C
Reverse Transfer Capacitance C
Thermal Resistance Junction to Case R
Thermal Resistance Junction to Ambient R

GSS

ON

OFF

g(10)

g(TH)

ISS

OSS

RSS

θJC
θJA

VGS = ±20V - - 100 nA

= 70A, VGS = 10V (Figure 8) - - 0.010 Ω

VDD = 15V, ID≅ 70A,
RL = 0.214Ω, VGS= 10V,
RGS = 2.5Ω

r

- - 80 ns

-20-ns

-20-ns

-40-ns

f

-25-ns

- - 125 ns

= 0V to 20V VDD = 24V, ID≅ 70A,
VGS = 0V to 10V - 120 145 nC
VGS = 0V to 2V - 6.5 8.0 nC

RL = 0.343Ω
I

= 1.0mA

g(REF)

(Figure 12)

VDS = 25V, VGS = 0V,
f = 1MHz
(Figure 11)

- 215 260 nC

- 3300 - pF

- 1750 - pF

- 750 - pF
(Figure 3) - - 1.0
TO-220, TO-263 - - 62

o
o

C/W
C/W

Source to Drain Diode Specifications

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Source to Drain Diode Voltage V
Reverse Recovery Time t

2

SD

rr

ISD = 70A - - 1.5 V
ISD = 70A, dISD/dt = 100A/µs - - 125 ns

Typical Performance Curves

RFP70N03, RF1S70N03SM

1.2

1.0

0.8

0.6

0.4

0.2

POWER DISSIPATION MULTIPLIER

0

0 25 50 75 100 175

125

150

TC, CASE TEMPERATURE (oC)

FIGURE 1. NORMALIZED POWERDISSIPATION vs CASE

TEMPERATURE

0

10

0.5

0.2

-1

0.1

10

0.05

0.02

0.01

, NORMALIZED THERMAL IMPEDANCE

θJC

Z

10

-2

-5

10

SINGLE PULSE

10

-4

-3

10

t1, RECTANGULAR PULSE DURATION (s)

80
70

60

50

40

30

, DRAIN CURRENT (A)

20

D

I

10

0

25 50 75 100 125 150 175

, CASE TEMPERATURE (oC)

T

C

FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs

CASE TEMPERATURE

P

DM

NOTES:
DUTY FACTOR: D = t1/t
PEAK TJ = PDM x Z

-2

10

-1

10

2

x R

θJC

-0

10

t

1

t

2

+ T

θJC

C

1

10

FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE

300

100

OPERATION IN THIS
AREA MAY BE
LIMITED BY r

10

, DRAIN CURRENT (A)

D

I

TC = 25oC
T

= MAX RATED

J

SINGLE PULSE

1

1

DS(ON)

V

DSS(MAX)

10 50

V

, DRAIN TO SOURCE VOLTAGE (V)

DS

= 30V

FIGURE 4. FORWARD BIAS SAFE OPERATING AREA

3

100µs

1ms

10ms

100ms
DC

300

I

DM

STARTING TJ = 25oC
STARTING TJ = 150oC

100

If R = 0

, AVALANCHE CURRENT (A)

tAV = (L) (IAS)/(1.3 x RATED BV

AS

I

If R ≠ 0

= (L/R) ln [(IAS x R)/(1.3 x RATED BV

t

AV

10

0.01
t

AV

0.10
, TIME IN AVALANCHE (ms)

DSS

- VDD)

- VDD) +1]

DSS

110

NOTE: Refer to Intersil Application Notes AN9321 and AN9322.

FIGURE 5. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY

RFP70N03, RF1S70N03SM

Typical Performance Curves

200

160

120

80

, DRAIN CURRENT (A)

D

I

40

0

0 1.5 3.0 4.5 6.0 7.5

VGS = 8VVGS = 10V

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
T

C

VDS, DRAIN TO SOURCE VOLTAGE (V)

(Continued)

= 25oC

FIGURE 6. SATURATION CHARACTERISTICS FIGURE 7. TRANSFER CHARACTERISTICS

2.0

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VGS = 10V, ID= 70A

1.5

VGS = 7V

VGS = 6V

VGS = 5V

VGS = 4V

200

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
V

= 15V

DD

160

120

80

DRAIN CURRENT (A)

40

0

0246810

2.0

1.6

VGS, GATE TO SOURCE VOLTAGE (V)

VGS = VDS,ID = 250µA

-55oC

25oC

175oC

1.0

ON RESISTANCE

0.5

NORMALIZED DRAIN TO SOURCE

0

-80 -40 0 40 80 120 160 200
T

, JUNCTION TEMPERATURE (oC)

J

FIGURE 8. NORMALIZED DRAIN TO SOURCE ON

RESISTANCE vs JUNCTION TEMPERATURE

2.0
ID = 250µA

1.6

1.2

0.8

BREAKDOWN VOLTAGE

0.4

NORMALIZED DRAIN TO SOURCE

0

-80 -40 0 40 80 120 160 200
T

, JUNCTION TEMPERATURE (oC)

J

1.2

0.8

NORMALIZED

0.4

GATE THRESHOLD VOLTAGE

0

-80 -40 0 40 80 120 160 200
, JUNCTION TEMPERATURE (oC)

T

J

FIGURE 9. NORMALIZED GATE THRESHOLD VOLTAGEvs

JUNCTION TEMPERATURE

7000

6000

5000

C

4000

3000

2000

C, CAPACITANCE (pF)

1000

0

0 5 10 15 20 25

ISS

C

OSS

C

RSS

VDS, DRAIN TO SOURCE VOLTAGE (V)

VGS = 0V, f = 1MHz

= CGS + C

C
C
C

ISS
RSS
OSS

= C
= CDS + C

GD

GD

GD

FIGURE 10. NORMALIZED DRAIN TO SOURCE BREAKDOWN

VOLTAGE vs JUNCTION TEMPERATURE

4

FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE

RFP70N03, RF1S70N03SM

Typical Performance Curves

30.0

22.5

15.0

, DRAIN SOURCE VOLTAGE (V)

DS

V

NOTE: Refer to Intersil Application Notes AN7254 and AN7260.

FIGURE 12. GATE CHARGE WAVEFORMS FOR CONSTANT GATE CURRENT

Test Circuits and Waveforms

VARY t

TO OBTAIN

P

REQUIRED PEAK I

V

GS

AS

R

G

(Continued)

VDD = BV

7.5

0

20

V

DS

L

DUT

DSS

0.75BV

0.50BV

0.25BV

IgREF

()

---------------------

IgACT()

+

V

DD

-

DSS
DSS
DSS

RL = 0.43Ω
I

= 3.0mA

g(REF)

= 10V

V

GS

t, TIME (µs)

VDD = BV

0.75BV

0.50BV

0.25BV

DSS

DSS
DSS
DSS

()

IgREF

---------------------

80

IgACT()

10.0

7.5

5.0

2.5

0

, GATE SOURCE VOLTAGE (V)

GS

V

BV

DSS

t

P

I

AS

V

DS

V

DD

0V

P

I

AS

0.01Ω

0

t

AV

t

FIGURE 13. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 14. UNCLAMPED ENERGY WAVEFORMS

t

ON

t

DS

10%

d(ON)

90%

50%

t

10%

r

PULSE WIDTH

V

DS

V

R

DUT

L

+

V

DD

-

0

V

GS

0

V

GS

R

GS

V

GS

t

d(OFF)

90%

FIGURE 15. SWITCHING TIME TEST CIRCUIT FIGURE 16. SWITCHING WAVEFORMS

t

OFF

50%

t

f

90%

10%

5

RFP70N03, RF1S70N03SM

Test Circuits and Waveforms

V

DS

V

GS

I

g(REF)

FIGURE 17. GATE CHARGE TEST CIRCUIT FIGURE 18. GATE CHARGE WAVEFORM

(Continued)

R

L

DUT

V

DD

+

V

DD

-

VGS= 2V

0

I

g(REF)

0

V

GS

Q

Q

g(TH)

V

DS

g(10)

Q

g(TOT)

VGS= 20V

VGS = 10V

6

PSPICE Electrical Model

.SUBCKT RFP70N03 2 1 3 ; rev 9/16/92

*NOM TEMP = 25

CA 12 8 6.09e-9
CB 15 14 6.05e-9
CIN 6 8 3.40e-9

DBODY 7 5 DBDMOD
DBREAK 5 11 DBKMOD
DPLCAP 10 5 DPLCAPMOD

EBREAK 11 7 17 18 35.4
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTO 20 6 18 8 1

IT 8 17 1

LDRAIN 2 5 1e-9
LGATE 1 9 3.10e-9
LSOURCE 3 7 1.82e-9

MOS1 16 6 8 8 MOSMOD M=0.99
MOS2 16 21 8 8 MOSMOD M=0.01

RBREAK 17 18 RBKMOD 1
RDRAIN 5 16 RDSMOD 30.7e-6
RGATE 9 20 0.890
RIN 6 8 1e9
RSOURCE 8 7 RDSMOD 3.92e-3
RVTO 18 19 RVTOMOD 1

o

C

RFP70N03, RF1S70N03SM

10

DPLCAP

-

6

ESG

8

GATE

1

LGATE

+

EVTO

+

-

209

18

RGATE

8

S1A S2A

12 15

13

8

+

-

VTO

-

6

RIN CIN

14
13

S2BS1B
13

6

EDSEGS

8

5

RDRAIN

16
+

21

MOS1

CBCA

14

+

5
8

-

8

DBREAK

MOS2

EBREAK

RSOURCE

11

+

17
18

RBREAK

-

7

DRAIN

LDRAIN

DBODY

LSOURCE

SOURCE

1817

RVTO

19IT

-

VBAT

+

2

3

S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD

VBAT 8 19 DC 1
VTO 21 6 0.605

.MODEL DBDMOD D (IS=7.91e-12 RS=3.87e-3 TRS1=2.71e-3 TRS2=2.50e-7 CJO=4.84e-9 TT=4.51e-8)
.MODEL DBKMOD D (RS=3.9e-2 TRS1=1.05e-4 TRS2=3.11e-5)
.MODEL DPLCAPMOD D (CJO=4.8e-9 IS=1e-30 N=10)
.MODEL MOSMOD NMOS (VTO=3.46 KP=47 IS=1e-30 N=10 TOX=1 L=1u W=1u)
.MODEL RBKMOD RES (TC1=8.46e-4 TC2=-8.48e-7)
.MODEL RDSMOD RES (TC1=2.23e-3 TC2=6.56e-6)
.MODEL RVTOMOD RES (TC1=-3.29e-3 TC2=3.49e-7)
.MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-8.35 VOFF=-6.35)
.MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-6.35 VOFF=-8.35)
.MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-2.0 VOFF=3.0)
.MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=3.0 VOFF=-2.0)

.ENDS

NOTE: For further discussion of the PSPICE model consult A New PSPICE Sub-circuit for the Power MOSFET Featuring Global
Temperature Options; written by William J. Hepp and C. Frank Wheatley.

7

RFP70N03, RF1S70N03SM

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.

Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with­out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see web site http://www.intersil.com

Sales Office Headquarters

NORTH AMERICA

Intersil Corporation
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: [phone]
FAX: [phone]

8

EUROPE

Intersil SA
Mercure Center
100, Rue de la Fusee
1130 Brussels, Belgium
TEL: [phone]
FAX: [phone]

ASIA

Intersil (Taiwan) Ltd.
7F-6, No. 101 Fu Hsing North Road
Taipei, Taiwan
Republic of China
TEL: [phone]
FAX: [phone]

RFP70N03, RF1S70N03SM

Data Sheet July 1999 File Number

70A, 30V, 0.010 Ohm, N-Channel Power
MOSFETs

These N-Channel power MOSFETs are manufacturedusing
the MegaFET process. This process, which uses feature
sizes approaching those of LSI integrated circuits gives
optimum utilization of silicon, resulting in outstanding
performance. They were designed for use in applications
such as switching regulators, switching converters, motor
drivers, and relay drivers. These transistors can be operated
directly from integrated circuits.

Formerly developmental type TA49025.

Ordering Information

PART NUMBER PACKAGE BRAND

RFP70N03 TO-220AB RFP70N03
RF1S70N03SM TO-263AB F1S70N03

NOTE: When ordering,use the entire part number. Add the suffix9A to
obtain the TO-263AB variant in tape and reel, e.g., RF1S70N03SM9A

Features

• 70A, 30V

DS(ON)

= 0.010Ω

®

Model

•r

• Temperature Compensating PSPICE

• Peak Current vs Pulse Width Curve

• UIS Rating Curve (Single Pulse)

o

C Operating Temperature

• 175

• Related Literature

- TB334 “Guidelines for Soldering Surface Mount
Components to PC Boards”

Symbol

D

G

S

3404.4

Packaging

DRAIN

(FLANGE)

JEDEC TO-220AB JEDEC TO-263AB

SOURCE

DRAIN

GATE

GATE
SOURCE

DRAIN

(FLANGE)

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.

PSPICE® is a registered trademark of MicroSim Corporation.

http://www.intersil.com or 407-727-9207

| Copyright © Intersil Corporation 1999

RFP70N03, RF1S70N03SM

Absolute Maximum Ratings T

= 25oC, Unless Otherwise Specified

C

UNITS

Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

DSS

DGR

GS

30 V
30 V

±20 V

Drain Current

Continuous (Figure 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I

Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I

Pulsed Avalanche Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P

D

DM

AS

D

Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, T

STG

Maximum Temperature for Soldering

Leads at 0.063in (1.6mm) from case for 10s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .T

Package Body for 10s, see Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationofthe
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

L

pkg

70

200

Figures 5, 13, 14

150

1.0

-55 to 175

300
260

A
A

W

W/oC

o

C

o

C

o

C

NOTE:

1. TJ = 25oC to 150oC.

Electrical Specifications T

= 25oC, Unless Otherwise Specified

C

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Drain to Source Breakdown Voltage BV
Gate to Source Threshold Voltage V
Zero Gate Voltage Drain Current I

DSSID

GS(TH)VGS

DSS

= 250µA, VGS = 0V (Figure 10) 30 - - V

= VDS, ID = 250µA (Figure 9) 2 - 4 V
VDS = 30V, VGS = 0V - - 1 µA
VDS = 30V, VGS = 0V, TC = 150oC--50µA

Gate to Source Leakage Current I
Drain to Source On Resistance r

DS(ON)ID

Turn-On Time t
Turn-On Delay Time t

d(ON)

Rise Time t
Turn-Off Delay Time t

d(OFF)

Fall Time t
Turn-Off Time t
Total Gate Charge Q

g(TOT)VGS

Gate Charge at 10V Q
Threshold Gate Charge Q
Input Capacitance C
Output Capacitance C
Reverse Transfer Capacitance C
Thermal Resistance Junction to Case R
Thermal Resistance Junction to Ambient R

GSS

ON

OFF

g(10)

g(TH)

ISS

OSS

RSS

θJC
θJA

VGS = ±20V - - 100 nA

= 70A, VGS = 10V (Figure 8) - - 0.010 Ω

VDD = 15V, ID≅ 70A,
RL = 0.214Ω, VGS= 10V,
RGS = 2.5Ω

r

- - 80 ns

-20-ns

-20-ns

-40-ns

f

-25-ns

- - 125 ns

= 0V to 20V VDD = 24V, ID≅ 70A,
VGS = 0V to 10V - 120 145 nC
VGS = 0V to 2V - 6.5 8.0 nC

RL = 0.343Ω
I

= 1.0mA

g(REF)

(Figure 12)

VDS = 25V, VGS = 0V,
f = 1MHz
(Figure 11)

- 215 260 nC

- 3300 - pF

- 1750 - pF

- 750 - pF
(Figure 3) - - 1.0
TO-220, TO-263 - - 62

o
o

C/W
C/W

Source to Drain Diode Specifications

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Source to Drain Diode Voltage V
Reverse Recovery Time t

2

SD

rr

ISD = 70A - - 1.5 V
ISD = 70A, dISD/dt = 100A/µs - - 125 ns

Typical Performance Curves

RFP70N03, RF1S70N03SM

1.2

1.0

0.8

0.6

0.4

0.2

POWER DISSIPATION MULTIPLIER

0

0 25 50 75 100 175

125

150

TC, CASE TEMPERATURE (oC)

FIGURE 1. NORMALIZED POWERDISSIPATION vs CASE

TEMPERATURE

0

10

0.5

0.2

-1

0.1

10

0.05

0.02

0.01

, NORMALIZED THERMAL IMPEDANCE

θJC

Z

10

-2

-5

10

SINGLE PULSE

10

-4

-3

10

t1, RECTANGULAR PULSE DURATION (s)

80
70

60

50

40

30

, DRAIN CURRENT (A)

20

D

I

10

0

25 50 75 100 125 150 175

, CASE TEMPERATURE (oC)

T

C

FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs

CASE TEMPERATURE

P

DM

NOTES:
DUTY FACTOR: D = t1/t
PEAK TJ = PDM x Z

-2

10

-1

10

2

x R

θJC

-0

10

t

1

t

2

+ T

θJC

C

1

10

FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE

300

100

OPERATION IN THIS
AREA MAY BE
LIMITED BY r

10

, DRAIN CURRENT (A)

D

I

TC = 25oC
T

= MAX RATED

J

SINGLE PULSE

1

1

DS(ON)

V

DSS(MAX)

10 50

V

, DRAIN TO SOURCE VOLTAGE (V)

DS

= 30V

FIGURE 4. FORWARD BIAS SAFE OPERATING AREA

3

100µs

1ms

10ms

100ms
DC

300

I

DM

STARTING TJ = 25oC
STARTING TJ = 150oC

100

If R = 0

, AVALANCHE CURRENT (A)

tAV = (L) (IAS)/(1.3 x RATED BV

AS

I

If R ≠ 0

= (L/R) ln [(IAS x R)/(1.3 x RATED BV

t

AV

10

0.01
t

AV

0.10
, TIME IN AVALANCHE (ms)

DSS

- VDD)

- VDD) +1]

DSS

110

NOTE: Refer to Intersil Application Notes AN9321 and AN9322.

FIGURE 5. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY

RFP70N03, RF1S70N03SM

Typical Performance Curves

200

160

120

80

, DRAIN CURRENT (A)

D

I

40

0

0 1.5 3.0 4.5 6.0 7.5

VGS = 8VVGS = 10V

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
T

C

VDS, DRAIN TO SOURCE VOLTAGE (V)

(Continued)

= 25oC

FIGURE 6. SATURATION CHARACTERISTICS FIGURE 7. TRANSFER CHARACTERISTICS

2.0

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VGS = 10V, ID= 70A

1.5

VGS = 7V

VGS = 6V

VGS = 5V

VGS = 4V

200

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
V

= 15V

DD

160

120

80

DRAIN CURRENT (A)

40

0

0246810

2.0

1.6

VGS, GATE TO SOURCE VOLTAGE (V)

VGS = VDS,ID = 250µA

-55oC

25oC

175oC

1.0

ON RESISTANCE

0.5

NORMALIZED DRAIN TO SOURCE

0

-80 -40 0 40 80 120 160 200
T

, JUNCTION TEMPERATURE (oC)

J

FIGURE 8. NORMALIZED DRAIN TO SOURCE ON

RESISTANCE vs JUNCTION TEMPERATURE

2.0
ID = 250µA

1.6

1.2

0.8

BREAKDOWN VOLTAGE

0.4

NORMALIZED DRAIN TO SOURCE

0

-80 -40 0 40 80 120 160 200
T

, JUNCTION TEMPERATURE (oC)

J

1.2

0.8

NORMALIZED

0.4

GATE THRESHOLD VOLTAGE

0

-80 -40 0 40 80 120 160 200
, JUNCTION TEMPERATURE (oC)

T

J

FIGURE 9. NORMALIZED GATE THRESHOLD VOLTAGEvs

JUNCTION TEMPERATURE

7000

6000

5000

C

4000

3000

2000

C, CAPACITANCE (pF)

1000

0

0 5 10 15 20 25

ISS

C

OSS

C

RSS

VDS, DRAIN TO SOURCE VOLTAGE (V)

VGS = 0V, f = 1MHz

= CGS + C

C
C
C

ISS
RSS
OSS

= C
= CDS + C

GD

GD

GD

FIGURE 10. NORMALIZED DRAIN TO SOURCE BREAKDOWN

VOLTAGE vs JUNCTION TEMPERATURE

4

FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE

RFP70N03, RF1S70N03SM

Typical Performance Curves

30.0

22.5

15.0

, DRAIN SOURCE VOLTAGE (V)

DS

V

NOTE: Refer to Intersil Application Notes AN7254 and AN7260.

FIGURE 12. GATE CHARGE WAVEFORMS FOR CONSTANT GATE CURRENT

Test Circuits and Waveforms

VARY t

TO OBTAIN

P

REQUIRED PEAK I

V

GS

AS

R

G

(Continued)

VDD = BV

7.5

0

20

V

DS

L

DUT

DSS

0.75BV

0.50BV

0.25BV

IgREF

()

---------------------

IgACT()

+

V

DD

-

DSS
DSS
DSS

RL = 0.43Ω
I

= 3.0mA

g(REF)

= 10V

V

GS

t, TIME (µs)

VDD = BV

0.75BV

0.50BV

0.25BV

DSS

DSS
DSS
DSS

()

IgREF

---------------------

80

IgACT()

10.0

7.5

5.0

2.5

0

, GATE SOURCE VOLTAGE (V)

GS

V

BV

DSS

t

P

I

AS

V

DS

V

DD

0V

P

I

AS

0.01Ω

0

t

AV

t

FIGURE 13. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 14. UNCLAMPED ENERGY WAVEFORMS

t

ON

t

DS

10%

d(ON)

90%

50%

t

10%

r

PULSE WIDTH

V

DS

V

R

DUT

L

+

V

DD

-

0

V

GS

0

V

GS

R

GS

V

GS

t

d(OFF)

90%

FIGURE 15. SWITCHING TIME TEST CIRCUIT FIGURE 16. SWITCHING WAVEFORMS

t

OFF

50%

t

f

90%

10%

5

RFP70N03, RF1S70N03SM

Test Circuits and Waveforms

V

DS

V

GS

I

g(REF)

FIGURE 17. GATE CHARGE TEST CIRCUIT FIGURE 18. GATE CHARGE WAVEFORM

(Continued)

R

L

DUT

V

DD

+

V

DD

-

VGS= 2V

0

I

g(REF)

0

V

GS

Q

Q

g(TH)

V

DS

g(10)

Q

g(TOT)

VGS= 20V

VGS = 10V

6

PSPICE Electrical Model

.SUBCKT RFP70N03 2 1 3 ; rev 9/16/92

*NOM TEMP = 25

CA 12 8 6.09e-9
CB 15 14 6.05e-9
CIN 6 8 3.40e-9

DBODY 7 5 DBDMOD
DBREAK 5 11 DBKMOD
DPLCAP 10 5 DPLCAPMOD

EBREAK 11 7 17 18 35.4
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTO 20 6 18 8 1

IT 8 17 1

LDRAIN 2 5 1e-9
LGATE 1 9 3.10e-9
LSOURCE 3 7 1.82e-9

MOS1 16 6 8 8 MOSMOD M=0.99
MOS2 16 21 8 8 MOSMOD M=0.01

RBREAK 17 18 RBKMOD 1
RDRAIN 5 16 RDSMOD 30.7e-6
RGATE 9 20 0.890
RIN 6 8 1e9
RSOURCE 8 7 RDSMOD 3.92e-3
RVTO 18 19 RVTOMOD 1

o

C

RFP70N03, RF1S70N03SM

10

DPLCAP

-

6

ESG

8

GATE

1

LGATE

+

EVTO

+

-

209

18

RGATE

8

S1A S2A

12 15

13

8

+

-

VTO

-

6

RIN CIN

14
13

S2BS1B
13

6

EDSEGS

8

5

RDRAIN

16
+

21

MOS1

CBCA

14

+

5
8

-

8

DBREAK

MOS2

EBREAK

RSOURCE

11

+

17
18

RBREAK

-

7

DRAIN

LDRAIN

DBODY

LSOURCE

SOURCE

1817

RVTO

19IT

-

VBAT

+

2

3

S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD

VBAT 8 19 DC 1
VTO 21 6 0.605

.MODEL DBDMOD D (IS=7.91e-12 RS=3.87e-3 TRS1=2.71e-3 TRS2=2.50e-7 CJO=4.84e-9 TT=4.51e-8)
.MODEL DBKMOD D (RS=3.9e-2 TRS1=1.05e-4 TRS2=3.11e-5)
.MODEL DPLCAPMOD D (CJO=4.8e-9 IS=1e-30 N=10)
.MODEL MOSMOD NMOS (VTO=3.46 KP=47 IS=1e-30 N=10 TOX=1 L=1u W=1u)
.MODEL RBKMOD RES (TC1=8.46e-4 TC2=-8.48e-7)
.MODEL RDSMOD RES (TC1=2.23e-3 TC2=6.56e-6)
.MODEL RVTOMOD RES (TC1=-3.29e-3 TC2=3.49e-7)
.MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-8.35 VOFF=-6.35)
.MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-6.35 VOFF=-8.35)
.MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-2.0 VOFF=3.0)
.MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=3.0 VOFF=-2.0)

.ENDS

NOTE: For further discussion of the PSPICE model consult A New PSPICE Sub-circuit for the Power MOSFET Featuring Global
Temperature Options; written by William J. Hepp and C. Frank Wheatley.

7

RFP70N03, RF1S70N03SM

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.

Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with­out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see web site http://www.intersil.com

Sales Office Headquarters

NORTH AMERICA

Intersil Corporation
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: [phone]
FAX: [phone]

8

EUROPE

Intersil SA
Mercure Center
100, Rue de la Fusee
1130 Brussels, Belgium
TEL: [phone]
FAX: [phone]

ASIA

Intersil (Taiwan) Ltd.
7F-6, No. 101 Fu Hsing North Road
Taipei, Taiwan
Republic of China
TEL: [phone]
FAX: [phone]