Datasheet RF1S50N06LESM, RFG50N06LE, RFP50N06LE Datasheet (Intersil)

RFG50N06LE, RFP50N06LE, RF1S50N06LESM

Data Sheet October 1999 File Number 4072.3

50A, 60V, 0.022 Ohm, Logic Level
N-Channel Power MOSFETs

These N-Channel enhancement mode power MOSFETs are
manufactured using the latest manufacturing process
technology. This process, which uses feature sizes
approaching those of LSI circuits, gives optimum utilization
of silicon, resulting in outstanding performance. They were
designed for use in applications such as switching
regulators, switching converters, motor drivers, and relay
drivers. These transistors can be operated directly from
integrated circuits.

Formerly developmental type TA49164.

Ordering Information

P AR T NUMBER P ACKAGE BRAND

RFG50N06LE TO-247 FG50N06L
RFP50N06LE TO-220AB FP50N06L
RF1S50N06LESM TO-263AB F50N06LE

NOTE: Whenordering, usethe entirepartnumber. Addthe suffix9A
to obtain the TO-263AB variant in tape and reel, i.e.
RF1S50N06LESM9A.

Features

• 50A, 60V

•r

DS(ON)

• Temperature Compensating PSPICE

= 0.022Ω

®

Model

• Peak Current vs Pulse Width Curve

• UIS Rating Curve

o

C Operating Temperature

• 175

• Related Literature

- TB334 “Guidelines for Soldering Surface Mount
Components to PC Boards”

Symbol

D

G

S

Packaging

DRAIN

(BOTTOM

SIDE METAL)

JEDEC STYLE TO-247 JEDEC TO-220AB

SOURCE

DRAIN

GATE

DRAIN (FLANGE)

JEDEC TO-263AB

DRAIN

GATE

SOURCE

(FLANGE)

SOURCE

DRAIN

GATE

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.

PSPICE® is a registered trademark of MicroSim Corporation.

www.intersil.com or 407-727-9207

| Copyright © Intersil Corporation 1999

RFG50N06LE, RFP50N06LE, RF1S50N06LESM

Absolute Maximum Ratings T

= 25oC, Unless Otherwise Specified

C

RFG50N06LE, RFP50N06LE,

RF1S50N06LESM UNITS

Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V

Drain to Gate Voltage (RGS= 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . V

Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V

Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I

Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I

Pulsed Avalanche Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P

DSS

DGR

GS

DM

AS

D

Refer to Peak Current Curve

D

Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, T

STG

Maximum Temperature for Soldering

Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . T

Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .T

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

L

pkg

60 V
60 V

±10 V

50

Refer to UIS Curve

142

0.95

-55 to 175

300
260

A

W

W/oC

o

C

o

C

o

C

NOTE:

1. TJ= 25oC to 150oC.

Electrical Specifications T

= 25oC, Unless Otherwise Specified

C

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Drain to Source Breakdown Voltage BV
Gate Threshold Voltage V
Zero Gate Voltage Drain Current I

DSS

GS(TH)

DSS

ID = 250µA, VGS = 0V, Figure 13 60 - - V
VGS= VDS, ID = 250µA, Figure 12 1 - 3 V
VDS = 55V, VGS = 0V - - 1 µA

VDS = 50V, VGS = 0V, TC = 150oC - - 250 µA
Gate to Source Leakage Current I
Drain to Source On Resistance (Note 2) r

DS(ON)ID

Turn-On Time t
Turn-On Delay Time t

d(ON)

Rise Time t
Turn-Off Delay Time t

d(OFF)

Fall Time t
Turn-Off Time t
Total Gate Charge Q

g(TOT)

Gate Charge at 5V Q
Threshold Gate Charge Q

Input Capacitance C
Output Capacitance C
Reverse Transfer Capacitance C
Thermal Resistance Junction to Case R
Thermal Resistance Junction to Ambient R

GSS

ON

r

f

OFF

g(5)

g(TH)

ISS
OSS
RSS

θJC

θJA

VGS = ±10V - - 10 µA

= 50A, VGS = 5V, Figure 11 - - 0.022 Ω

VDD = 30V, ID = 50A,
RL = 0.6Ω, VGS = 5V,
RGS = 2.5Ω
Figures 10, 18, 19

- - 230 ns

-20- ns

- 170 - ns

-48- ns

-90- ns

- - 165 ns
VGS = 0V to 10V VDD = 48V,
VGS = 0V to 5V - 57 70 nC
VGS = 0V to 1V - 2.2 2.7 nC

ID = 50A,
RL = 0.96Ω
Figures 21, 21

VDS = 25V, VGS = 0V,
f = 1MHz
Figure 14

- 96 120 nC

- 2100 - pF

- 600 - pF

- 230 - pF

- - 1.05
TO-247 - - 30
TO-220AB and TO-263AB - - 80

o
o
o

C/W
C/W
C/W

Source to Drain Diode Specifications

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Source to Drain Diode Voltage V
Diode Reverse Recovery Time t

SD

rr

NOTES:

2. Pulse test: pulse width ≤ 80µs, duty cycle ≤ 2%.

3. Repetitive rating: pulse width limited by Max junction temperature. See Transient Thermal Impedance curve (Figure 3).

2

ISD = 45A - - 1.5 V
ISD = 45A, dISD/dt = 100A/µs - - 125 ns

RFG50N06LE, RFP50N06LE, RF1S50N06LESM

Typical Performance Curves Unless Otherwise Specified

1.2

1.0

0.8

0.6

0.4

0.2

POWER DISSIPATION MULTIPLIER

0

0 25 50 75 100 175

125

150

TC, CASE TEMPERATURE (oC)

FIGURE 1. NORMALIZED POWER DISSIPATION vsCASE

TEMPERATURE

2

1

0.5

0.2

0.1

0.1

, NORMALIZED

JC

Z

θ

THERMAL IMPEDANCE

0.01
10

-5

0.05

0.02

0.01
SINGLE PULSE

-4

10

-3

10

t, RECTANGULAR PULSE DURATION (s)

60

50

40

30

20

, DRAIN CURRENT (A)

D

I

10

0

25 50 75 100 125 150

TC, CASE TEMPERATURE (oC)

FIGURE 2. MAXIMUM CONTINUOUS DRAINCURRENT vs

CASE TEMPERATURE

P

DM

t

1

t

2

NOTES:
DUTY FACTOR: D = t
PEAK TJ = PDM x Z

-2

10

-1

10

1/t2

x R

JC

θ

0

10

175

+ T

JC

C

θ

1

10

FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE

500

100

10

, DRAIN CURRENT (A)

D

I

OPERATION IN THIS
AREA MAY BE
LIMITED BY r

1

1 10 100

DS(ON)

VDS, DRAIN TO SOURCE VOLTAGE (V)

TC = 25oC

T

= MAX RATED

J

100µs

1ms

10ms

200

1000

100

THERMAL IMPEDANCE
MAY LIMIT CURRENT

DM

10

IN THIS REGION

-5

10

, PEAK CURRENT CAPABILITY (A)
I

VGS = 10V

VGS = 5V

FOR TEMPERATURES
ABOVE 25
CURRENT AS FOLLOWS:

-4

10

-3

10

10

I = I

-2

o

C DERATE PEAK

175 - T

25

-1

10

t, PULSE WIDTH (s)

FIGURE 4. FORWARD BIAS SAFE OPERATING AREA FIGURE 5. PEAK CURRENT CAPABILITY

3

150

TC = 25oC

C

0

10

1

10

RFG50N06LE, RFP50N06LE, RF1S50N06LESM

Typical Performance Curves Unless Otherwise Specified (Continued)

300

100

10

STARTING TJ = 150oC

, AVALANCHE CURRENT (A)

AS

I

1

= (L/R)ln[(IAS*R)/(1.3*RATED BV

t

AV

If R ≠ 0

tAV = (L)(IAS)/(1.3*RATED BV

If R = 0

tAV, TIME IN AVALANCHE (ms)

DSS

STARTING TJ = 25oC

1 10 1000.01 0.1

DSS

- VDD)

- VDD) +1]

100

TC = 25oC

75

50

, DRAIN CURRENT (A)

25

D

I

0

0 1.5 3.0 4.5 6.0

VDS, DRAIN TO SOURCE VOLTAGE (V)

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX

VGS = 10V
VGS = 5V

NOTE: Refer to Intersil Application Notes AN9321 and AN9322

FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING FIGURE 7. SATURATION CHARACTERISTICS

100

V

= 15V

DD

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX

75

50

25

, DRAIN TO SOURCE CURRENT (A)

DS(ON)

I

0

0 3.0 4.5 6.01.5

VGS, GATE TO SOURCE VOLTAGE (V)

-55oC
25oC

175oC

80

60

40

, DRAIN TO SOURCE

20

ON RESISTANCE (mΩ)

DS(ON)

r

0

ID = 12.5A

ID = 25A

VDD= 15V
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX

2.0

3.0

, GATE TO SOURCE VOLTAGE (V)

V

GS

ID = 50A

3.5 4.5 5.0

VGS = 4V

VGS = 3V

VGS = 2.5V

ID = 100A

4.02.5

FIGURE 8. TRANSFER CHARACTERISTICS FIGURE 9. DRAIN TO SOURCEON RESISTANCEvs GATE

VOLTAGE AND DRAIN CURRENT

600

VDD = 30V, ID = 50A, RL= 0.6Ω

500

400

300

200

SWITCHING TIME (ns)

100

0

10

RGS, GATE TO SOURCE RESISTANCE (Ω)

t

r

t

d(OFF)

t

f

t

d(ON)

20 30 40 500

2.5
V

= 5V, ID = 50A

GS

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX

2.0

1.5

ON RESISTANCE

1.0

NORMALIZED DRAIN TO SOURCE

0.5

-80 -40 0 40 80 120 160
TJ, JUNCTION TEMPERATURE (oC)

FIGURE 10. SWITCHING TIME vs GATE RESISTANCE FIGURE 11. NORMALIZED DRAIN TO SOURCE ON

RESISTANCE vs JUNCTION TEMPERATURE

4

200

RFG50N06LE, RFP50N06LE, RF1S50N06LESM

Typical Performance Curves Unless Otherwise Specified (Continued)

2.0
VGS = VDS,

1.5

1.0

NORMALIZED GATE

0.5

THRESHOLD VOLTAGE

0

-80 -40 0 40 80 120 160

I

= 250µA

D

TJ, JUNCTION TEMPERATURE (oC)

200

FIGURE 12. NORMALIZED GATE THRESHOLD VOLTAGE vs

JUNCTION TEMPERATURE

2500

C

ISS

2000

VGS = 0V, f = 1MHz
C

= CGS + C

1500

1000

C, CAPACITANCE (pF)

500

0

0 5 10 15 20 25

VDS, DRAIN TO SOURCE VOLTAGE (V)

ISS

C

= C

RSS

C

OSS

GD

≈ CDS + C

GD

GD

C

OSS

C

RSS

FIGURE 14. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE

1.2
ID = 250µA

1.1

1.0

0.9

BREAKDOWN VOLTAGE

NORMALIZED DRAIN TO SOURCE

0.8

-80

-40 0 40 80 120
T

, JUNCTION TEMPERATURE (oC)

J

160

FIGURE 13. NORMALIZED DRAIN TO SOURCE BREAKDOWN

VOLTAGE vs JUNCTION TEMPERATURE

60

45

30

15

, DRAIN TO SOURCE VOLTAGE (V)

DS

V

0

VDD = BV

I

GREF()

--------------------- -

20

I

GACT()

DSS

RL =1.2Ω

= 1.2mA

I

G(REF)

= 5V

V

GS

PLATEAU VOLTAGES IN
DESCENDING ORDER:

= BV

V

DD

VDD = 0.75 BV
VDD = 0.50 BV
VDD = 0.25 BV

DSS

DSS
DSS
DSS

t, TIME (µs)

VDD = BV

I

GREF()

--------------------- -

80

I

G ACT()

5.0

DSS

3.75

2.5

1.25

0

NOTE: Refer to Intersil Application Notes AN7254 and AN7260.

FIGURE 15. NORMALIZED SWITCHINGWAVEFORMSFOR

CONSTANT GATE CURRENT

200

, GATE TO SOURCE VOLTAGE (V)

GS

V

Test Circuits and Waveforms

V

DS

BV

DSS

L

VARY t

TO OBTAIN

P

REQUIRED PEAK I

V

GS

t

0V

P

AS

R

G

DUT

I

AS

0.01Ω

+

V

DD

-

0

FIGURE 16. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 17. UNCLAMPED ENERGY WAVEFORMS

5

t

P

I

AS

t

AV

V

DS

V

DD

RFG50N06LE, RFP50N06LE, RF1S50N06LESM

Test Circuits and Waveforms (Continued)

t

ON

t

10%

d(ON)

90%

50%

10%

t

r

PULSE WIDTH

V

DS

V

DS

R

DUT

L

+

V

DD

-

0

V

GS

0

V

GS

R

GS

V

GS

FIGURE 18. SWITCHING TIME TEST CIRCUIT FIGURE 19. RESISTIVE SWITCHING WAVEFORMS

V

I

g(REF)

DS

R

L

V

GS

+

V

DD

-

DUT

V

DD

VGS= 2V

0

Q

g(TOT)

V

DS

Q

OR Q

g(10)

V

GS

VGS= 1V FOR

g(5)

V

GS

VGS= 5V FOR

2

L

DEVICES

L2 DEVICES

Q

g(TH)

t

d(OFF)

90%

= 10V

t

OFF

t

f

10%

50%

V

GS

L2 DEVICES

90%

VGS= 20V
= 10V FOR

I

g(REF)

0

FIGURE 20. GATE CHARGE TEST CIRCUIT FIGURE 21. GATE CHARGE WAVEFORMS

6

RFG50N06LE, RFP50N06LE, RF1S50N06LESM

PSPICE Electrical Model

SUBCKT 50N06LE 2 1 3 ; rev 8/11/95

CA 12 8 3.73e-9
CB 15 14 3.73e-9
CIN 6 8 2.08e-9

DBODY 7 5 DBODYMOD
DBREAK 5 11 DBREAKMOD
DPLCAP 10 5 DPLCAPMOD

EBREAK 11 7 17 18 66.5
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTHRES 6 21 19 8 1
EVTEMP 20 6 18 22 1

IT 8 17 1
LDRAIN 2 5 4.0e-9

LGATE 1 9 6.0e-9
LSOURCE 3 7 3.0e-9

GATE

1

MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD

RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 3.75e-3
RGATE 9 20 1.0
RLDRAIN 2 5 40
RLGATE 1 9 60
RLSOURCE 3 7 30
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD 6.15e-3
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1

S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD

LGATE

RLGATE

RGATE

9

CA

-

ESG

+

EVTEMP
+

-

18
22

20

S1A

12

13

8

S1B

EGS EDS

13

10

6
8

+

+

RSLC2

6

S2A

14
13

S2B

6
8

-

-

DPLCAP

EVTHRES

+

19

8

CIN

15

CB

-

+

-

5

RSLC1

51

5

51

50
RDRAIN

21

MSTRO

14

5
8

+

-

ESLC

16

8

MMED

DBREAK

11

EBREAK

MWEAK

RSOURCE

RBREAK

17 18

IT

8

RVTHRES

+

17
18

-

7

RVTEMP
19

-

+

22

LDRAIN

RLDRAIN

DBODY

LSOURCE

RLSOURCE

VBAT

DRAIN

2

SOURCE

3

S2B 13 15 14 13 S2BMOD
VBAT 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*200),4))}
.MODEL DBODYMOD D (IS = 1.70e-12 RS = 3.20e-3 TRS1 = 1.75e-3 TRS2 = 1.75e-6 CJO = 2.55e-9 IKF = 13 XTI = 5.2 TT = 7.00e-8 M = 0.47)

.MODEL DBREAKMOD D (RS = 1.70e-1 IKF = 0.1 TRS1 = 2.00e-3 TRS2 = 8.00e-7)
.MODEL DPLCAPMOD D (CJO = 2.00e-9 IS = 1e-30 VJ = 1.1 M = 0.83 N = 10)
.MODEL MMEDMOD NMOS (VTO = 2.00 KP = 5 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 1.0)
.MODEL MSTROMOD NMOS (VTO = 2.42 KP = 128 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL MWEAKMOD NMOS (VTO = 1.60 KP = 0.01 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 10.0 RS = 0.1)
.MODEL RBREAKMOD RES (TC1 = 1.13e-3 TC2 = 0)
.MODEL RDRAINMOD RES (TC1 = 1.20e-2 TC2 = 6.00e-5)
.MODEL RSLCMOD RES (TC1 = 2.00e-3 TC2 = 1.00e-6)
.MODEL RSOURCEMOD RES (TC1 = 2.00e-3 TC2 =-1.00e-5)
.MODEL RVTHRESMOD RES (TC1 = -2.50e-3 TC2 = -8.50e-6)
.MODEL RVTEMPMOD RES (TC1 = -2.00e-3 TC2 = 5.00e-6)

.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -5.3 VOFF= -2.5)
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -2.5 VOFF= -5.3)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -1.4 VOFF= 0.5)
.MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 0.5 VOFF= -1.4)

.ENDS

NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.

7

RFG50N06LE, RFP50N06LE, RF1S50N06LESM

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.

Intersil semiconductor productsare sold by description only. Intersil Corporation reservesthe right to make changes in circuit design and/orspecifications at any time with­out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor forany infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

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8

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