Datasheet RFG50N05, RFP50N05 Datasheet (Intersil)

RFG50N05, RFP50N05

Data Sheet July 1999 File Number

50A, 50V, 0.022 Ohm, N-Channel Power
MOSFETs

These are N-Channel power MOSFET’S manufactured
using the MegaFET process. This process, which uses
feature sizes approaching those of LSI integrated circuits,
gives optimum utilization of silicon, resulting in outstanding
performance. They were designed for use in applications
such as switching regulators, switching converters, motor
drivers, relay drivers and emitter switches for bipolar
transistors.

Formerly developmental type TA09772.

Ordering Information

PART NUMBER PACKAGE BRAND

RFG50N05 TO-247 RFG50N05
RFP50N05 TO-220AB RFP50N05

NOTE: When ordering, include the entire part number.

Features

• 50A, 50V

DS(ON)

= 0.022Ω

•r

• UIS Rating Curve (Single Pulse)

o

C Operating Temperature

• 175

Symbol

D

G

S

2873.3

Packaging

DRAIN

(BOTTOM

SIDE METAL)

JEDEC STYLE TO-247 JEDEC TO-220AB

SOURCE

DRAIN

GATE

DRAIN

(FLANGE)

SOURCE

DRAIN

GATE

4-462

CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.

http://www.intersil.com or 407-727-9207

| Copyright © Intersil Corporation 1999

RFG50N05, RFP50N05

Absolute Maximum Ratings T

= 25oC, Unless Otherwise Specified

C

RFG50N05, RFP50N05 UNITS

Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V

Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . V

DSS

DGR

Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I

Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I

Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V

Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P

D

DM

GS

D

50 V
50 V

50 A
120 A
±20 V
132 W

Linear Derating Factor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.88 W/oC

Single Pulse Avalanche Energy Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E

Operating and Storage Junction Temperature Range . . . . . . . . . . . . . . . . . TJ, T

as

STG

Maximum Temperature for Soldering

Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . T

Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .T

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationofthe
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

L

pkg

Refer to UIS SOA Curve

-55 to 175

300
260

o

C

o

C

o

C

NOTE:

1. TJ= 25oC to 150oC.

Electrical Specifications T

= 25oC, Unless Otherwise Specified

C

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Drain to Source Breakdown Voltage BV
Gate Threshold Voltage V
Zero Gate Voltage Drain Current I

DSSID

GS(TH)VDS

DSS

Zero Gate Voltage Drain Current, VDS = 0.8 x Rated BV
Gate to Source Leakage Current I
Drain to Source On Resistance (Note 2) r
Turn-On Time t
Turn-On Delay Time t
Rise Time t
Turn-Off Delay Time t
Fall Time t
Turn-Off Time t
Total Gate Charge Q
Gate Charge at 10V Q
Threshold Gate Charge Q
Thermal Resistance Junction to Case R
Thermal Resistance Junction to Ambient R

GSS

DS(ON)ID

(ON)

d(ON)

r

d(OFF)

f

(OFF)

g(tot)VGS
g(10)VGS

g(th)

θJC
θJA

= 0.250µA, VGS = 0V (Figure 9) 50 - - V

= VGS, ID = 0.250µA (Figure 8) 2.0 - 4.0 V

VDS = Rated BV

, VGS = 0V - - 1 A

DSS

, VGS = 0V, TJ = 150oC- -25µA

DSS

VGS = ±20V - - ±100 nA

= 50A, VGS = 10V (Figure 7) - - 0.022 Ω

VDD = 25V, I
RGS = 6.67Ω, VGS = 10V
(Figure 11)

≈ 25A, R

D

= 1.0Ω,

L

- - 100 ns

-15- ns

-55- ns

-60- ns

-15- ns

- - 100 ns
= 0-20V VDD - 40V, ID = 50A
= 0-10V - - 80 nC

RL = 0.8Ω, I
(Figure 11)

G(REF)

= 1.5mA

- - 160 nC

VGS = 0-2V - - 6 nC

- - 1.14oC/W

TO-220 - - 62
TO-247 30

o
o

C/W
C/W

Source to Drain Diode Specifications

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Source to Drain Diode Voltage (Note 2) V
Diode Reverse Recovery Time t

NOTES:

2. Pulsed test: pulse width ≤ 300µs duty cycle ≤ 2%.

3. Repetitive rating: pulse width is limited by maximum junction temperature.

4-463

ISD = 50A - 1.5 V

SD

ISD = 50A, dlSD/dt = 100A/µs - 125 ns

rr

RFG50N05, RFP50N05

Typical Performance Curves

1.2

1.0

0.8

0.6

0.4

0.2

POWER DISSIPATION MULTIPLIER

0

25 50 75 100

0

0

TC, CASE TEMPERATURE (oC)

Unless Otherwise Specified

125

FIGURE 1. NORMALIZED POWER DISSIPATION vsCASE

TEMPERATURE

100

Tj = MAX RATED
TC = 25oC

150

175

60

50

40

30

20

, DRAIN CURRENT (A)

D

I

10

0

25 125 150 17575

50 100

T

, CASE TEMPERATURE (Co)

C

FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs

CASE TEMPERATURE

1000

If R = 0
tav = (L)(Ias)/(1.3 RATED BV
If R ≠ 0
tav = (L/R) In[(Ias x R)/(1.3 RATED BV

dss

- Vdd)

- Vdd) + 1]

dss

10

OPERATION IN THIS AREA
MAY BE LIMITED BY r

1

, DRAIN CURRENT (A)

D

I

0.1
1 100

V

DS

DS(ON)

10

, DRAIN TO SOURCE VOLTAGE (V)

DC

I

dm

100

Starting Tj = 25oC

, AVALANCHE CURRENT (A)

AS

I

Starting Tj = 150oC

10

0.01 10

0.1 1

, TIME IN AVALANCHE (ms)

t

AV

FIGURE 3. FORWARD BIAS SAFE OPERATING AREA FIGURE 4. UNCLAMPED INDUCTIVE SWITCHING

120

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX

TC = 25oC

100

80

60

40

, DRAIN CURRENT (A)

D

I

20

0

0

VGS = 10V

12345

V

DS,

VGS = 7V

VGS = 8V

VGS = 9V

DRAIN TO SOURCE VOLTAGE (V)

VGS = 6V

VGS = 5V

VGS = 4V

120

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX

100

80

60

40

, DRAIN TO SOURCE CURRENT (A)

20

DS(ON)

I

0

0 2.5 5 7.5 10

, GATE TO SOURCE VOLTAGE (V)

V

GS

-55oC

25oC

175oC

FIGURE 5. SATURATION CHARACTERISTICS FIGURE 6. TRANSFER CHARACTERISTICS

4-464

RFG50N05, RFP50N05

Typical Performance Curves

3

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VGS = 10V, ID = 50A

2.5

2

1.5

1

ON RESISTANCE

0.5

NORMALIZED DRAIN TO SOURCE

0

-50 50 150

FIGURE 7. NORMALIZED DRAIN TOSOURCE ON

2.0
I

1.6

0 100

TJ,JUNCTION TEMPERATURE (Co)

RESISTANCE vs JUNCTION TEMPERATURE

= 250µA

D

Unless Otherwise Specified (Continued)

2.0

1.8

1.2

0.8

THRESHOLD VOLTAGE

0.4

NORMALIZED GATE TO SOURCE

0

200

-50 50 150

FIGURE 8. NORMALIZED GATE THRESHOLD VOLTAGE vs

5000

4000

VGS = V

DS

I

= 250µA

D

0 100

TJ,JUNCTION TEMPERATURE (Co)

JUNCTION TEMPERATURE

VGS = 0V, f = 1MHz

= CGS + C

C
C
C

ISS
RSS
OSS

= C
= CDS + C

GD

GD

GD

200

1.2

0.8

BREAKDOWN VOLTAGE

0.4

NORMALIZED DRAIN TO SOURCE

0

-50 50 150

0 100 200

TJ,JUNCTION TEMPERATURE (Co)

FIGURE 9. NORMALIZED DRAIN TOSOURCE BREAKDOWN

VOLTAGE vs. JUNCTION TEMPERATURE

50

37.5

12.5

, DRAIN TO SOURCE VOLTAGE (V)

DS

V

VDD= BV

25

0

DSS

0.75BV

0.50BV

0.25 BV

DRAIN SOURCE VOLTAGE

I

G(REF)

20 80

I

G(ACT)

SOURCE

VOLTAGE

RL = 1Ω

I

G(REF)

V

GS

DSS
DSS

DSS

t, TIME (µs)

GATE

= 1.5mA

= 10V

0.75BV

0.50BV

0.25BV

3000

2000

C, CAPACITANCE (pF)

1000

0

125

C

ISS

C

OSS

C

RSS

5

V

DS

10 15 20

, DRAIN TO SOURCE VOLTAGE (V)

FIGURE 10. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE

10

8

VDD= BV

DSS
DSS
DSS

DSS

I

G(REF)

I

G(ACT)

6

4

2

0

, GATE TO SOURCE VOLTAGE (V)

GS

V

NOTE: Refer to Intersil Application Notes AN7254 and AN7260

FIGURE 11. NORMALIZED SWITCHING WAVEFORMS FOR CONSTANT GATE CURRENT

4-465

RFG50N05, RFP50N05

Test Circuits and Waveforms

V

DS

BV

DSS

L

VARY t

TO OBTAIN

P

REQUIRED PEAK I

V

GS

AS

R

G

+

V

DD

-

DUT

0V

P

I

AS

0.01Ω

0

t

FIGURE 12. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 13. UNCLAMPED ENERGY WAVEFORMS

t

P

I

AS

t

AV

V

DS

V

DD

t

ON

t

10%

d(ON)

90%

50%

t

10%

r

PULSE WIDTH

V

DS

V

DS

R

DUT

L

+

V

DD

-

0

V

GS

0

V

GS

R

GS

V

GS

FIGURE 14. SWITCHING TIME TEST CIRCUIT FIGURE 15. RESISTIVE SWITCHING WAVEFORMS

V

I

g(REF)

DS

R

L

V

GS

+

V

DD

-

DUT

V

DD

V

VGS= 2V

0

GS

Q

g(TH)

Q

V

DS

g(10)

Q

g(TOT)

VGS = 10V

t

d(OFF)

90%

t

OFF

50%

t

f

10%

VGS= 20V

90%

I

g(REF)

0

FIGURE 16. GATE CHARGE TEST CIRCUIT FIGURE 17. GATE CHARGE WAVEFORMS

4-466

RFG50N05, RFP50N05

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Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changesin circuit design and/or specifications at any time with­out notice . Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
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