Datasheet RF1S4N100SM, RFP4N100 Datasheet (Intersil)

Page 1
RFP4N100, RF1S4N100SM
Data Sheet August 1999 File Number
4.3A, 1000V, 3.500 Ohm, High Voltage, N-Channel Power MOSFETs
The RFP4N100 and RFP4N100SM are N-Channel enhancement mode silicon gate power field effect transistors. They are designed for use in applications such as switching regulators, switching converters, motor drivers, relay drivers, and drivers for high power bipolar switching transistors requiring high speed and low gate drive power. This type can be operated directly from an integrated circuit.
Formerly developmental type TA09850.
Ordering Information
PART NUMBER PACKAGE BRAND
RFP4N100 TO-220AB RFP4N100 RF1S4N100SM TO-263AB F1S4N100
NOTE: When ordering, use the entire part number.
Features
• 4.3A, 1000V
DS(ON)
= 3.500
•r
• UIS Rating Curve (Single Pulse)
o
C to 150oC Operating Temperature
• -55
• Related Literature
- TB334 “Guidelines for Soldering Surface Mount Components to PC Boards”
Symbol
D
G
S
2457.4
Packaging
DRAIN (FLANGE)
JEDEC TO-220AB JEDEC TO-263AB
SOURCE
DRAIN
GATE
GATE
SOURCE
DRAIN
(FLANGE)
4-528
CAUTION: These devices are sensitive to electrostatic discharge; follow properS ESD Handling Procedures.
http://www.intersil.com or 407-727-9207
| Copyright © Intersil Corporation 1999
Page 2
RFP4N100, RF1S4N100SM
Absolute Maximum Ratings T
= 25oC, Unless Otherwise Specified
C
RFP4N100,
RF1S4N100SM UNITS
Drain to Source Breakdown Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V
Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
DGR
Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V
Single Pulse Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .E
DS
DM
GS AS
D
(See UIS SOA Curve)
1000 V 1000 V
4.3 A 17 A
±20 V
mJ
(Figures 4, 14, 15)
Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .P
D
Linear Derating Factor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TJ, T
STG
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from case for 10s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
Package Body for 10s, see Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationofthe device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
L
pkg
150
1.2
-55 to 150
300 260
W
W/oC
o
C
o
C
o
C
NOTE:
1. TJ= 25oC to 125oC.
Electrical Specifications T
= 25oC, Unless Otherwise Specified
C
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Drain to Source Breakdown Voltage BV Gate Threshold Voltage V Zero Gate Voltage Drain Current I
Gate to Source Leakage Current I Drain to Source On Resistance (Note 2) r Turn-On Delay Time t Rise Time t Turn-Off Delay Time t Fall Time t Total Gate Charge
Q
(Gate to Source + Gate to Drain) Thermal Resistance Junction to Case R Thermal Resistance Junction to Ambient R
Source to Drain Diode Specifications
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
DSSID
GS(TH)VGS
DSS
VDS = 1000V, VGS = 0V - - 25 µA VDS = 800V, VGS = 0V, TC = 150oC - - 100 µA
GSS
DS(ON)ID
d(ON)
VGS = ±20V - - ±100 nA
VDD = 500V, I RL = 120)
r
d(OFF)
f
g(TOT)VGS
(Figure 13)
θJC
θJA
= 250µA, VGS = 0V (Figure 10) 1000 - - V
= VDS, ID = 250µA2-4V
= 2.5A, VGS = 10V (Figures 8, 9) - - 3.500
3.9A, R
D
GS
= 9.1Ω,
--30ns
--50ns
- - 170 ns
--50ns
= 20V, ID = 3.9A, VDS = 800V
- - 120 nC
- - 0.83
o
C/W
--62oC/W
Source to Drain Diode Voltage V Reverse Recovery Time t
SD
ISD = 4.3A - - 1.8 V ISD = 3.9A, dISD/dt = 100A/µs - - 1000 ns
rr
NOTES:
2. Pulse test: pulse width 80µs, duty cycle 2%.
3. Repetitive rating: pulse width limited by maximum junction temperature.
4-529
Page 3
RFP4N100, RF1S4N100SM
Typical Performance Curves
1.2
1.0
0.8
0.6
0.4
0.2
POWER DISSIPATION MULTIPLIER
0.0 0 25 50 75 100 150
TA, AMBIENT TEMPERATURE (oC)
TC = 25oC, Unless Otherwise Specified
125
FIGURE 1. NORMALIZED POWERDISSIPATION vs AMBIENT
TEMPERATURE
100
RFP4N100, RF1S4N100SM
10
100µs
10µs
4.5
4.0
3.5
3.0
2.5
2.0
1.5
, DRAIN CURRENT (A)
D
I
1.0
0.5 0
25 50 75 100 125 150
T
, CASE TEMPERATURE (oC)
C
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
100
IF R = 0 t
= (L)(Ias) / (1.3 x RATED BV
av
IF R 0
= (L/R) In ((Ias x R) / (1.3 x RATED BV
t
av
DSS
- VDD)
- VDD) + 1)
DSS
1
OPERATION IN THIS
, DRAIN CURRENT (A)
D
I
0.1
TC = 25oC T
= MAX RATED
J
SINGLE PULSE
0.01
110
AREA MAY BE LIMITED BY r
DS(ON)
, DRAIN TO SOURCE VOLTAGE (V)
V
DS
1ms
10ms
DC
100 1000
Idm
10
, AVALANCHECURRENT (A)
AS
I
1
0.01 0.10 1 10 tAV, TIME IN AVALANCHE (ms)
STARTING TJ = 25oC STARTING T
= 150oC
J
FIGURE 3. FORWARD BIAS SAFE OPERATING AREA FIGURE 4. UNCLAMPED INDUCTIVE SWITCHING SOA
10
VGS = 10V
8
6
4
, DRAIN CURRENT (A)
D
I
2
0
0 100 200 300 400 500
PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX
V
, DRAIN TO SOURCE VOLTAGE (V)
DS
VGS = 6V
VGS = 5V
VGS = 4V
10
PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX
8
6
4
, DRAIN CURRENT (A)
D
I
2
0
0 1020304050
VDS, DRAIN TO SOURCE VOLTAGE (V)
VGS = 10V
VGS = 6V
VGS = 5V
VGS = 4V
FIGURE 5. OUTPUT CHARACTERISTICS FIGURE 6. SATURATION CHARACTERISTICS
4-530
Page 4
RFP4N100, RF1S4N100SM
Typical Performance Curves
5
PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX
= 15V
V
DS
4
3
2
150oC 25oC
1
, DRAIN TO SOURCE CURRENT (A)
DS(ON)
I
0
02 46 8
, GATE TO SOURCE VOLTAGE (V)
V
GS
TC = 25oC, Unless Otherwise Specified (Continued)
FIGURE 7. TRANSFER CHARACTERISTICS FIGURE 8. DRAIN TOSOURCEON RESISTANCE vs DRAIN
3.0 VGS = 10V, ID = 4.3A
PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX
2.5
6
VGS = 10V PULSE DURATION = 80µs
5
DUTY CYCLE = 0.5% MAX
4
3
, DRAIN TO SOURCE
2
ON RESISTANCE ()
DS(ON)
r
1
0
024681012
I
, DRAIN CURRENT (A)
D
CURRENT
1.3 ID = 250µA
1.2
2.0
1.5
ON RESISTANCE
1.0
NORMALIZED DRAIN TO SOURCE
0.5
-50 0 50 , JUNCTION TEMPERATURE (oC)
T
J
100
FIGURE 9. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
3000
2500
C
2000
1500
1000
C, CAPACITANCE (pF)
500
0
1 10 100
ISS
C
OSS
C
RSS
VDS, DRAIN TO SOURCE VOLTAGE (V)
VGS = 0V, f = 1MHz
= CGS + C
C
ISS
C
= C
RSS
C
OSS
GD
CDS + C
GD
GD
150
1.1
1.0
BREAKDOWN VOLTAGE
0.9
NORMALIZED DRAIN TO SOURCE
0.8
-40 0 40 , JUNCTION TEMPERATURE (oC)
T
J
80
120
160
FIGURE 10. NORMALIZED DRAIN TO SOURCEBREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
100
10
1
, SOURCE TO DRAIN CURRENT (A)
D
I
0.1 0 0.3 0.6 0.9 1.2
V
TJ = 150oC
, SOURCE TO DRAIN VOLTAGE (V)
SD
TJ = 25oC
1.5
FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE FIGURE 12. DRAIN CURRENT vs SOURCE TO DRAIN DIODE
VOLTAGE
4-531
Page 5
RFP4N100, RF1S4N100SM
Typical Performance Curves
16
12
, GATE TO SOURCE VOLTAGE (V)
GS
V
FIGURE 13. GATE TO SOURCE VOLTAGE vs GATE CHARGE
Test Circuits and Waveforms
VARY t
TO OBTAIN
P
REQUIRED PEAK I
V
GS
AS
R
G
TC = 25oC, Unless Otherwise Specified (Continued)
ID = 3.9A
V
= 100V
DS
VDS = 200V VDS = 400V
8
4
0
0 20406080
V
DS
L
DUT
, TOTAL GATE CHARGE (nC)
Q
g
+
V
DD
-
t
P
I
AS
BV
DSS
V
DS
V
DD
0V
P
I
AS
0.01
0
t
AV
t
FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 15. UNCLAMPED ENERGY WAVEFORMS
t
ON
t
d(ON)
t
R
L
+
V
R
G
DUT
V
GS
DD
-
V
DS
0
V
GS
0
90%
10%
r
10%
50%
PULSE WIDTH
t
d(OFF)
90%
FIGURE 16. SWITCHING TIME TEST CIRCUIT FIGURE 17. RESISTIVE SWITCHING WAVEFORMS
t
OFF
50%
t
f
90%
10%
4-532
Page 6
RFP4N100, RF1S4N100SM
Test Circuits and Waveforms
V
DS
V
GS
I
g(REF)
FIGURE 18. GATE CHARGE TEST CIRCUIT FIGURE 19. GATE CHARGE WAVEFORMS
(Continued)
R
L
DUT
V
DD
+
V
DD
-
VGS= 2V
0
I
g(REF)
0
V
GS
Q
g(TH)
Q
V
DS
g(10)
Q
g(TOT)
VGS= 20V
VGS = 10V
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Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with­out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or otherrights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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4-533
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