Datasheet RF1S42N03LSM, RFP42N03L Datasheet (Intersil)

RFP42N03L, RF1S42N03LSM

Data Sheet July 1999 File Number

42A, 30V, 0.025 Ohm, Logic Level, N-Channel Power MOSFET

These are N-Channel power MOSFETs manufacturedusing the MegaFET process. This process, which uses feature sizes approaching those of LSI circuits, gives optimum utilization of silicon, resulting in outstanding performance. They were designed for use in applications such as switchingregulators,switchingconverters, motor drivers and relaydrivers. These transistors can be operated directly from integrated circuits.

Formerly developmental type TA49030.

Ordering Information

PART NUMBER PACKAGE BRAND

RFP42N03L TO-220AB FP42N03L RF1S42N03LSM TO-263AB F42N03L

NOTE: When ordering, use the entire part number .Add the suffix, 9A, to obtain the TO-263AB variant in tape and reel, e.g., RF1S42N03LSM9A.

4302.2

Features

• 42A, 30V

•r

DS(ON)

• Temperature Compensating PSPICE

= 0.025Ω

®

Model

• Can be Driven Directly from CMOS, NMOS, and TTL Circuits

• Peak Current vs Pulse Width Curve

• UIS Rating Curve

o

C Operating Temperature

• 175

• Related Literature

- TB334 “Guidelines for Soldering Surface Mount

Components to PC Boards”

Symbol

D

Packaging

DRAIN (FLANGE)

G

S

JEDEC TO-220AB JEDEC TO-263AB

SOURCE

DRAIN

GATE

SOURCE

DRAIN

(FLANGE)

6-267

CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.

PSPICE® is a registered trademark of MicroSim Corporation.

http://www.intersil.com or 407-727-9207

RFP42N03L, RF1S42N03LSM

Absolute Maximum Ratings T

= 25oC, Unless Otherwise Speciﬁed

C

RFP42N03L, RF1S42N03LSM UNITS

Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V

Drain to Gate Voltage (RGS= 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . V

Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V

Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I

Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I

Pulsed Avalanche Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .P

DSS

DGR

GS

DM

AS

D

Refer to Peak Current Curve

D

Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, T

STG

Maximum Temperature for Soldering

Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . T

Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .T

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationofthe device at these or any other conditions above those indicated in the operational sections of this speciﬁcation is not implied.

L

pkg

30 V 30 V

±10 V

42

Refer to UIS Curve

90

0.606

-55 to 175

300 260

A

W

W/oC

o

C

o

C

o

C

NOTE:

1. TJ= 25oC to 150oC.

Electrical Speciﬁcations T

= 25oC, Unless Otherwise Speciﬁed

C

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Drain to Source Breakdown Voltage BV Gate to Source Threshold Voltage V

GS(TH)VGS

Zero Gate Voltage Drain Current I

Gate to Source Leakage Current I Drain to Source On Resistance (Note 2) r

DS(ON)ID

Turn-On Time t Turn-On Delay Time t

d(ON)

Rise Time t Turn-Off Delay Time t

d(OFF)

Fall Time t Turn-Off Time t Total Gate Charge Q

g(TOT)VGS

Gate Charge at 5V Q Threshold Gate Charge Q

Input Capacitance C Output Capacitance C Reverse Transfer Capacitance C Thermal Resistance Junction-to-Case R Thermal Resistance Junction-to-Ambient R

DSSID

DSS

GSS

ON

r

f

OFF

g(5)

g(TH)VGS

ISS OSS RSS

θJC

θJA

= 250µA, VGS = 0V 30 - - V

= VDS, ID = 250µA1-2V VDS = Rated BV VDS = 0.8 x Rated BV

, VGS = 0V - - 1 µA

DSS

, VGS = 0V, TC = 150oC- - 25 µA

DSS

VGS = ±10V - - ±100 nA

= 42A, VGS = 5V (Figure 11) - - 0.025 Ω

VDD = 15V, I VGS = 5V, RGS = 5Ω (Figures 10, 18, 19)

≈ 42A, R

D

= 0.357Ω,

L

- - 260 ns

-15- ns

- 160 - ns

-20- ns

- - 60 ns

= 0V to 10V VDD = 24V, I

VGS = 0V to 5V - 30 36 nC

= 0V to 1V - 1.5 1.8 nC

RL = 0.571Ω I

G(REF)

(Figures 15, 20, 21)

VDS = 25V, VGS = 0V, f = 1MHz (Figure 14)

D

= 0.6mA

≈ 42A,

-5060nC

- 1650 - pF

- 575 - pF

- 200 - pF

- - 1.65oC/W

--80oC/W

Source to Drain Diode Speciﬁcations

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Source to Drain Diode Voltage V

SD

Diode Reverse Recovery Time t

NOTES:

2. Pulse test: pulse width ≤ 300µs, duty cycle ≤ 2%.

3. Repetitive rating: pulse width limited by Max junction temperature. See Transient Thermal Impedance curve (Figure 3).

6-268

ISD = 42A - - 1.5 V ISD = 42A, dISD/dt = 100A/µs - - 125 ns

rr

RFP42N03L, RF1S42N03LSM

Typical Performance Curves

1.2

1.0

0.8

0.6

0.4

0.2

POWER DISSIPATION MULTIPLIER

0

0 25 50 75 100 175

TC, CASE TEMPERATURE (oC)

Unless Otherwise Speciﬁed

125

FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE

TEMPERATURE

2

1

150

50

40

30

20

, DRAIN CURRENT (A)

D

I

10

0

25 50 75 100 125 150

TC, CASE TEMPERATURE (oC)

FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs

CASE TEMPERATURE

175

0.1

, NORMALIZED

JC

θ

Z

THERMAL IMPEDANCE

0.01

500

TC = 25oC, TJ = 175oC

100

10

, DRAIN CURRENT (A)

D

I

OPERATION IN THIS AREA MAY BE LIMITED BY r

1

0.05

0.02

0.01

-5

10

VDS, DRAIN TO SOURCE VOLTAGE (V)

0.5

0.2

0.1

SINGLE PULSE

DS(ON)

NOTES: DUTY FACTOR: D = t

PEAK TJ = PDM x Z

-4

10

-3

10

t, RECTANGULAR PULSE DURATION (s)

-2

10

-1

10

FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE

500

VGS = 10V

VGS = 5V

100µs

1ms

10ms

100ms DC

10

50

100

TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION

, PEAK CURRENT CAPABILITY (A)

DM

I

10

-5

10

-4

10

-3

10

t, PULSE WIDTH (s)

P

DM

t

1

t

2

1/t2

x R

JC

θ

0

10

FOR TEMPERATURES ABOVE 25 CURRENT AS FOLLOWS:

-2

10

I = I

o

C DERATE PEAK

175 - T

25

150

-1

10

+ T

C

TC = 25oC

0

10

1

10

1

10

FIGURE 4. FORWARD BIAS SAFE OPERATING AREA FIGURE 5. PEAK CURRENT CAPABILITY

6-269

RFP42N03L, RF1S42N03LSM

Typical Performance Curves

200

100

STARTING TJ = 150oC

10

If R = 0

, AVALANCHE CURRENT (A)

tAV = (L)(IAS)/(1.3*RATED BV

AS

I

If R ≠ 0 t

= (L/R)ln[(IAS*R)/(1.3*RATED BV

AV

1

0.001

0.01 0.1 10 tAV, TIME IN AVALANCHE (ms)

DSS

Unless Otherwise Speciﬁed (Continued)

STARTING TJ = 25oC

- VDD)

) +1]

DSS-VDD

1 100

NOTE: Refer to Intersil Application Notes AN9321 and AN9322.

FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING

100

75

50

= 15V

V

DD

PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX

-55oC

25oC

175

o

C

100

= 10V

V

GS

75

PULSE DURATION = 80µs

50

, DRAIN CURRENT (A)

D

25

I

0

0123 5

VDS, DRAIN TO SOURCE VOLTAGE (V)

DUTY CYCLE = 0.5% MAX TC = 25oC

VGS = 5V

V

GS

V

GS

V

GS

VGS = 3V

4

= 4.5V

= 4V = 3.5V

FIGURE 7. SATURATION CHARACTERISTICS

100

75

50

ID = 15A

ID = 30A

ID = 42A

25

, DRAIN TO SOURCE CURRENT (A)

DS(ON)

I

0

0 3.0 4.5 6.0 7.51.5

VGS, GATE TO SOURCE VOLTAGE (V)

FIGURE 8. TRANSFER CHARACTERISTICS FIGURE 9. DRAIN TOSOURCE ON RESISTANCEvs GATE

350

VDD = 15V, ID = 42A, RL = 0.357Ω

300

250

200

150

100

SWITCHING TIME (ns)

50

0

010203040

RGS, GATE TO SOURCE RESISTANCE (Ω)

t

r

t

f

t

d(OFF)

t

d(ON)

, DRAIN TO SOURCE

ON RESISTANCE (mΩ)

25

DS(ON)

r

ID = 2A

PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX

0

2.5

3.0 3.5 4.0 4.5 VGS, GATE TO SOURCE VOLTAGE (V)

5.0

VOLTAGE AND DRAIN CURRENT

2.0

PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX VGS = 5V, ID = 42A

1.5

1.0

ON RESISTANCE

0.5

NORMALIZED DRAIN TO SOURCE

0

50

-80 -40 0 40 80 120 160 TJ, JUNCTION TEMPERATURE (oC)

200

FIGURE 10. SWITCHING TIME vs GATE RESISTANCE FIGURE 11. NORMALIZED DRAIN TOSOURCE ON

RESISTANCE vs JUNCTION TEMPERATURE

6-270

RFP42N03L, RF1S42N03LSM

Typical Performance Curves

2.0 VGS = VDS, ID = 250µA

1.5

1.0

NORMALIZED GATE

0.5

THRESHOLD VOLTAGE

0

-80 -40 0 40 80 120 160 TJ, JUNCTION TEMPERATURE (oC)

Unless Otherwise Speciﬁed (Continued)

FIGURE 12. NORMALIZED GATE THRESHOLD VOLTAGE vs

JUNCTION TEMPERATURE

2500

2000

1500

1000

C, CAPACITANCE (pF)

500

0

0 5 10 15 20 25

V

, DRAIN TO SOURCE VOLTAGE (V)

DS

C

ISS

OSS

RSS

VGS = 0V, f = 0.1MHz

= CGS + C

C

ISS

C

= C

RSS

C

OSS

GD

≈ CDS + C

GD

FIGURE 14. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE

200

2.0 ID = 250µA

1.5

1.0

0.5

BREAKDOWN VOLTAGE

NORMALIZED DRAIN TO SOURCE

0

-80 -40 0 40 80 120 160 , JUNCTION TEMPERATURE (oC)

T

J

FIGURE 13. NORMALIZED DRAIN TO SOURCE BREAKDOWN

VOLTAGE vs JUNCTION TEMPERATURE

30

24

18

12

6

, DRAIN TO SOURCE VOLTAGE (V)

DS

V

0

V

= BV

DD

I

G REF()

--------------------- -

20

I

GACT()

DSS

0.75 BV

0.50 BV

0.25 BV

RL = 0.714Ω

= 0.6mA

I

G(REF)

= 5V

V

GS

t, TIME (µs)

DSS DSS DSS

VDD = BV

I

G REF()

--------------------- -

80

I

G ACT()

DSS

4

3

2

NOTE: Refer to Intersil Application Notes AN7254 and AN7260.

FIGURE 15. NORMALIZED SWITCHING WAVEFORMS FOR

CONSTANT GATE CURRENT

200

5

1

, GATE TO SOURCE VOLTAGE (V)

GS

V

0

Test Circuits and Waveforms

V

DS

BV

DSS

L

VARY t

TO OBTAIN

P

REQUIRED PEAK I

V

GS

t

0V

P

AS

R

G

DUT

I

AS

0.01Ω

+

V

DD

-

0

FIGURE 16. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 17. UNCLAMPED ENERGY WAVEFORMS

6-271

t

P

I

AS

t

AV

V

DS

V

DD

RFP42N03L, RF1S42N03LSM

Test Circuits and Waveforms

V

GS

R

GS

V

GS

FIGURE 18. SWITCHING TIME TEST CIRCUIT

V

DS

V

GS

I

g(REF)

(Continued)

DS

R

L

DUT

R

L

DUT

t

ON

t

d(ON)

t

V

DS

+

V

DD

-

0

V

GS

10%

0

r

90%

10%

50%

PULSE WIDTH

t

d(OFF)

90%

t

OFF

50%

t

f

90%

10%

FIGURE 19. RESISTIVE SWITCHING WAVEFORMS

V

DD

+

V

DD

-

V

GS

VGS= 1V

0

Q

g(TH)

V

g(5)

DS

Q

g(TOT)

VGS= 10V

VGS= 5V

FIGURE 20. GATE CHARGE TEST CIRCUIT

6-272

I

G(REF)

0

FIGURE 21. GATE CHARGE WAVEFORMS

RFP42N03L, RF1S42N03LSM

PSPICE Electrical Model

.SUBCKT RFP42N03L 2 1 3 ; rev 12/24/96

CA 12 8 2.55e-9 CB 15 14 2.64e-9 CIN 6 8 1.45e-9

DBODY 7 5 DBDMOD DBREAK 5 11 DBKMOD DPLCAP 10 5 DPLCAPMOD

EBREAK 11 7 17 18 33.3 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 6 10 6 8 1 EVTO 20 6 18 8 1

IT 8 17 1

LDRAIN 2 5 1e-9 LGATE 1 9 4.9e-9 LSOURCE 3 7 4.9e-9

MOS1 16 6 8 8 MOSMOD M = 0.99 MOS2 16 21 8 8 MOSMOD M = 0.01

RBREAK 17 18 RBKMOD 1 RDRAIN 50 16 RDSMOD 0.14e-3 RGATE 9 20 0.89 RLDRAIN 2 5 10 RLGATE 1 9 49 RLSOURCE 3 7 49 RSCL1 5 51 RSCLMOD 1e-6 RSCL2 5 50 1e3 RSOURCE 8 7 RDSMOD 10.31e-3 RVTO 18 19 RVTOMOD 1

GATE

1

LGATE

RLGATE

9

RGATE

-

LSOURCE

7

RLSOURCE

IT

LDRAIN

RLDRAIN

DBODY

18

RVTO

19

VBAT

+

2

DRAIN

3

SOURCE

DPLCAP

10

-

6

ESG

8

+

VTO

EVTO

20

+

-

18

8

S1A

12

13814

S1B

CA

EGS

-

6

S2A

15

13

S2B

13

+

6

EDS

8

+

CIN

CB

5

RSCL1RSCL2

51

+

5

ESCL

51

50 RDRAIN

16

21

MOS1

14

+

5 8

--

8

DBREAK

EBREAK

MOS2

RSOURCE

11

17

+

17 18

RBREAK

S1A 6 12 13 8 S1AMOD S1B 13 12 13 8 S1BMOD S2A 6 15 14 13 S2AMOD S2B 13 15 14 13 S2BMOD

VBAT 8 19 DC 1 VTO 21 6 0.583

ESCL 51 50 VALUE = {(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)*1e6/176,6))}

.MODEL DBDMOD D (IS = 3.61e-13 RS = 5.06e-3 TRS1 = 3.05e-3 TRS2 = 7.57e-6 CJO = 2.16e-9 TT = 2.18e-8) .MODEL DBKMOD D (RS = 1.66e-1 TRS1 = -2.97e-3 TRS2 = 7.57e-6) .MODEL DPLCAPMOD D (CJO = 0.96e-9 IS = 1e-30 N = 10) .MODEL MOSMOD NMOS (VTO = 2.313 KP = 53.82 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u) .MODEL RBKMOD RES (TC1 = 8.95e-4 TC2 = -1e-7) .MODEL RDSMOD RES (TC1 = 3.82e-3 TC2 = 1.17e-5) .MODEL RSCLMOD RES (TC1 = 2.03e-3 TC2 = 0.45e-5) .MODEL RVTOMOD RES (TC1 = -2.27e-3 TC2 = -5.75e-7) .MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -4.82 VOFF= -2.82) .MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -2.82 VOFF= -4.82) .MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -2.67 VOFF= 2.33) .MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 2.33 VOFF= -2.67)

.ENDS

NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; written by William J. Hepp and C. Frank Wheatley.

6-273

RFP42N03L, RF1S42N03LSM

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Intersil semiconductor products are sold by description only.Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

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6-274

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