Datasheet RFP25N05L Datasheet (Intersil)

RFP25N05L

Data Sheet July 1999

25A, 50V, 0.047 Ohm, Logic Level,
N-Channel Power MOSFET

The RFP25N05L is an N-Channel logic level power
MOSFETs are manufactured using the MegaFET process.
This process, which uses featuresizesapproachingthoseof
LSI integrated circuits gives optimum utilization of silicon,
resulting in outstanding performance. The RFP25N05L was
designed for use with logic level (5V) driving sources in
applications such as programmable controllers, automotive
switching, switching regulators, switching converters, motor
relaydriversandemitter switches for bipolar transistors. This
performance is accomplished through a special gate oxide
design which provides full rated conductance at gate biases
in the 3V to 5V range, thereby facilitating true on-off power
control directly from logic circuit supply voltages.

Formerly developmental type TA09871.

Ordering Information

PART NUMBER PACKAGE BRAND

RFP25N05L TO-220AB RFP25N05L

NOTE: When ordering, include the entire part number.

File Number

2270.3

Features

• 25A, 50V

•r

• UIS SOA Rating Curve (Single Pulse)

• Design Optimized for 5V Gate Drives

• Can be Driven Directly from CMOS, NMOS, TTL Circuits

• Compatible with Automotive Drive Requirements

• SOA is Power Dissipation Limited

• Nanosecond Switching Speeds

• Linear Transfer Characteristics

• High Input Impedance

• Majority Carrier Device

• Related Literature

- TB334 “Guidelines for Soldering Surface Mount

= 0.047Ω

DS(ON)

Components to PC Boards”

Symbol

D

Packaging

G

S

JEDEC TO-220AB

SOURCE

DRAIN

GATE

DRAIN (FLANGE)

6-243

CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.

http://www.intersil.com or 407-727-9207

| Copyright © Intersil Corporation 1999

RFP25N05L

Absolute Maximum Ratings T

= 25oC, Unless Otherwise Specified

C

RFP25N05L UNITS

Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V

Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V

DGR

Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I

Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I

DS

D

DM

50 V
50 V
25 A

65 A

Single Pulse Avalanche Energy Rating (See Figures 4, 15, and 16). . . . . . . . . . . . . . . . . . . . . . Refer to UIS SOA Curve

Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V

Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P

GS

D

±10 V

60 W

Linear Derating Factor above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.48 W/oC

Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, T

STG

-55 to 150

Maximum Temperature for Soldering

Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T

Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .T

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationofthe
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

L

pkg

300
260

o

C

o

C

o

C

NOTE:

1. TJ = 25oC to 125oC.

Electrical Specifications T

= 25oC, Unless Otherwise Specified

C

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Drain to Source Breakdown Voltage BV
Gate to Threshold Voltage V
Gate to Source Leakage I
Zero Gate Voltage Drain Current I

DSS

GS(TH)

GSS
DSS

VGS = 0V, ID = 250µA (Figure 10) 50 - - V
VGS = VDS, ID = 250µA (Figure 9) 1.0 - 2.0 V
VGS = ±10V, VDS = 0V - - ±100 nA
VDS = 40V, VGS = 0V - - 1.0 µA
TC = 150oC--50µA

Drain to Source On Resistance (Note 2) r

DS(ON)

VGS = 5V, ID = 25A (Figures 7, 8) - - 0.047 Ω

VGS = 4V, ID = 25A - - 0.056 Ω
Turn-On Time t
Turn-On Delay Time t

d(ON)

Rise Time t
Turn-Off Delay Time t

d(OFF)

Fall Time t
Turn-Off Time t
Total Gate Charge

(OFF)

Q

g(TOT)

(Gate to Source + Gate to Drain)
Gate Charge at 5V Q
Threshold Gate Charge Q
Thermal Resistance Junction to Case R
Thermal Resistance Junction to Ambient R

(ON)

g(5)

g(TH)

θJC
θJA

VDD = 25V, ID =12.5A

RL = 2Ω, RGS = 5Ω

(Figures 15, 16)

r

- - 60 ns

-15- ns

-35- ns

-40- ns

f

-14- ns

- - 100 ns

VGS = 0 - 10V VDD = 40V, ID = 25A,

- - 80 nC

RL = 1.6Ω

VGS = 0 - 5V - - 45 nC

(Figures 17, 18)

VGS = 0 - 1V - - 3.0 nC

- - 2.083oC/W

--80oC/W

Source to Drain Diode Specifications

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Source to Drain Diode Voltage V
Diode Reverse Recovery Time t

SD

rr

NOTES:

2. Pulse Test: Pulse width ≤ 80µs, duty cycle ≤ 2%.

3. Repetitive Rating: Pulse width limited by Max junction temperature.

6-244

ISD= 25A - - 1.5 V
ISD = 25A, dISD/dt = 100A/µs - - 125 ns

RFP25N05L

Typical Performance Curves

1.2

1.0

0.8

0.6

0.4

0.2

POWER DISSIPATION MULTIPLIER

0

0 50 100 150

TC, CASE TEMPERATURE (oC)

Unless Otherwise Specified

FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE

TEMPERATURE

2

10

ID MAX CONTINUOUS

TJ = MAX RATED, TC = 25oC

30

20

10

, DRAIN CURRENT (A)

D

I

0

25 50 75 100 150

T

, CASE TEMPERATURE (oC)

C

125

FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs

CASE TEMPERATURE

2

10

Idm

10

OPERATION IN THIS AREA
LIMITED BY r

1

, DRAIN CURRENT (A)

D

I

0.1
1

DS(ON)

VDS, DRAIN TO SOURCE VOLTAGE (V)

V

DSS

10

(MAX) = 50V

DC

10

, AVALANCHE CURRENT (A)

AS

I

2

10

STARTING TJ = 150oC

If R = 0
tAV = (L)(IAS)/(1.3 RATED BV

If R ≠ 0

= (L/R)ln[(IAS*R)/(1.3 RATED BV

t

AV

1

tAV, TIME IN AVALANCHE (ms)

STARTING TJ = 25oC

- VDD)

DSS

- VDD) +1]

DSS

1100.01 0.10

FIGURE 3. FORWARD BIAS SAFE OPERATING AREA FIGURE 4. UNCLAMPED INDUCTIVE SWITCHING SOA

(SINGLE PULSE UIS SOA)

65

55

45

35

25

15

, DRAIN TO SOURCE CURRENT (A)

DS

5

I

0 3.0 4.5 7.51.5

V

DS,

10V

5.0V

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX

DRAIN TO SOURCE VOLTAGE (V)

6.0

TC= 25oC

VGS = 4.0V

3.0V

2.0V

65

VDS = 15V
PULSE DURATION = 80µs

55

DUTY CYCLE = 0.5% MAX

45

35

25

15

, DRAIN TO SOURCE CURRENT (A)

5

DS(ON)

I

0 3.0 4.5 7.51.5

VGS, GATE TO SOURCE VOLTAGE (V)

6.0

FIGURE 5. SATURATION CHARACTERISTICS FIGURE 6. TRANSFER CHARACTERISTICS

6-245

RFP25N05L

Typical Performance Curves

1.4

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX

1.3
ID = 25A

1.2

1.1

1.0

0.9

0.8

ON RESISTANCE

0.7

NORMALIZED DRAIN TO SOURCE

0.6

0.5

547

VGS, GATE TO SOURCE VOLTAGE (V)

Unless Otherwise Specified (Continued)

6

FIGURE 7. DRAIN TO SOURCE ON RESISTANCEvs GATE

VOLTAGE AND DRAIN CURRENT

1.4

ID = 250µA

V

GS

= V

DS

1.3

1.2

1.1

1.0

0.9

2.5
ID = 25A, VGS = 5V

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX

2.0

1.5

1.0

ON RESISTANCE

0.5

NORMALIZED DRAIN TO SOURCE

0

-50

0 50 150 200

T

, JUNCTION TEMPERATURE (oC)

J

100

FIGURE 8. NORMALIZED DRAIN TO SOURCE ON

RESISTANCE vs JUNCTION TEMPERATURE

1.4
ID = 250µA

1.2

1.0

0.8

0.8

THRESHOLD VOLTAGE

NORMALIZED GATE TO

0.7

0.6

-50

0 200

T

J

50 100 150

, JUNCTION TEMPERATURE (oC)

FIGURE 9. NORMALIZED GATETOTHRESHOLD vs

JUNCTION TEMPERATURE

2000

1600

1200

800

C, CAPACITANCE (pF)

400

0

0 10152025

5

V

DRAIN TO SOURCE VOLTAGE (V)

DS,

VGS = 0V, f = 1MHz

= CGS + C

C

ISS

C

= C

RSS
OSS

GD

≈ CDS + C

C

ISS

C

OSS

C

RSS

C

FIGURE 11. CAPACITANCE vs VOLTAGE

GD

GD

BREAKDOWN VOLTAGE

0.6

NORMALIZED DRAIN TO SOURCE

0

0 150

T

J

50-50

, JUNCTION TEMPERATURE (oC)

100 200

FIGURE 10. NORMALIZED DRAIN TO SOURCE BREAKDOWN

VOLTAGE vs JUNCTION TEMPERATURE

50

37.5

25

12.5

, DRAIN TO SOURCE VOLTAGE (V)

DS

V

VDD = BV

0

20

RL = 2Ω, VGS = 5V

I

= 0.60mA

G(REF)

PLATEAU VOLTAGES IN
DESCENDING ORDER:

VDD = BV
VDD = 0.75 BV

DSS

VDD = 0.50 BV
VDD = 0.25 BV

DRAIN SOURCE VOLTAGE

I

GREF()

------------------------ ­I

GACT()

DSS

GATE

SOURCE

VOLTAGE

t, TIME (µs)

DSS
DSS
DSS

VDD = BV

I

G REF()

80

------------------------ ­I

G ACT()

DSS

NOTE: Refer to Intersil Application Notes AN7254 and AN7260

FIGURE 12. NORMALIZED SWITCHING WAVEFORMSFOR

CONSTANT GATE CURRENT

10

8

6

4

2

, GATE TO SOURCE VOLTAGE (V)

GS

V

0

6-246

RFP25N05L

Test Circuits and Waveforms

V

DS

BV

DSS

L

VARY t

TO OBTAIN

P

REQUIRED PEAK I

V

GS

AS

R

G

+

V

DD

-

DUT

0V

P

I

AS

0.01Ω

0

t

FIGURE 13. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 14. UNCLAMPED ENERGY WAVEFORMS

t

P

I

AS

t

AV

V

DS

V

DD

t

ON

t

10%

d(ON)

90%

50%

10%

t

r

PULSE WIDTH

V

DS

V

DS

R

DUT

L

+

V

DD

-

0

V

GS

0

V

GS

R

GS

V

GS

FIGURE 15. SWITCHING TIME TEST CIRCUIT FIGURE 16. RESISTIVE SWITCHING WAVEFORMS

V

DS

12V

BATTERY

0

0.2µF

I

g(REF)

CURRENT

REGULATOR

50kΩ

0.3µF

G

IG CURRENT

SAMPLING

RESISTOR RESISTOR

SAME TYPE
AS DUT

D

DUT

S

CURRENT

I

D

SAMPLING

(ISOLATED
SUPPLY)

V

DS

V

DD

Q

g(TOT)

Q

gd

Q

gs

V

DS

0

I

g(REF)

0

t

d(OFF)

90%

V

GS

t

OFF

50%

t

f

90%

10%

FIGURE 17. GATE CHARGE TEST CIRCUIT FIGURE 18. GATE CHARGE WAVEFORMS

6-247

RFP25N05L

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Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with­out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
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