Datasheet RFP25N05 Datasheet (Intersil)

RFP25N05

Data Sheet July 1999 File Number

25A, 50V, 0.047 Ohm, N-Channel Power
MOSFET

The RFP25N05 N-channel power MOSFET is manufactured
using the MegaFET process. This process which uses
feature sizes approaching those of LSI integrated circuits,
gives optimum utilization of silicon, resulting in outstanding
performance. It wasdesignedfor use in applications such as
switching regulators, switching converters, motor drivers,
and relay drivers. This transistor can be operated directly
from integrated circuits.

Formerly developmental type TA09771.

Ordering Information

PART NUMBER PACKAGE BRAND

RFP25N05 TO-220AB RFP25N05

NOTE: When ordering use the entire part number.

Features

• 25A, 50V

DS(ON)

= 0.047Ω

®

Model

•r

• Temperature Compensating PSPICE

• Peak Current vs Pulse Width Curve

• UIS Rating Curve

o

C Operating Temperature

• 175

• Related Literature

- TB334 “Guidelines for Soldering Surface Mount
Components to PC Boards”

Symbol

D

G

2112.4

Packaging

DRAIN

(FLANGE)

JEDEC TO-220AB

SOURCE

DRAIN

GATE

S

4-504

CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.

PSPICE® is a registered trademark of MicroSim Corporation.

http://www.intersil.com or 407-727-9207

| Copyright © Intersil Corporation 1999

RFP25N05

Absolute Maximum Ratings T

= 25oC, Unless Otherwise Specified

C

RFP25N05 UNITS

Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

Drain to Gate Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I

Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I

Pulsed Avalanche Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E

Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P

DSS

DGR

GS

DM

AS

D

Refer to Peak Current Curve A

D

Linear Derating Factor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.48 W/oC

Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ,T

STG

Maximum Temperature for Soldering

Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .T

Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationofthe
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

L

pkg

50 V
50 V

±20 V

25 A

Refer to UIS Curve

72 W

-55 to 175

300
260

o

C

o

C

o

C

NOTE:

1. TJ= 25oC to 150oC.

Electrical Specifications T

= 25oC, Unless Otherwise Specified

C

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Drain to Source Breakdown Voltage BV
Gate Threshold Voltage V

GS(TH)VGS

Zero Gate Voltage Drain Current I

Gate to Source Leakage Current I
Drain to Source On Resistance r

DS(ON)ID

Turn-On Time t
Turn-On Delay Time t

d(ON)

Rise Time t
Turn-Off Delay Time t

d(OFF)

Fall Time t
Turn-Off Time t
Total Gate Charge Q

G(TOT)VGS

Gate Charge at 10V Q
Threshold Gate Charge Q
Input Capacitance C
Output Capacitance C
Reverse Transfer Capacitance C
Thermal Resistance Junction to Case R
Thermal Resistance Junction to Ambient R

DSSID

DSS

GSS

ON

r

f

OFF

G(10)
G(TH)VGS

ISS
OSS
RSS

θJC

θJA

= 250µA, VGS = 0V (Figure 11) 50 - - V

= VDS, ID = 250mA (Figure 10) 2 - 4 V
VDS = Rated BV
VDS = 0.8 x Rated BV

, VGS = 0V - - 1 µA

DSS

= 150oC- - 25µA

DSS,TC

VGS = ±20V - - ±100 nA

= 25A, VGS = 10V (Figure 9) - - 0.047 Ω

VDD = 25V, I
VGS = 10V, RG = 10Ω
(Figure 13)

≈ 12.5A, R

D

= 2.0Ω,

L

- - 60 ns

-14-ns

-30-ns

-45-ns

-22-ns

- - 100 ns

= 0V to 20V VDD = 40V,
VGS = 0V to 10V - - 45 nC

= 0V to 2V - - 3 nC

ID = 25A, RL = 1.6Ω
I

= 0.75mA

g(REF)

(Figure 13)

VDS = 25V, VGS = 0V,
f = 1MHz
(Figure 12)

- - 80 nC

- 1075 - pF

- 350 - pF

- 100 - pF

(Figure 3) - - 2.083

o

C/W

--80oC/W

Source to Drain Diode Specifications

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Source to Drain Diode Voltage (Note 2) V
Reverse Recovery Time t

SD

RR

NOTES:

2. Pulse test: pulse width ≤ 300µs, duty cycle ≤ 2%.

3. Repetitive rating: pulse width limited by maximum junction temperature. See Transient Thermal Impedance curve (Figure 3) and Peak Current
Capability Curve (Figure 5).

4-505

ISD = 25A - - 1.5 V
ISD = 25A, dISD/dt = 100A/µs - - 125 ns

Typical Performance Curves

RFP25N05

1.2

1.0

0.8

0.6

0.4

0.2

POWER DISSIPATION MULTIPLIER

0

0 25 50 75 100 175

125 150

TC, CASE TEMPERATURE (oC)

FIGURE 1. NORMALIZED POWERDISSIPATION vsCASE

TEMPERATURE

2

1

0.5

0.2

0.1

0.1

0.05

THERMAL IMPEDANCE

0.01
10

0.02

0.01

-5

SINGLE PULSE

10

-4

-3

10

t1, RECTANGULAR PULSE DURATION (s)

NORMALIZED TRANSIENT

θJC,

Z

30

25

20

15

10

, DRAIN CURRENT (A)

D

I

5

0

25 50 75 100 125 150

TC, CASE TEMPERATURE (oC)

FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs

CASE TEMPERATURE

P

DM

t

1

t

2

NOTES:
DUTY FACTOR: D = t
PEAK TJ = PDM x Z

-2

10

-1

10

10

1/t2

θJC

0

x R

θJC

+ T

175

A

1

10

FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE

200

100

10

OPERATION IN THIS
AREA MAY BE

, DRAIN CURRENT (A)

LIMITED BY r

D

I

1

1

VDS, DRAIN TO SOURCE VOLTAGE (V)

DS(ON)

TC = 25oC

T

= MAX RATED

J

SINGLE PULSE

100µs

1ms

10ms

100ms
DC

10 100

200

100

, PEAK CURRENT CAPABILITY (A)

DM

I

10

10

VGS = 20V

VGS = 10V

TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION

-5

-4

10

10

TC = 25oC
FOR TEMPERATURES

ABOVE 25
CURRENT AS FOLLOWS:

I = I

-3

-2

10

t, PULSE WIDTH (s)

o

C DERATE PEAK

25

-1

10

FIGURE 4. FORWARD BIAS SAFE OPERATING AREA FIGURE 5. PEAK CURRENT CAPABILITY

4-506

175 - T

150

10

C

0

1

10

RFP25N05

Typical Performance Curves

100

10

STARTING TJ = 150oC

If R = 0

, AVALANCHE CURRENT (A)

tAV = (L)(IAS)/(1.3*RATED BV

AS

I

If R ≠ 0
t

= (L/R)ln[(IAS*R)/(1.3*RATED BV

AV

1

0.01

0.1 1 10

tAV, TIME IN AVALANCHE (ms)

DSS

(Continued)

STARTING TJ = 25oC

- VDD)

) +1]

DSS-VDD

NOTE: Refer to Intersil Application Notes AN9321 and AN9322.

FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY

70

VDD= 15V
PULSE DURATION 80µs

60

DUTY CYCLE = 0.5% MAX

50

40

-55oC

25

o

C

175oC

70

V

= 20V

GS

60

50

40

30

20

, DRAIN CURRENT (A)

D

I

10

0

0

VDS, DRAIN TO SOURCE VOLTAGE (V)

VGS = 10V

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
TC = 25oC

V

= 4.5V

GS

2468

FIGURE 7. SATURATION CHARACTERISTICS

2.5

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VGS = 10V, ID = 25A

2

1.5

= 8V

V

GS

V

= 7V

GS

VGS = 6V

VGS = 5V

30

20

, DRAIN TO SOURCE CURRENT (A)

10

DS(ON)

I

0

0468102

VGS, GATE TO SOURCE VOLTAGE (V)

1

ON RESISTANCE

0.5

NORMALIZED DRAIN TO SOURCE

0

-80 -40 0 40 80 120 160
TJ, JUNCTION TEMPERATURE (oC)

FIGURE 8. TRANSFER CHARACTERISTICS FIGURE 9. NORMALIZED DRAIN TO SOURCE ON

RESISTANCE vs JUNCTION TEMPERATURE

2

VGS = V

DS

ID = 250µA

1.5

1

NORMALIZED GATE

0.5

THRESHOLD VOLTAGE

0

-80 -40 0 40 80 120 160
TJ, JUNCTION TEMPERATURE (oC)

200

2

ID = 250µA

1.5

1

0.5

BREAKDOWN VOLTAGE

NORMALIZED DRAIN TO SOURCE

0

-80 -40 0 40 80 120 160
T

, JUNCTION TEMPERATURE (oC)

J

200

200

FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGEvs

JUNCTION TEMPERATURE

4-507

FIGURE 11. NORMALIZED DRAIN TO SOURCEBREAKDOWN

VOLTAGE vs JUNCTION TEMPERATURE

RFP25N05

Typical Performance Curves

1600

1200

C

ISS

(Continued)

VGS = 0V, f = 1MHz

= CGS + C

C
C
C

ISS
RSS
OSS

= C

≈ CDS + C

GD

GD

800

C

OSS

C, CAPACITANCE (pF)

400

0

0 5 10 15 20 25

C

RSS

V

, DRAIN TO SOURCE VOLTAGE (V)

DS

FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE

Test Circuits and Waveforms

V

DS

L

VARY t

TO OBTAIN

P

REQUIRED PEAK I

V

GS

AS

R

G

DUT

+

-

V

GS

DD

50

37.5

25

12.5

, DRAIN TO SOURCE VOLTAGE (V)

DS

V

0

VDD = BV

DSS

0.75 BV

0.50 BV

0.25 BV

RL = 2.0Ω

= 0.75mA

I

G(REF)

= 10V

V

GS

IG (REF)

20 80

I

(ACT)

G

t, TIME (µs)

DSS
DSS
DSS

V

DD

= BV

IG (REF)
I

(ACT)

G

DSS

10

7.5

5.0

2.5

0

NOTE: Refer to Intersil Application Notes AN7254 and AN7260.

FIGURE 13. NORMALIZED SWITCHING WAVEFORMS FOR

CONSTANT GATE CURRENT

BV

DSS

t

P

I

AS

V

DS

V

DD

, GATE TO SOURCE VOLTAGE (V)

GS

V

0V

P

I

AS

0.01Ω

0

t

AV

t

FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 15. UNCLAMPED ENERGY WAVEFORMS

t

ON

t

d(ON)

t

R

L

+

V

R

G

DD

-

V

DS

90%

0

r

10%

DUT

V

GS

V

GS

10%

0

50%

PULSE WIDTH

t

d(OFF)

90%

FIGURE 16. SWITCHING TIME TEST CIRCUIT FIGURE 17. RESISTIVE SWITCHING WAVEFORMS

t

OFF

50%

t

f

90%

10%

4-508

RFP25N05

Test Circuits and Waveforms

V

DS

V

GS

I

g(REF)

FIGURE 18. GATE CHARGE TEST CIRCUIT FIGURE 19. GATE CHARGE WAVEFORM

(Continued)

R

L

DUT

V

DD

+

V

DD

­VGS= 2V

0

I

g(REF)

0

V

GS

Q

Q

g(TH)

V

DS

g(10)

Q

g(TOT)

VGS= 20V

VGS = 10V

4-509

PSPICE Electrical Model

.SUBCKT RFP25N05 2 1 3; rev 8/19/94

CA 12 8 1.83e-9
CB 15 14 1.98e-9
CIN 6 8 9.7e-10

DBODY 7 5 DBDMOD
DBREAK 5 11 DBKMOD
DPLCAP 10 5 DPLCAPMOD

EBREAK 11 7 17 18 65.9
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTO 20 6 18 8 1

IT 8 17 1

LDRAIN 2 5 1e-9
LGATE 1 9 4.92e-9
LSOURCE 3 7 4.5e-9

MOS1 16 6 8 8 MOSMOD M = 0.99
MOS2 16 21 8 8 MOSMOD M = 0.01

RBREAK 17 18 RBKMOD 1
RDRAIN 50 16 RDSMOD 1.1e-3
RGATE 9 20 2.88
RIN 6 8 1e9
RSCL1 5 51 RSCLMOD 1e-6
RSCL2 5 50 1e3
RSOURCE 8 7 RDSMOD 20.3e-3
RVTO 18 19 RVTOMOD 1

S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD

GATE

1

LGATE

RGATE

RFP25N05

ESG

EVTO

+

209

18

8

S1A S2A

12

13

8

CA

EGS EDS

10

DPLCAP

RSCL2

-

6
8

+

-

+

RIN

-

VTO

6

15

14
13

S2BS1B

13

6
8

CIN

CB

5

LDRAIN

RSCL1
51

+

5

ESCL

51

50
RDRAIN

16

+

21

MOS1

14

+

5
8

-

8

DBREAK

11

EBREAK
MOS2

RSOURCE

17 18

+

17
18

-

RBREAK

7

IT

DBODY

LSOURCE

RVTO

19

VBAT

+

DRAIN
2

3

SOURCE

VBAT 8 19 DC 1
VTO 21 6 0.764

ESCL 51 50 VALUE = {(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)*1e6/108,6))}

.MODEL DBDMOD D (IS = 2.32e-13 RS = 5.72e-3 TRS1 = 2.56e-3 TRS2 = -5.13e-6 CJO = 1.18e-9 TT = 5.62e-8)
.MODEL DBKMOD D (RS = 2.00e-1 TRS1 = 3.33e-4 TRS2 = 2.68e-6)
.MODEL DPLCAPMOD D (CJO = 6.55e-10 IS = 1e-30 N = 10)
.MODEL MOSMOD NMOS (VTO = 3.89 KP = 15.03 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL RBKMOD RES (TC1 = 1.04e-3 TC2 = -1.04e-6)
.MODEL RDSMOD RES (TC1 = 5.85e-3 TC2 = 1.77e-5)
.MODEL RSCLMOD RES (TC1 = 2.0e-3 TC2 = 1.5e-6)
.MODEL RVTOMOD RES (TC1 = -5.35e-3 TC2 = -3.77e-6)
.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -5.04 VOFF= -3.04)
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -3.04 VOFF= -5.04)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -3.02 VOFF= 1.98)
.MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 1.98 VOFF= -3.02)

.ENDS

NOTE: For further discussion of the PSPICE model consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; written by William J. Hepp and C. Frank Wheatley.

4-510

RFP25N05

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.

Intersil semiconductor products are sold by description only.Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with­out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

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