Datasheet RFP14N06 Datasheet (Intersil)

RFP14N06

Data Sheet July 1999

14A, 60V, 0.100 Ohm, N-Channel Power
MOSFET

This N-Channel power MOSFET is manufactured using the
MegaFET process. This process which uses feature sizes
approaching those of LSI integrated circuits, gives optimum
utilization of silicon, resulting in outstanding performance. It
was designed for use in applications such as switching
regulators, switching convertors, motor drivers, and relay
drivers. This transistor can be operated directly from
integrated circuits.

Formerly developmental type TA09770.

Ordering Information

PART NUMBER PACKAGE BRAND

RFP14N06 TO-220AB RFP14N06

NOTE: When ordering, use the entire part number.

File Number

Features

• 14A, 60V

•r

• Temperature Compensating PSPICE

• Peak Current vs Pulse Width Curve

• UIS Rating Curve

• 175

• Related Literature

- TB334 “Guidelines for Soldering Surface Mount

= 0.100Ω

DS(ON)

o

C Operating Temperature

Components to PC Boards”

®

Model

Symbol

D

G

4002.3

Packaging

DRAIN (FLANGE)

TO-220AB

SOURCE

DRAIN

GATE

S

4-492

CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures

PSPICE® is a registered trademark of MicroSim Corporation.

http://www.intersil.com or 407-727-9207

| Copyright © Intersil Corporation 1999

RFP14N06

Absolute Maximum Ratings T

= 25oC Unless Otherwise Specified

C

RFP14N06 UNITS

Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V

Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . V

Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V

Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I

Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I

Pulsed Avalanche Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P

DSS

DGR

GS

DM

AS

D

Refer to Peak Current Curve

D

Linear Derating Factor Above TC = 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, T

STG

Maximum Temperature for Soldering

Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . T

Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .T

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationofthe
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

L

pkg

60 V
60 V

±20 V

14

Refer to UIS Curve

48

0.32

-55 to 175

300
260

A

W

W/oC

o

C

o

C

o

C

NOTE:

1. TJ= 25oC to 150oC.

Electrical Specifications T

= 25oC, Unless Otherwise Specified

C

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Drain to Source Breakdown Voltage BV
Gate Threshold Voltage V

GS(TH)VGS

Zero Gate Voltage Drain Current I

Gate to Source Leakage Current I
Drain to Source On Resistance (Note 2) r

DS(ON)ID

Turn-On Time t
Turn-On Delay Time t

d(ON)

Rise Time t
Turn-Off Delay Time t

d(OFF)

Fall Time t
Turn-Off Time t
Total Gate Charge Q

g(TOT)VGS

Gate Charge at 10V Q
Threshold Gate Charge Q

Input Capacitance C
Output Capacitance C
Reverse Transfer Capacitance C
Thermal Resistance Junction to Case R
Thermal Resistance Junction to Ambient R

DSSID

DSS

GSS

ON

r

f

OFF

g(10)VGS

g(TH)VGS

ISS

OSS

RSS

θJC
θJA

= 250µA, VGS = 0V (Figure 11) 60 - - V

= VDS, ID = 250µA, (Figure 10) 2 - 4 V
VDS = Rated BV
VDS= 0.8 x Rated BV

, VGS = 0V - - 1 µA

DSS

DSS,VGS

= 0V,TC= 150oC- - 25 µA

VGS = ±20V - - ±100 nA

= 14A, VGS = 10V, (Figure 9) - - 0.100 Ω

VDD =30V, ID = 7A, RL = 4.3Ω,
VGS = 10V, RGS = 25Ω
(Figure 13)

- - 60 ns

-14- ns

-26- ns

-45- ns

-17- ns

- - 100 ns
= 0V to 20V VDD = 48V, ID = 14A,
= 0V to 10V - - 25 nC
= 0V to 2V - - 1.5 nC

RL = 3.42Ω,
I

= 0.4mA

G(REF)

(Figure 13)

VDS = 25V, VGS = 0V, f = 1MHz
(Figure 12)

- - 40 nC

- 570 - pF

- 185 - pF

-50- pF

- - 3.125oC/W

TO-220AB - - 62

o

C/W

Source to Drain Diode Specifications

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Source to Drain Diode Voltage V
Diode Reverse Recovery Time t

NOTES:

2. Pulse test: pulse width ≤ 300µs, duty cycle ≤ 2%.

3. Repetitive rating: pulse width limited by maximum junction temperature. See Transient Thermal Impedance curve (Figure 3) and Peak Current
Capability Curve (Figure 5).

4-493

ISD = 14A - - 1.5 V

SD

ISD = 14A, dISD/dt = 100A/µs - - 125 ns

rr

RFP14N06

Typical Performance Curves

1.2

1.0

0.8

0.6

0.4

0.2

POWER DISSIPATION MULTIPLIER

0

0 25 50 75 100 175

TC, CASE TEMPERATURE (oC)

Unless Otherwise Specified

150

125

FIGURE 1. NORMALIZED POWERDISSIPATION vs CASE

TEMPERATURE

1

0.5

16

12

8

, DRAIN CURRENT (A)

4

D

I

0

25 50 75 100

TC, CASE TEMPERATURE (oC)

125

150

FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs

CASE TEMPERATURE

175

0.2

NORMALIZED

JC,

Z

100

10

, DRAIN CURRENT (A)

D

I

1

0.1

0.1

0.05

θ

0.02

THERMAL IMPEDANCE

0.01

0.01

-5

10

OPERATION IN THIS
AREA MAY BE
LIMITED BY r

1

VDS, DRAIN TO SOURCE VOLTAGE (V)

SINGLE PULSE

DS(ON)

10

NOTES:
DUTY FACTOR: D = t

PEAK TJ = PDM x Z

-4

10

-3

10

t, RECTANGULAR PULSE DURATION (s)

-2

10

-1

10

FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE

TC = 25oC

= MAX RATED

T

J

SINGLE PULSE

100µs

1ms

10ms
100ms

DC

100

200

TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION

100

VGS = 20V

-5

VGS = 10V

-4

10

, PEAK CURRENT (A)

DM

I

10

10

-3

10

t, PULSE WIDTH (s)

P

DM

t

1

t

2

1/t2

x R

JA

θ

0

10

FOR TEMPERATURES
ABOVE 25
CURRENT AS FOLLOWS:

10

-2

o

II

=

25

10

+ T

JA

θ

C DERATE PEAK

175 T

–



---------------------



150



TC = 25oC

-1

10

A

1

10

C

0

1

10

FIGURE 4. FORWARD BIAS SAFE OPERATING AREA FIGURE 5. PEAK CURRENT CAPABILITY

4-494

RFP14N06

Typical Performance Curves

50

10

STARTING TJ = 150oC

If R = 0

, AVALANCHE CURRENT (A)

tAV = (L)(IAS)/(1.3*RATED BV

AS

I

If R ≠ 0
t

= (L/R)ln[(IAS*R)/(1.3*RATED BV

AV

1

0.01

0.1 1 10

tAV, TIME IN AVALANCHE (ms)

DSS

- VDD)

Unless Otherwise Specified (Continued)

STARTING TJ = 25oC

) +1]

DSS-VDD

NOTE: Refer to Intersil Application Notes AN9321 and AN9322

FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING

35

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX

30

VDD= 15V

25

20

-55oC

25oC

175

35

VGS = 20V

30

VGS = 10V

25

20

15

10

, DRAIN CURRENT (A)

D

I

5

0

024 8

VDS, DRAIN TO SOURCE VOLTAGE (V)

VGS = 8V

PULSE DURATION = 250µs
DUTY CYCLE = 0.5% MAX
T

= 25oC

C

VGS = 7V

VGS = 6V

VGS = 5V

VGS = 4.5V

6

FIGURE 7. SATURATION CHARACTERISTICS

2.5

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX

o

C

VGS = 10V, ID = 14A

2.0

1.5

15

10

, DRAIN TO SOURCE CURRENT (A)

5

DS(ON)

I

0

0468102

VGS, GATE TO SOURCE VOLTAGE (V)

1.0

ON RESISTANCE

0.5

NORMALIZED DRAIN TO SOURCE

0

-80 -40 0 40 80 120 160
TJ, JUNCTION TEMPERATURE (oC)

FIGURE 8. TRANSFER CHARACTERISTICS FIGURE 9. NORMALIZED DRAIN TO SOURCE ON

RESISTANCE vs JUNCTION TEMPERATURE

2.0
VGS = VDS, ID = 250µA

1.5

1.0

NORMALIZED GATE

0.5

THRESHOLD VOLTAGE

0

-80 -40 0 40 80 120 160
TJ, JUNCTION TEMPERATURE (oC)

200

2.0
ID = 250µA

1.5

1.0

0.5

BREAKDOWN VOLTAGE

NORMALIZED DRAIN TO SOURCE

0

-80 -40 0 40 80 120 160
T

, JUNCTION TEMPERATURE (oC)

J

200

200

FIGURE 10. NORMALIZED GATETHRESHOLD VOLTAGE vs

JUNCTION TEMPERATURE

4-495

FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN

VOLTAGE vs JUNCTION TEMPERATURE

RFP14N06

Typical Performance Curves

Unless Otherwise Specified (Continued)

700

C

C

ISS

OSS

VGS = 0V, f = 1MHz

= CGS + C

C
C
C

ISS
RSS
OSS

= C

≈ C

GD
DS

+ C

GD

GD

600

500

400

300

200

C, CAPACITANCE (pF)

100

0

0 5 10 15 20 25

C

RSS

V

, DRAIN TO SOURCE VOLTAGE (V)

DS

FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE

Test Circuits and Waveforms

V

DS

L

VARY t

TO OBTAIN

P

REQUIRED PEAK I

V

GS

AS

R

G

DUT

+

-

60

45

30

15

, DRAIN TO SOURCE VOLTAGE (V)

DS

V

0

V

= BV

DD

DSS

0.75 BV

0.50 BV

0.25 BV

RL = 4.28Ω
I

G(REF)

V

= 10V

GS

I

G(REF)

20

I

G(ACT)

t, TIME (µs)

DSS
DSS
DSS

= 0.4mA

VDD = BV

80

DSS

I
I

G(REF)
G(ACT)

10

7.5

5.0

2.5

0

, GATE TO SOURCE VOLTAGE (V)

GS

V

NOTE: Refer to Intersil Application Notes AN7254 and AN7260.

FIGURE 13. NORMALIZED SWITCHING WAVEFORMS FOR

CONSTANT GATE CURRENT

BV

DSS

t

P

I

AS

V

DD

V

DS

V

DD

0V

P

I

AS

0.01Ω

0

t

AV

t

FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 15. UNCLAMPED ENERGY WAVEFORMS

t

ON

t

10%

d(ON)

90%

50%

10%

t

r

PULSE WIDTH

V

DS

V

DS

R

DUT

L

+

V

DD

-

0

V

GS

0

V

GS

R

GS

V

GS

t

d(OFF)

90%

FIGURE 16. SWITCHING TIME TEST CIRCUIT FIGURE 17. RESISTIVE SWITCHING WAVEFORMS

t

OFF

50%

t

f

90%

10%

4-496

RFP14N06

Test Circuits and Waveforms

V

DS

V

GS

DUT

I

g(REF)

FIGURE 18. GATE CHARGE TEST CIRCUIT FIGURE 19. GATE CHARGE WAVEFORM

(Continued)

R

L

+

-

V

DD

Q

V

DD

VGS= 2V

0

I

g(REF)

0

V

GS

Q

g(TH)

V

DS

g(10)

Q

g(TOT)

VGS= 20V

VGS = 10V

4-497

PSPICE Electrical Model

.SUBCKT RFP14N06 2 1 3 ; rev 9/12/94

CA 12 8 8.84e-10
CB 15 14 9.34e-10
CIN 6 8 5.2e-10

DBODY 7 5 DBDMOD
DBREAK 5 11 DBKMOD
DPLCAP 10 5 DPLCAPMOD

EBREAK 11 7 17 18 62.87
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTO 20 6 18 8 1

IT 8 17 1

LDRAIN 2 5 1e-9
LGATE 1 9 4.34e-9
LSOURCE 3 7 3.79e-9

MOS1 16 6 8 8 MOSMOD M = 0.99
MOS2 16 21 8 8 MOSMOD M = 0.01

RBREAK 17 18 RBKMOD 1
RDRAIN 50 16 RDSMOD 2.2e-3
RGATE 9 20 5.64
RIN 6 8 1e9
RSCL1 5 51 RSCLMOD 1e-6
RSCL2 5 50 1e3
RSOURCE 8 7 RDSMOD 42.3e-3
RVTO 18 19 RVTOMOD 1

S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD

GATE

1

LGATE

RGATE

RFP14N06

ESG

EVTO

+

209

18

8

S1A S2A

12

13

CA

EGS EDS

10

DPLCAP

RSCL2

-

6
8

+

-

8

RIN

+

-

VTO

6

15

14
13

S2BS1B
13

6
8

CIN

CB

5

LDRAIN

RSCL1

51

+

5

51

50
RDRAIN

16

+

MOS1

14

+

5
8

-

ESCL

21

8

DBREAK

11

EBREAK

MOS2

RSOURCE

17 18

+

17
18

-

RBREAK

7

IT

DBODY

LSOURCE

RVTO

19

VBAT

+

DRAIN
2

3

SOURCE

VBAT 8 19 DC 1
VTO 21 6 0.82

ESCL 51 50 VALUE = {(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)*1e6/50,6))}

.MODEL DBDMOD D (IS = 1.5e-13 RS = 10.9e-3 TRS1 = 2.3e-3 TRS2 = -1.75e-5 CJO = 6.84e-10 TT = 4.2e-8)
.MODEL DBKMOD D (RS = 4.15e-1 TRS1 = 3.73e-3 TRS2 = -3.21e-5)
.MODEL DPLCAPMOD D (CJO = 26.2e-11 IS = 1e-30 N = 10)
.MODEL MOSMOD NMOS (VTO = 3.91 KP = 12.68 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL RBKMOD RES (TC1 = 7.73e-4 TC2 = 2.12e-6)
.MODEL RDSMOD RES (TC1 = 5.0e-3 TC2 = 2.53e-5)
.MODEL RSCLMOD RES (TC1 = 2.05e-3 TC2 = 1.35e-5)
.MODEL RVTOMOD RES (TC1 = -4.44e-3 TC2 = -6.45e-6)
.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -5.29 VOFF= -3.29)
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -3.29 VOFF= -5.29)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -2.25 VOFF= 2.75)
.MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 2.75 VOFF= -2.25)

.ENDS

NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; written by William J. Hepp and C. Frank Wheatley.

4-498

RFP14N06

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.

Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with­out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

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