Datasheet RFP14N05L Datasheet (Intersil)

Page 1
RFD14N05L, RFD14N05LSM, RFP14N05L
Data Sheet April 1999
These are N-channel power MOSFETs manufactured using the MegaFET process. This process, which uses feature sizes approaching those of LSI integrated circuits, gives optimum utilization of silicon, resulting in outstanding performance. They were designed for use in applications such as switching regulators, switching converters, motor drivers and relay drivers. This performance isaccomplished through a special gate oxide design which provides full rated conductance at gate bias in the 3V-5V range, thereby facilitating true on-off power control directly from logic level (5V) integrated circuits.
Formerly developmental type TA09870.
Ordering Information
PART NUMBER PACKAGE BRAND
RFD14N05L TO-251AA 14N05L RFD14N05LSM TO-252AA 14N05L RFP14N05L TO-220AB FP14N05L
NOTE: When ordering, use the entire part number. Add the suffix 9A to obtain the TO-252AAvariant in the tape and reel, i.e., RFD14N05LSM9A.
File Number
Features
• 14A, 50V
DS(ON)
= 0.100
•r
• Temperature Compensating PSPICE™ Model
• Can be Driven Directly from CMOS, NMOS, and TTL Circuits
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
o
C Operating Temperature
• 175
• Related Literature
- TB334 “Guidelines for Soldering Surface Mount
Components to PC Boards”
Symbol
D
G
S
2246.3
Packaging
DRAIN (FLANGE)
JEDEC TO-251AA JEDEC TO-252AA
SOURCE
DRAIN
GATE
GATE
SOURCE
JEDEC TO-220AB
SOURCE
DRAIN
GATE
DRAIN (FLANGE)
DRAIN (FLANGE)
6-135
CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.
PSPICE™ is a trademark of MicroSim Corporation.
http://www.intersil.com or 407-727-9207
| Copyright © Intersil Corporation 1999
Page 2
RFD14N05L, RFD14N05LSM, RFP14N05L
Absolute Maximum Ratings T
= 25oC, Unless Otherwise Specified
C
RFD14N05L, RFD14N05LSM,
RFP14N05L UNITS
Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V
Drain to Gate Voltage (RGS = 20k) (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . V
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V
Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I
Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
Pulsed Avalanche Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P
DSS
DGR
GS
DM
AS
D
Refer to Peak Current Curve
D
Derate above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ,T
STG
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . T
Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .T
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationofthe device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
L
pkg
50 V 50 V
±10 V
14
Refer to UIS Curve
48
0.32
-55 to 175
300 260
A
W
W/oC
o
C
o
C
o
C
NOTE:
1. TJ= 25oC to 150oC.
Electrical Specifications T
= 25oC, Unless Otherwise Specified
C
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Drain to Source Breakdown Voltage BV Gate Threshold Voltage V Zero Gate Voltage Drain Current I
DSSID
GS(TH)VGS
DSS
= 250µA, VGS = 0V, Figure 13 50 - - V
= VDS, ID = 250µA, Figure12 1 - 2 V VDS = 40V, VGS = 0V - - 1 µA VDS = 40V, VGS = 0V, TC = 150oC--50µA
Gate to Source Leakage Current I Drain to Source On Resistance (Note 2) r
DS(ON)ID
Turn-On Time t Turn-On Delay Time t
d(ON)
Rise Time t Turn-Off Delay Time t
d(OFF)
Fall Time t Turn-Off Time t Total Gate Charge Q
(OFF) g(TOT)VGS
Gate Charge at 5V Q Threshold Gate Charge Q Input Capacitance C Output Capacitance C Reverse Transfer Capacitance C Thermal Resistance Junction to Case R Thermal Resistance Junction to Ambient R
R
GSS
(ON)
g(TH)VGS
OSS RSS
VGS = ±10V - - ±100 nA
= 14A, VGS = 5V, Figures 9, 11 - - 0.100
VDD = 25V, ID = 7A, RL = 3.57, VGS = 5V, RGS = 0.6
r
- - 60 ns
-13 - ns
-24 - ns
-42 - ns
f
-16 - ns
- - 100 ns
= 0V to 10V VDD= 40V,ID=14A, VGS = 0V to 5V - - 25 nC
g(5)
RL = 2.86 Figures 20, 21
- - 40 nC
= 0V to 1V - - 1.5 nC VDS = 25V, VGS = 0V, f = 1MHz
ISS
Figure 14
- 670 - pF
- 185 - pF
-50 - pF
θJC
TO-251 and TO-252 - - 100
θJA
TO-220 - - 80
θJA
- - 3.125oC/W
o o
C/W C/W
Source to Drain Diode Specifications
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Source to Drain Diode Voltage (Note 2) V Diode Reverse Recovery Time t
NOTES:
2. Pulse Test: Pulse Width 300ms, Duty Cycle 2%.
3. Repetitive Rating: Pulse Width limited by max junction temperature. See Transient Thermal Impedance Curve (Figure 3) and Peak Current Capability Curve (Figure 5).
6-136
ISD = 14A - - 1.5 V
SD
ISD = 14A, dISD/dt = 100A/µs - - 125 ns
rr
Page 3
RFD14N05L, RFD14N05LSM, RFP14N05L
Typical Performance Curves
1.2
1.0
0.8
0.6
0.4
0.2
POWER DISSIPATION MULTIPLIER
0
25 50 75 100
0
0
TC, CASE TEMPERATURE (oC)
Unless Otherwise Specified
125
FIGURE 1. NORMALIZED POWERDISSIPATION vs CASE
TEMPERATURE
2
1
150
175
16
12
8
, DRAIN CURRENT (A)
4
D
I
0
25 50 75 100
TC, CASE TEMPERATURE (oC)
125
150
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
TEMPERATURE
175
0.5
0.2
0.1
0.1
, NORMALIZED
JC
θ
Z
100
10
, DRAIN CURRENT (A)
D
I
1
0.5 1
0.05
0.02
THERMAL IMPEDANCE
0.01 SINGLE PULSE
0.01
-5
10
OPERATION IN THIS AREA MAY BE LIMITED BY r
VDS, DRAIN TO SOURCE VOLTAGE (V)
DS(ON)
NOTES: DUTY FACTOR: D = t1/t PEAK TJ = PDM x Z
-4
10
-3
10
t, RECTANGULAR PULSE DURATION (s)
-2
10
-1
10
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
TC = 25oC
TJ = MAX. RATED
100µs
1ms
10ms 100ms
DC
10
100
200
TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION
100
, PEAK CURRENT CAPABILITY (A)
DM
I
TC = 25oC
10
-5
10
VGS = 5V VGS = 10V
-4
10
-3
10
t, PULSE WIDTH (s)
P
DM
t
1
t
2
2
x R
JC
θ
0
10
FOR TEMPERATURES ABOVE 25 CURRENT AS FOLLOWS:
I = I
25
-2
10
+ T
JC
C
θ
o
C DERATE PEAK
175 - T
C
150
-1
10
10
1
10
0
1
10
FIGURE 4. FORWARD BIAS SAFE OPERATING AREA FIGURE 5. PEAK CURRENT CAPABILITY
6-137
Page 4
RFD14N05L, RFD14N05LSM, RFP14N05L
Typical Performance Curves
50
10
STARTING TJ = 150oC
, AVALANCHE CURRENT (A)
If R = 0 tAV = (L)(IAS)/(1.3*RATED BV
AS
I
If R 0
= (L/R)ln[(IAS*R)/(1.3*RATED BV
t
AV
1
0.01
0.1 1 10
tAV, TIME IN AVALANCHE (ms)
DSS
- VDD)
Unless Otherwise Specified (Continued)
STARTING TJ = 25oC
) +1]
DSS-VDD
NOTE: Refer to Intersil Application Notes AN9321 and AN9322.
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING
35
-55oC
30
25
20
25oC
175oC
35
V
= 10V
GS
30
25
20
15
10
, DRAIN CURRENT (A)
D
I
5
0
0
1.5 VDS, DRAIN TO SOURCE VOLTAGE (V)
PULSE DURATION = 80µs, TC = 25oC DUTY CYCLE = 0.5% MAX.
VGS = 5V
VGS = 4.5V
3.0 4.5 7.5
FIGURE 7. SATURATION CHARACTERISTICS
250
ID = 7A
200
150
ID = 14A
ID = 28A
V
GS
VGS= 3V
VGS = 2.5V
6.0
= 4V
15
10
, DRAIN TO SOURCE CURRENT (A)
5
DS(ON)
I
0
0 3.0 4.5 6.0 7.51.5
VGS, GATE TO SOURCE VOLTAGE (V)
PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX.
= 15V
V
DD
, DRAIN TO SOURCE
DS(ON)
r
ID = 3.5A
100
ON RESISTANCE (m)
50
PULSE DURATION = 80µs
0
2.5 3.0 3.5 4.0 4.5 VGS, GATE TO SOURCE VOLTAGE (V)
DUTY CYCLE = 0.5% MAX.
FIGURE 8. TRANSFER CHARACTERISTICS FIGURE 9. DRAIN TO SOURCE ON RESISTANCE vs GATE
VOLTAGE AND DRAIN CURRENT
160
VDD = 25V, ID = 14A, RL = 3.57
140
120
100
80
60
SWITCHING TIME (ns)
40
20
0
010
RGS, GATE TO SOURCE RESISTANCE ()
20 30 40
t
d(OFF)
t
r
t
f
t
d(ON)
50
2.5
PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX.
VGS = 10V, ID = 14A
2.0
1.5
1.0
ON RESISTANCE
0.5
NORMALIZED DRAIN TO SOURCE
0
-80 -40 0 40 80 120 160 TJ, JUNCTION TEMPERATURE (oC)
5.0
200
FIGURE 10. SWITCHING TIME vs GATE RESISTANCE FIGURE 11. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
6-138
Page 5
RFD14N05L, RFD14N05LSM, RFP14N05L
Typical Performance Curves
2.0 VGS = VDS, ID = 250µA
1.5
1.0
NORMALIZED GATE
0.5
THRESHOLD VOLTAGE
0
-80 -40 0 40 80 120 160 TJ, JUNCTION TEMPERATURE (oC)
Unless Otherwise Specified (Continued)
FIGURE 12. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
800
C
ISS
600
VGS = 0V, f = 1MHz C
= CGS + C
ISS
C
= C
400
C, CAPACITANCE (pF)
200
0
0 5 10 15 20 25
, DRAIN TO SOURCE VOLTAGE (V)
V
DS
C
RSS OSS
CDS + C
GD
C
C
GD
GD
OSS
RSS
FIGURE 14. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
200
2.0 ID = 250µA
1.5
1.0
0.5
BREAKDOWN VOLTAGE
NORMALIZED DRAIN TO SOURCE
0
-80 -40 0 40 80 120 160 T
, JUNCTION TEMPERATURE (oC)
J
FIGURE 13. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
50
40
30
20
10
, DRAIN TO SOURCE VOLTAGE (V)
DS
V
0
= BV
V
DD
I
G REF()
20
------------------------ ­I
G ACT()
DSS
0.75 BV
0.50 BV
0.25 BV
RL = 3.57 I
= 0.4mA
G(REF)
= 5V
V
GS
t, TIME (µs)
DSS DSS DSS
VDD = BV
I
G REF()
80
------------------------ ­I
GACT()
DSS
5
4
3
2
1
0
NOTE: Refer to Intersil Application Notes AN7254 and AN7260,
FIGURE 15. TRANSCONDUCTANCE vs DRAIN CURRENT
200
, GATE TO SOURCE VOLTAGE (V)
GS
V
6-139
Page 6
RFD14N05L, RFD14N05LSM, RFP14N05L
Test Circuits and Waveforms
V
DS
BV
DSS
L
VARY t
TO OBTAIN
P
REQUIRED PEAK I
V
GS
AS
R
G
+
V
DD
-
DUT
0V
P
I
AS
0.01
0
t
FIGURE 16. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 17. UNCLAMPED ENERGY WAVEFORMS
t
P
I
AS
t
AV
V
DS
V
DD
t
ON
t
DS
10%
d(ON)
90%
50%
t
10%
r
PULSE WIDTH
V
DS
V
R
DUT
L
+
V
DD
-
0
V
GS
0
V
GS
R
GS
V
GS
FIGURE 18. SWITCHING TIME TEST CIRCUIT FIGURE 19. RESISTIVE SWITCHING WAVEFORMS
V
I
G(REF)
DS
R
L
V
GS
+
V
DD
-
DUT
V
DD
VGS= 1V
0
Q
g(TOT)
V
DS
Q
g(5)
V
GS
Q
g(TH)
VGS= 5V
t
d(OFF)
90%
t
OFF
50%
t
f
10%
VGS= 10V
90%
I
G(REF)
0
FIGURE 20. GATE CHARGE TEST CIRCUIT FIGURE 21. GATE CHARGE WAVEFORMS
6-140
Page 7
RFD14N05L, RFD14N05LSM, RFP14N05L
PSPICE Electrical Model
.SUBCKT RFP14N05L 2 1 3 ; rev 9/15/94
CA 12 8 1.464e-9 CB 15 14 1.64e-9 CIN 6 8 6.17e-10
DBODY 7 5 DBDMOD DBREAK 5 11 DBKMOD DPLCAP 10 5 DPLCAPMOD
EBREAK 11 7 17 18 65.35 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 6 10 6 8 1 EVTO 20 6 18 8 1
IT 8 17 1
LDRAIN 2 5 1e-9 LGATE 1 9 5.68e-9 LSOURCE 3 7 5.35e-9
MOS1 16 6 8 8 MOSMOD M = 0.99 MOS2 16 21 8 8 MOSMOD M = 0.01
RBREAK 17 18 RBKMOD 1 RDRAIN 50 16 RDSMOD 33.1e-3 RGATE 9 20 5.85 RIN 6 8 1e9 RSCL1 5 51 RSCLMOD 1e-6 RSCL2 5 50 1e3 RSOURCE 8 7 RDSMOD 14.3e-3 RVTO 18 19 RVTOMOD 1
GATE
1
LGATE
9
RGATE
10
ESG
EVTO
20
+
18
8
S1A
12
13
8
S1B
CA
EGS
DPLCAP
RSCL2
6 8
+
+
RIN
14 13
VTO
6
S2A
15
S2B
13
6 8
EDS
CIN
CB
5
LDRAIN
RSCL1
51
+
5
51
50
RDRAIN
16
+
MOS1
14
+
5 8
ESCL
21
8
DBREAK
EBREAK
MOS2
RSOURCE
11
17
+
17 18
7
RBREAK
IT
DBODY
LSOURCE
DRAIN 2
3 SOURCE
18
RVTO
19
VBAT
+
S1A 6 12 13 8 S1AMOD S1B 13 12 13 8 S1BMOD S2A 6 15 14 13 S2AMOD S2B 13 15 14 13 S2BMOD
VBAT 8 19 DC 1 VTO 21 6 0.485
ESCL 51 50 VALUE = {(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)*1e6/46,7))}
.MODEL DBDMOD D (IS = 2.23e-13 RS = 1.15e-2 TRS1 = 1.64e-3 TRS2 = 7.89e-6 CJO = 6.83e-10 TT = 3.68e-8) .MODEL DBKMOD D (RS = 3.8e-1 TRS1 = 1.89e-3 TRS2 = 1.13e-5) .MODEL DPLCAPMOD D (CJO = 25.7e-11 IS = 1e-30 N = 10) .MODEL MOSMOD NMOS (VTO = 1.935 KP = 18.89 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u) .MODEL RBKMOD RES (TC1 = 7.18e-4 TC2 = 1.53e-6) .MODEL RDSMOD RES (TC1 = 4.45e-3 TC2 = 2.9e-5) .MODEL RSCLMOD RES (TC1 = 2.8e-3 TC2 = 6.0e-6) .MODEL RVTOMOD RES (TC1 = -1.7e-3 TC2 = -2.0e-6) .MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -3.55 VOFF= -1.55) .MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -1.55 VOFF= -3.55) .MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -2.55 VOFF= 2.45) .MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 2.45 VOFF= -2.55)
.ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-circuit for the Power MOSFET Featuring Global Temperature Options; authored by William J. Hepp and C. Frank Wheatley.
6-141
Page 8
RFD14N05L, RFD14N05LSM, RFP14N05L
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Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with­out notice. Accordingly ,the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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NORTH AMERICA
Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240
6-142
EUROPE
Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05
ASIA
Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029
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