Datasheet RFP10P03L Datasheet (Fairchild Semiconductor)

May 1997

RFD10P03L, RFD10P03LSM,

SEMICONDUCTOR

RFP10P03L

10A, 30V, 0.200Ω, Logic Level

P-Channel Power MOSFET

Features

• 10A, 30V

•r

Temperature Compensating

•

• PSPICE Thermal Model

• Peak Current vs Pulse Width Curve

• UIS Rating Curve

• 175

= 0.200Ω

DS(ON)

o

C Operating Temperature

PSPICE Model

Ordering Information

PART NUMBER P ACKAGE BRAND

RFD10P03L TO-251AA 10P03L RFD10P03LSM TO-252AA 10P03L RFP10P03L TO-220AB F10P03L

NOTE: When ordering, use the entire part number. Add the sufﬁx, 9A, to obtain theTO-252AA variant in tape and reel, i.e.RFD10P03LSM9A..

Formerly developmental type TA49205.

Description

These products are P-Channel power MOSFETs manufactured using the MegaFET process. This process, which uses feature sizes approaching those of LSI circuits, gives optimum utilization of silicon, resulting in outstanding performance. They were designed for use in applications such as switching regulators, switching converters, motor drivers, and relay drivers. These transistors can be operated directly from integrated circuits.

Symbol

D

G

S

Packaging

DRAIN (FLANGE)

JEDEC TO-220AB JEDEC TO-251AA

SOURCE

DRAIN

GATE

JEDEC TO-252AA

DRAIN (FLANGE)

GATE

SOURCE

DRAIN (FLANGE)

SOURCE

DRAIN

GATE

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper ESD Handling Procedures. Copyright

1

File Number 3515.1

RFD10P03L, RFD10P03LSM, RFP10P03L

Absolute Maximum Ratings T

= 25oC, Unless Otherwise Speciﬁed

C

RFD10P03L, RFD10P03LSM,

RFP10P03L UNITS

Drain to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

Drain to Gate Voltage (RGS = 20KΩ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

DSS

DGR

GS

-30 V

±10 V

Drain Current

RMS Continuous. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I

Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I

Single Pulse Avalanche Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .E

Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .P

Derate Above 25oC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, T

STG

Maximum Lead Temperature for Soldering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T

D

DM

AS

D

L

10

See Figure 5

Refer to UIS Curve

65

0.43

-55 to 175 300

A

W

W/oC

o

C

o

C

(0.063in (1.6mm) from case for 10s)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this speciﬁcation is not implied.

Electrical Speciﬁcations T

= 25oC, Unless Otherwise Speciﬁed

C

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Drain to Source Breakdown Voltage BV Gate Threshold Voltage V

GS(TH)

Zero Gate Voltage Drain Current I

Gate to Source Leakage Current I Drain to Source On Resistance

r

DS(ON)ID

(Note 1)

Turn-On Time t Turn-On Delay Time t

d(ON)

Rise Time t Turn-Off Delay Time t

d(OFF)

Fall Time t Turn-Off Time t Total Gate Charge Q

g(TOT)

Gate Charge at -5V Q Threshold Gate Charge Q Input Capacitance C Output Capacitance C Reverse Transfer Capacitance C Thermal Resistance, Junction to Case R Thermal Resistance, Junction to Ambient R

DSS

GSS

ON

r

f

OFF

g(-5)

g(TH)

ISS OSS RSS

θJC

θJA

ID = 250µA, VGS = 0V -30 - - V VGS = VDS, ID = 250µA -1 - -2 V VDS = -30V, TC = 25oC---1µA V

= 0V TC = 150oC - - -50 µA

GS

VGS = ±10V - - ±100 nA

= 10A, VGS = -5V - - 0.200 Ω ID = 10A, VGS = -4.5V 0.220 Ω VDD = 15V, ID≅ 10A

RL = 1.5Ω, RGS = 5Ω, VGS = -5V

- - 100 ns

-15- ns

-50- ns

-35- ns

-20- ns

- - 80 ns VGS = 0 to -10V VDD = -24V, VGS = 0 to -5V - 13 16 nC

ID≅ 10A, RL = 2.4Ω

-2530nC

VGS = 0 to -1V - 1.2 1.5 nC VDS = -25V, VGS = 0V

f = 1MHz

- 1035 - pF

- 340 - pF

-35- pF

- - 2.30 RFD10P03L, RFD10P03LSM - - 100 RFP10P03L 80

o o o

C/W C/W C/W

Source to Drain Diode Speciﬁcations

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Source to Drain Forward Voltage V Reverse Recovery Time t

NOTE:

1. Pulse Test: Pulse width ≤ 300µs, Duty Cycle ≤ 2%.

SD

rr

ISD = -10A - - -1.5 V ISD = -10A, dISD/dt = -100A/µs--75ns

2

RFD10P03L, RFD10P03LSM, RFP10P03L

Typical Performance Curves

Unless Otherwise Speciﬁed

1.2

1.0

0.8

0.6

0.4

0.2

POWER DISSIPATION MULTIPLIER

0.0 0 25 50 75 100 175

125

TC, CASE TEMPERATURE (oC)

FIGURE 1. NORMALIZED POWER DISSIPATION vs

CASE TEMPERATURE

2.0

1.0

0.5

150

-12

-10

-8

-6

-4

, DRAIN CURRENT (A)

D

I

-2

0

25 50 75 100

125

150

TC, CASE TEMPERATURE (oC)

FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs

CASE TEMPERATURE

175

0.2

0.1

0.05

0.02

0.01

, NORMALIZED THERMAL IMPEDANCE

θJC

Z

0.01 10

SINGLE PULSE

-5

-100

-10

, DRAIN CURRENT (A)

D

I

OPERATION IN THIS AREA MAY BE LIMITED BY r

-1

-1 -10

DS(ON)

V

, DRAIN TO SOURCE VOLTAGE (V)

DS

NOTES: DUTY FACTOR: D = t1/t PEAK TJ = PDM x Z

-4

10

-3

10

-2

10

-1

10

t, RECTANGULAR PULSE DURATION (s)

FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE

-100

VGS = -10V

VGS = -5V

-10

, PEAK CURRENT CAPABILITY (A)

DM

I

-5

10

FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT CAPABILITY AS FOLLOWS:

TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION

-4

10

-3

10

t, PULSE WIDTH (s)

V

DSS

MAX = -30V

TJ = MAX RATED

= 25oC

T

C

100µs

1ms

10ms 100ms

DC

-100

-2

10

P

DM

xR

θJC

0

10

175 TC–



II

=

----------------------- -



25

150



-1

10

t

1

t

2

+ T

θJC

T

C

10

2

C

= 25oC

0

1

10

1

10

FIGURE 4. FORWARD BIAS SAFE OPERATING AREA FIGURE 5. PEAK CURRENT CAPABILITY

3

RFD10P03L, RFD10P03LSM, RFP10P03L

Typical Performance Curves

-50

-10 STARTING TJ = 150oC

If R = 0

, AVALANCHE CURRENT (A) I

= (L) (IAS)/(1.3 RATED BV

t

AV

AS

IF R ≠ 0 t

= (L/R) ln [(IAS*R)/(1.3 RATED BV

AV

-1

0.01 0.1 1 10 t

, TIME IN AVALANCHE (ms)

AV

DSS

Unless Otherwise Speciﬁed (Continued)

STARTING TJ = 25oC

- VDD)

- VDD) + 1]

DSS

NOTE: Refer to Application Notes AN9321 and AN9322.

FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING

CAPABILITY

-25 PULSE TEST

PULSE DURATION = 250µs DUTY CYCLE = 0.5% MAX

-20 VDD= -15V

-15

-10

-5

, ON-STATE DRAIN CURRENT (A)

D(ON)

I

0

0 -3.0 -4.5 -6.0-1.5

VGS, GATE TO SOURCE VOLTAGE (V)

-55oC

175oC

25oC

-25

PULSE DURATION = 250µs,

= 25oC

T

C

-20

= -10V

V

-15

-10

, DRAIN CURRENT (A)

D

I

-5

0

0 -1.0

GS

VDS, DRAIN TO SOURCE VOLTAGE (V)

-2.0

VGS = -5V

V

-3.0 -5.0

FIGURE 7. SATURATION CHARACTERISTICS

400

ID = -20A

= -10A

I

300

200

DRAIN TO SOURCE

100

ON RESISTANCE (mΩ)

DS(ON),

r

0

-2.0 -4.0 -6.0 -8.0 -10.0 , GATE TO SOURCE VOLTAGE (V)

V

GS

D

= -5A

I

D

I

= -2.5A

D

= -4V

GS

VGS =-3.5V

VGS = -3V

-4.0

T

= 25oC

C

FIGURE 8. TRANSFER CHARACTERISTICS FIGURE 9. DRAIN TO SOURCE ON RESISTANCE vs GATE

2.0 VGS = -5V, ID = -10.0A

1.5

1.0

ON RESISTANCE

0.5

NORMALIZED DRAIN TO SOURCE

0.0

-80

-40 0 T

, JUNCTION TEMPERATURE (oC)

J

40

120

80

FIGURE 10. NORMALIZED DRAIN TO SOURCE ON

RESISTANCE vs JUNCTION TEMPERATURE

160 200

VOLTAGE AND DRAIN CURRENT

1.2 ID =- 250uA

1.1

1.0

0.9

BREAKDOWN VOLTAGE

NORMALIZED DRAIN TO SOURCE

0.8

-80 160 200

-40 0 40 , JUNCTION TEMPERATURE (oC)

T

J

120

80

FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN

VOLTAGE vs JUNCTION TEMPERATURE

4

RFD10P03L, RFD10P03LSM, RFP10P03L

Typical Performance Curves

1.2

1.0

0.8

NORMALIZED GATE

0.6

THRESHOLD VOLTAGE

0.4

-80 -40 0 40 80 120 160 TJ, JUNCTION TEMPERATURE (oC)

Unless Otherwise Speciﬁed (Continued)

VGS = VDS,ID = -250µA

FIGURE 12. NORMALIZED GATE THRESHOLD VOLTAGE vs

JUNCTION TEMPERATURE

-30

-22.5

-15

-7.5

, DRAIN TO SOURCE VOLTAGE (V)

DS

V

= -0.25mA

0.75 BV

0.50 BV

0.25 BV

= -5V

VDD = BV

DSS DSS DSS

80

DSS

I

G(REF)

I

G(ACT)

VDD =BV

DSS

RL = 3.0Ω

I

G(REF)

0.75 BV

DSS

0.50 BV

DSS

0.25 BV

DSS

V

GS

0

20

I

G(REF)

I

G(ACT)

t, TIME ( µs)

-5.00

-3.75

-2.50

-1.25

0.00

200

150

125

100

SWITCHING TIME (ns)

FIGURE 13. SWITCHING TIME vs GATE RESISTANCE

1200

1000

800

600

400

C, CAPACITANCE (pF)

, GATE TO SOURCE VOLTAGE (V)

GS

V

200

VDD = -15V, ID = -10A, RL= 1.50Ω

t

d(OFF)

75

50

25

0

0 -5 -10 -15 -20 -25

10

RGS, GATE TO SOURCE RESISTANCE (Ω)

VDS, DRAIN TO SOURCE VOLTAGE(V)

20 30 40 500

VGS = 0V, f = 1MHz

C

ISS

C

OSS

C

RSS

t

r

t

f

d(ON)

NOTE: Refer to Application Notes AN7254 and AN7260.

FIGURE 14. NORMALIZED SWITCHING WAVEFORMS FOR

CONSTANT GATE CURRENT

FIGURE 15. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE

5

RFD10P03L, RFD10P03LSM, RFP10P03L

Test Circuits and Waveforms

V

DS

t

BV

AV

DSS

L

0

VARY t

TO OBTAIN

P

REQUIRED PEAK I

0V V

GS

t

P

AS

R

G

DUT

I

AS

0.01Ω

-

V

DD

+

V

DD

I

AS

t

P

FIGURE 16. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 17. UNCLAMPED ENERGY WAVEFORMS

V

DS

t

ON

t

d(ON)

t

R

L

DUT

R

V

GS

G

-

V

DD

+

0

V

DS

V

GS

0

10%

r

10%

90%

50%

PULSE WIDTH

FIGURE 18. SWITCHING TIME TEST CIRCUIT FIGURE 19. RESISTIVE SWITCHING WAVEFORMS

V

I

G(REF)

DS

R

L

0

VGS= -1V

V

GS

DUT

V

DD

+

V

0

I

g(REF)

-V

DD

GS

Q

g(TH)

Q

g(-5)

Q

g(TOT)

VGS= -5V

t

d(OFF)

V

DS

t

90%

OFF

90%

50%

t

f

10%

VGS= -10V

FIGURE 20. GATE CHARGE TEST CIRCUIT FIGURE 21. GATE CHARGE WAVEFORMS

6

RFD10P03L, RFD10P03LSM, RFP10P03L

PSpice Electrical Model

.SUBCKT RFD10P03L 2 1 3 REV 22 Aug 96

CA 12 8 1.29e-9 CB 15 14 9.90e-10 CIN 6 8 1.01e-9

DBODY 5 7 DBODYMOD DBREAK 7 11 DBREAKMOD DPLCAP 10 6 DPLCAPMOD

EBREAK 5 11 17 18 -36.49 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 5 10 8 6 1 EVTHRES 6 21 19 8 1 EVTEMP 6 20 18 22 1

IT 8 17 1

LDRAIN 2 5 1e-9 LGATE 1 9 3.40e-9 LSOURCE 3 7 3.22e-9

MMED 16 6 8 8 MmedMOD MSTRO 16 6 8 8 MstroMOD MWEAK 16 21 8 8 MweakMOD

RBREAK 17 18 RBREAKMOD 1 RDRAIN 50 16 RDRAINMOD 68.25e-3 RGATE 9 20 2.54 RSCL1 5 51 RSCLMOD 1e-6 RSCL2 5 50 1e3 RSOURCE 8 7 RSourceMOD 25.00e-3 RVTHRES 22 8 RVTHRESMOD 1 RVTEMP 18 19 RVTEMPMOD 1

S1A 6 12 13 8 S1AMOD S1B 13 12 13 8 S1BMOD S2A 6 15 14 13 S2AMOD S2B 13 15 14 13 S2BMOD

GATE

+

-

11

7

LDRAIN

RLDRAIN

DBODY

LSOURCE

RLSOURCE

RVTEMP

19

-

VBAT

+

22

DRAIN

2

SOURCE

3

ESG

+

13

RSLC2

6

14 13

+

6 8

-

8 6

EVTHRES

+

S2A

S2B

10

DPLCAP

LGATE

1

RLGATE

9

RGATE

CA

EVTEMP

-

18 22

20

S1A

12

13

8

S1B

EGS EDS

5

+-

RSLC1

51

+

5

ESLC

51

-

50

RDRAIN

16

21

-

19

8

MSTRO

CIN

15

CB

+

8

14

5 8

-

EBREAK

MWEAK

MMED

DBREAK

RSOURCE

17 18

IT

8

17 18

RBREAK

RVTHRES

VBAT 22 19 DC 1

ESCL 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*33),5.0))}

.MODEL DBODYMOD D (IS=9.15e-13 RS=3.25e-2 IKF=0.05 N=0.97 TRS1=4.11e-5 TRS2=2.03e-6 CJO=1.13e-9 M=0.40 TT=3.72e-8) .MODEL DBREAKMOD D ( RS=2.62e-1 TRS1=1.74e-3 TRS2=-3.81e-6) .MODEL DPLCAPMOD D (CJO=1.46e-10 IS=1e-30 N=10 M=0.50) .MODEL MSTRONGMOD PMOS (VTO=-1.95 KP=11.60 IS=1e-30 N=10 TOX=1 L=1u W=1u) .MODEL MMEDMOD PMOS (VTO=-1.65 KP=1.00 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=2.54) .MODEL MWEAKMOD PMOS (VTO=-1.43 KP=0.09 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=25.4 RS=0.1) .MODEL RBREAKMOD RES (TC1=9.17e-4 TC2=-2.74e-7) .MODEL RDRAINMOD RES (TC1=6.35e-3 TC2=1.98e-5) .MODEL RSOURCEMOD RES (TC1=0 TC2=0) .MODEL RSCLMOD RES (TC1=2e-3 TC2=0) .MODEL RVTHRESMOD RES (TC1=1.23e-3 TC2=1.97e-6) .MODEL RVTEMPMOD RES (TC1=-1.18e-3 TC2=1.44e-6) .MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=4.80 VOFF=1.80) .MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=1.80 VOFF=4.80) .MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-0.40 VOFF=-3.40) .MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-3.40 VOFF=-0.40) ENDS

For further discussion of the PSPICE model consult A New PSPICE Sub-circuit for the Power MOSFet Featuring Global Temperature Options; authored by William J. Hepp and C. Frank Wheatley.

7

PSpice Thermal Model

RFD10P03L, RFD10P03LSM, RFP10P03L

REV 29 Aug 96

RFP10P03L

CTHERM1 7 6 5.00e-7 CTHERM2 6 5 5.35e-4 CTHERM3 5 4 5.50e-4 CTHERM4 4 3 1.75e-3 CTHERM5 3 2 1.25e-2 CTHERM6 2 1 0.45

RTHERM1 7 6 1.00e-2 RTHERM2 6 5 2.05e-2 RTHERM3 5 4 5.39e-2 RTHERM4 4 3 5.45e-1 RTHERM5 3 2 1.01 RTHERM6 2 1 0.50

RFD10P03L, RFD10P03LSM

CTHERM1 7 6 5.00e-7 CTHERM2 6 5 5.35e-4 CTHERM3 5 4 5.50e-4 CTHERM4 4 3 1.75e-3 CTHERM5 3 2 1.25e-2 CTHERM6 2 1 0.11

RTHERM1 7 6 1.00e-2 RTHERM2 6 5 2.05e-2 RTHERM3 5 4 5.39e-2 RTHERM4 4 3 5.45e-1 RTHERM5 3 2 1.01 RTHERM6 2 1 0.50

RTHERM1

RTHERM2

RTHERM3

RTHERM4

JUNCTION

7

CTHERM1

6

CTHERM2

5

CTHERM3

4

CTHERM4

3

RTHERM5

RTHERM6

CTHERM5

2

CTHERM6

1

CASE

8

RFD10P03L, RFD10P03LSM, RFP10P03L

TO-220AB

3 LEAD JEDEC TO-220AB PLASTIC PACKAGE

ØP

Q

D

E

1

L

1

E

H

1

D

1

b

1

A

1

SYMBOL

A 0.170 0.180 4.32 4.57 -

A

1

TERM. 4

o

45

b 0.030 0.034 0.77 0.86 3, 4

b

1

c 0.014 0.019 0.36 0.48 2, 3 , 4

D 0.590 0.610 14.99 15.49 -

D

1

INCHES MILLIMETERS

NOTESMIN MAX MIN MAX

0.048 0.052 1.22 1.32 -

0.045 0.055 1.15 1.39 2, 3

- 0.160 - 4.06 -

E 0.395 0.410 10.04 10.41 -

L

o

60

1

e

1

b

c

E

1

- 0.030 - 0.76 -

e 0.100 TYP 2.54 TYP 5

3

2

e

J

1

e

1

H

1

J

1

0.200 BSC 5.08 BSC 5

0.235 0.255 5.97 6.47 -

0.100 0.110 2.54 2.79 6

L 0.530 0.550 13.47 13.97 -

LEAD NO. 1 - GATE LEAD NO. 2 - DRAIN LEAD NO. 3 - SOURCE TERM. 4 - DRAIN

L

1

0.130 0.150 3.31 3.81 2

ØP 0.149 0.153 3.79 3.88 -

Q 0.102 0.112 2.60 2.84 -

NOTES:

1. These dimensions are within allowable dimensions of Rev. J of JEDEC TO-220AB outline dated 3-24-87.

2. Lead dimension and finish uncontrolled in L1.

3. Lead dimension (without solder).

4. Add typically 0.002 inches (0.05mm) for solder coating.

5. Position of lead to be measured 0.250 inches (6.35mm) from bottom of dimension D.

6. Position of lead to be measured 0.100 inches (2.54mm) from bottom of dimension D.

7. Controlling dimension: Inch.

8. Revision 1 dated 1-93.

9

RFD10P03L, RFD10P03LSM, RFP10P03L

TO-251AA

3 LEAD JEDEC TO-251AA PLASTIC PACKAGE

D

L

H

1

L

1

b

123

E

b

2

b

1

c

e

1

LEAD NO. 1 - GATE LEAD NO. 2 - DRAIN LEAD NO. 3 - SOURCE TERM. 4 - DRAIN

A

1

TERM. 4

SEATING PLANE

SYMBOL

A 0.086 0.094 2.19 2.38 -

A

1

b 0.028 0.032 0.72 0.81 3, 4

b

1

b

2

INCHES MILLIMETERS

NOTESMIN MAX MIN MAX

0.018 0.022 0.46 0.55 3, 4

0.033 0.040 0.84 1.01 3

0.205 0.215 5.21 5.46 3, 4

c 0.018 0.022 0.46 0.55 3, 4 D 0.270 0.290 6.86 7.36 E 0.250 0.265 6.35 6.73 -

e 0.090 TYP 2.28 TYP 5

J

1

e

1

H

1

J

1

0.180 BSC 4.57 BSC 5

0.035 0.045 0.89 1.14 -

0.040 0.045 1.02 1.14 6

L 0.355 0.375 9.02 9.52 -

L

1

0.075 0.090 1.91 2.28 2

NOTES:

1. These dimensions are within allowable dimensions of Rev. C of JEDEC TO-251AA outline dated 9-88.

2. Solder finish uncontrolled in this area.

3. Dimension (without solder).

4. Add typically 0.002 inches (0.05mm) for solder plating.

5. Position of lead to be measured 0.250 inches (6.35mm) from bottom of dimension D.

6. Position of lead to be measured 0.100 inches (2.54mm) from bottom of dimension D.

7. Controlling dimension: Inch.

8. Revision 2 dated 10-95.

10

RFD10P03L, RFD10P03LSM, RFP10P03L

TO-252AA

SURFACE MOUNT JEDEC TO-252AA PLASTIC PACKAGE

H

1

D

13

b

TERM. 4

b

3

BACK VIEW

E

b

2

L

2

b

1

e

1

L

3

0.070 (1.8)

0.063 (1.6)

0.090 (2.3)

MINIMUM PAD SIZE RECOMMENDED FOR SURFACE-MOUNTED APPLICATIONS

LEAD NO. 1 - GATE LEAD NO. 3 - SOURCE TERM. 4 - DRAIN

A

1

L

c

J

1

0.265 (6.7)

SEATING PLANE

L

1

0.265 (6.7)

0.118 (3.0)

0.063 (1.6)

0.090 (2.3)

INCHES MILLIMETERS

SYMBOL

NOTESMIN MAX MIN MAX

A 0.086 0.094 2.19 2.38 -

A

1

0.018 0.022 0.46 0.55 4, 5

b 0.028 0.032 0.72 0.81 4, 5

b

1

b

2

b

3

0.033 0.040 0.84 1.01 4

0.205 0.215 5.21 5.46 4, 5

0.190 - 4.83 - 2

c 0.018 0.022 0.46 0.55 4, 5 D 0.270 0.290 6.86 7.36 E 0.250 0.265 6.35 6.73 -

e 0.090 TYP 2.28 TYP 7

e

1

H

1

J

1

0.180 BSC 4.57 BSC 7

0.035 0.045 0.89 1.14 -

0.040 0.045 1.02 1.14 -

L 0.100 0.115 2.54 2.92 -

L

1

L

2

L

3

0.020 - 0.51 - 4, 6

0.025 0.040 0.64 1.01 3

0.170 - 4.32 - 2

NOTES:

1. These dimensions are within allowable dimensions of Rev . B of JEDEC TO-252AA outline dated 9-88.

2. L3 and b3 dimensions establish a minimum mounting surface for terminal 4.

3. Solder finish uncontrolled in this area.

4. Dimension (without solder).

5. Add typically 0.002 inches (0.05mm) for solder plating.

6. L1 is the terminal length for soldering.

7. P osition of lead to be measured 0.090 inches (2.28mm) from bottom of dimension D.

8. Controlling dimension: Inch.

9. Revision 6 dated 10-96.

11

TO-252AA

16mm TAPE AND REEL

RFD10P03L, RFD10P03LSM, RFP10P03L

330mm

22.4mm

13mm

50mm

16.4mm

COVER TAPE

1.5mm

DIA. HOLE

16mm

4.0mm

8.0mm

USER DIRECTION OF FEED

GENERAL INFORMATION

1. USE "9A" SUFFIX ON PART NUMBER.

2. 2500 PIECES PER REEL.

3. ORDER IN MULTIPLES OF FULL REELS ONLY.

4. MEETS EIA-481 REVISION "A" SPECIFICATIONS.

2.0mm

1.75mm

C

L

Revision 6 dated 10-96

All Harris Semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certiﬁcation.

Harris Semiconductor products are sold by description only. Harris Semiconductor reser ves the right to make changes in circuit design and/or speciﬁcations at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Harris is believed to be accurate and reliable. However, no responsibility is assumed by Harris or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Harris or its subsidiaries.

Sales Ofﬁce Headquarters

For general information regarding Harris Semiconductor and its products, call 1-800-4-HARRIS

NORTH AMERICA

Harris Semiconductor P. O. Box 883, Mail Stop 53-210 Melbourne, FL 32902 TEL: 1-800-442-7747 (407) 729-4984 FAX: (407) 729-5321

EUROPE

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SEMICONDUCTOR

12

ASIA

Harris Semiconductor PTE Ltd. No. 1 Tannery Road Cencon 1, #09-01 Singapore 1334 TEL: (65) 748-4200 FAX: (65) 748-0400

Datasheet RFP10P03L Datasheet (Fairchild Semiconductor)

Specifications and Main Features

Frequently Asked Questions

User Manual