Datasheet RF2908 Datasheet (RF Micro Devices)

RF2908

11

Typical Applications

• Digital Cordless Telephones

• Secure Communication Links

•WirelessLANs

Product Description

The RF2908 is a monolithic integrated circuit specifically
designed for direct-sequence spread-spectrum systems
operating in the 902MHz to 928M Hz ISM band. The part
includes a direct conversion receiver, quadrature demod­ulator, dual IF amplifiers with gain control and RSSI, on­chip programmable baseband filters, dual data compara­tors, and a serially programmable 86-channel PLL fre­quency synthesizer.Two cell or regulated three cell (3.6V
maximum) battery applicationsare supported by the part.
The part is also designed to operate in compliance with
FCC Part 15.247. The device is provided in 48-lead plas­tic LQFP packaging.

915MHZ SPREAD SPECTRUM RECEIVER WITH

PLL FREQUENCY SYN THESIZER

• Inventory Tracking

• Wireless Security

• Battery Powered Applications

.362
.346

7°MAX

0°MIN

.362
.346

.280
.272

.011
.007

.280
.272

.057
.053

.006
.002

.020

Optimum Technology Matching® Applied

Si BJT GaAs MESFETGaAs HBT
Si Bi-CMOS

ü

6

LNA IN

PLL

Freq. Synth.

Ref

Refer to the Detailed FunctionalBlock Diagramfor descriptionof fullfunctionality

LNA

2423

SiGe HBT

MOUT Q± INQ±

1,2

47,48

+45°

-45°

11,12 13,14

MOUT I± IN I±

IF Amp

IF Amp

RSSI

Gain Control

Si CMOS

Q Data Amp

I Data Amp

Functional Block Diagram

39

42

19

21

Q DATA

IF OUT Q

IF OUT I

I DATA

.007

.031
.021 MAX

Package Style: LQFP-48

Features

• FCC Part 15.247 Compliant

• Direct Conversion Receiver

• On-Chip 86 Channel Frequency
Synthesizer

• On-Chip Selectable IF Bandwidths

• 2.7V to 3.6V Operation

Ordering Information

RF2908 915MHz Spread Spectrum Receiver with PLLFre-

RF Micro Devices, Inc.
7628 Thorndike Road
Greensboro,NC 27409, USA

quency Synthesizer

Tel [phone]

Fax [phone]

http://www.rfmd.com

11

TRANSCEIVERS

Rev C1 010904

11-85

RF2908

Absolute Maximum Ratings

Parameter Ratings Unit

Supply Voltage -0.5 to +3.6 V
Control Voltages -0.5 to +3.6 V
Input RF Level +20 dBm

Output Load VSWR 50:1
Operating Ambient Temperature -40 to +85 ° C
Storage Temperature -40 to +150 °C

DC
DC

Caution! ESD sensitive device.

RF Micro Devices believes the furnished information is correct and accurate
at the time of this printing. However, RF Micro Devices reserves the right to
make changes to its products without notice. RF Micro Devices does not
assume responsibility for the use of the described product(s).

11

Parameter

Min. Typ. Max.

Overall

Frequency Range 902 to 928 MHz
Cascaded Voltage Gain 100 dB
Cascaded Noise Figure 6.0 8.0 dB
Cascaded Input IP

RX Sensitivity -100 dBm IF BW=960kHz, Freq=915MHz, S/N =8dB
LO Leakage -65 dBm At LNA IN
RSSI DC Output Range 0.35 to 3.1 V R

RSSI Sensitivity 30 mV/dB
RSSI Dynamic Range 60 65 dB

3

Specification

-12 dBm High Gain

+5.5 dBm Low Gain

Unit Condition

T=25°C, VCC=3.6V, Freq=915MHz

=51kΩ

LOAD

LNA and Mixer

Operating Frequency Range 902 to 928 MHz
Voltage Gain 22 dB
Noise Figure 6.0 8.0 dB
RF Input Impedance 50 Ω
RF Input VSWR 2:1
Input IP

3

Quadrature Phase Balance ±3 ±5 ° With expected LO amplitude and harmonic
Quadrature Amplitude Balance ±1 dB

Mixer Output Impedance 150 200 250 Ω Differential
DC Current Consumption 26 33 39 mA Operating at a 3.3V supply voltage.

-20 -12 dBm At maximum gain. ATTN=LOW
+5.5 dBm At minimum gain. ATTN=HIGH

content.

TRANSCEIVERS

11-86

Rev C1 010904

RF2908

Parameter

Min. Typ. Max.

Specification

Unit Condition

IF and Data Amplifiers

IF Frequency Range Note 1 9.6 MHz
VoltageGain 77 80 83 dB
Noise Figure 5 dB At maximum gain setting

35 dB At minimum gain setting

Input IP3 -65 dBm At maximum gain setting

+2 dBm At minimum gain setting
Output DC Offset 0 25 mV
Gain Control Ra nge 65 70 dB
Gain Control Voltage Range 1.2 2.0 V
Gain Control S ensitivity -0.08 dB/mV
VGA Output Voltage 500 mV

VGA D C Output Voltage 1.7 V
Output P1dB 1 1.64 V

RSSI Range 60 dB At maximum gain setting
RSSI Output Voltage Compli-

ance

Input Impedance 1.5 2 2.5 kΩ Differential

55 0.5 to 2.4 V Maximum RSSI is 2.5V or V

PP

PP

Driving a 5kΩ load

ever is less.

Note 1. The lower cutoff frequency is a func­tion of: a) input DC blocking cap size; b) DC
feedback capacitor; and, c) gain setting. But,
recommended component values will yield a
cutoff of <10kHz.

-0.3, which-

CC

Filters

Characteristics Five pole Bessel Five pole Bessel internal LPF.
Bandwidth 1, 2, 4, 8 MHz Selectable from 1, 2, 4, and 8MHz. Refer to
Passband Ripple 1 dB

Group Delay 100 ns At 8MHz, increasing as bandwidth

Ultimate Rejec t ion 80 100 dB

Three pole external LPF.
“IF Bandwidth Response” chart.

decreases.

Data Amplifiers

VoltageGain 100 dB
Bandwidth 10 MHz
Rise and FallTime 2 5 ns
Logic High Output V

Logic Low Output 0.3 V Can sink/source 1mA and maintain these

-0.3V V Can sink/source 1mA and maintain these

CC

logic levels.
logic levels.

PLL, Synthesizer,VCO and
LO

VCO Tuning Range 800 to 1200 MHz
VCO Sensitivity 20 30 40 MHz/V Determined by external resistor.
Charge Pump Current 100 µAKPD=100µA/2π=0.0159ma/2π rad
Reference Frequency Crystal 9.6 20 MHz
Reference Crystal Rs 60 80 Ω
Phase Noise -66 dBc/Hz 10kHz offset.

-96 dBc/Hz 100kHz offset.
LO Output Level -10 dBm Into 100Ω differential load
Lock Time 1.5 ms From sleep mode.
Step Size 300 kHz 86 channels in the 902MHz to 928MHz ISM

band.

11

TRANSCEIVERS

Rev C1 010904

11-87

RF2908

Parameter

Min. Typ. Max.

Specification

Unit Condition

Power Down Control

Logical Controls “ON” VCC-0.3V VCC+0.3V V Voltage supplied to the input

Logical Controls “OFF” 0 0.3 V Voltage supplied to the input
Control Input Impe dance >1 MΩ
Turn On Time 1 ms Reference Crys tal=9.6MHz. Dependent on

Turn Off Time 1 ms Reference Crystal=9.6MHz. Dependent on

RXtoTXandTXtoRXTime 100 µs

reference crystal. Higher frequencies reduce
turn on/off times.

reference crystal. Higher frequencies reduce
turn on/off times.

Power Supply

Voltage 2.7 3.3 3.6 V
Current Consumption 50 62 mA V

50 µAV
45 57 mA V

=3.3V; RXENABL=HIGH;

CC

PLLENABL=HIGH

=3.3V; Sleep Mode

CC

=3.3V; RXENABL=LOW;

CC

PLLENABL=HIGH

11

TRANSCEIVERS

11-88

Rev C1 010904

RF2908

Pin Function Description Interface Schematic

1MOUTQ­2MOUTQ+

3MIXVCC
4 MIX GND
5LNAGND
6LNAIN
7SWGND
8LNAVCC
9 SW GND2

10 ATTN

11 MOUT I+
12 MOUT I-

13 IN I+
14 IN I­15 GND2
16 DCFB I
17 VCC2

18 GND3
19 IF OUT I
20 VCC3
21 I DATA

22 RSSI I
23 OSC B

24 OSC E
25 LE
26 PLL CLK

27 PLL DATA

28 PLL GND
29 PLLD VCC
30 LO OUT B
31 RESNTR+

32 RESNTR­33 LO OUT
34 DO

The complementary quadrature phase signal output from the front-end
mixer. See pin 2.

The quadrature phase signal output from the front-end mixer.
Supply voltage for the front-end quadrat ure mixers.
Ground connection for the front-end quadrature mixers.
Ground connection for the low noise amplifier (LNA).
Input to the attenuator and LNA.
Ground connection for the input attenuator.
Supply voltage for the LNA.
Ground connection for the input attenuator.
Input attenuator control point. When connected “high”, the attenuator

adds 20dB of series attenuation. When connected “low”, the attenuator
adds 0dB of series attenuation.

The in-phase signal output from the front-end mixer.
The complementary in-phase signal output from the front-end mixer.

See pin 12.
Input for the in-phase IF channel.

Complementary input for the in-phase IF channel.
Ground for VCC2.
DC feedback capacitor for in-phase channel.
Powersupply for VGA amplifier 3, differential to single-ended converter,

and post filter.
Ground for VCC3.

Analog signal IF output for in-phase channel.
Power supply for data amplifier.
Logic-level data output for the in-phase channel. This is a digital output

signal obtained from the output of a Schmitt trigger.
Received signal strength indicator for the in-phase channel.

Base connection point for external reference crystal. The reference
crystal is connected between this pin and ground.

Emitter connection point for external reference crysta l. Feedback
capacitors are connected between this pin and ground.

Latches data entered into the serial port. Data is clocked into the latch
on the rising edge of LE. S ee table and timing diagram.

PLL shift register clock. The rising edges of this clocking signal load in
the serial data present at the PLL DATA input pin into the internal latch.
See table and timi ng diagram.

Input data for loading the counters. Clocked, seri al data at this po rt is
presented to the shift register, then to the latch, and finally to the
counter. Each clock transition sends a single bit to the on-board 7-bit
shift register. The MSB is loaded first. See table and timing diagram.

Ground connection for the PLL.
Supply voltage for the PLL.
Complementary local oscillator output. See pin 33.
This port is used to supply DC voltage to the VCO as well as tune the

center frequency of the VCO.
This is the complementary port to pin 31. Refer to pin 31.

Local oscillator output.
Connection point for the loop filter.

11

TRANSCEIVERS

Rev C1 010904

11-89

RF2908

Pin Function Description Interface Schematic

35 PLL ENABL

36 RX ENABL

37 BW SEL2
38 BW SEL1
39 Q DATA
40 RSSI Q

41 VREF
42 IF OUT Q
43 VGC
44 VCC1

45 DCFB Q
46 GND1
47 IN Q­48 IN Q+

This pin is used to power up or down the VCO and PLL. A logic high
(PLL ENABL>2.0V) powers up the VCO and PLL circuitry. A logic low
(PLL ENABL<1.0V) powers down the PLL and VCO.

Enable pin for the receiver circuits. RX ENABL>2.0V powers up all
receiver functions. RX ENABL<1.0V turns off all receiver functions
except the PLL functions and the RF mixer.

Bandwidth select logic input. Pin 37 and pin 38 provide a two bit control
word for the setting of the IF bandwidth. See Table1.

Bandwidth select logic input. Pin 37 and pin 38 provide a two bit control
word for the setting of the IF bandwidth. See Table1.

Logic-level data output for the quadrature channel. This is a digital out­put signal obtained from the output of a Schmitt trigger.

Received signal strength indicator for the quadrature channel.
Gain control reference voltage.
Analog signal IF output for quadrature channel.
Gain control voltage.
Power supply for bias circuits and VGA amplifiers for both the in-phase

and quadrature channels.
DC feedback capac itor for quadrature channel.

Ground for V CC1 for both the in-phase and quadrature channels.
Minus input for quadrature channel
Plus input for quadrature channel

11

Table 1: Bandwidth Selection Controls

BWSEL1 BWSEL2

Frequency
001MHz
012MHz
104MHz
118MHz

TRANSCEIVERS

IF

-3dB

11-90

Rev C1 010904

Table 2: Channel Plan

Data f, MHz Data f, MHz Data f, MHz Data f, MHz

0 902.4 22 909 44 915.6 66 922.2
1 * 23 909.3 45 915.9 67 922.5
2 903 24 909.6 46 916.2 68 922.8
3 903.3 25 909.9 47 916.5 69 923.1
4 903.6 26 910.2 48 916.8 70 923.4
5 903.9 27 910.5 49 917.1 71 923.7
6 904.2 28 910.8 50 917.4 72 924
7 904.5 29 911.1 51 917.7 73 924.3
8 904.8 30 911.4 52 918 74 924.6

9 905.1 31 911.7 53 918.3 75 924.9
10 905.4 32 912 54 918.6 76 925.2
11 905.7 33 912.3 55 918.9 77 925.5
12 906 34 912.6 56 919.2 78 925.8
13 906.3 35 912.9 57 919.5 79 926.1
14 906.6 36 913.2 58 919.8 80 926.4
15 906.9 37 913.5 59 920.1 81 926.7
16 907.2 38 913.8 60 920.4 82 927
17 907.5 39 914.1 61 920.7 83 927.3
18 907.8 40 914.4 62 921 84 927.6
19 908.1 41 914.7 63 921.3 85 927.9
20 908.4 42 915 64 921.6
21 908.7 43 915.3 65 921.9

RF2908

*Data 1 is invalid.

Timing Diagram

Minimum Times:

= 143 ns

t

CWH

= 143 ns

t

CWL

t

=74ns

EW

t

= 143 ns

ES

=36ns

t

CS

=36ns

t

CH

DATA

CLK

H

000 0 011

L

MSB LSB

H

L

t

LE

CWH

H

L

0

t

CWL

Example: Load Sequence for Channel #10 (905.4 MHz)

t

CS

t

CH

time

Decimal 10 = 0001010

MSB

LSB

Binary

11

...

...

t

ES

t

EW

TRANSCEIVERS

...

t

Rev C1 010904

11-91

RF2908

Differential Filter Design Information

Butterworth Response

11

100000

C1

L

C1

C2bw

------------------------------------- -

2 π fc RL⋅⋅ ⋅

L

1

-- -

10

⋅⋅

2

C2

12

RL

RL

Lbw RL 10

-----------------------------------

L

=;=;=

⋅⋅

2 π fc⋅⋅

6

12

1

C1bw

------------------------------------- -

-- -

10

⋅⋅

2

2 π fc RL⋅⋅ ⋅

RS

RS

C2

C1bw 4.5325 C2bw; 13.5691 Lbw; 0.1743===

RS

------ -

RS 125 RL; 1000

DifferentialLC Filter C omponent Values

(Butterworth Response)

; 0.125== =

RL

10000

1000

TRANSCEIVERS

C2 (pF)

C1 (pF)

L(µH)

Rev C1 010904

11-92

100

Component Value

10

1

1.E+05 1.E+06 1.E+07

Frequency

Differential Filter Design Information (Cont.)

Bessel Response

RF2908

100000

L

C1

C2bw

⋅⋅

------------------------------------- -

2 π fc RL⋅⋅ ⋅

C2

L

12

1

-- -

10

2

RL

RL

Lbw RL 10

-----------------------------------

L

=;=;=

C1

12

1

C1bw

------------------------------------- -

-- -

10

⋅⋅

2

2 π fc RL⋅⋅ ⋅

RS

RS

C2

C1bw 2.6163 C2bw; 13.6373 Lbw; 0.1083===

RS

------ -

RS 125 RL; 1000

DifferentialLC Filter C omponent Values

(Bessel Response)

; 0.125== =

RL

⋅⋅

2 π fc⋅⋅

6

11

Rev C1 010904

10000

1000

100

Component Value

10

1

1.E+05 1.E+06 1.E+07

Frequency

TRANSCEIVERS

C2 (pF)

C1 (pF)

L(µH)

11-93

RF2908

IN Q+

48 454647

Pin Out

IN Q-

GND1

DCFB Q

VCC1

VGC

IF OUT Q

VREF

RSSI Q

QDATA

BW SEL1

BW SEL2

44 43 42 41 40 39 38 37

11

MOUT Q-

MOUT Q+

MIX VCC

MIX GND

LNA GND

LNA IN

SW GND

LNA VCC

SW GND2

ATTN

MOUT I+

MOUT I-

1

2

3

4

5

6

7

8

9

10

11

12

13 161514 17 18 19 20 21 22 23 24

IN I-

IN I+

GND2

VCC2

DCFB I

GND3

VCC3

IF OUT I

IDATA

36

RX ENABL

35

PLL ENABL

34

DO

33

LO OUT

32

RESNTR-

31

RESNTR+

30

LO OUT B

29

PLLD VCC

28

PLL GND

27

PLL DATA

26

PLL CLK

25

LE

RSSI I

OSC B

OSC E

TRANSCEIVERS

11-94

Rev C1 010904

Detailed Functional Block Diagram

RF2908

7-Bit Shift

Register

VCC3

LNA VCC

ATTN

810

LNA

6

LNA IN

SW GND1

SW GND2

LNA GND

RX ENABL

BW SEL2
BW SEL1

MIX VCC
MOUT I+

7

9
5

35

PLL ON

36
37
38

3

11

MOUT I-

12

IN I+

13

IN I- GND1

OSC B

23

OSC E

24

-0.5/-20.5

Chip

Control

Ref. Osc.

5-bit Counter

MIX VCC

MOUT Q+

MOUT Q-

1 2 48 47 444

+45°

-45°

300 kHz

/32

902-928

MHz

30 31 32 33 2928

VCO

IN Q-

32/33

VCC1

Phase

Detector

Charge Pump

7-Bit Counter

/94

300 kHz

7-Bit Swallow

Counter

0-85

IN Q+

0-25 dB 0-20 dB -12-+12 17dB 6dB

Prescaler

VCC2

17 20

7

7-Bit

Latch

7

39

42
45
22
41
40
43

21

19
18
16
15
4614
34
26

25
27

Q DATA

IF OUT Q
DCFB Q
RSSI I
VREF
RSSI Q
VGC

I DATA

IF OUT I
GND3
DCFB I
GND2

DO
PLL CLK
LE
PLL DATA

Rev C1 010904

LO OUT B

RESNTR+

LO OUT

RESNTR-

PLLD GND

11

PLLD VCC

TRANSCEIVERS

11-95

RF2908

Application Schematic

915MHz

0.1µF

+3.3V REG

10Ω

0.01µF 47pF

6.8nH

Refer to Filter Design

Information for

Component Values

L

L

+3.3V REG

10Ω

0.01µF 47pF

6

-0.5/-20.5

7

9

5
35
36

Chip

Control

37
38

4
11

CC

12

0.1µF

13

Ref. Osc.

23

100pF

24

100pF

902-928 MHz VCO

Refer t o Filter Design Information

for Component Values

810

LNA

+45°

-45°

5-bit Counter

/32

L

CC

L

0.1µF

1 2 47 48 443

0-25 dB 0-20 dB -12-12dB 17dB 6dB

300 kHz

Prescaler

32/33

0.1µF

0.1µF 47pF

Phase

Detector

Charge Pump

7-Bit Counter

/94

+3.3V REG

10Ω

300 kHz

7-Bit Swallow

+3.3V REG

10Ω

17 20

Counter

7

0-85

0.1µF 47pF

7

7-Bit
Latch

7-Bit Shift

Register

+3.3V REG

10Ω

0.1µF 47pF

39

42

0.27µF

45
22

1µF

41
40
43

21

19
18
16
15
4614
34
26
25

27

56pF

56pF

0.27µF

11

30 31 32 33 2928

+3.3V REG

0.1µF

47pF

10Ω

22kΩ

220pF

Loop Filter

2.2nF

6.8nH

6.8nH

2kΩ

47pF0.1µF 4.7µF

TRANSCEIVERS

11-96

Rev C1 010904

J9

Q MIX OUT

VCC

J1

RF IN

VCC

ATTN

J2

I MIX OUT

RF2908

Evaluation Board Schemati c

(Download Bill of Materials from www.rfmd.com.)

ENBL

BW SEL1

BW SEL2

LO OUT

RESNTR-

RESNTR+

LO OUT B

PLLD VCC

PLL GND

PLL DATA

PLL CLK

OSC B

P4-1

NC

P8-1

P8-3

C44

68 pF

RX

DO

LE

OSC E

33 pF

C2

68 pF

9.6 MHz

R7

Ω

0

J8

IF OUT Q
VREF

Q RSSI

J7

Q DATA
BW SEL1

BW SEL2

36

35

34

33

32

31

30

29

28

27

26

25

C1

X1

P4

1
2
3

P8

1
2
3

I RSSI

C43

68 pF

IF VCC

I DATA

DCFBI
GND

BW SEL1
GND
BW SEL2

L3

5.6 nH
L2

5.6nH

J4

C14

220 pF

R4

Ω

33 k

C11

47 pF

C9

10 nF

C5

47 pF

C3

10 nFC422 pF

P5

AMP D-Sub

1

NC

2

P5-2

3

P5-3

4

NC

5

NC
NC

6

NC

7

P5-8

8
9

4.7 nF

C12

Open

C6

Open

C15

R7

0

C10

22 pF

R3

0

27 k

R13

27 k

R11

27 k

Ω

Ω

R9

Open

Open

Ω

Ω

Ω

LE
PLL DATA

PLL CLK
GND

C13

50

50

12 k

12 k

12 k

RX ENABL
PLL ENABL

J6

LO OUT

Ω µ

strip

PLL VCC

R2

Ω

1k

Ω µ

strip

J5

C7

R2

1k

R8

R12

R10

LO OUTB

PLL VCC

C45

Ω

µ

F

1

PLL DATA

Ω

PLL CLK

Ω

LE

Ω

11

TRANSCEIVERS

GC

IF VCC

C46

µ

F

1

C22

IN Q+

IN I+

C20

220 nF

C32

10 nF

220 nF

44 43 42 41 40 39 38 37

IN Q-

GND1

IN I-

GND2

P2

P2-3

P6

P6-1

P6-3

VGC

VCC1

DCFB Q

DCFB I

1
2
3

1
2
3

VCC2

IF VCC
GND
GC

PLL VCC
GND
PLL ON

GND3

IF OUT Q

IF OUT I

P3-1

P3-3

P7-1

P7-3

DCFBQ

C23

L8

100 nF

µ

H

10

C25

C26

1nF

470 pF

L9

C24

µ

C33

10 nF

C35

10 nF

C16

470 pF

C29

100 pF

10

C34

22 pF

C36

22 pF

10

10

P1-1

P1-3

L6

L7

µ

µ

C30

10 nF

T2
5:1

T1
5:1

C27

100 pF

C41

10 nF

C40

10 nF

R6

Ω

10

R5

Ω

10

C37

10 nF

C38

10 nF

2908400-

C28

10 nF

C42

50

50

50

10 pF

Ω µ

strip

L5

8.2 nH

Ω µ

strip

Ω µ

strip

C39

10 pF

P2-1

48 454647

H

100 nF

1

MOUT Q­MOUT Q+

2

MIX VCC

3

MIX GND

4

LNA GND

5

LNA IN

6

SW GND

7

LNA VCC

8

SW GND2

9

ATTN

10

MOUT I+

11

MOUT I-

12

C19

13 161514 17 18 19 20 21 22 23 24

H

100 nF

C18

H

100 nF

IF VCC
I DCFB

J3

IF OUT

C31

100 pF

P1

1

DCFBQ

2

GND
VREF

3

VREF

VCC3

P3

1
2
3

P7

1
2
3

RSSI Q

IDATA

Q RSSI
GND
I RSSI

ATTN
GND
RX ENABL

QDATA

RSSI I

C21

47 nF

PLL ENABL

Rev C1 010904

11-97

RF2908

Evaluation Board Layout

Board Size 3.050” x 3.050”

Board Thickness 0.032”, Board Material FR-4, Multi-Layer

Assembly

11

TRANSCEIVERS

11-98

Rev C1 010904

Top

RF2908

Mid 1

11

TRANSCEIVERS

Rev C1 010904

11-99

RF2908

Mid 2

11

Back

TRANSCEIVERS

11-100

Rev C1 010904

65.0

55.0

45.0

35.0

25.0

RF2908

RF2908 IF Bandwidth Response

15.0

Gain (dB)

5.0

-5.0

-15.0

-25.0

-35.0

0.1 1.0 10.0 100.0

BW_SEL (0-0)

BW_SEL (0-1)

BW_SEL (1-0)

BW_SEL (1-1)

IF Frequency (MHz)

11

Rev C1 010904

TRANSCEIVERS

11-101

RF2908

IIP3 versus Voltage Gain

10.0

0.0

-10.0

-20.0

-30.0

-40.0

IP3 (dB)

-50.0

-60.0

-70.0

-80.0

0.0 10.0 20.0 30.0 40.0 50. 0 60.0 70.0 80.0 90.0

VoltageGain(dB)

Voltage Gain versus Gain Control Voltage

90.0

80.0

70.0

60.0

-40°C
+25°C
+100°C

-40°C
+25°C
+100°C

Noise Figure versus Voltage Gain

40.0

35.0

30.0

25.0

20.0

15.0

Noise Figure (dB)

10.0

5.0

0.0

0.0 10.0 20.0 30.0 40.0 50.0 60.0 70.0 80.0 90.0

(Non-Matched Input Z)

Voltage Gain (dB)

-40°C
+25°C
+100°C

11

50.0

40.0

Voltage Gain (dB)

30.0

20.0

10.0

0.0

1.21.31.41.51.61.71.81.9 2

GainControl Voltage(V)

TRANSCEIVERS

11-102

Rev C1 010904