Datasheet RF2690, RF2690PCBA Datasheet (RF Micro Devices)

7-39
7
QUADRATURE
DEMODULATORS
Preliminary
Product Description
Ordering Information
Typical Applications
Functional Block Diagram
RF Micro Devices, Inc. 7628 Thorndike Road Greensboro,NC 27409, USA
Tel (336) 664 1233
Fax (336) 664 0454
http://www.rfmd.com
Optimum Technology Matching® Applied
Si BJT GaAs MESFETGaAs HBT Si Bi-CMOS
ü
SiGe HBT
Si CMOS
7
GND
Gain
Control
Div
4
I/Q Cal
Mode Control
&Biasing
8
LO
4W-CDMA IN+
2NC
6
VCC
20
VGC21VGC1
17
IF+
14 I OUT+
15 ENCAL 16 FCLK
11 Q OUT-
19 VREF2V
10
EN RX
3NC
5W-CDMA IN-
9
EN WUP
12 Q OUT+
13 I OUT-
18
IF-
RF2690
W-CDMA RECEIVE AGC
AND DEMODULATOR
• W-CDMA Systems
The RF2690 is an integrated complete IF AGC amplifier and quadrature demodulator designed for the receive section of W-CDMA applications. It is designed to amplify received IF signals, while providing 70dB of gain control range, a total of 90dB gain, and demodulation to base­band I and Q signals. This circuit is designed as part of RFMD’s single mode W-CDMA chipset, which includes the RF9678 as modulator and IFAGCand theRF2638 as upconvertor. The IC is manufactured on an advanced 25 GHz F
T
Silicon Bi-CMOS process, and is packaged in
a 20-pin, 4mmx 4mm, leadless chip carrier.
• Digitally Controlled Power Down Mode
• 2.7V to 3.3V Operation
• Digital LO Quadrature Divide-by-4
•IFAGCAmpwith70dBGainControl
• 80dB Maximum Voltage Gain
RF2690 W-CDMA Receive AGC and Demodulator RF2690 PCBA Fully Assembled EvaluationBoard
7
Rev A4 010918
1.00
0.90
4.00 sq.
0.60
0.24 typ
3
0.20
0.75
0.50
0.23
0.13
4PLCS
0.50
2.10 sq.
0.65
0.30
4PLCS
0.05
12°
MAX
Dimensionsin mm.
Note orientation of package .
NOTES:
Package Warpage: 0.05 mm max.
4
Die Thickness Allowable: 0 .305 mm max.
5
Pin 1 identifier must existon top surface of package by identification mark or feature on the package body. Exact shape and size is optional.
2
Shaded lead is Pin 1.
1
Dimension applies to p lated terminal: to be measured between 0.02 mm and 0.25 mm from terminal end.
3
Package Style: LCC, 20-Pin, 4x4
Preliminary
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QUADRATURE
DEMODULATORS
Absolute Maximum Ratings
Parameter Rating Unit
Supply Voltage -0.5 to +5 V
DC
Power Down Voltage(VPD) -0.5toVCC+0.7 V
DC
Input RF Power +3 dBm Ambient Operating Temperature -40 to +85 °C Storage Temperature -40 to +150 °C
Parameter
Specification
Unit Condition
Min. Typ. Max.
Overall Inputs and AGC
Temp=25°C, VCC=3V, Z
LOAD
=60kΩ diff.,
LO =760MHz@-10dBm, Z
SOURCE
=500
diff. IF Frequency 190 MHz W-CDMA IF Input Impe dance 1200 Single-ended
2400 Balance. An external resistor across thedif-
ferential input is used to define the input
impedance. LO Frequency 760 MHz LO Input Level -20 -10 0 dBm LO Input Impedance 50 Single-ended. Maximum Voltage Gain 76 81 dB Pin-to-Pin voltage gain.
Note: 10dB additional voltage gain in input
match 50to 500Ω. Minimum Voltage Gain 5 12 15 Gain Variation versus V
CC
and
Temperature
-3 +1+3dB
Gain Control Voltage 0.3 2.4 V Defined with external 10kresistor in series
with V
GC1
pin. Analog gai n control.
Input IP3 Blockers at 10MHz and 20MHz offset.
-52 -48 dBm Maximum Gain. V
GC
=2.4V
-5 0 dBm Minimum Gain. V
GC
=0.3V
Noise Figure 5 dB Maximum Gain. V
GC
=2.4V
Inband Output 1dB Compression 1.5 2.0 V
P-P
Measured differentia lly. Compression Out of band blocker causing 1dB of inband
gain compression. Blocker at 5MHz.
-48 dBm Maximum Gain. V
GC
=2.4V
-17 dBm Minimum Gain. V
GC
=0.3V
Butterworth thirdorder, F
C
2.5M+10%
Baseband 3dB Bandwidth 2.25 2.5 2.75 MHz
Calibrated. F
CLK
=13MHz
Sideband Suppression 27 dB A measure of IQ gain match and IQ quadra-
ture accuracy. Measured for baseband fre-
quencies 100kHz to 2.5MHz. DC Offset +
40 mV
Baseband External Load 20 60 k Resistive Load Impedance.
Differentially across pins.
5 pF Capacitive Load Impedance.
To ground. Output DC Voltage V
CC
-1.3 VCC-1.6 VCC-1.9 V IQ Amplitude Balance +0.2 +0.5 dB VGC=0.3V,PIN=-40dBm IQ Phase Balance +
2+5 degree VGC=0.3V,PIN=-40dBm
Caution! ESD sensitive device.
RF Micro Devices believes the furnished information is correct and accurate at the time of this printing. However, RF Micro Devices reserves the right to make changes to its products without notice. RF Micro Devices does not assume responsibility for the use of the described product(s).
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QUADRATURE
DEMODULATORS
1
Bondout option available for 15.36MHz, 18MHz and 19 MHz.
Parameter
Specification
Unit Condition
Min. Typ. Max.
Auto Calibration
F
CLK
Input Frequency
1
13 MHz
F
CLK
Signal Level 0.4 1.0 V
P-P
F
CLK
Pin Input Impedance 20 k Single-ended.
Calibration Time 200 us Current, Auto Cal. 1 mA Disabled after calibration. Current, Once Auto Cal Finished 1 uA CALEN TBD
DC Specifications
Supply Voltage 2.7 3.0 3.3 V Current Consumption
Power Down <1 µA W-CDMA Warm-up 5 mA W-CDMA 8 mA
Logic Levels
V
EN
High Voltage 1.8 V
CC
V
V
EN
Low Voltage 0 0.5 V
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QUADRATURE
DEMODULATORS
Auto Calibration Mode
The filters are automatically tuned when the ENCAL pin goeshigh. The filters are reset toa nominal value whenever the ENCAL pin goes low. The auto calibration circuitry is independentof the EN WUP and the EN RX control pins. The EN RX and ENCAL pins can be connected together if desired.
Mode Control Truth Table
Logic
Mode EN RX EN WUP Power Down 0 X W-CDMARX Warm-Up 1 0 W-CDMA RX 1 1
EN RX Chip Enable If EN RX=0, then entire IC i s powered down. EN WUP Warm-up Enable If EN WUP=0, then IC is in warm-up mode.
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DEMODULATORS
Pin Function Description Interface Schematic
1VGC1
Analog gain control. Validcontrol voltageranges are from 0.5V to 2.5 V. These voltages are valid with a 10kresistor in series with GC pin.
2NC
Unused. Connect to signal ground in application.
3NC
Unused. Connect to signal ground in application.
4W-CDMA
IN+
W-CDMA balanced input pin. This pin is internally DC-biased and should be DC-blocked if connected to a device with a DC level present. For single-ended input operation, one pin is used as an input and the other W-CDMA input is AC coupled to ground. The balanced input impedance is 2.4k, while the single-ended input impedance is 1.2kΩ.
5W-CDMA
IN-
Same as pin 4, except complementary input. See pin 4.
6VCC
Supply
7GND
Connect to ground.
8LO
LO input pin. This input is internal ly DC-biased and should be DC­blocked if connected to a device with DC present. The frequency of the signal applied to this pin is internally divided by a factor of four, hence the LO applied should be four times the frequency of the IF.
9ENWUP
Warm-up mode enable. The input LO buffers and divider chains are enabled. When logic “low” (<
0.5V), chip is in warm-up mode. When
logic “high” (VCC-0.3V), chip is in W-CDMA RX mode.
10 EN RX
Chip enable. Power down. When logic “low” (<0.5V), all circuits are turned off. When logic “high” (VCC-0.3V), all circuits are operating.
11 Q OUT-
Complementary output to Q OUT+.
12 Q OUT+
Balanced baseband output of Q mixer. This pin is internally DC-biased and should be DC-blocked externally. The output may be used single­ended by leaving one of the pins unconnected, however half of the out­put voltage will be lost.
13 I OUT-
Complementary output to I OUT+.
14 I OUT+
Balanced baseband output.
15 ENCAL
Calibration enable.
16 FCLK
F
CLK
clock reference for the automatic calibration circuitry.
17 IF-
Complementary output to IF+.
18 IF+
IF test point output. This balanced node is pinned out to allow for moni­toring of the AGC output signal as it enters the demodulat or. During normal operation, this pin and its complementary output should be left floating and not connected.
1200 1200
W-CDMA IN+
BIAS BIAS
W-CDMA IN-
150 µA
QOUT-
QOUT+
V
CC
V
CC
150 µA
150 µA
IOUT-
IOUT+
150 µA
V
CC
V
CC
20 k
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QUADRATURE
DEMODULATORS
Pin Function Description Interface Schematic
19 VREF2V
2V voltage reference decouple (i.e., 10nF to ground).
20 VGC2
Gain control decouple (i.e., 10nF to ground).
Pkg
Base
Die
Flag
Ground.
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QUADRATURE
DEMODULATORS
Application Notes
Voltage Gain Measurement Set-up
The evaluation board uses a unity voltage gain Op-Amp to simulate the 60kdifferential load impedance condition for thechip.The50Ω output impedance of Op-Amp makes the use of a 50Ω spectrum analyzer power measurement possi- ble. The power gain measured will be considered as RAW Gain. The input impedance of the chip is 500differential by adding a parallel 680resistor. The input transformer matches 50 to 500and results in 10dB difference between voltage gain and power gain, hence, the voltage gain of the chip is RAW G ain minus 10dB. Because the input trans­former loss is 0.8dB, it needs to be added to the gain. Since the Op-Amp has the unity voltage gain, the voltage at the evaluation board output is the same as the voltage at chip I or Q output. Therefore,the voltage gain of the chip with 60k load can be calculated by
Gv=RAW Gain-10+0.8(dB)
Input IP3 Measurement
The input IP3 measurement is based on a two tone inter-modulation test condition from the 3GPP standard, which spec­ifies two tones with offset frequencies at 10MHz and 20MHz. Due to the on-chip baseband filtering, the two tone output is attenuated and cannot be seen. Since the only parameter observable is the IM3 product, the input IP3 then is calcu­lated by
IIP3=Pin+0.5*(P in+RAW Gain-IM3)
Noise Figure Measurement
The noise figure measurement is based on the noise figure definition NF=N
O-NI
-Gain, where NOis the output noise
density, N
I
is the input noise density (-174dBm/Hz when no input signal is applied) and Gain is the RAW Gain. The out-
put noise density N
O
is measured at 1MHz offset when no signal input is applied. The NF is calculated by NF=NO-
174 dBm/Hz-RAW Gain. Since the I and Q re-combination will provide 3dB extra for signal-to-noise ratio, the actual
noise figure is should be reduced by 3 dB. In addition, noise figure should be reduced by the input transformer loss of
0.8 d B. Therefore, the NF is calculated by NF=N
O
+174-RAW Gain-3-0.8(dB)
1dB Gain Compression Point Voltage at Baseband Output
The device has a relativelyconstant1dB gain compression point versus V
GC
. Gain compression is tested with a CW sig-
nal with 60kload differential.
How to Calculate the Power Gain of the Demodulator
In the system analysis for cascaded gain, noise and IP,it is often required to calculate the power gain of the demodulator chip itself in matched load condition. Below is an example on how to determine this power gain value.
For this example, the load impedance is 60kdifferential, the output AC impedance of the I or Q port is 500 ,themea­sured RAW Gain is 95dB.
First, the power gain from the input of the chip to the input of Op-Amp needs to be calculated. Since the voltage at the 50 load and the voltage at Op-Amp input are the same, the difference of the power gain across the Op-Amp is the ratio of load impedances. Hence, the power gain to the Op-Amp input is 95dB-10log(60000/50)=95-30=65dB.
Second, the power gain of the demodulator itself with matched load is calculated. The mismatch coefficient a is deter­mined by the mismatch coefficient equation
α 10
4R
SRL
RSRL+()
2
--------------------------
log 10
4 500 60000
⋅⋅
500 60000+()
2
-------------------------------------
log 15dB== =
Preliminary
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QUADRATURE
DEMODULATORS
Since the power gain to the input of the Op-Amp GP’=αGP, where GPis the power gain of demodulator for matched load. Therefore, the demodulator power gain is 65+15=80dB.
AC Coupling in Evaluation Board
The output I and Q baseband signal is AC coupled for evaluation purposes only. T he high-pass corner frequency is at 1/(2π RC)=1/(6.28 *30kΩ*100nF)=56Hz.
I and Q Output DC Voltage and Its Offset
Although the I and Q output is AC coupled on the evaluation board, in most applications, it would be DC coupled to the ADC input buffer. The DC voltage at the IC output is V
CC
-1.6V with a possible variation of ±0.3V due to temperature and
tolerance. The differential circuit asymmetry would cause common mode DC offset to the extent of ±40mV.
Baseband Filter Calibration Process
The BB (baseband) filter calibration process is same for both WCDMA and GSM/DCS. After calibration is done, the WCDMA mode sets the circuitry to have a 3dB bandwidth of 2.5 M Hz, the GSM/DCS mode (if the chip has GSM/DCS mode) sets the circuitry to have a 3dB bandwidth of 250kHz.
The BB filter in the I and Q path needs to be calculated every time after power down. When the FCLK pin is connected to a signal generator with 0dBm output level at 13.0MHz, a logic high at CALEN pin for 200µs will calibrate the filter to have
2.5MHz bandwidth with 10% accuracy when WCDMA mode is set, or to 250kHz bandwidth with 10% accuracy when GSM mode is set. The calibration is done when the chip is powered on only. Calibration is independent from all other conditions,e.g. the chip enable could be off.
The calibration circuitry consumes 400µA. When the calibration sequence is complete after 200µs, the I
CC
drops to
0mA. The 3dB bandwidth is defined to be from the reference level at 1MHz for WCDMA and at 50kHz for GSM/DCS. The 3dB
bandwidth is independent of V
GC
and VCC.
The filter can also be calibrated with different clock frequencies from 10MHz to 3 0MHz to tune the bandwidth over -40% to +60% from its default 3dB bandwidth (2.5MHz for WCDMA and 250kHz for GSM). The 3dB bandwidth is linear with clock frequency.
Preliminary
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QUADRATURE
DEMODULATORS
Pin Out
19
VREF2V
18 17
IF-16FCLK
14
13
12
10
EN RX
98
LO
7
GND
5
4
3
2NC
1VGC1
* *
* *
20
VGC2VCC
6
11 Q OUT-
15 ENCAL
*
Represents "GND".
NC
W-CDMA IN+
W-CDMA IN-
EN WUP
QOUT+
IOUT-
IOUT+
IF+
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QUADRATURE
DEMODULATORS
Applicatio n Schematic
1
3
6
4
5
2
7 8 9 10
1920 16
13
15
14
10 nF
10 k
10 nF
VGC
100 nF
V
CC
IOUTN
EN RX
10 nF
1nF
IOUTP
18 17
12
11
10 nF
VREF 2V
10 pF
FCLK
ENCAL
100 nF
100 nF
QOUTN
QOUTP
100 nF
EN WUP
LO IN
2.4 kBalanced
10 nF
W-CDMA
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QUADRATURE
DEMODULATORS
Evaluation Board Schematic
(Download Bill of Materials from www.rfmd.com.)
Drawing 2690400 Rev-
19 18 17 16
14
13
12
10987
5
4
3
2
1
* *
* *
20
6
11
15
R1
10 k
VGC
C2
5.1 pF
C4* DNI
50 Ωµstrip
J2
WCDMA
C6
100 pF
R7
680
L2
150 nH
C10
10 nF
VCC ENWUP
C23*
DNI
C20
100 pF
C24*
DNI
50 Ωµstrip
J4
LO IN
ENRX TP7
QOUTN
TP6
QOUTP
TP5
IOUTN
TP4
IOUTP
R12*
DNI
C12
100 nF
R2
10 k
C13
100 nF
R3
10 k
R14
20 k
32+
-
C14
100 nF
+5V
7
4
8
5
U2
R15
20 k
6
CLC426
R18
51
50 Ωµstrip
J5
IOUT
C15
100 nF
-5V
R13*
DNI
C18
100 nF
R4
10 k
C19
100 nF
R5
10 k
R16
20 k
32+
-
C16
100 nF
+5V
7
4
8
5
U3
R17
20 k
6
CLC426
R19
51
50 Ωµstrip
J6
QOUT
C17
100 nF
-5V
ENCAL
C9
100 pF
C8
1nF
TP1
VREF2V
TP2
IFP
TP3
IFN
C11
10 pF
J3
FCLK
CON3
JP3
+5V
-5V
1 2 3
C21
1uF(16V)
+
C22
1 uF(16V)
+
HDR 8
8 7 6 5 4 3 2 1
JP1
ENRX ENCAL ENWUP
VCC
VGC
C7
1uF
+
R101MR91MR8
1M
Preliminary
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QUADRATURE
DEMODULATORS
Evaluation Board Layout
Board Size 3.1” x 3.0”
Board Thickness 0.032”, Board Material FR-4
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QUADRATURE
DEMODULATORS
Preliminary
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QUADRATURE
DEMODULATORS
NF versus V
GC
IF Freq. 190MHz, LO Freq. 760MHz @ -10dBm, VCC=3.0, VGC=2.4to 0.3V)
0.0
10.0
20.0
30.0
40.0
50.0
60.0
70.0
0.3 0.7 1.1 1.5 1.9 2.3
Vgc (V)
NF (dB)
NF[dB]
VoltageGain versus VGC(Temp. +25oC, - 40oC, +85oC)
(IF Freq. 190MHz, LOFreq. 760MHz @ -10dBm,VCC=2.7V,VGC=2.4V to 0.3V)
0.0
10.0
20.0
30.0
40.0
50.0
60.0
70.0
80.0
90.0
0.20.40.60.81.01.21.41.61.82.02.22.4
VGC(V)
Voltage Gain (dB)
Gain @2.7V,Temp.+25C Gain @2.7V,Temp.- 40C Gain @2.7V,Temp.+85C
Voltage Gain versus P
OUT
(1dB Compression)
(VCC=3.0V, VGC=2.4V,IF=191MHz, LO=760MHz @ -10dBm)
70.0
71.0
72.0
73.0
74.0
75.0
76.0
77.0
78.0
79.0
80.0
81.0
500 600 700 800 900 1000 1100 1200 1300 1400 1500 1600 1700
PowerOut (mV-peak)
Voltage Gain (dB)
Voltage Gain [dB]
W-CDMA Baseband Filter Response (Calibrated)
(IF=190MHz to 195MHz, LO=760MHz @ -10dBm, VCC=3.0V, VGC=2.4V)
-1.0
0.0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
0.00.51.01.52.02.53.03.5
Frequency(MHz)
Amplitude (dBm)
PowerOut[dBm]
IGCversus V
GC
(IF Freq. 190MHz LO Freq. 760MHz VCC=3.0V Temp. 25oC)
-25.0
-20.0
-15.0
-10.0
-5.0
0.0
5.0
10.0
15.0
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4
VGC(V)
I
GC
(uA)
Igc [uA]
Voltage Gain versus VGC(Temp. +25oC, - 40oC, +85oC)
(IFFreq.190MHz, LOFreq.760MHz @-10dBm,VCC=3.0V, VGC=2.4V to 0.3V)
0.0
10.0
20.0
30.0
40.0
50.0
60.0
70.0
80.0
90.0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4
VGC(V)
Voltage Gain (dB)
Gain @3.0V,Temp.+25C Gain @3.0V,Temp.- 40C Gain @3.0V,Temp.+85C
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DEMODULATORS
Voltage Gain versus VGC(Temp. -40oC)
(IF Freq. 190MHz, LO Freq. 760MHz @ -10dBm, VCC=3.3V, 3.0V,2.7V,VGC=2.4V to 0.3V)
0.0
10.0
20.0
30.0
40.0
50.0
60.0
70.0
80.0
90.0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4
VGC(VGC)
Voltage Gain (dB)
Gain @3.3V,Temp.- 40C Gain @3.0V,Temp.- 40C Gain @2.7V,Temp.- 40C
VoltageGain versus VGC(Temp.+25C, - 40C, +85oC)
IF Freq. 190MHz,LOFreq. 760MHz @ -10dBm, VCC=3.3V,VGC=2.4V to 0.3v)
0.0
10.0
20.0
30.0
40.0
50.0
60.0
70.0
80.0
90.0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4
VGC(V)
Voltage Gain (dB)
Gain @3.3V,Temp.25C Gain @3.3V,Temp.-40C Gain @3.3V,Temp.+85C
VoltageGain versus VGC(Temp. 25oC)
(IF Freq. 190MHz, LO Freq. 760MHz @ -10dBm, VCC=3.3V, 3.0 V, 2.7V & VGC=2.4V to 0.3V)
0.0
10.0
20.0
30.0
40.0
50.0
60.0
70.0
80.0
90.0
0.30.50.70.91.11.31.51.71.92.12.32.5
VGC(V)
Voltage Gain (dB)
Gain @3.3V,Temp.25C Gain @3.0V,Temp.25C Gain @2.7V,Temp.25C
VoltageGain versus VGC(Temp. +85oC)
(IF Freq. 190MHz, LO Freq. 760MHz @ -10dBm, VCC=3.3V, 3.0V,2.7V,VGC=2.4V to 0.3V)
0.0
10.0
20.0
30.0
40.0
50.0
60.0
70.0
80.0
90.0
0.20.40.60.81.01.21.41.61.82.02.22.4
VGC(V)
Voltage Gain (dB)
Gain @3.3V,Temp.+85C Gain @3.0V,Temp.+85C Gain @2.7V,Temp.+85C
IIP3 versus VGC(Temp. +25oC, - 40oC, +85oC)
(IF Freq.190MHz, LO Freq. 760MHz @ -10dBm, VCC=2.7V, VGC=2.4Vto 0.3V)
-60.0
-50.0
-40.0
-30.0
-20.0
-10.0
0.0
10.0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4
VGC(V)
IIP3 (dBm)
IIP3 @2.7V,Temp.+25C IIP3 @2.7V,Temp.-40C IIP3 @2.7V,Temp.+85C
IIP3 versus VGC(Temp. +25oC, - 40oC, +85oC)
IFFreq. 190MHz, LOFreq.760MHz @ -10dBm,VCC=3.0V, VGC=2.4V to 0.3V)
-60.0
-50.0
-40.0
-30.0
-20.0
-10.0
0.0
10.0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4
VGC(VGC)
IIP3 (dBm)
IIP3@3.0V,Temp.25C IIP3@3.0V,Temp.- 40C IIP3@3.0V,Temp.+85C
Preliminary
7-54
RF2690
Rev A4 010918
7
QUADRATURE
DEMODULATORS
IIP3 versus VGC(Temp. +25oC, - 40oC, +85oC)
(
IFFreq.190MHz, LOFreq.760MHz @ -10dBm, VCC=3.3V, VGC=2.4V to 0.3V)
-60.0
-50.0
-40.0
-30.0
-20.0
-10.0
0.0
10.0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4
VGC(V)
IIP3 (dBm)
IIP3 @3.3V,Temp.25C IIP3 @3.3V,Temp.- 40C IIP3 @3.3V,Temp. +85C
IIP3 versus VGC(Temp. 25oC)
(IF Freq. 190MHz, LO Freq. 760MHz @ -10dBm, VCC=3.3V ,3.0V,2.7V,VGC=2.4V to 0.3V)
-50.0
-45.0
-40.0
-35.0
-30.0
-25.0
-20.0
-15.0
-10.0
-5.0
0.0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4
VGC(V)
IIP3 (dBm)
IIP3@3.3V,Temp.25C IIP3@3.0V,Temp.25C IIP3@2.7V,Temp.25C
IIP3 versus VGC(Temp. +85oC)
(IF Freq. 190MHz, LO Freq. 760MHz @ -10dBm, VCC=3.3V, 3.0V, 2.7V,V
GC
=
2.4V to
0.3V)
-50.0
-45.0
-40.0
-35.0
-30.0
-25.0
-20.0
-15.0
-10.0
-5.0
0.0
5.0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4
VGC(V)
IIP3 (dBm)
IIP3 @3.3V,Temp. +85C IIP3 @3.0V,Temp.+85C IIP3 @2.7V,Temp. +85C
IIP3 versus VGC(Temp. -40oC)
(IF Freq. 190MHz, LO Freq. 760MHz @ -10dBm, VCC=3.3V, 3.0V,2.7V,VGC=2.4V to 0.3V)
-60.0
-50.0
-40.0
-30.0
-20.0
-10.0
0.0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4
VGC(V)
IIP3 (dBm)
IIP3 @3.3V,Temp.-40C IIP3 @3.0V,Temp.-40C IIP3 @2.7V,Temp.-40C
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