The RF2483 is a dual-band direct I/Q to RF modulator
designed for handset applications where multiple modes
of operation are required. The device provides common
differential I/Q inputs and a common AGC amplifier. Independent single-ended LO inputs and single-ended high
and low band RF outputs are provided. The device
achieves a very low out-of-band noise density of
-156dBm/Hz minimizing RF filtering. Operating from a
single 2.7V supply, the device is packaged in a
4mmx4mm, 20-pin, plastic leadless chip carrier.
LOW NOISE DUAL-BAND QUADRATURE
MODULATOR WITH AGC
• TDMA-Based Wireless Applications
• Wireless Local Loop
• Basestations
max
.00
0.85
.80
.65
12°
.05
.01
NOTES:
1
2
3
4
5
.60
.24 typ
.30
3
.18
.75
.50
Shaded Pin is Lead 1.
Pin 1 identifier must exist on top surface of package byidentification
mark or feature on the package body. Exact shape and sizeis optional.
Dimension applies to plated terminal: to be measured between 0.02
mm and 0.25 mm from terminal end.
Package Warpage: 0.05 mm max.
Die Thickness Allowable: 0.305 mm max.
4.00
sq.
.50
4 PLCS
1.85
1.55 sq.
.23
.13
.65
.30
4 PLCS
5
UPCONVERTERS
MODULATORS AND
Optimum Technology Matching® Applied
Si BJTGaAs MESFETGaAs HBT
Si Bi-CMOS
SiGe HBT
ü
GND2
RF OUT HB
GND3
**
**
1VCC3
2VCC2
3ISIG P
4ISIG N
5EN
20
Mode
Control
Biasing
67
VCC1
19
&
+45°
-45°
LO LB
17
18
Σ
+45°
-45°
8
9
GND LO
RF OUT LB
Power
Control
LO HB
Si CMOS
GC
16
15 GC DEC
14 VREF
13 QSIG P
12 QSIG N
11 BAND SEL
10
Represents "GND".
*
GND1
Functional Block Diagram
Package Style: LCC, 20-Pin, 4x4
Features
• Dual-Band Operation 700-2200MHz
• -156dBm/Hznoise@20MHz offset
•+19dBmOIP3
•+6dBmOP1dB
• 35dB Gain Control Range
• Single 2.7V to 3.3V Supply
Ordering Information
RF2483Low N oise Dual-Band Quadrature Modulator with
RF2483 PCBAFully Assembled Evaluation Board
RF Micro Devices, Inc.
7628 Thorndike Road
Greensboro,NC 27409, USA
AGC
Tel (336) 664 1233
Fax (336) 664 0454
http://www.rfmd.com
Rev A2 010904
5-29
Page 2
RF2483
Absolute Maximum Rat ings
ParameterRatingUnit
Supply Voltage-0.5 to 3.6V
Storage Temperature-40 to +150°C
Operating Ambient Temperature-40 to +85°C
Input Voltage, any pin-0.5 to 3.6V
Input Power, any pin+10dBm
Preliminary
Caution! ESD sensitive device.
RF Micro Devices believesthe furnishedinformation is correctand accurate
at the time of this printing. However, RF Micro Devices reserves the right to
make changes to its products without notice.RF Micro Devices does not
assume responsibility for the use of the described product(s).
5
Parameter
Min.Typ.Max.
Specification
UnitCondition
Operating Range
Supply Voltage*2.73.3V
Temperature Range*-40+85°C
High Band Frequency Range*17002200MHzBandsel=2.7V
Low Band Frequency Range*7001000MHzBandsel=0V
DC Parameters
High Band Supply Current6585110mAGC=2.0V, VCC=2.7V, EN=2.7V,
Bandsel=2.7V, IQ=1.2V
Low Band Supply Current6585110mAGC= 2.0V,V
Bandsel=0V, IQ=1.2V
Sleep Current<1.010µAEN=0V
UPCONVERTERS
MODULATORS AND
Logic Levels
Input Logic Low00.5V
Input Logic High1.4V
Logic Pins Input Current*<1.0µA
CC
V
=2.7V, EN=2.7V,
CC
DC,TA
DC,TA
=25oC
=25oC
LO Input Port
High Band Frequency Range*17002200MHzBandsel=2.7V
Low Band Frequency Range*7001000MHzBandsel=0V
High Band LO Input Power*-306dBmBandsel=2.7V
LO Band LO Input Power*-306dBmBandsel=0V
Input Impedance*50Ω
5-30
Rev A2 010904
Page 3
Preliminary
RF2483
Parameter
Min.Typ.Max.
I/Q Modulator High Band
Baseband Input Voltage*1.151.21.25VCommon mode voltage
Baseband Input Level0.8V
Baseband Input Impedance*5.5kΩMeasured at 100kHz
Input Bandwidth*50150MHzI/Q source impedance 50Ω
Sideband Suppression3043dBcGC=2.0V, no I/Q adjustment
Carrier Suppression3048dBcGC=2.0V, no I/Q ad justment
3rd Harmonic of Modulation
Suppression at FLO-3x100kHz4047dBcGC =2.0V
Baseband Inputs DC Current
Drain*
Baseband Inputs AC Current
Drain*
I/Q Modulator Low Band
Baseband Input Voltage*1.151.21.25VCommon mode voltage
Baseband Input Level0.8V
VCC=2.7V, EN=2.7V, Bandsel=0V,
FLO=0dBm, PLO=900MHz, LO LB and RF
OUT LB ports are matched to 50Ω. Input IQ
1.2Vdc, signals driven differentially and in
quadrature from a 50Ω source impedance.
=25oC
T
A
GC=2.0V and 0.5V
and 1.5V
P-P
baseband tones at 90kHz and 110kHz
applied differentially, in quadrature, at both I
and Q inputs, each tone 400mV
Two baseband tones at 90kHz and 110kHz
applied at both I and Q inputs, each tone
400mV
P-P
.
at 100kHz
P-P
at 100kHz
P-P
at 100kHz
P-P
at 100kHz
P-P
at 100kHz
P-P
P-P
.
5
UPCONVERTERS
MODULATORS AND
*=Nottestedinproduction
MODEENBANDSELCOMMENTS
Sleep0XI/Q and GC inputs go open circuit through the
use of a FET switch in sleep mode.
High Band Mode11LO input LO HB
RF output=RF OUT HB
Low Band Mode10LO input LO LB
RF output=RF OUT LB
Rev A2 010904
5-33
Page 6
RF2483
Preliminary
PinFunctionDescriptionInterface Schematic
1VCC3
Supply for RF output circuits.
VCC3
RF Output
Amplifier
5
2VCC2
3ISIGP
Supply for modulator and biasing circuits.
In phase I chann el positive baseband input port. Best performance is
achieved when the ISIGP and ISIGN are driven differentiall y. The recommended CW differential drive level (V
ISIGP-VISIGN
) is 800mV
P-P
.
VCC2
Modulator and
VGA
VCC2
This input should be DC-biased at 1.2V±0.05V. The common-mode
DC coltage on the ISIGP and ISIGN input signals is used to bias the
modulator. In sleep mode an internal FET switch is opened, the input
goes high impedance and the modulator is de-biased. The input impedance is typically 5.5kΩ at low frequencies and at higher frequencies
V
CC2
canbemodeledas50Ω in series with 12pF to ground.
UPCONVERTERS
MODULATORS AND
Phase or amplitude errors between the ISIGP and ISIGN signa ls may
result in the even order distortion of the modulation in the output spectrum.
50 Ω
12 pF
DC offsets between the ISIGP and IS IGN signals will result in
increased carrier leakage. Small DC o ffsets may be deliberately
applied between the ISIGP/ISIGN and QSIGP/QSIGN inputs to cancel
out LO leakage. The optimum corrective DC offsets will change with
mode, frequency and gain control.
Common-mode noise on the ISIGP and ISGN should be kept low as it
may degrade the noise performance of the modulator.
Phase offsets may be applied between the I and Q channels to improve
the sideband suppression performance.
4ISIGN
In phase I chann el negative b aseband input port. See ISIGP.
V
CC2
5ENABLE
6VCC1
5-34
Enables power to the device.
CMOS input.
Logic 1 (1.4V to VCC)=Enabled.
Logic 0 (0V to 0.5V)=Powered Down.
Supply for the LO buffers and quadrature network.
The sideband suppression is a function of the VCC1 voltage. The inclusion of R3 (39Ω) lowers the voltage on VCC1 by around 400mV and
results an improvement in sideband suppression but around a 0.2dB
increase in noise at 20MHz offset.
VCC1
LO Quadrature
Generator and
Buffers
GND1
50 Ω
12 pF
V
CC2
Rev A2 010904
Page 7
Preliminary
RF2483
PinFunctionDescriptionInterface Schematic
7LOLB
8GNDLO
9LOHB
10GND1
11BAND SEL
Local oscillator input low band.
This input is biased internally at around 1.6V when the chip is in low
band mode and 0V when the chip is in high band mode or powered
down. The LO signal typically needs to be AC coupled.
The noise performance, carrier suppression at low output powers and
sideband suppression are all a function of LO power.
The optimum LO power is between 0dBm and 3dBm.
The device will work with LO powers as low as -20dBm however this is
at the expense of h igher noise performance at high output powers and
poorer sideband suppression.
Ground return for the local osc illator input signa ls.
The GND LO pin is effectively the complementary LO input for both the
high band and low band LO signals. It has significant amounts of LO
signal flowing through it. This pin is brought out as an independent
ground to e nable the PCB board designer to isolate the LO return from
the RF outputs ground and the general chip ground.
It is recommended that this ground is kept isolated from the die flag
ground. Any connections between the GND LO and any other ground
shouldbe made througha ground plane.
Local oscillator input high band.
This input is biased internally at around 1.6V when the chip is in high
band mode and 0V when the chip is in low band mode or powered
down. The LO HB signal typically needs to be AC coupled.
The noise performance, carrier suppression at low output powers and
sideband suppression are all a function of LO power.
The optimum LO power is between 0dBm and 3dBm.
The device will work with LO powers as low as -20dBm however this is
at the expense of h igher noise performance at high output powers and
poorer sideband suppression.
Ground for LO buffers.See pin 6.
Band select input to define active mode.
CMOS input.
Logic 1 (1.4V to VCC)=High band mode.
Logic 2 (0V to 0.5V)=Low band mode.
Seepins7and9.
LOLB
GNDLO
LOHB
GND LO
V
CC2
5
UPCONVERTERS
MODULATORS AND
12QSIG N
Rev A2 010904
Quadrature channel negative baseband input port. See QSIGP.
V
CC2
50 Ω
12 pF
5-35
Page 8
5
RF2483
Preliminary
PinFunctionDescriptionInterface Schematic
13QSIG P
14VREF
UPCONVERTERS
MODULATORS AND
15GC DEC
16GC
Quadrature Q channel positive baseband input po rt.
Best performance is achieved when the ISIGP and ISIGN are driven
differentially.The recommended CW differential dr ive level (V
V
QSIGN
) is 800mV
P-P
.
QSIGP
-
This input should be DC-biased at 1.2V±0.05 V. The common-m ode
DC voltage on the QSIGP and QSIGN input signals is used to bias the
modulator. In sleep mode an internal FET switch is opened, the input
goes high impedance and the modulator is de-biased. The input impedance is typically 5.5kΩ at low frequencies and at higher frequencies
canbemodeledas50Ω in series with 12pF to ground.
Phase or amplitude errors between the QSIG P and QSIGN signals
which may result in an increase in the even order distortion of the modulation in the ou tput spectrum.
DC offsets between the QSIGP and QSIGN signals will result in an
increased carrier leakage. Small DC o ffsets may be deliberately
applied between the ISIGP/ISIGN and QSIGP/QSIGN inputs to cancel
out the LO leakage. The optimum corrective DC offsets will change with
mode, frequency and gain control.
Common-mode noise on the QSIGP and QSIGN should be kept low as
it may degrade the noise performance of the modulator.
Phase offsets may be applied between the I and Q channels to improve
the sideband suppression performance.
Voltage reference decouple with an external 10nF capacitor to ground.
The voltage on this pin is typically 1.67V when the chip isenabled.The
voltage is 0V when the chip is powered down.
The purpose of this decoupling capacitor is to f ilter out low frequency
noise (20MHz) on the gain control lines.
Poor positioning of the VREF d ecoupling capacitor can cause a degradation in LO leakage.
A voltage of around 2.5V on this pin indicates that the die flag under
the chip is not grounded and the chip is not biased correctly.
Voltage reference decouple with an external 1nF decoupling capacitor
to ground.
The voltage on this pin is a function of gain control (GC) voltage when
the chip is enabled. The voltage is 0V when the c hip is powered down.
The purpose of this decoupling capacitor is to f ilter out low frequency
noise (20MHz) on the gain control lines. The size of the capacitor on
the GC DEC line will effect the settling time response to a change in
gain control voltage. A 1nF capacitor equates to around 200ns settling
time and a 0.5nF capacitor equates to a 100ns settling time. There is a
trade-off between settling time and noise contributions by the gain control circuitry as gain control is applied.
Poor positioning of the VREF d ecoupling capacitor can cause a degradation in LO leakage.
Gain control voltage. Maximum output power at 2.0V. Minimum output
power at 0V.When the chip is enabled the input impedance is 10kΩ
referenced to 1.7V
. When the chip is powered down a FET switch is
DC
opened and the in put goes high impedance.
4kΩ
+
4kΩ
+
-
V
V
CC2
50 Ω
12 pF
V
CC2
V
CC2
CC2
10 kΩ
1.7 V
4kΩ
-
+
17RF OUT LB
18GND2
5-36
RF low band output. Open collector output.
The output should be biased at VCC through an inductor that c an be
used to form part of an output matching circuit.
In our proposed applications circuit some power is dissipated in R6
(130Ω) which appears as a de-Qing resistor in parallel with the output
inductor L4. If R6 is eliminated and the RFOUT LB pin is re-matched to
50Ω it is possible to get approximately 5dB extra power out of the
device in low band mode.
Ground for RF output sections.
Rev A2 010904
Page 9
Preliminary
RF2483
PinFunctionDescriptionInterface Schematic
19RF OUT H B
20GND3
Die
GND4
RF high band output. Open collector output.
The output should be biased at VCC through an inductor that can be
used to form part of an output matching circuit.
In our proposed applications circuit some power is dissipated in R4
(180Ω) which appears as a de-Qing resistor in parallel with the output
inductor L3. If R4 is eliminated and the RFOUT HB pin isre-matchedto
50Ω it is possible to get approximately 3dB extra power out of the
device in high band mode.
Ground for RF output sections.
Ground for modulator, variable gain amplifier and substrate.
Flag
5
UPCONVERTERS
MODULATORS AND
Rev A2 010904
5-37
Page 10
RF2483
Preliminary
Applicat ion Notes
5
The baseband inputs must be driven with balanced differential signals. We suggest amplitude and phase
matching <0.5dB and <0.5°. Phase or gain imbalances
between the complementary input signals will cause
additional distortion including some second order
baseband distortion.
The common-mode voltage on the baseband inputs
should be well controlled at 1.2V. We suggest that the
common-mode DC voltage be 1.2V+
0.05 V. The common-mode DC voltage is used to b ias the modulator;
hence, deviations from 1.2 V will result in changes in
the current consumption, noise and intermodulation
performance.
Thechipisdesignedtobedrivenwithasingle-ended
LO signal.
The GC DEC and VREF output pins should be decoupled to ground. We recommend a 10nF capacitor on
VREF, and a 1 nF capacitor on GC DEC. The purpose
UPCONVERTERS
MODULATORS AND
of this capacitor is to filter out low frequency noise
(20MHz) in the gain control lines, which may cause
noise on the RF signal. The capacitor on the GC DEC
line will effect the settling time response to a change in
power control voltage. A 1nF capacitor equates to
around a 200ns settling time, and a 0.5nF capacitor
equates to a 100ns settling time. There is a trade-off
between settling time and phase noise as you start to
apply gain control.
The ground lines for the LO sections, GNDLO and
GND1, are brought out of the chip independently from
the ground to the RF and modulator sections. This isolates the LO signals from the RF output sections.
The G ND LO pin is effectively the complementary LO
input for both the high band and low band LO signals.It
has significant amounts of LO signal flowing through it.
This is brought out as an independent ground to try to
enablethe PCB board designer to isolate the LO return
from the RF output sections and general chip ground.
The RF output ports of the RF2483 consist of open collector architecture and require pull up inductors to the
supply voltage. This, in conjunction with a DC blocking
capacitor provides a simple, broadband L-match network as shown in the schematic diagram. A shunt
resistor is included to control the Q of the matching
network and set the modulator output power. In this
case, both outputs were designed to provide 0dBm.
An alternate output match containing a third harmonic
trap was evaluated. This circuit uses a tapped-C
matching network, whereby the shunt C provides a low
impedance path near the third harmonic frequency.
Although an additional component is required, the benefit of suppressing the third harmonic distortion may
improve overall system intermodulation. This network
has been shown to provide better than 20dB of
improved suppression in high-band mode.