Page 1
RF2418
8
Typical Applications
• UHF Digital and Analog Receivers
• Digital Communication Systems
• Spread-Spectrum Communication Systems
Product Description
The RF2418 is a monolithic integrated UHF receiver
front-end. The IC contains all of the required components
to implement the RF functions of the receiver except for
the passive filtering and LO generation. It contains an
LNA (low-noise am plifier), a second RF amplifier, a dualgate GaAs FET mixer, and an IF output buffer amplifier
which will drive a 50Ω load. In addition, the IF buffer
amplifier may be disabled and a highimpedance output is
provided for easy matching to IF filters with high impedances. The output of the LNA is made available as an
output to permit theinsertion of a bandpass filter between
the LNA and the RF/Mixer section. The LNA section may
be disabled by removing the VDD1 connection to the IC.
LOW CURRENT LNA/MIXER
• Commercial and Consumer Systems
• 433 MHz and 915MHz ISM Band Receivers
• General Purpose Frequency Conversion
0
1
0
0
.
4
0
0
.
0
5
9
.
0
0
.
0
7
5
0
0.347
0.339
8° MAX
0° MIN
0.0500
0.0164
0.156
0.148
2
.
0
.
2
0
8
1
0
.
0
1
4
.
0.050
5
2
6
3
0.010
0.007
8
Optimum Technology Matching® Applied
Si BJT GaAs MESFETGaAs HBT
Si Bi-CMOS
LNA IN
GND
VDD1
VDD2
IF BYP
IF2 OUT
IF1 OUT
1
2
3
4
5
6
7
SiGe HBT
10pF
BUFFER
LNA
RF AMP
MIXER
ü
Si CMOS
LNA OUT
14
GND
13
GND
12
RF IN
11
GND
10
DEC
9
LO IN
8
Functional Block Diagram
Package Style: SOIC-14
Features
• Single 3V to 6.5V Power Supply
• High Dynamic Range
• Low Current Drain
• High LO Isolation
• LNA Power Down Mode for Large Signals
Ordering Information
RF2418 Low Current LNA/Mixer
RF2418 PCBA Fully Assembled Evaluation Board
RF Micro Devices, Inc.
7628 Thorndike Road
Greensboro,NC 27409, USA
Tel (336) 664 1233
Fax (336) 664 0454
http://www.rfmd.com
FRONT-ENDS
Rev A6 010717
8-35
Page 2
RF2418
Absolute Maximum Rat ings
Parameter Rating Unit
Supply Voltage -0.5 to 7 V
Input LO and RF Levels +6 dBm
Ambient Operating Temperature -40 to +85 °C
Storage Temperature -40 to +150 °C
DC
Caution! ESD sensitive device.
RF Micro Devices believes thefurnished information is correct and accurate
at the time of this printing. However, RF Micro Devices reserves the right to
make changes to its products without notice. RF Micro Devices does not
assume responsibility for the use of the described product(s).
8
Parameter
Min. Typ. Max.
Overall
RF Frequency Range 400 to 1100 MHz
Cascade Power Gain 23 dB High impedance output
Cascade IP
Cascade Noise Figure 2.4 dB Single sideband, includes image filter with
3
Specification
-13 dBm Referenced to the input
Unit Condition
T=25°C, VCC=5V, RF=850MHz,
LO=921MHz
1.0dB insertion loss
First Section (LNA)
Noise Figure 1.8 2.0 dB
Input VSWR 1.5:1 With external series matching inductor
Input IP3 +3.0 +4.0 dBm
Gain 13 14 dB
Reverse Isolation 40 dB
Output VSWR 1.5:1
Second Section (RF Amp,
High impedance output
Mixer, IF1)
Noise Figure 9.5 dB Single Sideband
Input VSWR 1.5:1 With external series matching inductor
Input IP3 +1 dBm
Conversion Power Gain 7 9 dB
Output Impedance 4000||10pF Ω Open Collector
FRONT-ENDS
Second Section (RF Amp,
Buffered output, 50Ω l oad
Mixer, IF2)
Noise Figure 10 dB Single Sideband
Input VSWR 1.5:1 With external series matching inductor
Input IP3 -0.5 0 dBm
Conversion Gain 5 6 dB
Output Impedance 30 Ω
LO Input
LO Frequency 300 to 1200 MHz
LO Level -6 to +6 dBm
LO to RF Rejection 15 dB
LO to IF Rejection 40 dB With pin 5 connected to ground.
LO Input VSWR 1.3:1 In order to achieve a low VSWR match at
this input, an 82Ω resistor to ground is
placed in parallel with this port.
Power Supply
Voltage 3.0 6.5 V
Current Consumption 14 mA V
12 20 26 mA V
6920mAV
=5.0V,LNA On, Mixer On, Buffer Off
CC
=5.0V,LNA On, Mixer On, Buffer On
CC
=5.0V,LNA Off, Mixer On, Buffer Off
CC
8-36
Rev A6 010717
Page 3
RF2418
Pin Function Description Interface Schematic
1LNAIN
A series 10 n H matchinginductoris necessaryto achieve specified gain
and noise figure at 900MHz. This pin is NOT internally DC-blocked. An
external blocking capacitor must beprovided if the pin is connected to a
device with DC present. A DC path to ground (i.e. an inductor or resistor to ground) is, however,acceptableat this pin. If a blocking capacitor
is required, a value of 22 pF is recommended.
LNA IN
2GND
3VDD1
4VDD2
5IFBYP
6IF2OUT
7IF1OUT
8LOIN
9RFBYP
Ground connection. Keep traces physically short and connect immediately to ground plane for best performance.
Supply Voltage for the LNA only. A 22pF external bypass capacitor is
required and an addi tional 0.01µF is required if no other low frequency
bypass capacitors are near by. The trace length between th e pin and
the bypass capacitors should be minimized. The ground side of th e
bypass capacitors should connect immediately to ground plane.
For large input signals, VDD1 may be disconnected, resulting in the
LNA’s gain changing from +11dB to -26dB and current drain decreasing by 4mA. If the LNA is never required for use, then this pin can be
left unconnected or grounded, and Pin 11 is used as the first input.
Power supply for the IF buffer amplifier. If the high impedance mixer
output is being used, then this pin is not connected.
If this pin is connected to ground, an internal 10pF capacitor is connected in parallel with the mixer output. Thi s capacitor functions as an
LO trap, which reduces the amount of LO to IF bleed-through and prevents high LO voltages at the mixer output from degrading the mixer’s
dynamic range. At higher IF frequencies, this capacitance, along with
parasitic layout capacitance, should be parallel resonated out by the
choice of the bias inductor value at pin 7. If the internal capacitor is not
connected to ground, the buffer amplifier could become unstable. A
~10pF capacitor should be added at the output to mai ntain the buffer’s
stability,but the gain will not be significantly affected.
50Ω buffered (open source) output port, one of two output options. Pin
7 must have a bias resistor to V
to ground (see Buffered Output Application Schematic) in order to turn
the buffer amplifier on. Current drain will increase by approximately
8mA at 5V, and by approximately 5mA at 3V. It is recommended that
these bias res istors be less than 1kΩ.
High impedance (open drain) output port, one of two output options.
This pin must be connected to V
order to bias the mixer,even when using IF2 Output. In addition, a
0.01µFbypass capacitor is required at the other end of thebiasresistor
or inductor. The ground side of the bypass capacitor should connect
immediately to ground plane. This output is intended to drive high
impedance IF fi lters. The recommended matching network is shunt L,
series C ( see the application schematic, high impedance output). This
topology will provide matching, bias, and DC-blocking.
Mixer LO input. A high-pass matching network, such as a single shunt
inductor (as shown in the application schematics), is the recommende d
topology because it also rejects IFnoiseat the mixer input. This filtering
is required to achieve the specified noise figures. This pin is NOT internally DC-blocked. An external blocking capacitor must be provided if
the pin is connected to a device with DC present. A DC path to ground
(i.e. an inductor or resistor to ground) is, however, acceptable at this
pin. If a blocking capacitor is required, a value of 22pF is recommended.
Connection for the external bypass capacitor for the mixer RF input
preamp. 1000pF is recommended. The trace length between the pin
and the capacitor should be minimized. The ground side of the bypass
capacitor should connect immediately to ground plane.
and pin 6 must have a bias resistor
DD
through a resistor or inductor in
DD
LO IN
IF2 OUT
IF1 OUT
8
FRONT-ENDS
Rev A6 010717
8-37
Page 4
8
RF2418
Pin Function Description Interface Schematic
10 GND
11 RF IN
12 GND
13 GND
14 LNA OUT
Same as pin 2.
Mixer RF Input port. For a 50Ω matchat900MHzusea15nHseries
inductor. This pin is NOT internally DC-blocked. An external blocking
capacitor must be provided if the pin is connected to a device with DC
present. A DC path to ground (i.e. an inductor or resis tor to ground) is,
however, acceptable at this pin. If a blocking capacitor is required, a
value of 22pF is recommended.To minimize the mixer’s noise figure, it
is recommended to havea RF bandpass filter before this input. This will
prevent the noise at the image frequency from being converted to the
IF.
Same as pin 2.
Same as pin 2.
50Ω output. Internally DC-blocked.
Application Schematic
High Impedance Output Configuration
850MHz
RF IN
LNA OUT
FRONT-ENDS
RF IN
V
DD
IF Filter, Hi Z
IF OUT
L1 and C1 are picked to match the mixer's output impedance (4 kΩ II 10 pF) to the IF
filter's impedance, at t h e IF frequency. C1 also serves as a DC block, in case the IF filter
is not an open circuit at DC.
10 nH
47 pF100 nF
V
DD
C1
1
2
3
4
5
6
7
L1
100 nF
10pF
BUFFER
LNA
RF AMP
MIXER
14
13
12
11
10
9
8
Image Filter 50 Ω
15 nH
1nF
4pF
LO IN
10 nH
8-38
Rev A6 010717
Page 5
Application Schemati c
Buffered Output Configuration
850MHz
RF2418
RF IN
IF OUT
IF Filter, 50Ω
V
DD
V
DD
C1
R1
100 nF 100 nF
10 nH
47 pF100 nF
1
2
3
4
10pF
5
6
BUFFER
7
L1R2
L1 should parallel res onate, at the IF frequency, with the internal
10pF capacitor plus any extra parasitic layout capacitance.
R1 and R2 are bias resistors that set the bias current for the buffer
amplifier. The value recommended is 510 W, each. Higher values
will decrease the current consumption but also decrease the output
level at which voltage clipping begins to occur. At lower IF
frequencies, where the internal 10 pF capacitor does not roll off the
conversion gain, L1 may be eliminated.
C1 is a blocking capacitor, in case the IF filter's input is not an open
circuit at DC.
LNA
RF AMP
MIXER
14
13
12
15nH
11
10
1nF
9
4pF
8
10 nH
Image Filter, 50 Ω
LO IN
8
FRONT-ENDS
Rev A6 010717
8-39
Page 6
RF2418
J1
LNA IN
50 Ωµstrip
Evaluation Board Schema t ic
RF=850MHz, IF=71MHz
(Download Bill of Materials from www.rfmd.com.)
L3
10 nH
R4
5.11 kΩ
1
2
LNA
14
13
50 Ω µstrip
J5
LNA OUT
8
FRONT-ENDS
P1-3
J2
IF OUT
Jumper
E2 E1
C1
0.1 µF
see note
R3
610 Ω
C3
47 pF
C4
0.1 µF
VDD
3
4
5
6
7
R1
300 Ω
10pF
BUFFER
1 µH
RF AMP
MIXER
TP1
see note
L1
Notes:
For high impedance output
1) Populate L1 and TP1
2) Remove jumper E1 to E2
12
11
10
9
8
2418400C
50 Ω µstrip
C2
1nF
C5
3pFto5pF
L4
10 nH
L2
18 nH
50 Ω µstrip
50 Ω µstrip
P1
1
NC
2
P1-3 VDD
3
J4
RF IN
J3
LO IN
GND
8-40
Rev A6 010717
Page 7
Evaluation Board Layout
Board Size 1.52” x 1.52”
Board Thickness 0 .031”, Board Material FR-4
RF2418
8
FRONT-ENDS
Rev A6 010717
8-41
Page 8
RF2418
8
FRONT-ENDS
High Im pedance Mixer Gain versus Voltage, RF=850MHz
10.0
9.5
9.0
8.5
Gain (dB)
8.0
7.5
7.0
3.03.54.04.55.05.56.06.5
T=-40
T=26
T=85
Voltage(V)
High Impedance Mixer Input IP3 versus Voltage,
4.0
3.5
3.0
2.5
2.0
IIP3 (dBm)
1.5
1.0
0.5
3.03.54.04.55.05.56.06.5
T=-40
T=26
T=85
RF=850MHz
Voltage(V)
High Impedance Casc. Gain versus Voltage,
26.0
24.0
22.0
20.0
Gain (dB)
18.0
16.0
14.0
3.03.54.04.55.05.56.06.5
RF=850MHz
T=-40
T=26
T=85
Voltage(V)
High Impedance Casc. Input IP3 versus Voltage,
-10.0
-10.5
-11.0
-11.5
-12.0
-12.5
IIP3 (dBm)
-13.0
-13.5
-14.0
-14.5
-15.0
3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5
T=-40
T=26
T=85
RF=850MHz
Voltage(V)
8-42
Buffered LNAGain versus Voltage,
17.0
16.0
15.0
14.0
13.0
12.0
Gain (dB)
11.0
10.0
9.0
8.0
7.0
3.03.54.04.55.05.56.06.5
RF=850MHz
T=-40
T=26
T=85
Voltage(V)
Buffered Mixer Gainversus Voltage,
15.0
T=-40
T=26
T=85
3.03.54.04.55.05.56.06.5
Gain (dB)
14.0
13.0
12.0
11.0
10.0
9.0
8.0
7.0
6.0
5.0
RF=850MHz
Voltage(V)
Rev A6 010717
Page 9
RF2418
Buffered Casc. Gain versus Voltage,
30.0
T=-40
T=26
T=85
3.03.54.04.55.05.56.06.5
Gain (dB)
25.0
20.0
15.0
10.0
5.0
RF=850MHz
Voltage(V)
Buffered MixerInput IP3 versus Voltage,
2.0
1.5
1.0
0.5
0.0
-0.5
IIP3 (dBm)
-1.0
-1.5
-2.0
-2.5
-3.0
3.03.54.04.55.05.56.06.5
T=-40
T=26
T=85
RF=850MHz
Voltage(V)
Buffered L NA Input versus Voltage,
6.0
T=-40
T=26
T=85
3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5
IIP3 (dBm)
-10.0
4.0
2.0
0.0
-2.0
-4.0
-6.0
-8.0
RF=850MHz
Voltage(V)
Buffered Casc. Input IP3 versus Voltage,
-10.0
T=-40
-11.0
-12.0
-13.0
T=26
T=85
IIP3 (dBm)
-14.0
-15.0
-16.0
3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5
RF=850MHz
Voltage(V)
8
FRONT-ENDS
Buffered LNA Noise Figure versus Voltage,
2.0
1.8
Gain (dB)
1.6
1.4
3.03.54.04.55.05.56.06.5
RF=850MHz Part to Part Variation
Voltage(V)
Rev A6 010717
Part 1
Part 2
Part 3
Part 4
Part 5
Buffered Mixer Noise Figure versus Voltage,
11.0
10.5
10.0
Gain (dB)
9.5
9.0
3.03.54.04.55.05.56.06.5
RF=850MHz Part to Part Variation
Part1
Part2
Part3
Part4
Part5
Voltage(V)
8-43
Page 10
RF2418
8
FRONT-ENDS
8-44
Rev A6 010717
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