Datasheet RF2196, RF2196PCBA Datasheet (RF Micro Devices)

Preliminary

RF2196

2

Typical Applications

• 3V CDMA PCS Handsets

• 3V CDMA KPCS Handsets

• 3V T DMA/GAIT PCS Handsets

Product Description

The RF2196 is a high-power, high-efficiency linear ampli­fier IC targeting 3V handheld systems. The device is
manufacturedon an advancedGallium Arsenide process,
and has been designed for use as the final RF am plifier in
3V CDMA and CDMA2000 handsets as well as other
applications in the 1750MHz to 1910MHz band. The
RF2196 has a low power mode to extend battery life
under low output power conditions. The package is an
ultra s mall 4mmx4mm leadless plastic package with
backside ground.

3V PCS LINEAR POWER AMPLIFIER

• 3 V CDMA 2000 PCS Handsets

• Spread-Spectrum Systems

• Portable Battery-Powered Equipment

2

3.75

Dimensions in mm.

INDEX AREA

0.75

0.50

3.75

12°

3

0.75

1.00

0.65

0.90

0.05

0.00

NOTES:

2

3

4
5 PackageWarpage: 0.05 max.

0.45

0.28

+

1.50 SQ

3.20

4.00

Shaded PinisLead 1.1
Dimension appliestoplated terminal and is measured between

0.10 mmand0.25 mm from terminal tip.
The terminal#1identifier and terminal numbering convention

shall conformtoJESD 95-1 SPP-012. Details of terminal #1
identifier areoptional,but must be located within the zone
indicated. Theidentifiermay be either a mold or marked
feature.

Pins 1and9 are fused.

2

0.80
TYP

1

1

POWER AMPLIFIERS

4.00

1.60

Optimum Technology Matching® Applied

Si BJT GaAs MESFETGaAs HBT
Si Bi-CMOS

ü

SiGe HBT

GND

1

2VPD1

3MODE

4VPD2

5

GND

NC

RF IN

15

16

67

NC

RF OUT8RF OUT

NC

14

Si CMOS

NC

13

12 VCC1

11 VCC1

10 VCC

9

GND

Functional Block Diagram

Package Style: LCC, 16-Pin, 4x4

Features

• Single 3V Supply

• 29dBm Linear Output Power

• 35% Linear Efficiency

•LowPowerMode(Upto20dBm)

• 55mA Idle Current

Ordering Information

RF2196 3V PCS LINEAR Power Amplifier
RF2196 PCBA Fully Assembled Evaluation Board

RF Micro Devices, Inc.
7625 Thorndike Road
Greensboro,NC 27409, USA

Tel [phone]

Fax [phone]

http://www.rfmd.com

Rev A0 010518

2-203

2

RF2196

Absolute Maximum Ratings

Parameter Rating Unit

Supply Voltage (RF off) +8.0 V
Supply Voltage (P
Mode Voltage (V
Control Voltage (V
Input RF Power +10 dBm

Operating Case Temperature -30 to +110 °C
Storage Temperature -30 to +150 °C
Moisture Sensitivity Modified JEDEC Level 2

≤31dBm) +5.2 V

OUT

)+4.2V

MODE

)+3.0V

REG

DC

DC
DC
DC

Preliminary

Caution! ESD sensitive device.

RF Micro Devices believesthe furnishedinformation is correctand accurate
at the time of this printing. However, RF Micro Devices reserves the right to
make changes to its products without notice. RF Micro Devices does not
assume responsibility for the use of the described product(s).

Parameter

POWER AMPLIFIERS

Specification

Min. Typ. Max.

Unit Condition

High Power State

(V

Frequency Range 1850 1910 MHz
Linear Gain 25 27 dB
Second Harmonic -50 dBc
Third Harmonic -63 dBc
Maximum Linear Output Power

(CDMA Modulation)

Total Linear Efficiency 35 % P
Adjacent Channel Power Rejec-

tion

Input VSWR <2:1
Output VSWR 10:1 No damage.

Noise Power -141 dBm/Hz At 80MHz offset.

MODE

Low)

29 dBm

-46 -44 dBc ACPR@1.25MHz

-62 -56 dBc ACPR@2.25MHz

6:1 No oscillations. >-70dBc

Low Power State

(V

Frequency Range 1850 1910 MHz
Linear Gain 16 20 dB
Second Harmonic -45 dBc
Third Harmonic -60 dBc
Maximum Linear Output Power

(CDMA Modulation)

Max I
Adjacent Channel Power Rejec-

tion

Input VSWR 2:1
Output VSWR 10:1 No damage.

MODE

CC

High)

16 20 dBm

160 mA P

< -50 -46 dBc ACPR@1.25MHz

< -60 -58 dBc ACPR@2.25MHz

6:1 No oscillations. >-70dBc

Case T =25°C, VCC=3.4V, V
V

=0V to 0.5V, Freq=1850MHz to

MODE

1910MHz (unless otherwise specified)

=29dBm

OUT

Case T =25°C, VCC=3.4V, V
V

=2V to 3V, Freq=1850MHz to

MODE

1910MHz (unless otherwise specified)

=+16dBm (all currents included)

OUT

REG

REG

=2.85V,

=2.85V,

2-204

Rev A0 010518

Preliminary

RF2196

Parameter

Min. Typ. Max.

High Power State CDMA
2000 1x (V

Frequency Range 1850 1910 MHz
Linear Gain 27 dB
Pilot+DCCH 9600
Maximum Linear Output Power

(CDMA 2000 Modulation)

Adjacent Channel Power Rejec-

tion

Pilot+FCH 9600+SCH0 9600
Maximum Linear Output Power

(CDMA 2000 Modulation)

Adjacent Channel Power Rejec-

tion

MODE

LOW)

Low Power State CDMA
2000 1x (V

Frequency Range 1850 1910 MHz
Linear Gain 19 dB
Pilot+DCCH 9600
Maximum Linear Output Power

(CDMA 2000 Modulation)

Adjacent Channel Power Rejec-

tion

Pilot+FCH 9600+SCHO 9600
Maximum Linear Output Power

(CDMA 2000 Modulation)

Adjacent Channel Power Rejec-

tion

MODE

HIGH)

Specification

26.5 dBm 2.5dBBackoff included in IS95D 5.4dB peak

-49 dBc ACPR@1.25MHz

-61 dBc ACPR@2.25MHz

29 dBm 4.5dB peak to average at CCDF of 1%

-46 dBc ACPR@1.25MHz

-63 dBc ACPR@2.25MHz

16 20 dBm 5.4dB peak to average at CCDF of 1%

-52 dBc ACPR@1.25MHz

-65 dBc ACPR@2.25MHz

16 20 dBm 4.5dB peak to average at CCDF of 1%

-52 dBc ACPR@1.25MHz

-65 dBc ACPR@2.25MHz

Unit Condition

Case T=25°C, VCC=3.4V,V
V

MODE

1910MHz (unless otherwise specified)

to average at CCDF of 1%

Case T=25°C, VCC=3.4V, V
V

MODE

1910MHz

DC Supply

Supply Voltage 3.0 3.4 4.2 V
Quiescent Current 185 mA V

55 mA V

Current 5 10 mA

V

REG

V

Current 1 mA

MODE

Total Current (Power Down) 10 µAV

“Low” Voltage 0 0.5 V

V

REG

V

“High” Voltage 2.75 2.85 2.95 V

REG

“Low” Voltage 0 0.5 V

V

MODE

V

“High” Voltage 2.0 3.0 V

MODE

MODE
MODE

REG

=Low

=2.85V,

=0V to 0.5V, Freq=1850MHz to

=2Vto 3V, Freq=1850MHzto

=Low
=High

REG

REG

=2.85V,

2

POWER AMPLIFIERS

Rev A0 010518

2-205

2

RF2196

Preliminary

Pin Function Description Interface Schematic

1GND
2VREG1

3MODE

4VREG2

5GND
6NC

POWER AMPLIFIERS

7RFOUT

8RFOUT
9GND

10 VCC
11 VCC1

12 VCC1
13 NC

14 NC

15 NC

16 RF IN

Pkg

GND

Base

This pin is internally grounded to the die flag.
Power Down control for first stage. Regulated voltage supply for ampli-

fier bias. In Power Down mode, both V
(<0.5V).
For nominal operation ( High Gain Mode), V
HIGH, the driver and final are dynamically scaled to reduce the device

size and as a res ult to reduce idle current.
PowerDowncontrolfor the second stage. Regulated voltage supply for

amplifier bias. In PowerDown mode, both V
LOW (<0.5 V).
Connect to ground plane via 15nH induc tor. DC return for the second

stage bias circuit.
This pin has no internal bonding; therefore, this pin can be connected

to output pin 7, connected to the ground plane,or not connected. Slight
tuning of the output match may be required due to stray capacitance of
the pin.

RF output and power supply for final stage. This is the unmatched col­lector output of the second stage. A DC block is required following the
matching components. The biasing may be provided via a parallel L-C
set for resonance at the operating frequency of 1710MHz to 1910MHz.
It is important to select an inductor with very low DC resistance with a
1A current rating. Alternatively, shunt microstrip techniques are also
applicable and provide very low DC resistance. Low frequency bypass­ing is required for stability.

Same as pin 7. See pin 7.
This pin is internally grounded to the die flag.
Supply for bias reference and control circuits. High frequency bypass-

ing may be necessary.
Power supply for first stage and interstage match. Pins 11 and 12

should be connected by a common trace where the pins contact the
printed circuit board.

Same as pin 11.
It is recommended that these pins be connected totheground plane for

improved isolation between RF IN (pin 16) and the VCC1 pins (pins 11
and 12).

It is recommended that these pins be connected totheground plane for
improved isolation between RF IN (pin 16) and the VCC1 pins (pins 11
and 12).

It is recommended that these pins be connected totheground plane for
improved isolation between RF IN (pin 16) and the VCC1 pins (pins 11
and 12).

RF input. An external 15pF series capacitor is required as a DC block.
In addition, the matchi ng circuit shown is req uired to improve input
VSWR.

Ground connection. The backside of the package should be soldered to
a top side ground pad which is connected to the ground plane with mul­tiple vias. The pad should have a short thermal path to the ground
plane.

REG

and V

MODE

REG

need to be LOW

MODE

issetLOW.Whenset

and V

MODE

need to be

RF IN

15 pF

3.6 pF

From Bias
Network

RF OUT

TL

From

Bias

Stages

VCC1

GND1

2-206

Rev A0 010518

Preliminary

RF2196

Application Schemati c

US - CDMA

VREG

VMODE

1 µF

+

Jumper

Bias return

Bypassing for

V

and V

REG1

REG2

Jumper

1kΩ

Matching network for

optimum load impedance

15 pF

15 pF

12 nH

15 pF

TL4

2

3

4

RF IN

4.7 pF

2.2 pF

3.6 pF

TL

15161

14 13

TL

1

2

15 pF

Matching network for
optimum input return loss

12

11

10

98765

2.5 nH

2.2 pF

TL

Interstagetuning for centering
frequency response

11 pF

3

15 pF

15 pF 10 nF

10 nF

Ferrite

10 Ω

RF Choke - Bias inductor
for the amplifier interstage

+

1 µF

VCC

4.7 µF

Bypassingfor V

2

CC

POWER AMPLIFIERS

Pins 1 and 9 are internally grounded to the die flag.

Rev A0 010518

RF OUT

Transmission

Line Length

CDMA (US)

TL

1

30 mils

TL

2

140 mils

TL

3

15 mils

TL

4

200 mils

2-207

RF2196

Preliminary

Evaluation Board Schema t ic

US - CDMA

RF IN

2

C5

15 pF

TL4

Ω

L1 (nH)

L4

12 nH

2.5

C27

15 pF

2

3

4

C13

15 pF

C14 (pF)

2.2

POWER AMPLIFIERS

Pins 1 and 9 areinternally grounded to the die flag.

Board C30 (pF)11C1 (pF)
CDMA (US)

C26
1uF

P2

Jumper

P3

R11

+

4.7

R12

Jumper

R1

1k

C1**

4.7 pF

C14**

2.2 pF

C24

3.6 pF

15161

TL

2

RF OUT

TL

C3

15 pF

14 13

1

P1 VCC

P3 VMODE

12

11

10

98765

L1*

2.5 nH

C7

2.2 pF

Transmission

Line Length

CDMA (US)

P1

1 P2 VREG

P1

1

C30

TL

15 pF

15 pF

* L1 is a High Q inductor (i.e., Coilcraft 0805HQ-series).
**C1 andC14 are HighQ capacitors

(i.e., Johanson C-series).

30 mils

11 pF

3

L2

Ferrite

10

C6

C4

TL

1

C28

10 nF

TL

140 mils

P1

1

P1

P4 GND

1

C8

10 nF

Ω

C2

4.7 uF

TL

2

3

15 mils

C25

+

1uF

TL

4

200 mils

P1

2-208

Rev A0 010518

Preliminary

Board Thickness 0.028”; Board Material FR-4; Multi-Layer; Ground Plane at 0.014”

RF2196

Evaluation Board Layout

Board Size 2.0” x 2.0”

2

POWER AMPLIFIERS

Rev A0 010518

2-209

2

RF2196

POWER AMPLIFIERS

Preliminary

2-210

Rev A0 010518