The RF2192 is a high-power, high-efficiency linear amplifier IC targeting 3V handheld systems. The device is
manufactured on an advanced Gallium Arsenide Heterojunction Bipolar Transistor (HBT) process, and has been
designed for use as the final RF amplifier in dual-mode
3V CDMA/AMPS and CDMA2000 handheld digital cellular equipment, spread-spectrum systems, and other
applications in the 800MHz to 960MHz band. The
RF2192 has a low power mode to extend battery life
under low output power conditions. The device is packaged in a 16 pin, 4mmx4m m leadless chip carrier.
3V 900MHZ LINEAR POWER AMPLIFIER
• 3V TDMA/GAIT Cellular H andsets
• Spread-Spectrum Systems
• Portable Battery-Powered Equipment
2
3.75
INDEX AREA
Dimensions in mm.
0.45
0.75
0.50
3.75
12°
3
0.75
1.00
0.65
0.90
0.05
0.00
NOTES:
2
3
4
5 Package Warpage: 0.05 max.
0.28
Shaded Pin isLead 1.1
Dimension appliesto plated terminal and is measured
0.10 mmand0.25mm from terminal tip.
The terminal#1 identifier and terminal numberingconv
shall conformtoJESD 95-1 SPP-012. Details of termin
identifierare optional, but must be locatedwithinthe z
indicated.Theidentifiermay be either a moldor marke
feature.
Pins 1 and 9arefused.
+
1.50 SQ
3.20
4.00
0.80
TYP
2
1
1
POWER AMPLIFIERS
4.00
1.60
Optimum Technology Matching® Applied
Si BJTGaAs MESFETGaAs HBT
Si Bi-CMOS
GND
GND
RF IN
ü
GND
2
3
4
VREG1
SiGe HBT
VCC1
VCC1
161131415
VREG2
VMODE
VCC BIAS
BIAS GND
Si CMOS
2F0
12
RF OUT
11
RF OUT
10
RF OUT
98765
GND
Functional Block Diagram
Package Style: LCC, 16-Pin, 4x4
Features
• Single 3V Supply
• 29dBm Linear Output Power
• 37% Linear Efficiency
• Low Power Mode
•45mAidlecurrent
• 47% Peak Efficiency 31dBm Output
Ordering Information
RF21923V 900MHz Linear Power Amplifier
RF2192 PCBAFully Assembled Evaluation Board
RF Micro Devices, Inc.
7628 Thorndike Road
Greensboro,NC 27409, USA
Tel (336) 664 1233
Fax (336) 664 0454
http://www.rfmd.com
Rev A1 010830
2-203
Page 2
2
RF2192
Absolute Maximum Ratings
ParameterRatingUnit
Supply Voltage (RF off)+8.0V
Supply Voltage (P
Mode Voltage (V
Control Voltage (V
Input RF Power+10dBm
Operating Case Temperature-30 to +110°C
Storage Temperature-30 to +150°C
Moisture SensitivityModified JEDEC Level 2
≤31dBm)+5.2V
OUT
)+4.2V
MODE
)+3.0V
REG
DC
DC
DC
DC
Preliminary
Caution! ESD sensitive device.
RF Micro Devices believesthe furnishedinformation is correctand accurate
at the time of this printing. However, RF Micro Devices reserves the right to
make changes to its products without notice. RF Micro Devices does not
assume responsibility for the use of the described product(s).
Parameter
POWER AMPLIFIERS
Min.Typ.Max.
Specification
UnitCondition
High Power State
(V
Frequency Range824849MHz
Linear Gain2730dB
Second Harmonic-33dBc
Third Harmonic<-60dBc
Maximum Linear Output Power
(CDMA Modulation)
Total Linear Efficiency37%P
Adjacent Channel Power Rejec-
tion
Input VSWR2:1
Output VSWR10:1No damage.
Noise Power-133dBm/HzAt 45MHz offset
MODE
Low)
29dBm
-48-44dBcACPR@885kHz
-58-56dB cACPR@1980kHz
6:1No oscillations. >-70dBc
Low Power State
(V
Frequency Range824849MHz
Linear Gain1922dB
Second Harmonic-33dBc
Third Harmonic<-60dBc
Maximum Linear Output Power
(CDMA Modulation)
Max I
Adjacent Channel Power Rejec-
tion
Input VSWR2:1
Output VSWR10:1No damage.
MODE
CC
High)
1620dBm
150mAP
-48-46dBcACPR@885kHz
< -60-58dBcACPR@1980kHz
6:1No oscillations. >-70dBc
Case T =25°C, VCC=3.4V,V
V
=0V to 0.5V, Freq=824 MHz to
MODE
849MHz (unless otherwise specified)
=29dBm
OUT
Case T =25°C,VCC=3.4V,V
V
=1.8V to 3V, Freq=824MHz to
MODE
849MHz (unless otherwise specified)
=+16dBm (all currents included)
OUT
REG
REG
=2.85V,
=2.85V,
2-204
Rev A1 010830
Page 3
Preliminary
RF2192
Parameter
Min.Typ.Max.
High Power State CDMA
2000 1x (V
Frequency Range824849MHz
Linear Gain29dB
Pilot+DCCH 9600
Maximum Linear Output Power
(CDMA 2000 Modulation)
Adjacent Channel Power Rejec-
tion
Pilot+FCH 9600+SCHO 9600
Maximum Linear Output Power
(CDMA 2000 Modulation)
Adjacent Channel Power Rejec-
tion
MODE
LOW)
Low Power State CDMA
2000 1x (V
Frequency Range824849MHz
Linear Gain22dB
Pilot+DCCH 9600
Maximum Linear Output Power
(CDMA 2000 Modulation)
Adjacent Channel Power Rejec-
tion
Efficiency15%P
Pilot+FCH 9600+SCHO 9600
Maximum Linear Output Power
(CDMA 2000 Modulation)
Adjacent Channel Power Rejec-
tion
MODE
HIGH)
FM Mode
Frequency Range824849MHz
Gain30dB
Second Harmonic-33dBc
Third Harmonic<-60dBc
Max CW Output Power3132dBm
Total Efficiency (AMPS mode)47%P
Input VSWR2:1
Output VSWR10:1No damage.
Note: DCCH: Dedicated C ontrol Channel
FCH: Fundamental Channel
CCDF: Complementary Cumulative Distribution Function
Specification
26.5dBm2.5dB Backoff included in IS98D CCDF 1%
-47dBcACPR@885kHz
<-60dBcACPR@1.98MHz
29dBm4.5dB Peak Average Ratio at CCDF 1%
-47dBcACPR@885kHz
<-60dBcACPR@1.98MHz
1620dBm5.4dB Peak to Average Ratio at CCDF 1%
-48dBcACPR@885kHz
<-85dBcACPR@1.98MHz
1620dBm4.5dB Peak to Average Ratio at CCDF 1%
<-50dBcACPR@885kHz
<-65dBcACPR@1.98MHz
6:1No oscillations. >-70dBc
UnitCondition
Case T=25oC, VCC=3.4V,V
V
=0V to 0.5V, Freq=824MHz to
MODE
849MHz (unless otherwise specified)
5.4dB Peak Average Ratio at CCDF 1%
Case T=25oC, VCC=3.4V,V
V
=1.8V to 3V, Freq=824MHz to
MODE
849MHz
=20dBm
OUT
Case T=25°C, VCC=3.4V,V
V
=0V to 0.5V, Freq=824MHz to
MODE
849MHz (unless otherwise specified)
=31dBm (room temperature)
OUT
REG
REG
REG
=2.85V.
2
POWER AMPLIFIERS
=2.85V.
=2.85V,
Rev A1 010830
2-205
Page 4
RF2192
Preliminary
2
Parameter
Min.Typ.Max.
Specification
UnitCondition
DC Supply
Supply Voltage3.03.44.2VThe maximum power out for VCC=3.0V is
28dBm.
Quiescent Current160mAV
4570mAV
V
Current10mA
REG
Current1mA
V
MODE
Turn On/Off Time<40µsTime betwe en V
Total Current (Power Down)10µAV
“Low” Voltage00.5V
V
POWER AMPLIFIERS
REG
“High” Voltage2.752.852.95V
V
REG
“Low” Voltage00.5V
V
MODE
“High” Voltage1.82.853.0V
V
MODE
=Low
MODE
=High
MODE
turned on and PA
REG
REG
line.
reaching full power. Turn on/off time can be
reduced by lowering the bypass capacitor
value on the V
=Low
REG
2-206
Rev A1 010830
Page 5
Preliminary
RF2192
PinFunctionDescriptionInterface Schematic
1GND
2GND
3GND
4RFIN
Ground connection.
Ground connection.
Ground connection.
RF input. An external 100pF series capacitoris required as a DC block.
In addition, shunt inductor and series capacitor are required to provide
2:1VSWR.
RF IN
100 pF
From
Bias
Stages
VCC1
GND1
2
5VREG1
6VMODE
7VREG2
8BIASGND
9GND
10RF OUT
11RF OUT
12RF OUT
132FO
14VCC BIAS
15VCC1
16VCC1
Pkg
GND
Base
Power Down control for first stage. Regulated voltage suppl y for amplifier bias. In Power Down mode, both V
(<0.5V).
For nominal operation (High Power Mode), V
set HIGH, the driver and final stage are dynamically scaled to reduce
the device size and as a result to reduce the idle current.
PowerDown control for the second stage. Regulated voltage supply for
amplifier bias. In Power Down mode, both V
LOW (<0.5V).
Bias circuitry ground. See application schematic.
Ground connection.
RF output and power supply for final stage. This is the unmatched col-
lector output of the second stage. A DC block is required following the
matching components. The biasing may be provided via a parallel L-C
set for resonance at the operating frequency of 824MHz to 849MHz. It
is importantto select an inductor with very low DC resistance with a 1A
current rating. Alternatively,shunt microstrip tec hniques are also applicable and provide very low DC resistance. Low frequency bypassing is
required for stability.
Same as pin 10.See pin 10.
Same as pin 10.
Harmonic trap.This pin connects to the RF output but is used for pro-
viding a low impedance to the second harmonic of the operating frequency.An inductor or transmission line resonating with an on chip
capacitor at 2fo is required at this pin.
Power supply for bias circuitr y. A 100pF high frequency bypass capacitor is recommended.
Power supply for first stage.
Same as Pin 15.
Ground connection. The backside of the package should be soldered to
a top side ground pad which is connected to the ground plane with multiple vias. The pad should have a short thermal path to the ground
plane.
REG
and V
MODE
issetLOW.When
MODE
and V
REG
need to be LOW
need to be
MODE
From Bias
Stages
POWER AMPLIFIERS
RF OUT
Rev A1 010830
2-207
Page 6
RF2192
Preliminary
Evaluation Board Schema t ic
US - CDMA
(Download Bill of Materials from www.rfmd.com.)
2
VCC
C25
4.7 µF
C30
TL
3
POWER AMPLIFIERS
C9
100 pF
R2
510 Ω
C27
100 pF
C26
4.7 µF
0 Ω
J1
RF IN
100 pF
VREG
VMODE
C5
L2
5.6 nH
C24
12 pF
161131415
2
3
4
R3
0 Ω
R4
0 Ω
R1
C6
100 pF
12
11
10
L4
39 nH
C13
100 pF
L5
1nH
TL
5
TL
1
98765
* L1 is a High Q inductor (i.e., Coilcraft 0805HQ-series).
**C1 and C14 are High Q capacitors