Datasheet RF2175, RF2175PCBA Datasheet (RF Micro Devices)

Preliminary

RF2175

2

Typical Applications

• 3V TETRA Cellular Handsets

• 3V CDMA Cellular Handsets

Product Description

The RF2175 is a high-power, high-efficiency linear ampli­fier IC targeting 3V handheld systems. The device is
manufactured on an advanced Gallium Arsenide Hetero­junction Bipolar Transistor (HBT) process, and has been
designed for use as the final RF amplifier in TETRA
hand-held digital cellular equipment, spread-spectrum
systems, and other applications in the 380MHz to
512 MHz band. The RF2175 has an analog bias control
voltagetomaximizeefficiency.Thedeviceisself-con­tained with 50Ω input, and the output can be easily
matched to obtain optimum power, efficiency, and linear­ity characteristics. The package is a smallSSOP-16 plas­tic with backside ground.

3V 400MHZ LINEAR AMPLIFIER

• Portable Battery-Powered Equipment

-A-

0.196

0.189

8° MAX

0° MIN

0.154

0.237

0.035

0.016

0.012

0.008

0.025

0.063

0.057
NOTES:

1. Shaded lead in Pin 1.

2. Lead coplanarity - 0.003 with respect to datum "A".

3. Lead standoff is specified from the lowestpoint on the

0.010

0.007

package underside.

0.004

0.002

Note 3

0.087

0.071

Exposed Heat

EXPOSED HEATSINK

Sink

0.123

0.107

2

POWER AMPLIFIERS

Optimum Technology Matching® Applied

Si BJT GaAs MESFETGaAs HBT
Si Bi-CMOS

VCC

NC

Q1C

GND1

RF IN

VREG

ü

SiGe HBT

1

2LTUNE

3

4

5

6

7

8

Bias

Si CMOS

16

15

14

13

12

11

10

9

VBIAS

RF OUT

RF OUT

RF OUT

Functional Block Diagram

Package Style: SSOP-16 Slug

Features

• Single 3V Supply

• 31.8dBm Linear Output Power

• 37.5 dB Linear Gain

• 30% Linear Efficiency

• On-Board Power Down Mode

• 380MHz to 512MHz Operation

Ordering Information

RF2175 3V 400MHz Linear Amplifier
RF2175 PCBA Fully Assembled Evaluation Board

RF Micro Devices, Inc.
7628 Thorndike Road
Greensboro,NC 27409, USA

Tel [phone]

Fax [phone]

http://www.rfmd.com

Rev A6 010718

2-243

2

RF2175

Absolute Maximum Ratings

Parameter Rating Unit

Supply Voltage (RF Off) +8.0 V
Supply Voltage (RF Applied) +4.5 V
Mode Voltage (V
Control Voltage (V
Input RF Power (Avg.) +5 dBm

Output VSWR - Inband 6:1
Output VSWR - Out of Band 20:1
Operating Ambient Temperature -30 to +100 °C
Storage Temperature -40 to +120 °C
Moisture Sensitivity JEDEC Level 5 *

)+5.0V

BIAS

)+5.0V

REG

DC
DC
DC
DC

Preliminary

Caution! ESD sensitive device.

RF Micro Devices believesthe furnishedinformation is correctand accurate
at the time of this printing. However, RF Micro Devices reserves the right to
make changes to its products without notice. RF Micro Devices does not
assume responsibility for the use of the described product(s).

POWER AMPLIFIERS

Parameter

Min. Typ. Max.

Overall

Usable Frequency Range 380 512 MHz
Typical Frequency Range 410 to 420 MHz
Linear Gain 35.0 37.5 39.0 dB
Harmonic -30 dBc
P3dB Output Power 34 dBm
Linear Output Power

(TETRA Modulation)
To tal Linear Efficiency 25 30 %
Adjacent Channel Power Rejec-

tion

Specification

31.8 dBm

-35 dBc ACPR@25 k Hz, TETRA modulation

-45 dBc ACPR@50 k Hz, TETRA modulation

Unit Condition

T=25°C, VCC=3.6V, Freq=410MHz to
420MHz unless otherwise specified, 25%

duty cycle. P

=31.8dBm

OUT

Power Supply

Power Supply Voltage 3.0 3.6 4.5 V
Idle Current 230 300 mA All V

Current 1650 mA All VCCpins, P

V

CC

Current 13 mA Pin 8

V

REG

Current 3 mA Pin 16

V

BIAS

Turn On/Off Time <150 µs Time for power to rise to 95% o f its final

Total Current (Power Down) 10 µAV

“Low” Voltage 0 0.2 V

V

REG

“High” Voltage 2.7 2.8 2.9 V

V

REG

V

Control Voltage Range 2.8 2.9 V

BIAS

* The RF2175 is considered JEDEC Level 5 for moisture sensitivity with a maximum peak reflow temperature of 220°C. To assure reli-

able performance, this part must be handled in accordance with JEDEC specifications for a Level 5 part.

pins, no RF input.

CC

=31.8dBm

OUT

value. Measured with 4.7 µF and 2.2µF
capacitors on both V

=Low

REG

REG

and V

BIAS

lines.

2-244

Rev A6 010718

Preliminary

RF2175

Pin Function Description Interface Schematic

1VCC
2LTUNE
3NC

4Q1C
5GND1

6RFIN
7NC

8VREG

9NC
10 NC
11 NC
12 RF OUT

13 RF OUT
14 RF OUT

15 NC
16 VBIAS

Pkg

GND

Base

Power supply for input bias circu itry. A 1nF hig h frequency bypass
capacitor is recommended.

Interstage Tuning. A shunt inductor to GND is required to optimize the
match.

No connection.
Powersupply for stage 1. VCCshould be fed througha 25nH or greater

inductor with a decoupling capacitor on the V
Ground for stage 1. For best performance, keep traces physically short

and connect immediately to ground plane. This ground should be iso­lated from the backside ground contact.

RF input. An external D C blocking capacitor is required if this port is
connected to a DC path to ground or a DC voltage.

No connection.
Power Down control. When this pin is “low”, all circuits are shut off.

When this pin is 2.8V, all circuits are operating normally. V
regulated 2.8V for the amplifier to operate properly over all specified

temperature and voltage ranges. A dropping resistor from a higher reg­ulated voltage may be used to provide the required 2.8V.A 100pF high
frequency bypass capacitor is recommended.

No connection.
No connection.
No connection.
RF output and power supply for the output stage. The bias for the out-

put stage is provided through this pin and pin 13. A n external matching
network is required to provide the optimum load impedance; see the
application schematics for details.

Same as pin 12.
Harmonic trap. This pin connects to the RF outp ut but is used for pro-

viding a low impedance to the second harmonic of the operating fre­quency.An inductor or transmission line resonating with a shunt
capacitor at 2f

No connection.
The bias pin allows higher efficiency in low power power modes. When

operating at full output, VBIAS should be 2.8V.
Ground connection. The backside of the package should be soldered to

a top side ground pad, which is connected to the ground plane with
multiple vias. The pad should have a short thermal path to the ground
plane.

is connec ted to this pin.

0

CC

side.

requires a

PD

2

POWER AMPLIFIERS

Rev A6 010718

2-245

2

RF2175

VCC = 3.0 V to 5.2 V

V

CC

0 Ω

Application Schematic

380MHz

1nF2.2 uF

1

Preliminary

33 nH

2.2 uF100 pF

16

4.7 µF

VMODE

56 nH

5.1 nH

POWER AMPLIFIERS

RF IN: TETRA Modulation

RF IN

VREG

33 nH

4.7 pF

1nF

100 pF2.2 uF

2

3

4

5

6

7

8

VREG (VACP) = 2.6 V on, 0 V off

25% duty cycle, 14.17 ms pulse width

Bias

15

5.6 nH

14

13

12

12.55 nH

11

10

9

5.6 pF

100 pF

3.6 nH

56 pF

1nF

12 pF

V

CC

RF OUT

2-246

Rev A6 010718

Preliminary

VCC

J1

RF IN

VREG

R1

0 Ω

50 Ωµstrip

L4

56 nH

4.7 pF

C16

C2

2.2 uF

L3

33 nH

C5

2.2 uF

Evaluation Board Schemati c

(Download Bill of Materials from www.rfmd.com.)

C3

1nF

L5

4.7 nH

C6

1nF

C8

100 pF

C15

100 pF

1

2

3

4

5

6

7

8

Bias

16

15

14

13

12

11

10

9

2175400A

L7

5.6 nH

L6

12.55 nH

C14

2.2 uF

C13

5.1 pF

C4

100 pF

P1-1 VCC

P1-3 VREG

L2

33 nH

C17

4.7 µF

L1

3.6 nH

C9

56 pF

CON3

RF2175

VMODE

2

C11
1nF

50 Ωµstrip

C10

12 pF

P1

1
2

GND

3

P2

1

P2-1 VCC

2

P2-3 VMODE

3

CON3

GND

J2

RF OUT

VCC

POWER AMPLIFIERS

Rev A6 010718

2-247

2

RF2175

Preliminary

Evaluation Board Layout

Board Size 2.0” x 2.0”

Board Thickness 0.028”, Board Material FR-4

POWER AMPLIFIERS

2-248

Rev A6 010718