Page 1
RF2173
2
Typical Applications
• 3V GSM Cellular Handsets
• 3V Dual-Band/Triple-Band Handsets
•GPRSCompatible
Product Description
The RF2173 is a high power, high efficiency power amplifier module offering high performance in GSM or GPRS
applications.The device is manufactured on an advanced
GaAs HBT process, and has been designed for use as
the final RF amplifier in GSM hand-held digital cellular
equipment and other applications in the 800 MHz to
950 MHz band. On-board power c ontrol provides over
70 dB of control range with an analog voltage input, and
provides power down with a logic "low" for standby operation. The device is self-contained with 50Ω input and the
output can be easily matched to obtain optimum power
and efficiency characteristics. The RF2173 can be used
together with the RF2174 for dual-band operation. The
deviceis packaged in an ultra-small plastic package, minimizing the required board space.
Optimum Technology Matching® Applied
Si BJT GaAs MESFETGaAs HBT
Si Bi-CMOS
ü
SiGe HBT
Si CMOS
3V GSM P OWER AMPLIFIER
• Commercial and Consumer Systems
• Portable Battery-Powered Equipment
2
3.75
Dimensions in mm.
INDEX AREA
0.75
0.50
3.75
12°
3
0.75
1.00
0.65
0.90
0.05
0.00
NOTES:
2
3
4
5 Package Warpage: 0.05 max.
0.45
0.28
+
1.50 SQ
3.20
4.00
Shaded Pin is Lead 1.1
Dimension applies to plated terminal and is measured between
0.10 mm and 0.25 mm from terminal tip.
The terminal #1 identifier and terminal numbering convention
shall conform to JESD 95-1 SPP-012. Details of terminal #1
identifier are optional, but must be located within the zone
indicated. The identifier may be either a mold or marked
feature.
Pins1 and 9 are fused.
Package Style: LCC, 16-Pin, 4x4
Features
2
0.80
TYP
1
1
POWER AMPLIFIERS
4.00
1.60
Functional Block Diagram
Rev A4 010914
GND16VCC215VCC214NC132F0
1
2GND2
3RF IN
4GND1
5
VCC1
7
6
APC2
APC1
12 RF OUT
11 RF OUT
10 RF OUT
8
VCC
• Single 2.7V to 4.8V Supply Voltage
• +36dBm Output Power at 3.5V
•32dBGainwithAnalogGainControl
• 56% Efficiency
• 800MHz to 950MHz Operation
• Supports GSM and E-GSM
9
Ordering Information
GND
RF2173 3V GSM Power Amplifier
RF2173 PCBA Fully Assembled Evaluation Board
RF Micro Devices, Inc.
7628 Thorndike Road
Greensboro,NC 27409, USA
Tel (336) 664 1233
Fax (336) 664 0454
http://www.rfmd.com
2-221
Page 2
2
RF2173
Absolute Maximum Ratings
Parameter Rating Unit
Supply Voltage -0.5 to +6.0 V
Power Control Voltage (V
) -0.5 to +3.0 V
APC1,2
DC Supply Current 2400 mA
Input RF Power +13 dBm
Duty Cycle at Max Power 50 %
Output Load VSWR 10:1
Operating Case Temperature -40 to +85 °C
Storage Temperature -55 to +150 °C
DC
Caution! ESD sensitive device.
RF Micro Devices believesthe furnishedinformation is correctand accurate
at the time of this printing. However, RF Micro Devices reserves the right to
make changes to its products without notice.RF Micro Devices does not
assume responsibility for the use of the described product(s).
Parameter
Min. Typ. Max.
POWER AMPLIFIERS
Overall
Specification
Unit Condition
Temp=25°C, VCC=3.5V,V
P
=+6dBm, Freq=880MHz to 915MHz,
IN
APC1,2
25% Duty Cycle, pulse width=1154µs
Operating Frequency Range 880 to 915 MHz See evaluation board schematic.
Usable Frequency Ran ge 800 to 950 MHz
Maximum Output Power +35.0 +36 dBm Temp=25°C, V
+34.0 +35.2 dBm Temp=+25°C, V
+34.0 dBm Temp=+85°C, V
+33.0 +34.0 dBm Temp=25°C, V
+32.5 dBm Temp=+85°C, V
Total Efficiency 50 56 % At P
56 % At P
12 % P
5%P
OUT,MAX
OUT,MAX
=+20dBm
OUT
=+10dBm
OUT
=3.5V,V
CC
=3.2V,V
CC
=3.2V,V
CC
=2.7V,V
CC
=2.7V,V
CC
,VCC=3.2V
,VCC=3.0V
APC1,2
APC1,2
Input Power for Max Output +4 +6 +8 dBm
Output No ise Power -72 dBm RBW=100kHz, 925MHz to 935MHz,
P
OUT,MIN<POUT<POUT,MAX
P
IN,MIN<PIN<PIN,MAX
,VCC=3.0V to 5.0V
-81 dBm RBW=100kHz, 935MHz to 960MHz,
P
OUT,MIN<POUT<POUT,MAX
Forward Isolation -45 -40 dBm V
-30 dBm V
P
IN,MIN<PIN<PIN,MAX
=0.2V,PIN=+6dBm
APC1,2
=0.2V,PIN=+8dBm
APC1,2
,VCC=3.0V to 5.0V
Second Harmonic -50 -38 dB c
Third Harmonic -65 -43 dBc
All Other Non-Harmonic
-36 dBm
Spurious
Input Impedance 50 Ω
Optimum Source Impedance 40+j10 Ω For best noise performance
Input VSWR 2.5:1 P
4:1 P
OUT,MAX
OUT<POUT,MAX
Output Load VSWR 10:1 Spurious<-36dBm, V
-5dB<P
OUT<POUT,MAX
-5dB
APC1,2
RBW=100kHz
Output Load Impedance 1.5-j1.7 Ω Load Impedance presented at RF OUT pad
=2.6V,
=2.6V
=2.6V
APC1,2
=2.6V
APC1,2
=2.6V
=2.6V
APC1,2
,
,
=0.2V to 2.6V,
2-222
Rev A4 010914
Page 3
RF2173
Parameter
Power Control V
Power Control “ON” 2.6 V Maximum P
Power Control “OFF” 0.2 0.5 V Minimum P
Power Control Range 75 dB V
Gain Control Slope 5 100 150 dB/V P
APC Input Capacitance 10 pF DC to 2MHz
APC Input Current 4.5 5 mA V
Turn On/Off Time 100 ns V
APC1VAPC2
Min. Typ. Max.
Specification
Unit Condition
input
APC1,2
=-10dBm to +35dBm
OUT
APC1,2
10 µAV
APC1,2
APC1,2
OUT
OUT
=0.2V to 2.6V
=2.6V
=0V
=0to2.6V
Power Supply
Power Supply Voltage 3.5 V Specifications
2.7 4.8 V Nominal operating limits, P
5.5 V With maximum output load VSWR 6:1,
Power Supply Current 2 A DC Current at P
50 200 375 mA Idle Current, PIN<-30dBm
110µAP
110µAP
<+35dBm
P
OUT
<-30dBm, V
IN
<-30dBm, V
IN
, Voltage supplied to the
, Voltage supplied to the input
<+35dBm
OUT
OUT,MAX
=0.2V
APC1,2
=0.2V,Temp=+85°C
APC1,2
2
POWER AMPLIFIERS
Rev A4 010914
2-223
Page 4
2
RF2173
Pin Function Description Interface Schematic
1GND
2 GND2
3RFIN
4 GND1
POWER AMPLIFIERS
5 VCC1
6APC1
7APC2
8VCC
9GND
10 RF OUT
11 RF OUT
12 RF OUT
13 2F0
14 NC
15 VCC2
16 VCC2
Pkg
GND
Base
Internally connected to the ground slug.
Ground connection for the driver stage. To minimize the noise power at
the output, it is recomm ended to connect this pin with a trace of about
40mil to the ground plane. This will slightly reduce the small signal
gain, and lower the noise power. It is important for stability that this pin
have it’s own vias to the grou nd plane, minimizing common inductance.
RF Input. This is a 50Ω input, but the actual impedance depends on the
interstage m a tching network c onnected to pin 5. An external DC blocking capacitor is requiredif this port is connectedto aD C path to ground
or a DC voltage.
Ground connection for the pre-amplifier stage. Keep traces physically
short and connect immediately to the ground plane for best performance. It is important for stability that this pin has it’s own vias to the
groundplane, to minimize any common inductance.
Power supply for the pre-amplifier stage and interstage matching. This
pin forms the shunt inductance needed for proper tuning of the int erstage match. Refer to the application schematic for proper configuration. Note that position and value of the components are important.
Power Control for the driver stage and pre-amplifier. When this pin is
"low," all circuits are shut off. A "low" is typically 0.5V or less at room
temperature. A shunt bypasscapacitor is required. During normal operation this pin is the power control.Controlrange varies from about 1.0V
for -10dBm to 2.6V for +35dBm RF output power. The maximum power
that can be achieved depends on the actual output matching; see the
application information for more details. The maximum current into this
pin is 5mA when V
Power Control for the output stage. See pin 6 for more details. See pin 6.
Power supply for the bias circuits. See pin 6.
Internally connected to the ground slug.
RF Output and power supply for the output stage. Bias voltage for the
final stage is provided through this wide output pin. An external matching networ k is required to provide the optimum load impedance.
Same as pin 10. Same as pin 10.
Same as pin 10. Same as pin 10.
Connection for the second harmonic trap. This pin is internally con-
nected to the RF OUT pins. The bonding wire together with an external
capacitor form a series resonator that should be tuned to the second
harmonic frequencyin orderto increaseefficiency and reduce spurious
outputs.
Not connected.
Power supply for the driver stage and interstage matching. This pin
forms the shunt inductance needed for proper tuning of the interstage
match. Please refer to the application schematic for proper configuration, and note that position and value of the components are important.
Same as pin 15. Same as pin 15.
Ground connecti on for the output stage.This pad should be connected
to the ground plane by vias directly under the device. A short path is
required to obtain optimum performance, as well as to provide a good
thermal path to the PCB for maximum heat dissipation.
=2.6V,and 0m A when V
APC1
APC
=0V.
See pin 15.
RF IN
From Bias
Stages
See pin 3.
See pin 3.
VCC
APC
GND
GND
From Bias
Stages
Same as pin 10.
From Bias
Stages
VCC1
GND1
RF OUT
GND
PCKG BASE
VCC2
GND2
To RF
Stages
2-224
Rev A4 010914
Page 5
RF2173
Theory of Operation and Application Information
The RF2173 is a three-stage device with 32 dB gain at
full power. Therefore, the drive required to fully saturate the output is +3dBm. Based upon HBT (Heterojunction Bipolar Transistor) technology, the part
requires only a single positive 3V supply to operate to
full specification. Power control is provided through a
single pin interface, with a separate Power Down control pin. The final stage ground is achieved through the
large pad in the middle of the backside of the package.
First and second stage grounds are brought out
through separate ground pins for isolation from the output. These grounds should be connected directly with
vias to the PCB ground plane, and not connected with
the output ground to form a so called “local ground
plane” on the top layer of the PCB. The output is
brought out through the wide output pad, and forms the
RF output signal path.
The amplifier operates in near Class C bias mode. The
final stage is "deep AB", meaning thequiescent current
is very low.As the RF drive is increased, the finalstage
self-biases, causing the bias point to shift up and, at
full power, draws about 2000mA. The optimum load for
the output stageis approximately 1.2Ω.Thisistheload
at the output collector, and is created by the series
inductance formed by the output bond wires, vias, and
microstrip, and 2 shunt capacitors external to the part.
The optimum load impedance at the RF Output pad is
1.5-j1.7Ω. With this match, a 50Ω terminal impedance
is achieved. The input is internally matched to 50Ω
with just a blocking capacitor needed. This data sheet
defines the configuration for GSM operation.
The input is DC coupled; thus, a blocking cap must be
inserted in series. Also, the first stage bias may be
adjusted by a resistive divider with high value resistors
on this pin to V
however, no external adjustment is necessary as internal resistors set the bias point optimally.
VCC1 and VCC2providesupply voltage to the first and
second stage, as well as provides some frequency
selectivity to tune to the operating band. Essentially,
the bias is fed to this pin through a short microstrip. A
bypass capacitor sets the inductance seen by the part,
so placement of the bypass cap can affect the frequency of the gain peak. This s upply should be
bypassed individually with 100 pF capacitors before
being combined with V
vent feedback and oscillations.
and ground. For nominal operation,
PC
for the output stage to pre-
CC
The RF OUT pin provides the output power. Bias for
the final stage is fed to this output line, and the feed
must be capableof suppor ting the approximately 2A of
current required. Care should be taken to keep the
losses low in the bias feed and output components. A
narrow microstrip line is recommended because DC
losses in a bias choke will degrade efficiency and
power.
While the part is safe under CW operation, maximum
power and reliability will be achievedunder pulsed conditions. The data shown in this data sheet is based on
a 12.5% duty cycle and a 600µs pulse, unless specified otherwise.
The part will operate over a 3.0V to 5.0V range. Under
nominal conditions, the power at 3.5V will be greater
than +34.5dBm at +90°C. As the voltage is increased,
however, the outputpowerwill increase. Thus, in a system design, the ALC (Automatic Level Control) Loop
will back down the power to the desired level. This
must occur during operation, or the device may be
damaged from too much power dissipation. At 5.0V,
over +38dBm may be produced; however, this level of
power is not recommended, and can cause damage to
the device.
The HBT breakdown voltage is >20V, so there are no
issue with overvoltage. However, under worst-case
conditions, with the RF drive at full power during transmit, and the output VSWR extremely high, a low load
impedance at the collector of the output transistors can
cause currents much higher than normal. Due to the
bipolar nature of the devices, there is no limitation on
the amount of current de device will sink, and the safe
current densities could be exceeded.
High current conditions are potentially dangerous to
any RF device. High currents leadto high channeltemperatures and may force early failures. The RF2173
includes temperature compensation circuits in the bias
network to stabilize the RF transistors, thus limiting the
current through the amplifier and protecting the
devices from damage. The same mechanism works to
compensate the currents due to ambient temperature
variations.
To avoid excessively high currents it is impor tant to
control the V
higher than 4.0V,such that the maximum output power
is not exceeded.
when operating at supply voltages
APC
2
POWER AMPLIFIERS
Rev A4 010914
2-225
Page 6
RF2173
1nF
Application Schematic
V
CC
120 pF
Very close to pin 15/16
2
Instead of a stripline,
0.9 pF
1 16 15 14 13
.040"
POWER AMPLIFIERS
RF IN
180 Ω
1nF
10 nH
V
CC
33 pF
2
3
4
33 pF33 pF
APC
12
11
10
98765
V
CC
33 pF
Note: All capacitors are standard 0402 multi layer
an inductor of ~10 nH
canbeused
Quarter wave
length
9pF
Spacing between
edge of device and
capacitor 0.062"
14 pF
33 pF
V
CC
50 Ωµstrip
center of capacitors
Instead of a stripline,
an inductor of 2.7 nH
can be used
33 pF
6.2 pF
Distancecenter to
0.416"
RF OUT
2-226
Rev A4 010914
Page 7
Internal Schematic
RF2173
RF IN
APC1
1.0k
Ω
PKG BASE
5
5
VCC1
Ω
Ω
4.5 pF
400
APC1
Ω
VCC
VCC2 RF OUT
GND2
300
APC2
Ω
VCC
PKG BASE
2
POWER AMPLIFIERS
Rev A4 010914
2-227
Page 8
RF2173
Evaluation Board Schema t ic
(Download Bill of Materials from www.rfmd.com.)
2
+
C19
3.3 uF
C5
1nF
C21
120 pF
C14
33 pF
C17
1nF
VCC
0.9 pF
P1
NC
1
2
GND
3
P1-3 VCC
P1-4 VCC
4
GND
5
CON5
1 16 15 14 13
POWER AMPLIFIERS
J1
RF IN
VCC
C20
3.3 uF
50 Ωµstrip
+
C12
1nF
VAPC
C11
33 pF
C25
10 nF
C1
1nF
R2
180 Ω
L1
10 nH
C16
1nF
2
3
4
C13
33 pF
C10
12
11
10
98765
2173400C
C15
33 pF
VCC
C7
3.3 uF
+
C8
1nF
C9
33 pF
L2
8.8 nH
C3
9pF
C22
1nF
C2
33 pF
C6
14 pFC46.2 pF
C23
10 nF
C18
3.3 uF
50 Ωµstrip
+
J2
RF OUT
VCC
J3
VAPC
C24
10 nF
50 Ωµstrip
2-228
Rev A4 010914
Page 9
Evaluation Board Layout
Board Size 2.0” x 2.0”
Board Thickness 0.032”; Board Material FR-4; Multi-Layer
RF2173
2
POWER AMPLIFIERS
Rev A4 010914
2-229
Page 10
2
RF2173
Typical Test Setup
Power Supply
V+V- S+S-
POWER AMPLIFIERS
RF Generator
Spectrum
Analyzer
10dB/5W3dB
Buffer
x1 OpAmp
Pulse
Generator
A buffer amplifier is recommendedbecause the current into the
changes with voltage. As analternative, the voltage may be
V
APC
monitored with an oscilloscope.
Notes about testing the RF2173
The test setup shown above includes two attenuators. The 3dB pad at the input is to minimize the effects that the
switching of the input impedance of the PA has on the signal generator. When V
input impedance change can cause the signal generator to vary its output signal, either in output level or in frequency.
Instead of an attenuator an isolator m ay also be used. The attenuator at the output is to prevent damage to the spectrum analyzer, and should be able to handle the power.
It is important not to exceed the rated supply currentand output power. When testing the device at higher than nominal
supply voltage, the V
the output it is important to monitor the forward power through a directional coupler. The forward power should not
exceed +36dBm, and V
this respect. To avoid damage, it is recommended to set the power supply to limiting the current during the burst, not to
exceed the maximum current rating.
should be adjusted to avoid the output power exceeding +36dBm. During load-pull testing at
APC
needs to be adjusted accordingly. This simulates the behavior for the power control loop in
APC
is switched quickly, the resulting
APC
2-230
Rev A4 010914
Loading...