Datasheet RF2162, RF2162PCBA Datasheet (RF Micro Devices)

Preliminary

RF2162

2

Typical Applications

• 3V CDMA/AMPS Cellular Handsets

• 3V JCDMA/TACS Cellular Handsets

• 3V TDMA/AMPS Cellular Handsets

Product Description

The RF2162 is a high-power, high-efficiency linear ampli­fier IC targeting 3V handheld systems. The device is
manufactured on an advanced Gallium Arsenide Hetero­junction Bipolar Transistor (HBT) process, and has been
designed for use as the final RF amplifier in dual-mode
3V CDMA/AMPS hand-held digital cellular equipment,
spread-spectrum systems, and other applications in the
800 MHz to 960MHz band. The RF2162 has an analog
bias control voltage to maximize efficiency. The device is
self-contained with 50Ω input and the output can be eas­ily matched to obtain optimum power, efficiency, and lin­earity characteristics. The device is packaged in a
compact 4mmx4mm, 16-pin, leadless chip carrier.

3V 900MHZ LINEAR AMPLIFIER

• Spread-Spectrum Systems

•CDPDPortableDataCards

• Portable Battery-Powered Equipment

2

3.75

Dimensions in mm.

INDEX AREA

0.75

0.50

3.75

12°

3

0.75

1.00

0.65

0.90

0.05

0.00

NOTES:

2

3

4
5 Package Warpage: 0.05max.

0.45

0.28

+

1.50 SQ

3.20

4.00

Shaded PinisLead 1.1
Dimension appliestoplated terminal and is measured between

0.10 mmand0.25 mm from terminal tip.
The terminal#1identifier and terminal numbering convention

shall conformtoJESD 95-1 SPP-012. Details of terminal #1
identifier areoptional,but must be located within the zone
indicated. Theidentifiermay be either a mold or marked
feature.

Pins 1and9 are fused.

2

0.80
TYP

1

1

POWER AMPLIFIERS

4.00

1.60

Optimum Technology Matching® Applied

Si BJT GaAs MESFETGaAs HBT
Si Bi-CMOS

GND

GND

RFIN

ü

GND

2

3

4

VREG1

SiGe HBT

VCC1

161 131415

VMODE

VCC1

VREG2

VCC BIAS

BIAS GND

Si CMOS

2F0

12

RF OUT

11

RF OUT

10

RF OUT

98765

GND

Functional Block Diagram

Package Style: LCC, 16-Pin, 4x4

Features

• Single 3V Supply

• 29dBm Linear Output Power

• 29dB Linear Gain

• 35% Linear Efficiency

• On-board Power Down Mode

• 800MHz to 960MHz Operation

Ordering Information

RF2162 3V 900MHz Linear Amplifier
RF2162 PCBA Fully Assembled Evaluation Board

RF Micro Devices, Inc.
7628 Thorndike Road
Greensboro,NC 27409, USA

Tel [phone]

Fax [phone]

http://www.rfmd.com

Rev A17 011011

2-205

2

RF2162

Absolute Maximum Ratings

Parameter Rating Unit

Supply Voltage (RF off) +8.0 V
Supply Voltage (P
Mode Voltage (V
Control Voltage (VPD)+3.0V
Input RF Power +12 dBm

Operating Case Temperature -30 to +110 °C
Storage Temperature -30 to +150 °C
Moisture Sensitivity Modified JEDEC Level 2

≤31dBm) +4.5 V

OUT

)+3.0V

MODE

DC

DC
DC
DC

RF Micro Devices believesthe furnishedinformation is correctand accurate
at the time of this printing. However, RF Micro Devices reserves the right to
make changes to its products without notice.RF Micro Devices does not
assume responsibility for the use of the described product(s).

Preliminary

Caution! ESD sensitive device.

Parameter

POWER AMPLIFIERS

Min. Typ. Max.

Specification

Unit Condition

Overall

Usable Frequency Range 800 960 MHz
Typical Frequency Range 824-849 MHz
Linear Gain 28 29 31 dB
Second Harmonic (including

second harmonic trap)
Max CW Output Power 31.5 dBm
To tal Efficiency (AMPS mode) 50 %
Maximum Linear Output Power

(CDMA Modulation)
Total Linear Efficiency 30 35 %
Adjacent Channel Power Rejec-

tion

Noise Power -90 -89 dBm V

Maximum Linear Output Power

(CDMA Modulation)
To tal Efficiency (AMPS mode) 50 %
Max CW Output Power 30 30.5 31 dBm
Total Linear Efficiency 30 36 %
Adjacent Channel Power Rejec-

tion

Input VSWR <2:1
Output Load VSWR 10:1 No damage.

-30 dBc

29 dBm

-46 -44 dBc ACPR @ 885kHz

-58 -56 dBc ACPR @1980kHz

29 dBm V

-46 -44 dBc ACPR @ 885kHz

-58 -56 dBc ACPR @ 1980kHz

TDMA

Linear Output Power 30 dBm
Linear ACP -29 -28 30kHZ offset
Linear ALT CP -49 -48 60kHZ offset
Efficiency 45 46 O/P=30dBm

Power Supply

Power Supply Voltage 3.0 3.4 4.5 V
Idle Current 135 200 mA V

V

Current 10 15 mA Total pins 6 and 7, V

REG

Turn On/Off time <100 ns
Total Current (Power down) 10 µAV

“Low” Voltage 0 0.2 V

V

REG

V

“High” Voltage 2.7 2.8 2.9 V

REG

VMODE Bias Control Voltage

Range

0to2.5 V

T=25°C, VCC=3.4V, Freq=824MHz to
849MHz unless otherwise specified

=3.4V; BW=30kHz; RX Band NF mea-

CC

sure from TX center band to RX center band.

=3.0V

CC

=0Vto0.5V

MODE

=2.8V

REG

=Low

PD

2-206

Rev A17 011011

Preliminary

RF2162

Pin Function Description Interface Schematic

1GND
2GND1

3GND1
4RFIN

5VREG1

6VMODE
7VREG2

8GND
9GND

10 RF OUT

11 RF OUT
12 RF OUT
13 2FO

14 VCC BIAS
15 VCC1

16 VCC1

Pkg

GND

Base

Ground connection. Connect to package base ground. This ground
should be isolated from the ba ckside ground contact on top metal layer.

Ground for stage 1. Keep traces physically short and connect immedi­ately to ground plane for best performance. This ground should be iso­lated from the backside ground contact on top metal layer.

Same as Pin 2.
RF input. An external D C blocking capacitor is required if this port is

connected to a DC path to ground or a DC voltage.

RF IN

Enable voltage for first stage. When this pin is “low”, all circuits are shut
off. When this pin is 2.8V, all circuits are operating normally. V

requires a regulated 2.8V for the amplifier to operate properly over all
specified tem perature and voltage ranges. A dropping resistor from a
higher regulated voltage may be u sed to provide the required 2.8V. A
100pF high frequency bypass capacitor is recommended.

This is an ana log bias current control pin. T he range is 0V for minimum
bias to 3.0 for maximum bias.

Enable voltage for second or output stage. When this pin is “low”, all
circuits are shut off. When this pin is 2.8V, all circuits are operating nor­mally. V

erly over all specified temperature and voltage ranges. A dropping
resistor from a higher regulated voltage may be used to provide the
required 2.8V. A 100pF h igh frequency bypass capacitor is recom­mended.

Bias circuitry ground. See application schematic.
Ground connection. Connect to package base ground. This ground

should be isolated from the ba ckside ground contact on top metal layer.
RF output and power supply for the output stage. The bias for the out-

put stage is provided through this pin and pin 13. A n external matching
network is required to provide the optimum load impedance; see the
application schematics for details.

Same as pin 10. See pin 10.
Same as pin 10.
Harmonic trap. This pin connects to the RF output but is used for pro-

viding a low impedance to the second harmonic of the operating fre­quency.An inductor or transmission line resonating with an on chip
capacitor at 2fo is required at this pin.

Power supply for bias circuitry. A 100pF high frequency bypass capaci­tor is recommended.

Interstage tuning and bias supply for first stage.
Interstage tuning and bias supply for first stage.
Ground connection. The backside of the package should be soldered to

a top side ground pad which is connected to the ground plane with mul­tiple vias. The pad should have a short thermal path to the ground
plane.

requires a regulated 2.8V for the amplifier to operate prop-

REG

REG

From Bias
Stages

From Bias
Stages

VCC1

GND1

RF OUT

2

POWER AMPLIFIERS

Rev A17 011011

2-207

2

RF2162

Application Schematic - US CDMA

V

CC

100 pF

100 pF

Interstage tuning for centering

frequency response

TL

3

1nH

10 nF

100 pF

Preliminary

Bypassing for V

2nd Harmonic Trap

CC

1.8 nH

161 131415

To Vary Gain

100 pF

100 pF

15 nH

330

Ω

100 pF

2

3

4

0

Ω

0

Ω

POWER AMPLIFIERS

RF IN

Matching network for

optimum input return loss

10 nH

100 pF

TL

4

12

11

10

98765

Bias Return

Bypassing for

and V

V

REG1

REG2

TL

27 nH*

1

9.1 pF** 5.1 pF**

TL

1pF

100 pF

2

RF OUT

Matching network for
optimum load impedance

VREG

1k

VMODE

Ω

* High Q inductor (i.e., Coilcraft 0805HQ-series).
**High Q capacitors (i.e., Johanson C-series).

2-208

Rev A17 011011

Preliminary

RF2162

Application Schematic - US TDMA

To Vary Gain

RF IN

Matching network for

optimum input return loss

VREG

Interstage tuning for

centering frequency response

100 pF

820 Ω

100 pF

15 nH

100 pF

C30

2

3

4

P1-1

0 Ω

TL

5

1.5 nH

161 131415

100 pF

27 nH

100 pF

10 nF

Bypassing for V

2nd Harmonic Trap

3.6 pF

TL

7

100 pF

16 nH*

1pF

12

TL

11

1

10

TL

12 pF**

98765

Bias Return

Bypassing for
V

and V

REG1

REG2

* L1 is a High Q inductor (i.e.,Coilcraft 0805HQ-series).
**C1 and C14 are High Q capacitors (i.e., Johanson C-series).

1.5 nH

2

Matching network for
optimum load
impedance

TL

3

4.7 pF**

CC

100 pF

2

POWER AMPLIFIERS

RF OUT

VMODE

Rev A17 011011

1kΩ

2-209

RF2162

Preliminary

Evaluation Board Schematic - US CDMA

(Download Bill of Materials from www.rfmd.com.)

2

P1-1

C25

C27

100 pF

C10

4.7 µF

4.7 µF

C30

2

3

4

R3

0 Ω

TL

4

L3

1.8 nH

TL

3

161 131415

R4

0 Ω

100 pF

18 nH

C13

100 pF

C6

L5

1nH

TL

5

12

TL

11

10

98765

L4

1

2162400B

P1

P1-1 VCC

P2-1 VREG

POWER AMPLIFIERS

1
2

P2

1
2

J1

RF IN

GND

VMODEP2-2

C18

100 pF

C5

100 pF

L2

15 nH

R2

C2

4.7 uF

C28

10 nF

C4

100 pF

L1*

TL

C1** C14**

C17

1pF

C3

100 pF

2

J4

RF OUT

2-210

P2-1

R1

TL

1kΩ

TL

2

3

L=15 mils

W=16 mils

P2-2

Board R2 (Ω) C14 (pF)C30 (pF) C1 (pF) L1 (nH)
CDMA (US)

Transmission
Line Length

CDMA (US)

330 5.1100 9.1 27

TL

1

175 mils

165 mils

TL

4

L=40-45 mils

from L3

W=16 mils

* L1 is a High Q inductor (i.e., Coilcraft0805HQ-series).
**C1 and C14 are High Q capacitors

(i.e., Johanson C-series).

TL

5

L=15-20 mils

W=14 mils

Rev A17 011011

Preliminary

RF2162

Evaluation Board Schematic - US TDMA

Er = 4.7
H = 14 mils
t=1mil

J1

RF IN

C5

100 pF

C18

100 pF

R2

L2

15 nH

C27

100 pF

C25
1 µF

C30

2

3

4

TL

5

L3

1.5 nH

TL

4

161 131415

R1

1kΩ

P1-1

C13

100 pF

100 pF

TL

6

C6

C2

4.7 uF

C28

10 nF

C4

100 pF

C55

3.6 pF

TL

7

L1*

12

TL

11

10

98765

1

L4

27 nH

2162401B

TL

C1**

C17

1pF

L10

1.5 nH

2

P1-1 VCC

P2-1 VREG

TL

3

P1

P2

C3

100 pF

C14**

1

GND

2

1

VMODEP2-2

2

2

POWER AMPLIFIERS

J4

RF OUT

R3

TL

P2-2

P2-1

2

0 Ω

Board R2 (Ω) C14 (pF)C30 (pF) C1 (pF) L1 (nH)
TDMA (US)

Transmission
Line Length

TDMA (US)

820 5.656 12 16

TL

1

90 mils

R4

0 Ω

TL

3

135 mils82 mils

* L1 is a High Q inductor (i.e., Coilcraft0805HQ-series).
**C1 and C14 are High Q capacitors (i.e., Johanson C-series).

TL

4

L=12 mils

W=16 mils

TL

5

L=49 mils

W=16 mils

TL

6

L=12 mils

TL

7

L=12 mils

W=14 mils

Rev A17 011011

2-211

2

RF2162

Preliminary

Evaluation Board Layout - CDMA

Board Size 2.0" x 2.0"

Board Thickness 0.031”, Board Material FR-4

POWER AMPLIFIERS

2-212

Rev A17 011011

Preliminary

RF2162

Evaluation Board Layout - TDMA

2

POWER AMPLIFIERS

Rev A17 011011

2-213

2

RF2162

POWER AMPLIFIERS

Preliminary

2-214

Rev A17 011011