Datasheet RF2153, RF2153PCBA Datasheet (RF Micro Devices)

RF2153

2

Typical Applications

• PACS Handsets and Base Stations

• 3V 1850-1910MHz CDMA PCS Handsets

• 3V 1750-1780MHz CDMA PCS Handsets

Product Description

The RF2153 is a high-power, high-efficiency linear ampli­fier IC targeting 3V handheld systems. The device is
manufactured on an advanced Gallium Arsenide Hetero­junction Bipolar Transistor (HBT) process, and has been
designed for use as the final RF amplifier in 3 V CDMA
and TDMA handheld digital equipment, spread-spectrum
systems, and other applications in the 1750MHz to
1910 MHz band. The device is packaged in a compact
4mmx4mm (LCC). The device’s frequency response can
be optimized for linear performance in the 1750MHz to
1910MHz band.

CDMA/TDMA/PACS

1900MHZ 3V P OWER AMPLIFIER

• 3V TDMA PCS Handsets

• Spread-Spectrum Systems

• Commercial and Consumer Systems

3.50

3.35

1.50

1.20

4.20

3.95

0.38

2.00

0.28

0.13

0.80

4.20

3.95

3.50

3.35

1

ALL SOLDER PAD TOLERANCES P0.05mm

0.40
sq.

1.50 sq.

2

POWER AMPLIFIERS

Optimum Technology Matching® Applied

Si BJT GaAs MESFETGaAs HBT
Si Bi-CMOS

GND2

VCC1

RFIN

!

SiGe HBT

VCC2

VCC2

16 1415

1

2

3

4

678

5

VPD1

GND1

VCC2

V MODE

VCC

VPD2

Si CMOS

2F0

13

12

RF OUT

11

RF OUT

10

RF OUT

9

BIAS GND

Functional Block Diagram

Package Style: MP16KO1A

Features

• Single 3V Supply

• 29dBm Linear Ou tput Power

• 30dB Linear Gain

• 33% Linear Efficiency CDMA

• 40% Linear Efficiency TDMA

• On-board Power Down Mode

Ordering Information

RF2153 CDMA/TDMA/PACS 1900MHz 3V Power Amplifier
RF2153 PCBA Fully Assembled Evaluation Board

RF Micro Devices, Inc.
7625 Thorndike Road
Greensboro, NC 27409, USA

Tel [phone]

Fax [phone]

http://www.rfmd.com

Rev A18 001114

2-167

2

RF2153

Absolute Maximum Ratings

Parameter Rating Unit

Supply Voltage (RF off) +8.0 V
Supply Voltage (P
Mode Voltage (V

≤31dBm) +4.5 V

OUT

)+3.5V

MODE

Control Voltage (VPD)+3.5V
Input RF Power +10 dBm

Operating Case Temperature -30 to +110 °C
Storage Temperature -30 to +150 °C

DC
DC
DC
DC

RF Micro Devices believes the furnished information is correct and accurate
at the time of this printi ng. However, RF Micro Devices reserves the right to
make changes to its products without notice. RF Micro Devices does not
assume responsibility for the use of the described product(s).

Caution! ESD sensitive device.

Specification

Unit Condition

Overall - CDMA

POWER AMPLIFIERS

Parameter

Min. Typ. Max.

Usable Frequency Range 1750 1910 MHz
Typi cal Frequency Range 1750-1780

1850-1910

MHz
MHz

Small Signal Gain 30 32 34 dB V

26 29 V

Linear Gain 26 29 dB V

Second Harmonic (including

-35 dBc

second harmonic trap)
Third Harmonic -40 dBc
Fourth Harmonic -45 dBc
Minimum Linear Output Power

29 dBm

(CDMA or TDMA Modulation)
Idle Current 90 100 200 mA V

CDMA Linear Efficiency 30 33 P
CDMA Adjacent Channel Power

-46 -44 dBc P

Rejection @ 1.25MHz
Minimum Linear Output Power

28 +29 dBm V

(CDMA Modulation)
Input VSWR < 2:1
Output Load VSWR 10:1 No Damage.
Turn On/Off Time 40 µs

Overall - TDMA

Idle Current 250 500 mA V
TDMA Linear Efficiency 30 40 % P
TDMA ACP @ 30kHz -29 -28 dBc P
TDMA ALT @ 60kHz -49 -48 dBc P

T=25°C, VCC=3.4V unless otherwise speci­fied

Output Matching Network Tune
Output Matching Network Tune

=Low 0V to 0.5V

MODE

=High 2.5V to 3.0V

MODE

=High 2.5V to 3V

MODE

P

=29dBm, VCC=3.4V, V

OUT

=>2.5V

MODE

=29dBm, VCC=3.4V, V

OUT

=29dBm, VCC=3.4V, V

OUT

=3.0V, V

CC

REG

=2.8V

REG

REG
REG

=2.8V

=2.8V
=2.8V

T=25°C, VCC=3.4V unless otherwise speci­fied

=0V to 0.5V

MODE

=30dBm, VCC=3.4V, V

OUT

=30dBm

OUT

=30dBm

OUT

REG

=2.8V

2-168

Rev A18 001114

RF2153

Parameter

Min. Typ. Max.

Specification

Unit Condition

Po wer Supply

Power Supply Voltage 3.0 3.4 4.5 V
V

Current 10 mA Total pins 6 and 8

PD

and V

V

PD

Total Current (Power down) 10 µAV

“Low” Voltage 0 0.2 V

V

PD

“High” Voltage 2.7 2.8 2.9 V

V

PD

MODE “High” Voltage 2.5 2.8 V R1=1kΩ
MODE “Low” Voltage 0 0.5 V R1 =1kΩ
Stability 3:1 Inband

Spurious <-60 dBc
Noise Power -136 dBm/Hz @ 80MHz offset

Current 11 13 mA Total pins 6, 7 and 8

MODE

= low

PD

20:1 Outband

2

POWER AMPLIFIERS

Rev A18 001114

2-169

2

POWER AMPLIFIERS

RF2153

Pin Function Description Interface Schematic

1 VCC2

2 GND2

3 VCC1

4RF IN

5 GND1

6 VPD1

7VMODE

8 VPD2

9 BIAS GND

10 RF OUT

11 RF OUT
12 RF OUT
13 2FO

14 VCC
15 VCC2

16 VCC2

Pkg

GND

Base

Power supply f or second stage and interstage match. Pins 1, 15 and 16
should be connected by a common trace where the pins contact the
printed circuit board.

Ground for second stage. Keep traces physically short and connect
immediately to ground plane for best performance. This ground should
be isolated from the backside ground contact on top metal layer.

Power supply for first stage and interstage match. VCC should be fed
through a 1.5nH inductor terminated with a 15pF capacitor on the sup-

ply side.
RF input. An external 15pF series capacitor is required as a DC block

and also provides for an input VSWR of <2:1 typical.

Ground for first stage. Keep traces physically short and connect imme­diately to ground plane for best performance. This ground should be
isolated from the backside ground contact on top metal layer.

Power Down control for first and second stages. When this pin is “low”,
all first and second stage circuits are shut off. When this pin is 2.8V, all
first stage circuits are operating normally. V

2.8V for the amplifier to operate properly over all specified temperature
and voltage ranges. A dropping resistor from a higher regulated voltage
may be used to provide the required 2.8V.

For full power operation, MODE is set low. VMODE will reduce the bias
current by up to 50% when set HIGH. Large Signal Gain is reduced
approximately 1.5dB at 29dBm P

approximately 6dB. An external series resistor is option al to limit the
amount of current required by the V

Power Down control for the third stage. When this pin is “low”, the third
stage circuit is shut off. When this pin is 2.8V, the third stage circuit is
operating normally. V

operate properly over all specified temperatu re and voltage ranges. A
dropping resistor from a higher regulated voltage may be used to pro­vide the required 2.8V. A 15pF high frequency bypass capacitor is rec­ommended.

Requires a 15nH inductor.
RF output and power supply for final stage. This is the unmatched col-

lector output of the third stage. A DC block is required following the
matching components. The biasing may be provided via a parallel L-C
set for resonance at the operating frequency of 1850MHz to 1910MHz.
It is important to select an inductor with very low DC resistance with a
1A current rating. Alternatively, shunt microstrip techniques are also
applicable and provide very low DC resistance. Low frequency bypass­ing is required for stability.

Same as pin 12. See pin 10.
Same as pin 12. See pin 10.
Second harmonic trap . Keep traces physically short and connect imme-

diately to ground plane. This ground should be isolated from backside
ground contact.

Supply for bias reference and control circuits. High frequency bypass­ing may be necessary.

Same as pin 1.
Same as pin 1.
Ground connection. The backside of the package should be soldered to

a top side ground pad which is connected to the ground plane with mul­tiple vias. The pad should have a short thermal path to the ground
plane.

requires a regulated 2.8V for the amplifier to

PD

and Small Signal Gain is reduced

OUT

MODE

requires a regulated

PD1

pin.

See pin 4.

RF IN

See pin 4.

From Bias
Network

RF OUT

From Bias
Network

VCC1

GND1

2-170

Rev A18 001114

Application Schemati c

US - CDMA

V

CC

2nd Interstage tuning for
centering frequency response

RF2153

Bypassing for V

CC

1st Interstage tuning to
match input return loss

To match input return loss

and vary gain

VMODE

10 nF

8 pF

15 pF

RF IN

VREG

Tied together for optimum linearity

1.5 nH

150

10 nF

10 pF

TL

3

16 1415

1

2

Ω

3

4

15 pF

13

12

11

10

TL

1

L4

15 nH

678

5

47

15 pF

Ω

1 k

Ω

27

15 pF

9

Ω

* High Q inductor (i.e., Coilcraft 0805HQ-series).
**High Q capacitors (i.e., Johanson C-series).

10 nF

15 pF

12 nH*

TL

1 pF

15 pF

2

4.7 pF** 2.2**

Ground for 2nd
Harmonic Trap

RF OUT

Matching Network for
optimum load impedance

Bypassing for

and V

V

REG1

REG2

2

POWER AMPLIFIERS

Rev A18 001114

Transmission

Line Length

CDMA (US)

TL

1

TL

2

TL

3

20 mils 100 mils 20 mils

2-171

RF2153

Application Schematic

Korea - CDMA

V

C

2nd Interstage tuning for

C

centering frequency response

Bypassing for V

CC

2

POWER AMPLIFIERS

1st Interstage tuning to

ma tc h inp u t re tu rn los s

To match input return loss

and vary gain

VMOD E

10 nF

9 pF

15 pF

RF IN

VREG

Tied together for optimum linearity

1.8 nH

180

10 nF

10 pF

TL

3

16 1415

1

2

Ω

3

4

15 pF

13

12

11

10

TL

1

15 nH

678

5

Ω

47

15 pF

Ω

1 k

Ω

27

15 pF

9

10 nF

15 pF

Ground for 2nd
Harm onic Trap

12 nH*

TL

5.6 pF** 2.2 pF**

* High Q inductor (i.e., Coilcraft 0805HQ-series).
**High Q capacitors (i.e., Johanson C-series).

2

1.0 pF + .25 pF

15 pF

Ma tc h ing Netw o rk for
optimum load impedance

Bias re turn

Bypassing for
V

REG1

RF OUT

and V

REG2

2-172

Transm ission

Line Length

CDM A (Korea)

TL

1

TL

2

TL

3

30 mils 100 m ils 3 0 mils

Rev A18 001114

Application Schemati c

US - TDMA

RF2153

1st Interstage tuning to
match input return loss

To match input return loss

and vary gain

RF IN

10 nF

15 pF

15 pF

1 nH

100

1 pF

Bypassing for V

Ground for 2nd
Harmonic Trap

CC

2

10 nF

10 pF

1

V

2nd Interstage tuning for

CC

centering frequency response

TL

3

16 1415

15 pF

13

10 nF

15 pF

12 nH*

POWER AMPLIFIERS

2

Ω

3

4

678

5

0

Ω

15 pF

12

11

10

0

Ω

15 pF

TL

1

TL

4.7 pF** 1.8 pF**

15 nH

9

15 pF

2

RF OUT

Matching Network for
optimum load impedance

Bias return

Bypassing for

and V

V

REG1

REG2

VREG

VMODE

Tied together for optimum linearity

Ω

4.7 k

Transmission

Line Length

TDMA (US)

* High Q inductor (i.e., Coilcraft 0805HQ-series).
**High Q capacitors (i.e., Johanson C-series).

TL

1

TL

2

TL

20 mils 160 mils 10 mils

3

Rev A18 001114

2-173

RF2153

Evaluation Board Schema t ic

US - CDMA

2

POWER AMPLIFIERS

J1

RF IN

P2-1

P2-2

50 Ω µstrip

C7

1 uF

C12

10 nF

C11
8 pF

L3

1.5 nH

C5

15 pF

Tied together for optimum linearity

R2

P1-1

C8

10 nF

C30

16 1415

1

2

3

4

678

5

R3

Ω

39

C27

15 pF

C10
1 uF

R1

1 k

TL

TL

C2

4.7 uF
+

C26

10 nF

4

3

Ω

C6

15 pF

13

12

11

10

R4

Ω

0

C13

15 pF

TL

1

L4

15 nH

9

2153400 Rev. A

* L1 is a High Q inductor (i.e., Coilcraft 0805HQ-series).
**C1 and C15 are High Q capacitors (i.e., Johanson C-series).

C4

15 pF

L1*

TL

C1** C15**

C14
1 pF

15 pF

2

P1-1 VCC

P2-1 VREG

C3

P1

P2

J2

RF OUT

1

GND

2

1

VMODEP2-2

2

Board R2 (Ω) C15 (pF)C30 (pF) C1 (pF) L1 (nH)
CDMA (US)

Transmission

Line Length

CDMA (US)

150 2.210 4.7 12

TL

1

20 mils

TL

2

100 mils

2-174

TL

3

20 mils

TL

100 mils

2.7 nH

or >

inductor

4

Rev A18 001114

Evaluation Board Schemati c

Korea - CDMA

RF2153

J1

RF IN

P2-1

P2-2

50 Ω µstrip

C7

1 uF

C12

10 nF

C11

9 pF

L3

1.5 nH

C5

15 pF

Tied together for optimum linearity

R2

P1-1

C8

10 nF

C30

16 1415

1

2

3

4

678

5

R3

Ω

39

C27

15 pF

C10

1 uF

R1

1 k

TL

TL

C2

4.7 uF
+

C26

10 nF

4

3

Ω

C6

15 pF

R4

Ω

0

C13

15 pF

13

12

TL

11

10

9

1

L4

15 nH

2153401 Rev.-

* L1 is a High Q inductor (i.e., Coilcraft 0805HQ-series).
**C1 and C15 are High Q capacitors (i.e., Johanson C-series).

C4

15 pF

L1*

TL

C1** C15**

C14

1.5 pF
C3

15 pF

2

P1-1 VCC

P2-1 VREG

P1

P2

J2

RF OUT

1

GND

2

1

VMODEP2-2

2

2

POWER AMPLIFIERS

Rev A18 001114

Board R2 (Ω) C15 (pF)C30 (pF) C1 (pF) L1 (nH)
CDMA (Korea)

Transmission

Line Length

CDMA (Korea)

180 2.211 5.6 12

TL

1

30 mils

TL

2

100 mils

TL

30 mils

3

100 mils

or >

inductor

TL

4

2.7 nH

2-175

RF2153

Evaluation Board Schema t ic

US - TDMA

2

POWER AMPLIFIERS

J1

RF IN

P2-1

P2-2

50 Ω µstrip

C7

1 uF

C12

10 nF

C11

15 pF

L3

1 nH

C5

15 pF

Tied together for optimum linearity

R2

P1-1

C8

10 nF

C30

16 1415

1

2

3

4

678

5

R3

Ω

0

C27

15 pF

R1

4.7 k

TL

C2

4.7 uF
+

C26

10 nF

C6

15 pF

3

13

12

TL

11

10

9

R4

Ω

0

C13

15 pF

Ω

* L1 is a High Q inductor (i.e., Coilcraft 0805HQ-series).
**C1 and C15 are High Q capacitors (i.e., Johanson C-series).

1

L4

15 nH

2153402A

C4

15 pF

L1*

TL

C1** C15**

P1-1 VCC

P2-1 VREG

C14
1 pF

C3

15 pF

2

P1

1
2

P2

1
2

J2

RF OUT

GND

VMODEP2-2

Board R2 (Ω) C15 (pF)C30 (pF) C1 (pF) L1 (nH)
TDMA (US)

100 1.810 4.7 12

2-176

Transmission

Line Length

TDMA (US)

TL

1

20 mils

TL

2

160 mils

TL

3

10 mils

Rev A18 001114

Evaluation Board Layout

US - CDMA

Board Size 2.0" x 2.0"

Board Thickness 0.031”, Board Material FR-4

RF2153

2

POWER AMPLIFIERS

Evaluation Board Layout

Korea - CDMA

Rev A18 001114

2-177

2

RF2153

Evaluation Board Layout

US - TDMA

POWER AMPLIFIERS

2-178

Rev A18 001114