Page 1
RF2140
2
Typical Applications
• 3V DCS1800 (PCN) Cellular Handsets
• 3V DCS1900 (PCS) Cellular Handsets
• 3V Dual-Band/Triple-Band Handsets
Product Description
The RF2140 is a high power, high efficiency power amplifier module offering high performance in GSM or GPRS
applications.The device is manufactured on an advanced
GaAs HBT process, and has been designed for use as
the final RF amplifier in DCS1800/1900 hand held-digital
cellular equipment and other applications in the
1700 MHz to 2000MHz band. On-board power control
provides over 65dB of control range with an analog voltage input, and provides power down with a logic “low” for
standby operation. The device is self-contained with 50Ω
input and the output can be easily matched to obtain optimum power and efficiency characteristics.The RF2140
can be used together with the RF2138 for dual-band
operation. The device is packaged in an ultra-small
ceramic package, minimizing the required board space.
Optimum Technology Matching® Applied
Si BJT GaAs MESFETGaAs HBT
Si Bi-CMOS
ü
SiGe HBT
Si CMOS
3V DCS POWER AMPLIFIER
• Commercial and Consumer Systems
• Portable Battery-Powered Equipment
•GPRSCompatible
3.50
3.35
sq.
1
ALL SOLDER PAD TOLERANCES P0.05mm
4.20
3.95
1.50
1.20
sq.
0.38
0.28
0.13
2.00
0.80
RF2174
t
Package Style: MP16K01A
duc
Features
o
0.40
sq.
1.50
sq.
2
POWER AMPLIFIERS
AT_EN
RF IN
GND1
S
Functional Block Diagram
Rev A12 011031
GND2
VCC2
16 1415
1
2
3
4
678
5
e
e
APC1
VCC1
VCC2
graded Pr
Up
APC2
• Single 2.7V to 4.8V Supply Voltage
• +33dBm Output Power at 3.5V
VCC2
2F0
13
•27dBGainwithAnalogGainControl
• 51% Efficiency
12
RF OUT
• 1700MHz to 1950MHz Operation
11
RF OUT
10
RF OUT
9
NC
VCC
• Supports DCS1800 and PCS1900
Ordering Information
RF2140 3V DCS Power Amplifier
RF2140 PCBA Fully Assembled Evaluation Board
RF Micro Devices, Inc.
7628 Thorndike Road
Greensboro,NC 27409, USA
Tel (336) 664 1233
Fax (336) 664 0454
http://www.rfmd.com
2-129
Page 2
2
RF2140
Absolute Maximum Ratings
Parameter Rating Unit
Supply Voltage -0.5 to +6.0 V
Power Control Voltage (V
Enable Voltage (V
DC Supply Current 1500 mA
Input RF Power +13 dBm
Duty Cycle at Max Power 50 %
Output Load VSWR 10:1
Operating Case Temperature -40 to +85 °C
Storage Temperature -55 to +150 °C
AT_EN
) -0.5 to +3.0 V
APC
) -0.5 to +3.0 V
DC
Caution! ESD sensitive device.
RF Micro Devices believesthe furnishedinformation is correctand accurate
at the time of this printing. However, RF Micro Devices reserves the right to
make changes to its products without notice.RF Micro Devices does not
assume responsibility for the use of the described product(s).
Specification
1850 to 1910 MHz A different tuning is required.
+31.5 dBm Temp=+85 °C, V
+31 dBm Temp=25°C,VCC=2.7V,V
51 % At P
15 % P
10 % P
+5 +7 +9 dBm
od
Unit Condition
ct
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P
ed
-40 -35 dBm V
rad
-36 dBm
3:1 P
Temp= 25 °C, VCC=3.5V,V
V
=2.6V,PIN=+6dBm, Freq=1710MHz
AT_EN
to 1910MHz, 25% Duty Cycle, pulse
width=1154µs
4
17
=3.5V,V
CC
=3.2V,V
CC
=3.2V,V
CC
RF2
=2.7V,V
CC
,VCC=3.5V
OUT,MAX
,VCC=3.0V
OUT,MAX
=+20dBm
OUT
=+10dBm
OUT
1930MHz to 1990MHz,
P
OUT,MIN<POUT<POUT,MAX
P
IN,MIN<PIN<PIN,MAX
=0.2V,PIN=+10dBm
APC1,2
=0.2V,PIN=+6dBm
APC1,2
OUT,MAX
OUT<POUT,MAX
RBW=100kHz
-5dB<P
OUT<POUT,MAX
-5dB
APC1,2
APC1,2
APC1,2
APC1,2
,VCC=3.0V to 5.0V
Range
ous
Parameter
ee
Min. Typ. Max.
+31.5 +32.8 dBm Temp=+25°C, V
+29.5 +30 dBm Temp=+85 °C, V
Upg
POWER AMPLIFIERS
Overall
Operating Frequency Range 1710 to 1785 MHz See application schematic for tuning details.
Usable Frequency Range 1700 to 2000 MHz
Maximum Output Power +32 +33 dBm Temp=25°C, V
Total Efficiency 45 51 % At P
Recommended Input Power
Output No ise Power -79 dBm RBW=100kHz, 1805MHz to 1880MHz and
Forward Isolation -37 -30 dBm V
Second Harmonic -60 -45 dBc
Third Harmonic -65 -50 dB c
Fourth Harmonic -50 -45 dBc
Fifth Harmonic -50 -45 dB c
Sixth Harmonic -50 -45 dBc
All Other Non-Harmonic Spuri-
Input Impedance 50 Ω
Input VSWR 2.2:1 P
S
Output Load VSWR 10:1 Spurious<-36dBm, V
Output Load Impedance 4.5-j3.9 Ω Load Impedance presented at RF OUT pin
=2.6V,
=2.6V
=2.6V
APC1,2
=2.6V
APC1,2
=2.6V
=2.6V
APC1,2
,
=0.2V to 2.6V,
2-130
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Page 3
RF2140
Parameter
Power Control
Power Control “ON” 2.6 V Maximum P
Power Control “OFF” 0.2 0.5 V Minimum P
Attenuator Enable “ON” 2.5 2.6 2.85 V For maximum isolation when V
Attenuator Enable “OFF” 0.2 0.5 V For power down mode
Power Control Range 62 68 dB V
Gain Control Slope 100 dB/V P
APC Input Capacitance 10 pF DC to 2MHz
APC Input Current 4.5 5 mA V
AT_EN Input Current 500 µAV
Turn On/Off Time 100 ns
Power Supply
Power Supply Voltage 3.5 V Specifications
Power Supply Current 1.3 A DC Current at P
Min. Typ. Max.
Specification
10 µAV
10 µAV
2.7 4.8 V Nominal operating limits, P
5.5 V With maximum output load VSWR 6:1,
55 295 mA Idle Current, PIN<-30dBm
110µAP
110µAP
Unit Condition
, Voltage supplied to the
input
APC1,2
P
=+10dBm
IN
OUT
APC1,2
APC1,2
AT_EN
AT_EN
OUT
, Voltage supplied to the input
OUT
=0.2V to 2.6V, V
=-10dBm to +33dBm
=2.6V
=0V
=2.6V,V
=0V, V
APC1,2
APC1,2
=0V
=0V
AT_EN
4
<+33dBm
P
OUT
17
<-30dBm, V
IN
<-30dBm, V
RF2
IN
OUT,MAX
=0.2V
APC1,2
=0.2V,Temp=+85°C
APC1,2
OUT
is low
APC
=2.6V,
<+33dBm
2
POWER AMPLIFIERS
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2
RF2140
Pin Function Description Interface Schematic
1 GND2
2AT_EN
3RFIN
POWER AMPLIFIERS
4 GND1
5 VCC1
6APC1
7APC2
8VCC
9NC
10 RF OUT
11 RF OUT
12 RF OUT
13 2F0
14 VCC2
ee
S
Ground connection for the driver stage. Keep t races physically short
and connect immediately to the ground planefor bestperformance. Itis
important for stability that this pin has it’s own vias to the groundplane,
to minimize any common inductance. This pin is internally connected to
the ground slug.
Control input for the PIN diode. The purpose of the PIN diode is to
attenuate the RF input drive level when the V
both to reduce the leakage through the device cause by self biasing
when driving with high level at the RF input, as well as to maintain a
good input match when the bias of the input sta g e is turned off. When
this pin is “high” the PIN diode control is turned on. See the Theory of
Operation for more details.
RF Input. This is a 50Ω input, but the actual impedance depends on the
interstage m a tching network c onnected to pin 5. An external DC blocking capacitor is requiredif this port is connecte d toa DCp ath to ground
or a DC voltage.
Ground connection for the pre-amplifier stage. Keep traces physically
short and connect immediately to the ground plane for best performance. It is important for stability that this pin has it’s own vias to the
groundplane, to minimize any common inductance.
Power supply for the pre-amplifier stage and interstage matching. This
pin forms the shunt inductance needed for proper tuning of the interstage match. Please refer to the application schematic for proper configuration, and note that position and value of the components are
important.
Power Control for the driver stage and pre-amplifier. When this pin is
"low," all circuits are shut off. A "low" is typically 0.5V or less at room
temperature. A shunt bypasscapacitor is required. During normal operation this pin is the power control.Controlrange varies from about 1.0V
for -10dBm to 2.6V for +33dBm RF output power. The maximum power
that can be achieved depends on the actual output matching; see the
application information for more details. The maximum current into this
pin is 5mA when V
=2.6V,and 0mA when V
APC1
Power Control for the output stage. See pin 6 for more details. See pin 6.
Power supply for the bias circuits. See pin 6.
Not connected. Connect this pin to the ground plane for compatibility
with future packages.
RF Output and power sup p ly for the output stage. Bias voltage for the
final stage is provided through this wide output pin. An external matching networ k is required to provide the optimum load impedance.
Upg
Same as pin 10. Same as pin 10.
Same as pin 10. Same as pin 10.
Connection for the second harmonic trap. This pin is internally con-
nected to the RF OUT pins. The bonding wire together with an external
capacitor form a series resonator that should be tuned to the second
harmonic frequencyin orderto increaseefficiency and reduce spurious
outputs.
Same as pin 15.
rad
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P
is low. This serves
APC
ct
u
=0V.
APC
RF2
See pin 15.
RF IN
See pin 3.
4
17
See pin 3.
Same as pin 10.
AT_EN
From Attn
control circuit
VCC
APC
GND
GND
From Bias
Stages
To PIN
diode
2k
Ω
GND1
VCC1
PIN
GND 1
From Bias
Stages
RF OUT
GND
PCKG BASE
To RF
Stages
2-132
Rev A12 011031
Page 5
RF2140
Pin Function Description Interface Schematic
From Bias
Stages
VCC2
GND2
15 VCC2
16 VCC2
Pkg
Base
GND
Power supply for the driver stage and interstage matching. This pin
forms the shunt inductance needed for proper tuning of the interstage
match. Please refer to the application schematic for proper configuration, and note that position and value of the components are importan t.
Same as pin 15. Same as pin 15.
Ground connection for the output stage. This pad should be connected
to the groundplane by vias directly under the device. A short path is
required to obtain optimum performance, as well as to provide a good
thermal path to the PCB for maximum heat dissipation.
4
2
POWER AMPLIFIERS
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RF2
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Page 6
2
RF2140
Theory of Operation and Application Information
TheRF2140isathree-stagedevicewith28dBgainat
full power. Therefore, the drive required to fully saturate the output is +5dBm. Based upon HBT (Heterojunction Bipolar Transistor) technology, the part
requires only a single positive 3 V s upply to operate to
full specification. Power control is provided through a
single pin interface, with a separate Power Down control pin. The final stage ground is achieved through the
large pad in the middle of the backside of the package.
First and second stage grounds are brought out
through separate ground pins for isolation from the output. These grounds should be connected directly with
vias to the PCB ground plane, and not connected with
POWER AMPLIFIERS
the output ground to form a s o called “local ground
plane” on the top layer of the PCB. The output is
brought out through the wide output pad, and forms the
RF output signal path.
The amplifier operates in near Class C bias mode. The
final stage is "deepAB", meaning the quiescent current
is very low. As the RFdrive is increased, the finalstage
self-biases, causing the bias point to shift up and, at
full power, draws about 1500mA. The optimum load for
the output stageis approximately 4.5Ω. This is the load
at the output collector, and is created by the series
inductance form ed by the output bond wires, vias, and
microstrip, and 2 shunt capacitors external to the part.
The optimum load impedance at the RF Output pad is
4.5 -j3.9Ω. With this match, a 50Ω terminal impedance
is achieved. The input is internally matched to 50Ω
with just a blocking c apacitor needed. This data sheet
defines the configuration for GSM operation.
The input is DC coupled; thus, a blocking cap must be
inserted in series. Also, the first stage bias may be
adjusted by a resistive divider with high value resistors
onthispintoV
however, no external adjustment is necessary as internal resistors set the bias point optimally.
When the device is dr iven at maximum input power self
biasing would occur. This results in less isolation than
one would expect, and the maximum output power
would be about -15dBm. If the drive power to the PA is
turned on before the GSM ramp-up, higher isolation is
required. In order to meet the GSM system specs
under those conditions, a PIN diode attenuator connected to the input can be turned on. The figure below
shows how the attenuator and its controls are connected.
and ground. For nominal operation,
PC
rad
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ed
P
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VCC
RF IN
750 Ω 500 Ω
5kΩ
APC
2kΩ
AT_EN
PIN
From Bias
Stages
4
The current through the PIN diode is controlled by two
signals: AT_EN and APC. The AT_EN signal allows
current through the PIN diode and is an on/off function.
The APC signal controls the amount of current through
the PIN diode. Normally, the AT_EN signal will be
derived from the VCO ENABLE signal available in
most GSM handset designs. If maximum isolation is
needed before the ramp-up, the AT_EN signal needs to
u
be turned on before the RF power is applied to the
device input. The current into this pin is not critical, and
can be reduced to a few hundred micro amps with an
external series resistor.Without the resistor, the pin will
draw about 700µA.
Because of the inverting stage at the APC input, the
current through the PIN diode is inverted from the APC
voltage. Thus, when V
power, the attenuator is turned off to obtain maximum
drive level for the first RF stage. When V
maximum isolation, the attenuator is be turned on to
reduce the drive level and to avoid self-biasing.
The PIN diodeis dimensioned such that a lowV
impedance of the diode is about 50 Ohm. Since the
input impedance of the first RF stage become very
high when the biasis turned off,this topologywill maintain a good input impedance over the entire V
trol range.
VCC1 and VCC2 provide supply voltage to thefirst and
second stage, as well as provides some frequency
selectivity to tune to the operating band. Essentially,
RF2
ct
17
APC
is high for maximum output
is low for
APC
APC
con-
APC
the
2-134
Rev A12 011031
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RF2140
the bias is fed to this pin through a short microstrip. A
bypass capacitor sets the inductance seen by the part,
so placement of the bypass cap can affect the frequency of the gain peak. This supply should be
bypassed individually with 100pF capacitors before
being combined with V
vent feedback and oscillations.
The RF OUT pin provides the output power. Bias for
the final stage is fed to this output line, and the feed
must be capable of supporting the approximately 1.5A
of current required. Care should be taken to keep the
losses low in the bias feed and output components. A
narrow microstrip line is recommended because DC
losses in a bias choke will degrade efficiency and
power.
While the part is safe under CW operation, maximum
power and reliability will be achievedunder pulsed conditions. The data shown in this data sheet is based on
a 12.5% duty cycle and a 600µs pulse, unless specified otherwise.
The part will operate over a 3.0V to 5.0V range. Under
nominal conditions, the power at 3.5V will be greater
than +32dBm at +85°C. As the voltage is increased,
however, the outputpowerwill increase. Thus, in a system design, the ALC (Automatic Level Control) Loop
will back down the power to the desired level. This
must occur during operation, or the device may be
damaged from too much power dissipation. At 5.0V,
over +36dBm may be produced; however, this level of
power is not recommended, and can cause damage to
the device.
The HBT breakdown voltage is >20V, so there is no
issue with overvoltage. However, under worst-case
conditions, with the RF drive at full power during transmit, and the output VSWR extremely high, a low load
impedance at the collector of the output transistors can
cause currents much higher than normal. Due to the
bipolar nature of the devices, there is no limitation on
the amount of current the device will sink, and the safe
current densities could be exceeded.
High current conditions are potentially dangerous to
any RF device. High currents leadto high channeltemperatures and may force early failures. The RF2140
includes temperature compensation circuits in the bias
network to stabilize the RF transistors, thus limiting the
current through the amplifier and protecting the
devices from damage. The same mechanism works to
compensate the currents due to ambient temperature
variations.
ee
S
for the output stage to pre-
CC
rad
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P
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To avoid excessively high currents it is impor tant to
control the V
higher than 4.0V,such that the maximum output power
is not exceeded.
when operating at supply voltages
APC
4
17
RF2
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POWER AMPLIFIERS
Rev A12 011031
2-135
Page 8
2
RF2140
Application Schematic
Instead of a
V
CC
1nF
GND2
VCC2
VCC2
16 1415
1
15 pF
AT_EN
2
RF IN
3
GND1
4
AT_EN
RF IN
POWER AMPLIFIERS
stripline an inductor
of ~6 nH can be
used
15pF
Veryclosetopin15/16
2F0
13
12
11
10
1.0 pF
RF OUT
VCC2
V
CC
15 pF
Quarter wave
length
50 Ωµstrip
5.1 pF
Note 1
Instead of a
strip linean
inductor can be
used
15 pF
RF OUT
1.0 pF
Note 1
RF IN
VCC
APC1
Distance center to
center of
capacitorsis
0.220"
RF2
ct
4
17
Distance between
edge of device
and capacitoris
0.240" to improve
the"off"isola tio n
3.9 Ω
V
CC
VCC1
5
APC1
15
pF
15
pF
678
VCC
APC2
15
pF
APC
9
NC
V
CC
15
pF
Distance between
edge of device
and capacitor is
0.080"
Note: All capacitors arestandard
0402 multi layer chip
Note 1: Usinga hi-Q capacitor
will increase efficiency slightly
Internal Schematic
u
VCC1
VCC2 RF OUT
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APC1
VCC
APC2
VCC
ed
500
750
Ω
5k
Ω
AT_EN
500
Ω
320
2.5k
Ω
Ω
rad
2k
Ω
Ω
2.5k
Ω
200
Ω
1.5k
Ω
2-136
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Upg
1.5k
Ω
GND1 GND2
PKG BASE
Rev A12 011031
Page 9
Evaluation Board Schemati c
(Download Bill of Materials from www.rfmd.com.)
RF2140
C20
3.3
J1
RF IN
µ
C22
1nF
C1
33 pF
C12
1nF
Capacitors are 0402.
*Murata GRM36COG series
** Johanson 500R07F series
All others are Panasonic ECU series
F
P1-3
P1-1 P1-3
C6
1nF
C21
1nF
R3
0
C11
33 pF
Ω
R1
3.9
GND2
1
AT_EN
2
RF IN
3
GND1
4
Ω
5
VCC1
C13
33 pF
C16
1nF
C19
µ
F
3.3
VCC2
VCC2
16 1415
678
APC1
APC1
VCC2
VCC
VCC
APC2
APC2
C14
33 pF
J3
V
APC
Schematic 2140400 Rev A
Board 2140410 Rev A
C5 *
12pF
C10 *
0.9 pF
2F0
13
12
RF OUT
11
package
edge to
10
inside C3
.050"
9
NC
NC
C15
33 pF
C17
1nF
C18
3.3
ct
u
50Ωµstrip
.150"
C3**
P1
1
ENABL
2
17
3
C9
33 pF
4
GND
VCC
C25
Quarter wave
length
C23** C24**
P1-1
µ
F
P1-3
RF2
P1-3
C8
1nF
3.3
C2
33 pF
C4**
C7
µ
F
J2
RF OUT
2
POWER AMPLIFIERS
Band
DCS
PCS
C3 (pF) C4 (pF) C23 (pF)
5.1 N/I1.8 N/I N/I
3.9 0.51.2 0.5 0.6
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Rev A12 011031
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C24 (pF) C25 (pF)
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2
RF2140
Evaluation Board Layout
Board size 2.0” x 2.0”
Board Thickness 0.014”; Board Material FR-4; Multi-Layer
POWER AMPLIFIERS
4
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Page 11
RF Generator
RF2140
Typical Test Setup
Power Supply
V- S- S+ V+
2
POWER AMPLIFIERS
Spectrum
Analyzer
4
10dB/5W3dB
17
Buffer
x1 OpAmp
Puls
Generator
RF2
ct
u
A buffer amplifier is recommended because the current into
the Vapc changes with voltage. As an alternative, the
voltage may be monitored with an oscilloscope.
Notes about testing the RF2140
The test setup shown above includes two attenuators. The 3dB pad at the input is to minimize the effects that the
switching of the input impedance of the PA has on the signal generator. When Vapc is switched quickly, the resulting
input impedance change can cause the signal generator to vary its output signal, either in output level or in frequency.
Instead of an attenuator an isolator may also be used. The attenuator at the output is to prevent damage to the spectrum analyzer, and should be able to handle the power.
ed
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P
rad
It is important not to exceed the rated supply currentand output power. When testing the device at higher than nominal
supply voltage, the V
the output it is important to monitor the forward power through a directional coupler. The forward power should not
exceed +36dBm, and V
this respect. To avoid damage, it is recommended to set the power supply to limiting the current during the burst, not to
exceed the maximum current rating.
ee
should be adjusted to avoid the output power exceeding +36dBm. During load-pull testing at
APC
Upg
needs to be adjusted accordingly. This simulates the behavior for the power control loop in
APC
S
Rev A12 011031
2-139
Page 12
2
RF2140
POWER AMPLIFIERS
4
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RF2
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Rev A12 011031
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