Page 1
RF2131
2
Typical Applications
• AMPS/ETACS Cellular Handsets
• CDPD Portable Data Cards
• 900MHz ISM Band Equipment
Product Description
The RF2131 is a high-power, high-efficiency amplifier IC.
The device is manufactured on an advanced Gallium Arsenide Heterojunction Bipolar Transistor (HBT) process,
and has been designed for use as the finalRF amplifier in
AMPS and ETACS handheld equipment, spread spectrum systems, CDPD, and other applications in the
800 MHz to 950MHz band. O n-board power control provides over 30dB of control range with an analog voltage
input, and provides power down with a logic "low" for
standby operation. Although it is intended for class C
operation, linear class AB operation can be achieved by
raising the bias level. The device is self-contained with
50 Ω input and the output can be easily matched to obtain
optimum power and efficiency characteristics.
HIGH EFFICIENCY AMPS/ETACS AMPLIFIER
• Commercial and Consumer Systems
• Portable Battery-Powered Equipment
-A-
0.009
0.004
0.050
8° MAX
0° MIN
0.392
0.386
0.158
0.150
0.244
0.230
0.035
0.016
0.010
0.008
0.021
0.014
0.069
0.064
0.060
0.054
2
POWER AMPLIFIERS
Optimum Technology Matching® Applied
Si BJT GaAs MESFETGaAs HBT
Si Bi-CMOS
PC
NC
VCC2
GND
GND
GND1
RF IN
VCC1
ü
SiGe HBT
1
2
3
4
5
6
7
8
BIAS
Si CMOS
16
NC
15
RF OUT
14
RF OUT
13
GND
12
GND
11
RF OUT
10
RF OUT
9
NC
Functional Block Diagram
Package Style: Standard Batwing
Features
• Single 4.0V to 7.0V Supply
• 1.2W Output Power
• 25dB Gain With Analog Gain Control
• 64% Efficiency
• Digitally Controlled Power Down Mode
• 800MHz to 950MHz Operation
Ordering Information
RF2131 High Efficiency A MPS/ETACSAmplifier
RF2131 PCBA Fully Assembled Evaluation Board
RF Micro Devices, Inc.
7628 Thorndike Road
Greensboro,NC 27409, USA
Tel (336) 664 1233
Fax (336) 664 0454
http://www.rfmd.com
Rev B4 010417
2-99
Page 2
2
RF2131
Absolute Maximum Ratings
Parameter Rating Unit
Supply Voltage -0.5 to +8.5 V
Power Control Voltage (VPC) -0.5 to +4.5 V
DC Supply Current 570 mA
Input RF Power +12 dBm
Output Load VSWR 10:1
Operating Case Temperature -40 to +100 °C
Ambient Operating Temperature -40 to +85 °C
Storage Temperature -40 to +150 °C
DC
Caution! ESD sensitive device.
RF Micro Devices believesthe furnishedinformation is correctand accurate
at the time of this printing. However, RF Micro Devices reserves the right to
make changes to its products without notice.RF Micro Devices does not
assume responsibility for the use of the described product(s).
Parameter
POWER AMPLIFIERS
Overall
Operating Frequency Range 824 to 849 MHz As configured in Application schematics
Usable Frequency Ran ge 800 to 950 MHz
Maximum CW Output Power +30.5 +31 dBm Depends on output matching
Total CW Efficiency 55 64 % At Max Output
DC Current at 1.2W Output 400 mA As configured in Application Circuit #1
Input Power for 1.2W output +6 +8 dBm
Noise Power Output -90 -85 dBm/30kHz In 869 - 894 MHz band (any gain or input
OFF Isolation 20 25 dB V
Second Harmonic -30 -25 dB c Depends upon external matching. Second
Input VSWR <2:1
Input Impedance 50 Ω
Specification
Min. Typ. Max.
Unit Condition
T=25°C, VCC=4.8V,VPCset for
P
=+31dBm, Freq=836MHz
OUT
power setting)
=0V,Input Power=+6dBm
PC
harmonic levelsdirectly from the IC are
approximately 20 to 25dBc
Power Down Control
Turn On/Off Time 100 ns
V
“OFF” Voltage 0.2 0.5 V
PC
“ON” V oltage 3.6 4.0 V
V
PC
Power Supply
Voltage 4.8 V Specifications
Voltage 4.0 7.0 V Operating Limits
2-100
Rev B4 010417
Page 3
RF2131
Pin Function Description Interface Schematic
1PC
Power Control. When this pin is "low", all circuits are shut off. A "low" is
typically 0.5V or less at room temperature. During normal operation
this pin is the power control. Control range varies from about 2V for
0dBm to 3.6V for +31dBm RF output power. The maximum power that
can be achieved depends on the actual output matching; see the application information for more details.
VCC1
PC
80
To Bias
Stages
Ω
2
2NC
3VCC2
4GND
5GND
6GND1
7RFIN
8VCC1
9NC
10 RF OUT
11 RF OUT
12 GND
13 GND
14 RF OUT
15 RF OUT
16 NC
Not connected.
Power supply for the driver stage and interstage matching. A shunt
capacitor is required for tuning the interstage to the proper frequency.
The value of this capacitor depends on the operating frequency and
power level. See the application information for details.
Ground connection. Keep traces physically short and connect immediately to the ground plane for best performance.
Same as pin 4.
Ground connection for the driver stage. Keep traces physically short
and connect immediately to the ground plane forbest performance. It is
recommended to use separate vias to the ground plane for this return
path.
RF Input. This is a 50Ω input, but the actual impedance depends on the
interstage matching network connected to pin 3. An external DC blocking capacitor is requiredif this port is connected to a DC path to ground
or a DC voltage.
Power supply for the bias circuits. An external RF bypass capacitor is
required. Keep the traces to the capacitor as short as possible, and
connect the capacitor immediately to the ground plane.
This pin is not connected internally; howeverit needs to be connected
to ground externally. This will improve performance by reducing coupling between pins.
RF Output and power supply for the output stage. The four output pins
are combined, and bias voltage for the final stage is provided through
these pins. The external path must be kept symmetric until combined to
ensure stability.An external matching networkis required toprovide the
optimum load impedance; see the application schematics for details.
Same as pin 10. See pin 10 schematic.
Ground connection for the output stage. Keep traces physically short
and connect immediately to the ground plane for be st performance.
Ground connection for the output stage. Keep traces physically short
and connect immediately to the ground plane for be st performance.
Same as pin 10. See pin 10 schematic.
Same as pin 10. See pin 10 schematic.
This pin is not connected internally, however it needs to be c onnected
to ground externally. This will improve performance by reducing coupling between pins.
Seepin1schematic.
Seepin3schematic.
Seepin1schematic.
RF IN
From Bias
Stages
From Bias
Stages
VCC2
RF OUT
POWER AMPLIFIERS
Rev B4 010417
2-101
Page 4
RF2131
Theory of Operation and Application Information
2
TheRF2131isatwo-stagedevicewith25dBgainat
full power. Therefore, for +31dBm output power, the
drive required to fully saturate the output is +6dBm.
Based upon HBT (Heterojunction Bipolar Transistor)
technology, the part requires only a single positive
4.8 V supply to operate to full specification. Bias control
is provided through a single pin interface, and the final
stage ground is achieved through the large pins on
both sides of the package. First stage ground is
brought out through a separate ground pin for isolation
from the output. These grounds should be connected
directly with vias to the PCB ground plane. The output
is brought out through the 4 output pins, and combined
POWER AMPLIFIERS
off-chip to form the RF output signal path.
The amplifier operates in Class AB bias mode. The
final stage is "deep AB", meaning the quiescentcurrent
is very low, around 40mA. As the RF drive is
increased, the final stage self-biases, causing the bias
point to shiftup and, at full power, draws about 340mA.
The optimum load for the outputstage is approximately
10 Ω. This is the load at the output collector, and is created by the series i nductance formed by the output
bond wires, leads, and microstrip, and a shunt capacitor external to the part. With this match, a 50Ω terminal
impedance is achieved. The input is matched to 50Ω
with just a blocking capacitor needed. This data sheet
defines the configuration for AMPS operation, but the
output load m ay be modified slightly for ETACS operation. In any case the optimum load for 1.2W is the
same at the device, and only the reactive elements
must change to perform the transformation from 50Ω
down to 10Ω.
The input is DC coupled; thus, a blocking cap must be
inserted in series. Also, the first stage bias m ay be
adjusted by a resistive divider with high value resistors
onthispintoV
however, no external adjustment is necessary as internal resistors set the bias point optimally.
V
provides supply voltage to the first stage, as well
CC2
as provides some frequency selectivity to tune to the
operating band. Essentially, the bias is fed to this pin
through a short microstrip. A bypass capacitor sets the
inductance seen by the part, so placement of the
bypass cap can affect the frequency of the gain peak.
For ETACS, the capacitor placement is slightly different
than for AMPS due to the frequency shift. This supply
should be bypassed individually with 33pF or 100 pF
capacitors before being combined with V
and ground. For nominal operation,
PC
CC
for the out-
put stage to prevent feedback and oscillations.
The RF OUT pins provide the output power. Pins 10
and 11 should be combined externallywith pins 14 and
15 with a symmetric combiner, as shown in the PCB
layout. Care should be taken to ensure that the output
paths are symmetric up to the point of combining. This
prevents "odd-mode" cancellation from occurring
wherein one side may get out-of-phase with the other,
affecting efficiency and stability. Bias for the final stage
is fed to this output line, and the feed must be capable
of supporting the approximately 400mA of current
required. Care should also be taken to keep the losses
low in the bias feed and output components. DC losses
in the bias choke will degrade efficiency and power.
The part will operate over a 4.0V to 4.8V range. If, for
example, the full power is desired at minimum voltage,
then the load can be optimized at that point. This is
illustrated in Application Schematic 2. At that point, the
specified efficiency and power should be attainable. As
the voltage is increased,however, the output power will
increase. Thus, in a system design, the ALC (Automatic Level Control) Loop will back d own the power to
the desired level. This will occur at a less-than-optimum efficiency, since the load is optimized for minimum voltage. If the load is set up to optimize power
and efficiency at nominal operating voltage, then max
efficiency should be attainable there. This case is illustrated in Application Schematic 1. As the voltage drops
to minimum, power will degrade, but the efficiency
tends to be maintained. For nominal 31.5dBm at 4.8V
setup, as the voltage drops to 4.0V, the output power
drops to 30.5dBm with a constant V
The HBT breakdown voltage is >20V, so nominally at
4.8 V there should be no issue with overvoltage. Under
extreme conditions, however, which can occur in a cellular handset environment, the supply voltage could be
as high as 7.5V to 8.5V. These conditions may correspond to operation in a battery charger, especially with
the batter y removed, which "unloads" the supply circuit. To add to this worst-case scenario, the RF drive
may be at full power during transmit, and the output
VSWR could be extremely high, corresponding to a
broken or removed antenna. Under all of the above
conditions,the peak RF voltages could well exceedtwo
times the supply voltage, forcing the device into breakdown. The RF2131 includes overvoltage protection
diodes at the output, which begin clipping the waveform peaks at approximately 15V. This protects the
device’s output from breaking down under these worst-
PC
.
2-102
Rev B4 010417
Page 5
case conditions, and provides a rugged, robust component for the system designer.
High current conditions are also potentially dangerous
to any RF device. High currents lead to high channel
temperatures and may force early failures. The
RF2131 includes temperature compensation circuits in
the bias network to stabilize the RF transistors, thus
limiting the current through the amplifier and protecting
the devices from damage. The same mechanism
works to compensate the currents due to ambient temperature variations.
RF2131
2
POWER AMPLIFIERS
Rev B4 010417
2-103
Page 6
RF2131
V
Application Schematic 1
Optimized f or Efficiency at 4.8V
VPC
CC
10 nF
V
CC
100 pF100 nF
2
33 pF
1
2
10 nF
3
POWER AMPLIFIERS
100 pF
RF IN
V
CC
4
5
6
7
8
100 pF
BIAS100 nF
16
10 nH
15
14
13
12
11
10
9
4.7 pF
4.7 pF
2.7 nH
10 nH
33 pF
0.200"
100 pF
5.6 pF
This schematic defines the optimum configuration for maximum efficiency at 4.8V. Under these conditions, as can be
seen in the data plots, the power drops at 4.0V. Over 70% power-added efficiency can be achieved at +30.8dBm with
4.8 V and +8dBm input level with this implementation.
RF OUT
2-104
Rev B4 010417
Page 7
RF2131
Application Schemat i c 2
Optimized for Pow er and Efficiency over 4.0V to 4.8V
VPC
V
CC
10 nF
V
CC
100 pF100 nF
33 pF
RF IN
1
2
10 nF
3
4
5
6
100 pF
7
V
CC
8
100 pF
BIAS100 nF
16
10 nH
15
14
13
12
11
10
9
4.7 pF
4.7 pF
2.7 nH
10 nH
33 pF
0.140"
100 pF
RF OUT
6.2 pF
This application circuit differs from Application schematic 1 only slightly in the output tuning. The output shunt capacitor
has been moved 0.060” closer to the device, and has increased from 5.6pF to 6.2pF. This retuning allows over
+30.8 dBm of output power to be achieved down to 4.0V, however a couple of percent points of efficiency are sacrificed.
This implementation is recommended for some additional margin on output power.
2
POWER AMPLIFIERS
Rev B4 010417
2-105
Page 8
RF2131
Evaluation Board Schema t ic
(Download Bill of Materials from www.rfmd.com.)
2
2131400A
VPC
C10
10 nF
VCC
POWER AMPLIFIERS
RF IN
J1
VCC
C12
10
nF
50
Ω µ
strip
C11
100 nF
R1
0
Ω
C1
100 pF
C13
100
pF
1
2
3
4
5
6
7
8
BIAS
16
15
C3
14
13
12
11
10
9
4.7 pF
C4
4.7 pF
C6
33 pF
L2
10 nH
L1
2.7 nH
L3
10 nH
C7
33 pF
C8
µ
10
C5
100 pF
C2
6.2 pF
VCC
C9
F
100 pF
50
Ω µ
strip
P1
P1-1
P1-3
RF OUT
J2
1
VCC
GND
2
PC
3
2-106
Rev B4 010417
Page 9
Evaluation Board Layout
3” x 2”
RF2131
2
POWER AMPLIFIERS
Rev B4 010417
2-107
Page 10
2
RF2131
POWER AMPLIFIERS
2-108
Rev B4 010417
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