Precision Micropower, Low Dropout
TP
V
S
SLEEP
GND
NC = NO CONNECT
TP PINS ARE FACTORY TEST POINTS,
NO USER CONNECTION
NC
NC
OUTPUT
TP
1
2
3
4
8
7
6
5
REF19x
SERIES
TOP VIEW
(Not to Scale)
Voltage References
REF19x Series
FEATURES
Initial Accuracy: ⴞ2 mV Max
Temperature Coefficient: 5 ppm/ⴗC Max
Low Supply Current: 45 A Max
Sleep Mode: 15 A Max
Low Dropout Voltage
Load Regulation: 4 ppm/mA
Line Regulation: 4 ppm/V
High Output Current: 30 mA
Short-Circuit Protection
APPLICATIONS
Portable Instrumentation
A/D and D/A Converters
Smart Sensors
Solar Powered Applications
Loop Current Powered Instrumentations
GENERAL DESCRIPTION
The REF19x series precision band gap voltage references use a
patented temperature drift curvature correction circuit and laser
trimming of highly stable thin-film resistors to achieve a very
low temperature coefficient and a high initial accuracy.
The REF19x series is made up of micropower, low dropout voltage
(LDV) devices providing a stable output voltage from supplies as
low as 100 mV above the output voltage and consuming less than
45 µA of supply current. In sleep mode, which is enabled by apply-
ing a low TTL or CMOS level to the SLEEP pin, the output is
turned off and supply current is further reduced to less than 15 µA.
The REF19x series references are specified over the extended
industrial temperature range (–40°C to +85°C) with typical
performance specifications over –40°C to +125°C for applications
such as automotive.
All electrical grades are available in 8-lead SOIC; the PDIP and
TSSOP are available only in the lowest electrical grade. Products
are also available in die form.
Test Pins (TP)
The test pins, Pin 1 and Pin 5, are reserved for in-package
Zener zap. To achieve the highest level of accuracy at the output,
the Zener zapping technique is used to trim the output voltage.
Since each unit may require a different amount of adjustment, the
resistance value at the test pins will vary widely from pin to pin as
well as from part to part. The user should not make any physical
or electrical connections to Pin 1 and Pin 5.
PIN CONFIGURATIONS
8-Lead SOIC and TSSOP
(S Suffix and RU Suffix)
1
TP
2
S
3
4
REF19x
SERIES
TOP VIEW
(Not to Scale)
V
SLEEP
GND
NC = NO CONNECT
TP PINS ARE FACTORY TEST POINTS,
NO USER CONNECTION
8
7
6
5
NC
NC
OUTPUT
TP
8-Lead PDIP (P Suffix)
Table I.
Part Nominal Output
Number Voltage (V)
REF191 2.048
REF192 2.50
REF193 3.00
REF194 4.50
REF195 5.00
REF196 3.30
REF198 4.096
REV. G
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
Information furnished by Analog Devices is believed to be accurate and
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 www.analog.com
Fax: 781/326-8703 © 2004 Analog Devices, Inc. All rights reserved.
REF19x Series
REF191–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
(@ VS = 3.3 V, TA = 25ⴗC, unless otherwise noted.)
Parameter Symbol Condition Min Typ Max Unit
INITIAL ACCURACY
E Grade V
1
I
O
= 0 mA 2.046 2.048 2.050 V
OUT
F Grade 2.043 2.053 V
G Grade 2.038 2.058 V
LINE REGULATION
E Grade ⌬VO/⌬V
2
IN
3.0 V ≤ VS ≤ 15 V, I
= 0 mA 2 4 ppm/V
OUT
F and G Grades 48ppm/V
LOAD REGULATION
E Grade ⌬VO/⌬V
2
LOADVS
= 5.0 V, 0 mA ≤ I
≤ 30 mA 4 10 ppm/mA
OUT
F and G Grades 615ppm/mA
DROPOUT VOLTAGE V
LONG-TERM STABILITY
3
NOISE VOLTAGE e
NOTES
1
Initial accuracy includes temperature hysteresis effect.
2
Line and load regulation specifications include the effect of self-heating.
3
Long-term drift is guaranteed by 1,000 hours life test performed on three independent wafer lots at 12 5°C, with an LTPD of 1.3.
Specifications subject to change without notice.
S
DV
N
– V
O
O
VS = 3.15 V, I
V
= 3.3 V, I
S
VS = 3.6 V, I
= 2 mA 0.95 V
LOAD
= 10 mA 1.25 V
LOAD
= 30 mA 1.55 V
LOAD
1,000 Hours @ 125°C 1.2 mV
0.1 Hz to 10 Hz 20 µV p-p
ELECTRICAL CHARACTERISTICS
(@ VS = 3.3 V, –40ⴗC ≤ TA ≤ +85ⴗC, unless otherwise noted.)
Parameter Symbol Condition Min Typ Max Unit
TEMPERATURE COEFFICIENT
E Grade TCVO/°CI
F Grade 510ppm/°C
G Grade
LINE REGULATION
3
4
E Grade ⌬VO/⌬V
1, 2
= 0 mA 2 5 ppm/°C
OUT
10 25 ppm/°C
IN
3.0 V ≤ VS ≤ 15 V, I
= 0 mA 5 10 ppm/V
OUT
F and G Grades 10 20 ppm/V
LOAD REGULATION
E Grade ⌬VO/⌬V
4
LOADVS
= 5.0 V, 0 mA ≤ I
≤ 25 C 5 15 ppm/mA
OUT
F and G Grades 10 20 ppm/mA
DROPOUT VOLTAGE V
– V
S
O
VS = 3.15 V, I
V
= 3.3 V, I
S
VS = 3.6 V, I
LOAD
LOAD
= 2 mA 0.95 V
LOAD
= 10 mA 1.25 V
= 25 mA 1.55 V
SLEEP PIN
Logic High Input Voltage V
Logic High Input Current I
Logic Low Input Voltage V
Logic Low Input Current I
H
H
L
L
2.4 V
–8 µA
0.8 V
–8 µA
SUPPLY CURRENT No Load 45 µA
Sleep Mode No Load 15 µA
NOTES
1
For proper operation, a 1 µF capacitor is required between the output pin and the GND pin of the device.
2
TCVO is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm /°C.
3
Guaranteed by characterization.
4
Line and load regulation specifications include the effect of self-heating.
Specifications subject to change without notice.
TCVO=(V
MAX–VMIN
)/ VO(T
MAX–TMIN
).
REV. G–2–
REF191–SPECIFICATIONS
REF19x Series
ELECTRICAL CHARACTERISTICS
(@ VS = 3.3 V, –40ⴗC ≤ TA ≤ +125ⴗC, unless otherwise noted.)
Parameter Symbol Condition Min Typ Max Unit
TEMPERATURE COEFFICIENT
E Grade TCVO/°CI
F Grade 5 ppm/°C
G Grade
LINE REGULATION
3
4
E Grade ⌬VO/⌬V
1, 2
= 0 mA 2 ppm/°C
OUT
10 ppm/°C
IN
3.0 V ≤ VS ≤ 15 V, I
= 0 mA 10 ppm/V
OUT
F and G Grades 20 ppm/V
LOAD REGULATION
E Grade ⌬VO/⌬V
4
LOADVS
= 5.0 V, 0 mA ≤ I
≤ 20 mA 10 ppm/mA
OUT
F and G Grades 20 ppm/mA
DROPOUT VOLTAGE V
NOTES
1
For proper operation, a 1 µF capacitor is required between the output pin and the GND pin of the device.
2
TCVO is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm /°C.
3
Guaranteed by characterization.
4
Line and load regulation specifications include the effect of self-heating.
Specifications subject to change without notice.
TCVO =(V
MAX–VMIN
S
)/ VO(T
– V
O
MAX–TMIN
VS = 3.3 V, I
VS = 3.6 V, I
).
= 10 mA 1.25 V
LOAD
= 20 mA 1.55 V
LOAD
REV. G
–3–
REF19x Series
REF192–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
(@ VS = 3.3 V, TA = 25ⴗC, unless otherwise noted.)
Parameter Symbol Condition Min Typ Max Unit
INITIAL ACCURACY
E Grade V
1
I
O
= 0 mA 2.498 2.500 2.502 V
OUT
F Grade 2.495 2.505 V
G Grade 2.490 2.510 V
LINE REGULATION
E Grade ⌬VO/⌬V
2
IN
3.0 V ≤ VS ≤ 15 V, I
= 0 mA 2 4 ppm/V
OUT
F and G Grades 48ppm/V
LOAD REGULATION
E Grade ⌬VO/⌬V
2
LOADVS
= 5.0 V, 0 mA ≤ I
≤ 30 mA 4 10 ppm/mA
OUT
F and G Grades 615ppm/mA
DROPOUT VOLTAGE V
LONG-TERM STABILITY
3
NOISE VOLTAGE e
NOTES
1
Initial accuracy includes temperature hysteresis effect.
2
Line and load regulation specifications include the effect of self-heating.
3
Long-term drift is guaranteed by 1,000 hours life test performed on three independent wafer lots at 12 5°C, with an LTPD of 1.3.
Specifications subject to change without notice.
ELECTRICAL CHARACTERISTICS
S
DV
N
– V
O
O
VS = 3.5 V, I
VS = 3.9 V, I
= 10 mA 1.00 V
LOAD
= 30 mA 1.40 V
LOAD
1,000 Hours @ 125°C 1.2 mV
0.1 Hz to 10 Hz 25 µV p-p
(@ VS = 3.3 V, TA = –40ⴗC ≤ TA ≤ +85ⴗC, unless otherwise noted.)
Parameter Symbol Condition Min Typ Max Unit
TEMPERATURE COEFFICIENT
E Grade TCVO/°CI
F Grade 510ppm/°C
G Grade
LINE REGULATION
3
4
E Grade ⌬VO/⌬V
1, 2
= 0 mA 2 5 ppm/°C
OUT
10 25 ppm/°C
IN
3.0 V ≤ VS ≤ 15 V, I
= 0 mA 5 10 ppm/V
OUT
F and G Grades 10 20 ppm/V
LOAD REGULATION
E Grade ⌬VO/⌬V
4
LOADVS
= 5.0 V, 0 mA ≤ I
≤ 25 mA 5 15 ppm/mA
OUT
F and G Grades 10 20 ppm/mA
DROPOUT VOLTAGE V
– V
S
O
VS = 3.5 V, I
VS = 4.0 V, I
= 10 mA 1.00 V
LOAD
= 25 mA 1.50 V
LOAD
SLEEP PIN
Logic High Input Voltage V
Logic High Input Current I
Logic Low Input Voltage V
Logic Low Input Current I
H
H
L
L
2.4 V
–8 µA
0.8 V
–8 µA
SUPPLY CURRENT No Load 45 µA
Sleep Mode No Load 15 µA
NOTES
1
For proper operation, a 1 µF capacitor is required between the output pin and the GND pin of the device.
2
TCVO is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm /°C.
3
Guaranteed by characterization.
4
Line and load regulation specifications include the effect of self-heating.
Specifications subject to change without notice.
TCVO=(V
MAX–VMIN
)/ VO(T
MAX–TMIN
).
–4–
REV. G
REF192–SPECIFICATIONS
REF19x Series
ELECTRICAL CHARACTERISTICS
(@ VS = 3.3 V, –40ⴗC ≤ TA ≤ +125ⴗC, unless otherwise noted.)
Parameter Symbol Condition Min Typ Max Unit
TEMPERATURE COEFFICIENT
E Grade TCVO/°CI
F Grade 5 ppm/°C
G Grade
LINE REGULATION
3
4
E Grade ⌬VO/⌬V
1, 2
= 0 mA 2 ppm/°C
OUT
10 ppm/°C
IN
3.0 V ≤ VS ≤ 15 V, I
= 0 mA 10 ppm/V
OUT
F and G Grades 20 ppm/V
LOAD REGULATION
E Grade ⌬VO/⌬V
4
LOADVS
= 5.0 V, 0 mA ≤ I
≤ 20 mA 10 ppm/mA
OUT
F and G Grades 20 ppm/mA
DROPOUT VOLTAGE V
NOTES
1
For proper operation, a 1 µF capacitor is required between the output pin and the GND pin of the device.
2
TCVO is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm /°C.
3
Guaranteed by characterization.
4
Line and load regulation specifications include the effect of self-heating.
Specifications subject to change without notice.
TCVO=(V
MAX–VMIN
)/ VO(T
– V
S
O
MAX–TMIN
VS = 3.5 V, I
VS = 4.0 V, I
).
= 10 mA 1.00 V
LOAD
= 20 mA 1.50 V
LOAD
REF193–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
(@ VS = 3.3 V, TA = 25ⴗC, unless otherwise noted.)
Parameter Symbol Condition Min Typ Max Unit
INITIAL ACCURACY
G Grade V
LINE REGULATION
G Grades ⌬VO/⌬V
LOAD REGULATION
G Grade ⌬VO/⌬V
DROPOUT VOLTAGE V
LONG-TERM STABILITY
NOISE VOLTAGE e
NOTES
1
Initial accuracy includes temperature hysteresis effect.
2
Line and load regulation specifications include the effect of self-heating.
3
Long-term drift is guaranteed by 1,000 hours life test performed on three independent wafer lots at 12 5°C, with an LTPD of 1.3.
Specifications subject to change without notice.
1
I
O
2
IN
2
LOADVS
– V
S
O
3
DV
N
O
= 0 mA 2.990 3.0 3.010 V
OUT
3.3 V, ≤ VS ≤ 15 V, I
= 5.0 V, 0 mA ≤ I
VS = 3.8 V, I
VS = 4.0 V, I
LOAD
LOAD
= 0 mA 4 8 ppm/V
OUT
≤ 30 mA 6 15 ppm/mA
OUT
= 10 mA 0.80 V
= 30 mA 1.00 V
1,000 Hours @ 125°C 1.2 mV
0.1 Hz to 10 Hz 30 µV p-p
REV. G
–5–
REF19x Series
REF193–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
= 3.3 V, TA = –40ⴗC ≤ TA ≤ +85ⴗC, unless otherwise noted.)
(@ V
S
Parameter Symbol Condition Min Typ Max Unit
TEMPERATURE COEFFICIENT
G Grade
LINE REGULATION
3
4
G Grade ⌬VO/⌬V
LOAD REGULATION
4
G Grade ⌬VO/⌬V
DROPOUT VOLTAGE V
1, 2
TCVO/°CI
IN
LOADVS
– V
S
O
= 0 mA 10 25 ppm/°C
OUT
3.3 V ≤ VS ≤ 15 V, I
= 5.0 V, 0 mA ≤ I
VS = 3.8 V, I
VS = 4.1 V, I
LOAD
LOAD
= 0 mA 10 20 ppm/V
OUT
≤ 25 mA 10 20 ppm/mA
OUT
= 10 mA 0.80 V
= 30 mA 1.10 V
SLEEP PIN
Logic High Input Voltage V
Logic High Input Current I
Logic Low Input Voltage V
Logic Low Input Current I
H
H
L
L
2.4 V
–8 µA
0.8 V
–8 µA
SUPPLY CURRENT No Load 45 µA
Sleep Mode No Load 15 µA
NOTES
1
For proper operation, a 1 µF capacitor is required between the output pin and the GND pin of the device.
2
TCVO is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm /°C.
3
Guaranteed by characterization.
4
Line and load regulation specifications include the effect of self-heating.
Specifications subject to change without notice.
TCVO=(V
MAX–VMIN
)/ VO(T
MAX–TMIN
).
ELECTRICAL CHARACTERISTICS
(@ VS = 3.3 V, –40ⴗC ≤ TA ≤ +125ⴗC, unless otherwise noted.)
Parameter Symbol Condition Min Typ Max Unit
TEMPERATURE COEFFICIENT
G Grade
LINE REGULATION
3
4
G Grade ⌬VO/⌬V
LOAD REGULATION
4
G Grade ⌬VO/⌬V
DROPOUT VOLTAGE V
NOTES
1
For proper operation, a 1 µF capacitor is required between the output pin and the GND pin of the device.
2
TCVO is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm /°C.
3
Guaranteed by characterization.
4
Line and load regulation specifications include the effect of self-heating.
Specifications subject to change without notice.
TCVO=(V
1, 2
MAX–VMIN
TCVO/°CI
IN
LOADVS
– V
S
O
OUT
3.3 V ≤ VS ≤ 15 V, I
VS = 3.8 V, I
VS = 4.1 V, I
)/ VO(T
MAX–TMIN
).
= 0 mA 10 ppm/°C
= 0 mA 20 ppm/V
OUT
= 5.0 V, 0 mA ≤ I
LOAD
LOAD
≤ 20 mA 10 ppm/mA
OUT
= 10 mA 0.80 V
= 20 mA 1.10 V
–6–
REV. G
REF194–SPECIFICATIONS
REF19x Series
ELECTRICAL CHARACTERISTICS
(@ VS = 5.0 V, TA = 25ⴗC, unless otherwise noted.)
Parameter Symbol Condition Min Typ Max Unit
INITIAL ACCURACY
E Grade V
1
I
O
= 0 mA 4.498 4.5 4.502 V
OUT
F Grade 4.495 4.505 V
G Grade 4.490 4.510 V
LINE REGULATION
E Grade ⌬VO/⌬V
2
IN
4.75 V ≤ VS ≤ 15 V, I
= 0 mA 2 4 ppm/V
OUT
F and G Grades 48ppm/V
LOAD REGULATION
E Grade ⌬VO/⌬V
2
LOADVS
= 5.8 V, 0 mA ≤ I
≤ 30 mA 2 4 ppm/mA
OUT
F and G Grades 48ppm/mA
DROPOUT VOLTAGE V
LONG-TERM STABILITY
3
NOISE VOLTAGE e
NOTES
1
Initial accuracy includes temperature hysteresis effect.
2
Line and load regulation specifications include the effect of self-heating.
3
Long-term drift is guaranteed by 1,000 hours life test performed on three independent wafer lots at 12 5°C, with an LTPD of 1.3.
Specifications subject to change without notice.
S
DV
N
– V
O
O
VS = 5.00 V, I
VS = 5.8 V, I
= 10 mA 0.50 V
LOAD
= 30 mA 1.30 V
LOAD
1,000 Hours @ 125°C2mV
0.1 Hz to 10 Hz 45 µV p-p
ELECTRICAL CHARACTERISTICS
(@ VS = 5.0 V, TA = –40ⴗC ≤ TA ≤ +85ⴗC, unless otherwise noted.)
Parameter Symbol Condition Min Typ Max Unit
TEMPERATURE COEFFICIENT
E Grade TCVO/°CI
F Grade 510ppm/°C
G Grade
LINE REGULATION
3
4
E Grade ⌬VO/⌬V
1, 2
= 0 mA 2 5 ppm/°C
OUT
10 25 ppm/°C
IN
4.75 V ≤ VS ≤ 15 V, I
= 0 mA 5 10 ppm/V
OUT
F and G Grades 10 20 ppm/V
LOAD REGULATION
E Grade ⌬VO/⌬V
4
LOADVS
= 5.80 V, 0 mA ≤ I
≤ 25 mA 5 15 ppm/mA
OUT
F and G Grades 10 20 ppm/mA
DROPOUT VOLTAGE V
– V
S
O
VS = 5.00 V, I
VS = 5.80 V, I
= 10 mA 0.5 V
LOAD
= 25 mA 1.30 V
LOAD
SLEEP PIN
Logic High Input Voltage V
Logic High Input Current I
Logic Low Input Voltage V
Logic Low Input Current I
H
H
L
L
2.4 V
–8 µA
0.8 V
–8 µA
SUPPLY CURRENT No Load 45 µA
Sleep Mode No Load 15 µA
NOTES
1
For proper operation, a 1 µF capacitor is required between the output pin and the GND pin of the device.
2
TCVO is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm /°C.
3
Guaranteed by characterization.
4
Line and load regulation specifications include the effect of self-heating.
Specifications subject to change without notice.
TCVO=(V
MAX–VMIN
)/ VO(T
MAX–TMIN
).
REV. G
–7–
REF19x Series
REF194–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
(@ VS = 5.0 V, –40ⴗC ≤ TA ≤ +125ⴗC, unless otherwise noted.)
Parameter Symbol Condition Min Typ Max Unit
TEMPERATURE COEFFICIENT
E Grade TCVO/°CI
F Grade 5 ppm/°C
G Grade
LINE REGULATION
3
4
E Grade ⌬VO/⌬V
1, 2
= 0 mA 2 ppm/°C
OUT
10 ppm/°C
IN
4.75 V ≤ VS ≤ 15 V, I
= 0 mA 5 ppm/V
OUT
F and G Grades 10 ppm/V
LOAD REGULATION
E Grade ⌬VO/⌬V
4
LOADVS
= 5.80 V, mA 0 ≤ I
≤ 20 mA 5 ppm/mA
OUT
F and G Grades 10 ppm/mA
DROPOUT VOLTAGE V
NOTES
1
For proper operation, a 1 µF capacitor is required between the output pin and the GND pin of the device.
2
TCVO is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm /°C.
3
Guaranteed by characterization.
4
Line and load regulation specifications include the effect of self-heating.
Specifications subject to change without notice.
TCVO=(V
MAX–VMIN
)/ VO(T
– V
S
O
MAX–TMIN
VS = 5.10 V, I
VS = 5.95 V, I
).
= 10 mA 0.60 V
LOAD
= 20 mA 1.45 V
LOAD
–8–
REV. G
REF195–SPECIFICATIONS
REF19x Series
ELECTRICAL CHARACTERISTICS
(@ VS = 5.10 V, TA = 25ⴗC, unless otherwise noted.)
Parameter Symbol Condition Min Typ Max Unit
INITIAL ACCURACY
E Grade V
1
I
O
= 0 mA 4.998 5.0 5.002 V
OUT
F Grade 4.995 5.005 V
G Grade 4.990 5.010 V
LINE REGULATION
E Grade ⌬VO/⌬V
2
IN
5.10 V ≤ VS ≤ 15 V, I
= 0 mA 2 4 ppm/V
OUT
F and G Grades 48ppm/V
LOAD REGULATION
E Grade ⌬VO/⌬V
2
LOADVS
= 6.30 V, 0 mA ≤ I
≤ 30 mA 2 4 ppm/mA
OUT
F and G Grades 48ppm/mA
DROPOUT VOLTAGE V
LONG-TERM STABILITY
3
NOISE VOLTAGE e
NOTES
1
Initial accuracy includes temperature hysteresis effect.
2
Line and load regulation specifications include the effect of self-heating.
3
Long-term drift is guaranteed by 1,000 hours life test performed on three independent wafer lots at 12 5°C, with an LTPD of 1.3.
Specifications subject to change without notice.
ELECTRICAL CHARACTERISTICS
S
DV
N
– V
O
O
VS = 5.50 V, I
VS = 6.30 V, I
= 10 mA 0.50 V
LOAD
= 30 mA 1.30 V
LOAD
1,000 Hours @ 125°C 1.2 mV
0.1 Hz to 10 Hz 50 µV p-p
(@ VS = 5.15 V, TA = –40ⴗC ≤ TA ≤ +85ⴗC, unless otherwise noted.)
Parameter Symbol Condition Min Typ Max Unit
TEMPERATURE COEFFICIENT
E Grade TCVO/°CI
F Grade 510ppm/°C
G Grade
LINE REGULATION
3
4
E Grade ⌬VO/⌬V
1, 2
= 0 mA 2 5 ppm/°C
OUT
10 25 ppm/°C
IN
5.15 V ≤ VS ≤ 15 V, I
= 0 mA 5 10 ppm/V
OUT
F and G Grades 10 20 ppm/V
LOAD REGULATION
E Grade ⌬VO/⌬V
4
LOADVS
= 6.30 V, 0 mA ≤ I
≤ 25 mA 5 10 ppm/mA
OUT
F and G Grades 10 20 ppm/mA
DROPOUT VOLTAGE V
– V
S
O
VS = 5.50 V, I
VS = 6.30 V, I
= 10 mA 0.50 V
LOAD
= 25 mA 1.30 V
LOAD
SLEEP PIN
Logic High Input Voltage V
Logic High Input Current I
Logic Low Input Voltage V
Logic Low Input Current I
H
H
L
L
2.4 V
–8 µA
0.8 V
–8 µA
SUPPLY CURRENT No Load 45 µA
Sleep Mode No Load 15 µA
NOTES
1
For proper operation, a 1 µF capacitor is required between the output pin and the GND pin of the device.
2
TCVO is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm /°C.
3
Guaranteed by characterization.
4
Line and load regulation specifications include the effect of self-heating.
Specifications subject to change without notice.
TCVO=(V
MAX–VMIN
)/ VO(T
MAX–TMIN
).
REV. G
–9–
REF19x Series
REF195–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
(@ VS = 5.20 V, –40ⴗC ≤ TA ≤ +125ⴗC, unless otherwise noted.)
Parameter Symbol Condition Min Typ Max Unit
TEMPERATURE COEFFICIENT
E Grade TCVO/°CI
F Grade 5 ppm/°C
G Grade
LINE REGULATION
3
4
E Grade ⌬VO/⌬V
1, 2
= 0 mA 2 ppm/°C
OUT
10 ppm/°C
IN
5.20 V ≤ VS ≤ 15 V, I
= 0 mA 5 ppm/V
OUT
F and G Grades 10 ppm/V
LOAD REGULATION
E Grade ⌬VO/⌬V
4
LOADVS
= 6.45 V, 0 mA ≤ I
≤ 20 mA 5 ppm/mA
OUT
F and G Grades 10 ppm/mA
DROPOUT VOLTAGE V
NOTES
1
For proper operation, a 1 µF capacitor is required between the output pin and the GND pin of the device.
2
TCVO is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm /°C.
3
Guaranteed by characterization.
4
Line and load regulation specifications include the effect of self-heating.
Specifications subject to change without notice.
TCVO=(V
MAX–VMIN
)/ VO(T
– V
S
O
MAX–TMIN
VS = 5.60 V, I
VS = 6.45 V, I
).
= 10 mA 0.60 V
LOAD
= 20 mA 1.45 V
LOAD
REF196–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
(@ VS = 3.5 V, TA = 25ⴗC, unless otherwise noted.)
Parameter Symbol Condition Min Typ Max Unit
INITIAL ACCURACY
G Grade V
LINE REGULATION
G Grades ⌬VO/⌬V
LOAD REGULATION
G Grade ⌬VO/⌬V
DROPOUT VOLTAGE V
LONG-TERM STABILITY
NOISE VOLTAGE e
NOTES
1
Initial accuracy includes temperature hysteresis effect.
2
Line and load regulation specifications include the effect of self-heating.
3
Long-term drift is guaranteed by 1,000 hours life test performed on three independent wafer lots at 12 5°C, with an LTPD of 1.3.
Specifications subject to change without notice.
1
I
O
2
IN
2
LOADVS
– V
S
O
3
DV
N
O
= 0 mA 3.290 3.3 3.310 V
OUT
3.50 V ≤ VS ≤ 15 V, I
= 5.0 V, 0 mA ≤ I
VS = 4.1 V, I
VS = 4.3 V, I
LOAD
LOAD
= 0 mA 4 8 ppm/V
OUT
≤ 30 mA 6 15 ppm/mA
OUT
= 10 mA 0.80 V
= 30 mA 1.00 V
1,000 Hours @ 125°C 1.2 mV
0.1 Hz to 10 Hz 33 µV p-p
–10–
REV. G
REF196–SPECIFICATIONS
REF19x Series
ELECTRICAL CHARACTERISTICS
(@ VS = 3.5 V, TA = –40ⴗC ≤ TA ≤ +85ⴗC, unless otherwise noted.)
Parameter Symbol Condition Min Typ Max Unit
TEMPERATURE COEFFICIENT
G Grade
LINE REGULATION
3
4
G Grade ⌬VO/⌬V
LOAD REGULATION
4
G Grade ⌬VO/⌬V
DROPOUT VOLTAGE V
1, 2
TCVO/°CI
IN
LOADVS
– V
S
O
= 0 mA 10 25 ppm/°C
OUT
3.5 V ≤ VS ≤ 15 V, I
= 5.0 V, 0 mA ≤ I
VS = 4.1 V, I
VS = 4.3 V, I
LOAD
LOAD
= 0 mA 10 20 ppm/V
OUT
≤ 25 mA 10 20 ppm/mA
OUT
= 10 mA 0.80 V
= 25 mA 1.00 V
SLEEP PIN
Logic High Input Voltage V
Logic High Input Current I
Logic Low Input Voltage V
Logic Low Input Current I
H
H
L
L
2.4 V
–8 µA
0.8 V
–8 µA
SUPPLY CURRENT No Load 45 µA
Sleep Mode No Load 15 µA
NOTES
1
For proper operation, a 1 µF capacitor is required between the output pin and the GND pin of the device.
2
TCVO is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm /°C.
3
Guaranteed by characterization.
4
Line and load regulation specifications include the effect of self-heating.
Specifications subject to change without notice.
TCVO=(V
MAX–VMIN
)/ VO(T
MAX–TMIN
).
ELECTRICAL CHARACTERISTICS
(@ VS = 3.50 V, –40ⴗC ≤ TA ≤ +125ⴗC, unless otherwise noted.)
Parameter Symbol Condition Min Typ Max Unit
TEMPERATURE COEFFICIENT
G Grade
LINE REGULATION
3
4
G Grade ⌬VO/⌬V
LOAD REGULATION
4
G Grade ⌬VO/⌬V
DROPOUT VOLTAGE V
NOTES
1
For proper operation, a 1 µF capacitor is required between the output pin and the GND pin of the device.
2
TCVO is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm /°C.
3
Guaranteed by characterization.
4
Line and load regulation specifications include the effect of self-heating.
Specifications subject to change without notice.
TCVO=(V
1, 2
MAX–VMIN
TCVO/°CI
IN
LOADVS
– V
S
O
OUT
3.50 V ≤ VS ≤ 15 V, I
VS = 4.1 V, I
VS = 4.4 V, I
)/ VO(T
MAX–TMIN
).
= 0 mA 10 ppm/°C
= 0 mA 20 ppm/V
OUT
= 5.0 V, 0 mA ≤ I
LOAD
LOAD
≤ 20 mA 20 ppm/mA
OUT
= 10 mA 0.80 V
= 20 mA 1.10 V
REV. G
–11–
REF19x Series
REF198–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
(@ VS = 5.0 V, TA = 25ⴗC, unless otherwise noted.)
Parameter Symbol Condition Min Typ Max Unit
INITIAL ACCURACY
E Grade V
1
I
O
= 0 mA 4.094 4.096 4.098 V
OUT
F Grade 4.091 4.101 V
G Grade 4.086 4.106 V
LINE REGULATION
E Grade ⌬VO/⌬V
2
IN
4.5 V ≤ VS ≤ 15 V, I
= 0 mA 2 4 ppm/V
OUT
F and G Grades 48ppm/V
LOAD REGULATION
E Grade ⌬VO/⌬V
2
LOADVS
= 5.4 V, 0 mA ≤ I
≤ 30 mA 2 4 ppm/mA
OUT
F and G Grades 48ppm/mA
DROPOUT VOLTAGE V
LONG-TERM STABILITY
3
NOISE VOLTAGE e
NOTES
1
Initial accuracy includes temperature hysteresis effect.
2
Line and load regulation specifications include the effect of self-heating.
3
Long-term drift is guaranteed by 1,000 hours life test performed on three independent wafer lots at 12 5°C, with an LTPD of 1.3.
Specifications subject to change without notice.
ELECTRICAL CHARACTERISTICS
S
DV
N
– V
O
O
VS = 4.6 V, I
VS = 5.4 V, I
= 10 mA 0.50 V
LOAD
= 30 mA 1.30 V
LOAD
1,000 Hours @ 125°C 1.2 mV
0.1 Hz to 10 Hz 40 µV p-p
(@ VS = 5.0 V, –40ⴗC ≤ TA ≤ +85ⴗC, unless otherwise noted.)
Parameter Symbol Condition Min Typ Max Unit
TEMPERATURE COEFFICIENT
E Grade TCVO/°CI
F Grade 510ppm/°C
G Grade
LINE REGULATION
3
4
E Grade ⌬VO/⌬V
1, 2
= 0 mA 2 5 ppm/°C
OUT
10 25 ppm/°C
IN
4.5 V ≤ VS ≤ 15 V, I
= 0 mA 5 10 ppm/V
OUT
F and G Grades 10 20 ppm/V
LOAD REGULATION
E Grade ⌬VO/⌬V
4
LOADVS
= 5.4 V, 0 mA ≤ I
≤ 25 mA 5 10 ppm/mA
OUT
F and G Grades 10 20 ppm/mA
DROPOUT VOLTAGE V
– V
S
O
VS = 4.6 V, I
VS = 5.4 V, I
= 10 mA 0.50 V
LOAD
= 25 mA 1.30 V
LOAD
SLEEP PIN
Logic High Input Voltage V
Logic High Input Current I
Logic Low Input Voltage V
Logic Low Input Current I
H
H
L
L
2.4 V
–8 µA
0.8 V
–8 µA
SUPPLY CURRENT No Load 45 µA
Sleep Mode No Load 15 µA
NOTES
1
For proper operation, a 1 µF capacitor is required between the output pin and the GND pin of the device.
2
TCVO is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm /°C.
3
Guaranteed by characterization.
4
Line and load regulation specifications include the effect of self-heating.
Specifications subject to change without notice.
TCVO=(V
MAX–VMIN
)/ VO(T
MAX–TMIN
).
–12–
REV. G
REF198–SPECIFICATIONS
REF19x Series
ELECTRICAL CHARACTERISTICS
(@ VS = 5.0 V, –40ⴗC ≤ TA ≤ +125ⴗC, unless otherwise noted.)
Parameter Symbol Condition Min Typ Max Unit
TEMPERATURE COEFFICIENT
E Grade TCVO/°CI
F Grade 5 ppm/°C
G Grade
LINE REGULATION
3
4
E Grade ⌬VO/⌬V
1, 2
= 0 mA 2 ppm/°C
OUT
10 ppm/°C
IN
4.5 V ≤ VS ≤ 15 V, I
= 0 mA 5 ppm/V
OUT
F and G Grades 10 ppm/V
LOAD REGULATION
E Grade ⌬VO/⌬V
4
LOADVS
= 5.6 V, 0 mA ≤ I
≤ 20 mA 5 ppm/mA
OUT
F and G Grades 10 ppm/mA
DROPOUT VOLTAGE V
NOTES
1
For proper operation, a 1 µF capacitor is required between the output pin and the GND pin of the device.
2
TCVO is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm /°C.
3
Guaranteed by characterization.
4
Line and load regulation specifications include the effect of self-heating.
Specifications subject to change without notice.
WAFER TEST LIMITS
TCVO=(V
MAX–VMIN
(@ I
LOAD
)/ VO(T
– V
S
O
MAX–TMIN
VS = 4.7 V, I
VS = 5.6 V, I
).
= 10 mA 0.60 V
LOAD
= 20 mA 1.50 V
LOAD
= 0 mA, TA = 25ⴗC, unless otherwise noted.)
Parameter Symbol Condition Limit Unit
INITIAL ACCURACY
REF191 V
O
2.043/2.053 V
REF192 2.495/2.505 V
REF193 2.990/3.010 V
REF194 4.495/4.505 V
REF195 4.995/5.005 V
REF196 3.290/3.310 V
REF198 4.091/4.101 V
LINE REGULATION ⌬VO/⌬V
LOAD REGULATION ⌬VO/⌬I
DROPOUT VOLTAGE V
– V+ I
O
IN
LOAD
(VO + 0.5 V) < VIN < 15 V, I
0 mA < I
= 10 mA 1.25 V
LOAD
I
= 30 mA 1.55 V
LOAD
< 30 mA, VIN = (VO + 1.3 V) 15 ppm/mA
LOAD
= 0 mA 15 ppm/V
OUT
SLEEP MODE INPUT
Logic Input High V
Logic Input Low V
SUPPLY CURRENT V
IH
IL
= 15 V No Load 45 µA
IN
2.4 V
0.8 V
Sleep Mode No Load 15 µA
For proper operation, a 1 µF capacitor is required between the output pins and the GND pin of the REF19x. Electrical tests and wafer probe to the limits shown.
Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard product dice. Consult factory to negotiate specifications
based on dice lot qualifications through sample lot assembly and testing.
REV. G
–13–
REF19x Series
ABSOLUTE MAXIMUM RATINGS
1, 2
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +18 V
Output to GND . . . . . . . . . . . . . . . . . . . . . –0.3 V, V
+ 0.3 V
S
Output to GND Short-Circuit Duration . . . . . . . . . Indefinite
Storage Temperature Range
P, S Package . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Operating Temperature Range
REF19x . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
Junction Temperature Range
P, S Package . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature Range (Soldering 60 sec) . . . . . . . . . 300°C
Package Type
3
JA
JC
Unit
8-Lead PDIP (P) 103 43 °C/W
8-Lead SOIC (S) 158 43 °C/W
8-Lead TSSOP (RU) 240 43 °C/W
NOTES
1
Absolute maximum rating applies to both DICE and packaged parts, unless
otherwise noted.
2
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
3
θJA is specified for worst-case conditions, i.e., θ
PDIP, and θJA is specified for device soldered in circuit board for SOIC package.
is specified for device in socket for
JA
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
REF19x features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
ORDERING GUIDE
Model Temperature Range Package Description Package Option Reel
REF191ES –40°C to +85°C 8-Lead SOIC S-Suffix (R-8)
REF191ES-REEL –40°C to +85°C 8-Lead SOIC S-Suffix (R-8) 2,500
REF191GP –40°C to +85°C 8-Lead PDIP P-Suffix (N-8
REF191GS –40°C to +85°C 8-Lead SOIC S-Suffix (R-8)
REF191GS-REEL7 –40°C to +85°C 8-Lead SOIC S-Suffix (R-8) 1,000
REF192ES –40°C to +85°C 8-Lead SOIC S-Suffix (R-8)
REF192ES-REEL –40°C to +85°C 8-Lead SOIC S-Suffix (R-8) 2,500
REF192ES-REEL7 –40°C to +85°C 8-Lead SOIC S-Suffix (R-8) 1,000
REF192FS –40°C to +85°C 8-Lead SOIC S-Suffix (R-8)
REF192FS-REEL –40°C to +85°C 8-Lead SOIC S-Suffix (R-8) 2,500
REF192FS-REEL7 –40°C to +85°C 8-Lead SOIC S-Suffix (R-8) 1,000
REF192FSZ-REEL7* –40°C to +85°C 8-Lead SOIC S-Suffix (R-8) 1,000
REF192GP –40°C to +85°C 8-Lead PDIP P-Suffix (N-8)
REF192GRU –40°C to +85°C 8-Lead TSSOP RU-8
REF192GRU-REEL7 –40°C to +85°C 8-Lead TSSOP RU-8 1,000
REF192GS –40°C to +85°C 8-Lead SOIC S-Suffix (R-8)
REF192GS-REEL –40°C to +85°C 8-Lead SOIC S-Suffix (R-8) 2,500
REF192GS-REEL7 –40°C to +85°C 8-Lead SOIC S-Suffix (R-8) 1,000
REF192GSZ-REEL7* –40°C to +85°C 8-Lead SOIC S-Suffix (R-8) 1,000
Minimum
Quantities/
–14–
REV. G
REF19x Series
ORDERING GUIDE (continued)
Minimum
Quantities/
Model Temperature Range Package Description Package Option Reel
REF193GS –40°C to +85°C 8-Lead SOIC R-8
REF193GS-REEL –40°C to +85°C 8-Lead SOIC R-8 2,500
REF194ES –40°C to +85°C 8-Lead SOIC R-8
REF194ES-REEL –40°C to +85°C 8-Lead SOIC R-8 2,500
REF194ESZ* –40°C to +85°C 8-Lead SOIC R-8
REF194ESZ-REEL* –40°C to +85°C 8-Lead SOIC R-8 2,500
REF194FS –40°C to +85°C 8-Lead SOIC R-8
REF194FSZ* –40°C to +85°C 8-Lead SOIC R-8
REF194GP –40°C to +85°C 8-Lead PDIP N-8
REF194GS –40°C to +85°C 8-Lead SOIC R-8
REF194GS-REEL –40°C to +85°C 8-Lead SOIC R-8 2,500
REF194GS-REEL7 –40°C to +85°C 8-Lead SOIC R-8 1,000
REF194GSZ* –40°C to +85°C 8-Lead SOIC R-8
REF195ES –40°C to +85°C 8-Lead SOIC R-8
REF195ES-REEL –40°C to +85°C 8-Lead SOIC R-8 2,500
REF195ESZ* –40°C to +85°C 8-Lead SOIC R-8
REF195ESZ-REEL* –40°C to +85°C 8-Lead SOIC R-8 2,500
REF195FS –40°C to +85°C 8-Lead SOIC R-8
REF195FS-REEL –40°C to +85°C 8-Lead SOIC R-8 2,500
REF195FSZ* –40°C to +85°C 8-Lead SOIC R-8
REF195FSZ-REEL* –40°C to +85°C 8-Lead SOIC R-8 2,500
REF195GP –40°C to +85°C 8-Lead PDIP N-8
REF195GRU –40°C to +85°C 8-Lead TSSOP RU-8
REF195GRU-REEL7 –40°C to +85°C 8-Lead TSSOP RU-8 1,000
REF195GS –40°C to +85°C 8-Lead SOIC R-8
REF195GS-REEL –40°C to +85°C 8-Lead SOIC R-8 2,500
REF195GS-REEL7 –40°C to +85°C 8-Lead SOIC R-8 1,000
REF195GSZ* –40°C to +85°C 8-Lead SOIC R-8
REF195GSZ-REEL7* –40°C to +85°C 8-Lead SOIC R-8 1,000
REF196GRU-REEL7 –40°C to +85°C 8-Lead TSSOP RU-8 1,000
REF196GS –40°C to +85°C 8-Lead SOIC R-8
REF196GS-REEL –40°C to +85°C 8-Lead SOIC R-8 2,500
REF196GSZ-REEL7* –40°C to +85°C 8-Lead SOIC R-8 1,000
REF198ES –40°C to +85°C 8-Lead SOIC R-8
REF198ES-REEL –40°C to +85°C 8-Lead SOIC R-8 2,500
REF198ESZ* –40°C to +85°C 8-Lead SOIC R-8
REF198ESZ-REEL* –40°C to +85°C 8-Lead SOIC R-8 2,500
REF198ESZ-REEL7* –40°C to +85°C 8-Lead SOIC R-8 1,000
REF198FS –40°C to +85°C 8-Lead SOIC R-8
REF198FS-REEL –40°C to +85°C 8-Lead SOIC R-8 2,500
REF198FSZ-REEL* –40°C to +85°C 8-Lead SOIC R-8 2,500
REF198GP –40°C to +85°C 8-Lead PDIP N-8
REF198GRU –40°C to +85°C 8-Lead TSSOP RU-8
REF198GRU-REEL7 –40°C to +85°C 8-Lead TSSOP RU-8 1,000
REF198GRUZ* –40°C to +85°C 8-Lead TSSOP RU-8
REF198GRUZ-REEL* –40°C to +85°C 8-Lead TSSOP RU-8 2,500
REF198GS –40°C to +85°C 8-Lead SOIC R-8
REF198GS-REEL –40°C to +85°C 8-Lead SOIC R-8 2,500
REF198GSZ* –40°C to +85°C 8-Lead SOIC R-8
REF198GSZ-REEL* –40°C to +85°C 8-Lead SOIC R-8 2,500
*Z = Pb-free part.
REV. G
–15–
REF19x Series–Typical Performance Characteristics
5.004
5.003
5.002
5.001
5.000
4.999
OUTPUT VOLTAGE (V)
4.998
4.997
4.996
3 TYPICAL PARTS
5.15V < V
< 15V
IN
–25–50
TEMPERATURE (ⴗC)
100
7550250
TPC 1. REF195 Output Voltage vs. Temperature
32
28
5.15V
V
15V
24
20
16
12
8
LOAD REGULATION (ppm/V)
4
S
–40ⴗC
+25ⴗC
+85ⴗC
50
45
BASED ON 600
UNITS, 4 RUNS
40
35
30
25
20
15
PERCENTAGE OF PARTS
10
5
0
–15
–20
TPC 4. TC – V
40
35
30
25
20
15
SUPPLY CURRENT (A)
10
5
TC – V
OUT
OUT
–40ⴗC
TA
(ppm/ⴗC)
Distribution
NORMAL MODE
SLEEP MODE
+85ⴗC
151050–5–10
20
0
50
I
LOAD
(mA)
TPC 2. REF195 Load Regulation vs. I
20
0mA ⱕ I
16
12
8
LINE REGULATION (ppm/mA)
4
0
6
4
OUT
< 25mA
VIN (V)
TPC 3. REF195 Line Regulation vs. V
1412108
25201510
LOAD
+85ⴗC
+25ⴗC
–40ⴗC
IN
30
0
–25–50
TEMPERATURE (ⴗC)
7550250
100
TPC 5. Quiescent Current vs. Temperature
–6
–5
A)
–4
–3
–2
SLEEP PIN CURRENT (
–1
16
0
–50
TPC 6.
–25
SLEEP
TEMPERATURE (ⴗC)
Pin Current vs. Temperature
V
L
V
H
100
7550250
REV. G–16–
REF19x Series
0
–20
–40
–60
–80
RIPPLE REJECTION (dB)
–100
–120
10 100 1M100k10k1k
FREQUENCY (Hz)
TPC 7a. Ripple Rejection vs. Frequency
10F
1k⍀
V
IN
= 15V
REF
10F
2
REF19x
6
1F
4
1k⍀
TPC 7b. Ripple Rejection vs. Frequency
Measurement Circuit
10F
OUTPUT
VIN = 15V
2
4
REF19x
6
1F
10mA
0
TPC 9b. Load Transient Response Measurement Circuit
2V
100
90
1mA
LOAD
10
0%
2V
30mA
LOAD
100s
TPC 10a. Power ON Response Time
VIN = 7V
2
4
REF19x
6
1F
V
= 7V
IN
4
3
(⍀)
2
O
Z
1
0
10 100 10M1M100k10k1k
2
REF19x
1F
4
FREQUENCY (Hz)
1F
200V
6
Z
VG = 2V p-p
V
= 4V
S
TPC 8. Output Impedance vs. Frequency
OFF
ON
5V
100
90
TPC 10b. Power ON Response Time Measurement Circuit
5V
100
ON
90
OFF
IL = 1mA
2ms
Response Time
6
1F
V
OUT
TPC 11b.
V
OUT
0%
TPC 11a.
VIN = 15V
SLEEP
IL = 10mA
10
1V
SLEEP
2
3
REF19x
4
Response Time Measurement Circuit
REV. G
10
0%
20mV
100s
TPC 9a. Load Transient Response
–17–
REF19x Series
5V
100
90
10
0%
200mV
TPC 12. Line Transient Response
200s
35
30
25
20
15
LOAD CURRENT (mA)
10
5
0
0.1
0
REF195 DROPOUT VOLTAGE (V)
0.80.70.60.50.40.30.2
TPC 13. Load Current vs. Dropout Voltage
0.9
V+
V
OUT
SLEEP (SHUTDOWN)
GND
Figure 1. Simplified Schematic
APPLICATIONS SECTION
Output Short-Circuit Behavior
The REF19x family of devices is totally protected from damage
due to accidental output shorts to GND or to V+. In the event
of an accidental short-circuit condition, the reference device will
shut down and limit its supply current to 40 mA.
Device Power Dissipation Considerations
The REF19x family of references is capable of delivering load
currents to 30 mA with an input voltage that ranges from 3.3 V
to 15 V. When these devices are used in applications with large
input voltages, care should be exercised to avoid exceeding
these devices’ maximum internal power dissipation. Exceeding
the published specifications for maximum power dissipation or
junction temperature could result in premature device failure.
The following formula should be used to calculate a device’s
maximum junction temperature or dissipation:
T–T
J
P
=
D
In this equation, TJ and TA are the junction and ambient temperatures, respectively, P
is the device power dissipation, and θJA is
D
A
θ
J
A
the device package thermal resistance.
Output Voltage Bypassing
For stable operation, low dropout voltage regulators and references generally require a bypass capacitor connected from their
V
pins to their GND pins. Although the REF19x family of
OUT
references is capable of stable operation with capacitive loads
exceeding 100 µF, a 1 µF capacitor is sufficient to guarantee rated
performance. The addition of a 0.1 µF ceramic capacitor in parallel
with the bypass capacitor will improve load current transient
performance. For best line voltage transient performance, it is
recommended that the voltage inputs of these devices be bypassed
with a 10 µF electrolytic capacitor in parallel with a 0.1 µF
ceramic capacitor.
Sleep Mode Operation
All REF19x devices include a sleep capability that is TTL/CMOS
level compatible. Internally, a pull-up current source to V
is
IN
connected at the SLEEP pin. This permits the SLEEP pin to be
driven from an open collector/drain driver. A logic low or a 0 V
condition on the SLEEP pin is required to turn off the output
stage. During sleep, the output of the references becomes a high
impedance state where its potential would then be determined
by external circuitry. If the sleep feature is not used, it is recommended that the SLEEP pin be connected to V
(Pin 2).
IN
Basic Voltage Reference Connections
The circuit in Figure 2 illustrates the basic configuration for the
REF19x family of references. Note the 10 µF/0.1 µF bypass net-
work on the input and the 1 µF/0.1 µF bypass network on the
output. It is recommended that no connections be made to Pins 1,
5, 7, and 8. If the sleep feature is not required, Pin 3 should be
connected to V
10F
.
IN
0.1F
NC
V
IN
SLEEP
NC = NO CONNECT
1
2
3
4
REF19x
NC
8
NC
7
6
OUTPUT
5
TANT
1F
NC
0.1F
Figure 2. Basic Voltage Reference Configuration
–18–
REV. G
REF19x Series
Membrane Switch Controlled Power Supply
With output load currents in the tens of mA, the REF19x family
of references can operate as a low dropout power supply in handheld instrument applications. In the circuit shown in Figure 3,
amembrane ON/OFF switch is used to control the operation of
the reference. During an initial power-on condition, the SLEEP
pin is held to GND by the 10 kΩ resistor. Recall that this condition
disables (read: three-state) the REF19x output. When the membrane ON switch is pressed, the SLEEP pin is momentarily pulled to
, enabling the REF19x output. At this point, current through
V
IN
the 10 kΩ is reduced and the internal current source connected
to the SLEEP pin takes control. Pin 3 assumes and remains at the
same potential as V
. When the membrane OFF switch is pressed,
IN
the SLEEP pin is momentarily connected to GND, which once
again disables the REF19x output.
NC
8
NC
7
OUTPUT
6
5
NC
1F
TANT
1k⍀
ON
OFF
NC
V
IN
5%
1
2
REF19x
3
4
10k⍀
NC = NO CONNECT
Figure 3. Membrane Switch Controlled Power Supply
Current-Boosted References with Current Limiting
While the 30 mA rated output current of the REF19x series is
higher than typical of other reference ICs, it can be boosted to
higher levels if desired with the addition of a simple external
PNP transistor, as shown in Figure 4. Full-time current limiting
is used for protection of the pass transistor against shorts.
+VS = 6V TO 9V
(SEE TEXT)
100F/25V
V
COMMON
R4
2⍀
Q2
2N3906
C2
D1
C
1N4148
(SEE TEXT
ON SLEEP)
V
S
U1
REF196
(SEE TABLE)
R1
1k⍀
R2
1.5k⍀
1.82k⍀
Q1
TIP32A
(SEE TEXT)
C3
0.1F
(TANTALUM)
R3
S
10F/25V
S
F
F
C1
OUTPUT TABLE
V
U1
OUT
REF192
REF193
REF196
REF194
REF195
+V
OUT
3.3V
@ 150mA
R1
V
OUT
COMMON
2.5
3.0
3.3
4.5
5.0
(V)
Figure 4. A Boosted 3.3 V Reference with Current Limiting
In this circuit, the power supply current of reference U1 flowing
through R1 to R2 develops a base drive for Q1, whose collector
provides the bulk of the output current. With a typical gain of
100 in Q1 for 100 mA to 200 mA loads, U1 is never required to
furnish more than a few mA, so this factor minimizes temperaturerelated drift. Short-circuit protection is provided by Q2, which
clamps drive to Q1 at about 300 mA of load current with values
as shown. With this separation of control and power functions,
dc stability is optimum, allowing best advantage use of premium
grade REF19x devices for U1. Of course, load management
should still be exercised. A short, heavy, low DCR (dc resistance)
conductor should be used from U1 to 6 to the V
sense point
OUT
S, where the collector of Q1 connects to the load, point F.
Because of the current limiting configuration, the dropout voltage
circuit is raised about 1.1 V over that of the REF19x devices, due
to the V
of Q1 and the drop across current sense resistor R4.
BE
However, overall dropout is typically still low enough to allow
operation of a 5 V to 3.3 V regulator/reference using the REF196
for U1 as noted, with a V
as low as 4.5 V and a load current
S
of 150 mA.
The requirement for a heat sink on Q1 depends on the maximum
input voltage and short-circuit current. With V
= 5 V and a
S
300 mA current limit, the worst-case dissipation of Q1 is 1.5 W,
less than the TO-220 package 2 W limit. However, if smaller
TO-39 or TO-5 packaged devices, such as the 2N4033, are
used, the current limit should be reduced to keep maximum
dissipation below the package rating. This is accomplished by
simply raising R4.
A tantalum output capacitor is used at C1 for its low ESR
(equivalent series resistance), and the higher value is required
for stability. Capacitor C2 provides input bypassing and can be
an ordinary electrolytic.
Shutdown control of the booster stage is shown as an option, and
when used, some cautions are needed. Because of the additional
active devices in the V
line to U1, direct drive to Pin 3 does not
S
work as with an unbuffered REF19x device. To enable shutdown
control, the connection from U1 to U2 is broken at the X, and
diode D1 then allows a CMOS control source V
to drive U1 to
C
3 for ON/OFF operation. Startup from shutdown is not as clean
under heavy load as it is in basic REF19x series and can require
several milliseconds under load. Nevertheless, it is still effective
and can fully control 150 mA loads. When shutdown control is
used, heavy capacitive loads should be minimized.
A Negative Precision Reference without Precision Resistors
In many current-output CMOS DAC applications where the
output signal voltage must be of the same polarity as the reference
voltage, it is often required to reconfigure a current-switching
DAC into a voltage-switching DAC through the use of a 1.25 V
reference, an op amp, and a pair of resistors. Using a currentswitching DAC directly requires an additional operational
amplifier at the output to reinvert the signal. A negative voltage
reference is then desirable because an additional operational
amplifier is not required for either reinversion (current-switching
mode) or amplification (voltage-switching mode) of the DAC
output voltage. In general, any positive voltage reference can be
converted into a negative voltage reference through the use of an
operational amplifier and a pair of matched resistors in an inverting configuration. The disadvantage to that approach is that the
largest single source of error in the circuit is the relative matching
of the resistors used.
REV. G
–19–
REF19x Series
The circuit illustrated in Figure 5 avoids the need for tightly
matched resistors by using an active integrator circuit. In this
circuit, the output of the voltage reference provides the input
drive for the integrator. The integrator, to maintain circuit equilibrium, adjusts its output to establish the proper relationship
between the reference’s V
and GND. Thus, any desired
OUT
negative output voltage can be chosen by simply substituting for
the appropriate reference IC. The sleep feature is maintained in
the circuit with the simple addition of a PNP transistor and a
10 kΩ resistor. One caveat with this approach should be mentioned: although rail-to-rail output amplifiers work best in the
application, these operational amplifiers require a finite amount
(mV) of headroom when required to provide any load current.
The choice for the circuit’s negative supply should take this issue
into account.
V
IN
10k⍀
SLEEP
TTL/CMOS
10k⍀
2N3906
3
V
SLEEP
REF19x
GND
2
IN
V
OUT
4
100k⍀
1k⍀
6
1F
1F
+5V
A1
–5V
A1 = 1/2 OP295,
1/2 OP291
100⍀
–V
REF
Figure 5. A Negative Precision Voltage Reference
Uses No Precision Resistors
Stacking Reference ICs for Arbitrary Outputs
Some applications may require two reference voltage sources that
are a combined sum of standard outputs. The circuit in Figure 6
shows how this stacked output reference can be implemented.
OUTPUT TABLE
VS > V
COMMON
+V
OUT2
S
V
IN
+ 0.15V
0.1F
0.1F
U1/U2
REF192/REF192
REF192/REF194
REF192/REF195
C1
C3
U2
REF19x
(SEE TABLE)
U1
REF19x
(SEE TABLE)
VO (U2)
VO (U1)
C2
1F
C4
1F
V
OUT1
(V)
2.5
2.5
2.5
R1
3.9k⍀
(SEE TEXT)
V
OUT2
5.0
7.0
7.5
+V
OUT2
+V
OUT1
V
OUT
COMMON
(V)
Figure 6. Stacking Voltage References with the REF19x
Two reference ICs are used, fed from a common unregulated
input, V
. The outputs of the individual ICs are simply con-
S
nected in series as shown, which provides two output voltages,
V
OUT1
and V
OUT2
. V
is the terminal voltage of U1, while
OUT1
is the sum of this voltage and the terminal voltage of U2.
V
OUT2
U1 and U2 are simply chosen for the two voltages that supply
the required outputs (see Table I). If, for example, both U1 and
U2 are REF192s, the two outputs are 2.5 V and 5.0 V.
While this concept is simple, some cautions are needed. Since
the lower reference circuit must sink a small bias current from
U2 (50 µA to 100 µA), plus the base current from the series PNP
output transistor in U2, either the external load of U1 or R1
must provide a path for this current. If the U1 minimum load is
not well defined, Resistor R1 should be used, set to a value that
will conservatively pass 600 µA of current with the applicable
V
across it. Note that the two U1 and U2 reference circuits
OUT1
are locally treated as macrocells, each having its own bypasses at
input and output for best stability. Both U1 and U2 in this circuit
can source dc currents up to their full rating. The minimum
input voltage, V
, is determined by the sum of the outputs, V
S
OUT2
,
plus the dropout voltage of U2.
A related variation on stacking two 3-terminal references is shown
in Figure 6, where U1, a REF192, is stacked with a 2-terminal
reference diode such as the AD589. Like the 3-terminal stacked
reference above, this circuit provides two outputs, V
V
, which are the individual terminal voltages of D1 and U1,
OUT2
respectively. Here this is 1.235 and 2.5, which provides a V
OUT1
and
OUT2
of 3.735 V. When using 2-terminal reference diodes, such as
D1, the rated minimum and maximum device currents must be
observed and the maximum load current from V
greater than the current set up by R1 and V
with V
equal to 2.5 V, R1 provides a 500 µA bias to D1, so
O(U1)
the maximum load current available at V
+V
S
VS > V
OUT2
COMMON
+ 0.15V
V
IN
0.1F
U1
AD589
REF192
D1
VO (U1)
VO (D1)
C1
O(U1)
is 450 µA or less.
OUT1
C2
1F
C3
1F
can be no
OUT1
. In the case
+V
OUT2
3.735V
R1
4.99k⍀
(SEE TEXT)
+V
OUT1
1.235V
V
OUT
COMMON
Figure 7. Stacking Voltage References with the REF19x
A Precision Current Source
Many times, in low power applications, the need arises for a
precision current source that can operate on low supply voltages.
As shown in Figure 8, any one of the devices in the REF19x
family of references can be configured as a precision current
source. The circuit configuration illustrated is a floating current
source with a grounded load. The reference’s output voltage is
bootstrapped across R
, which sets the output current into the
SET
load. With this configuration, circuit precision is maintained for
load currents in the range from the reference’s supply current
(typically 30 µA) to approximately 30 mA. The low dropout
voltage of these devices maximizes the current source’s output
voltage compliance without excess headroom.
–20–
REV. G
V
IN
V
IN
REF19x
SLEEP
VIN I
OUT
V
OUT
I
= + ISY (REF19x)
OUT
R
SET
V
OUT
R
SET
V
REF
GND
ⴛ RL (MAX) + VSY (MIN)
SY
E.G., REF195: V
>> I
1F
ADJUST
R1
I
SY
P1
I
OUT
R
L
= 5V
OUT
I
= 5mA
OUT
R1 = 953⍀
P1 = 100⍀, 10-TURN
R
SET
Figure 8. A Low Dropout, Precision Current Source
The circuit’s governing equations are
VI R V REF x
=× +
IN OUT L SY
V
I
=+
OUT
R
V
OUT
I REF x
〉〉
R
SET
() (, )
Max Min 19
OUT
I REF x
()
SY
SET
()
SY
19
19
Switched Output 5 V/3.3 V Reference
Applications often require digital control of reference voltages,
selecting between one stable voltage and a second. With the
sleep feature inherent to the REF19x series, switched output
reference configurations are easily implemented with relatively
little additional hardware.
The circuit of Figure 9 illustrates the general technique, which
takes advantage of the output “wire-OR” capability of the REF19x
device family. When OFF, a REF19x device is effectively an
open circuit at the output node with respect to the power supply.
When ON, a REF19x device can source current up to its current
rating, but sink only a few µA (essentially just the relatively low
current of the internal output scaling divider). As a result, for
two devices wired together at their common outputs, the output
voltage is simply that of the ON device. The OFF state device
will draw a small standby current of 15 µA (max), but otherwise
will not interfere with operation of the ON device, which can
operate to its full current rating. Note that the two devices in
the circuit conveniently share both input and output capacitors,
and with CMOS logic drive, it is power efficient.
REF19x Series
OUTPUT TABLE
U1/U2
REF195/
REF196
= 6V
+V
S
V
V
COMMON
C
IN
U3A
74HC04
3412
U3B
74HC04
0.1F
U1
REF19x
(SEE TABLE)
U2
REF19x
(SEE TABLE)
C1
REF194/
REF195
*CMOS LOGIC LEVELS
Figure 9. Switched Output Reference
Using dissimilar REF19x series devices with this configuration
allows logic selection between the U1/U2 specified terminal voltages. For example, with U1 (a REF195) and U2 (a REF196), as
noted in the table in Figure 9, changing the CMOS compatible
VC logic control voltage from HI to LO selects between a nominal output of 5.000 V and 3.300 V and vice versa. Other REF19x
family units can also be used for U1/U2, with similar operation
in a logic sense, but with outputs as per the individual paired
devices (see table again). Of course, the exact output voltage
tolerance, drift, and overall quality of the reference voltage will
be consistent with the grade of individual U1 and U2 devices.
Because of the nature of the wire-OR, there is one application
caveat that should be understood about this circuit. Since U1
and U2 can only source current effectively, negative going output
voltage changes, which require the sinking of current, will necessarily take longer than positive going changes. In practice, this
means that the circuit is quite fast when undergoing a transition
from 3.3 V to 5 V, but the transition from 5 V to 3.3 V will take
longer. Exactly how much longer will be a function of the load
resistance, R
seen at the output and the typical 1 µF value of
L,
C2. In general, a conservative transition time here will be on the
order of several milliseconds for load resistances in the range of
100 Ω to 1 kΩ. Note that for highest accuracy at the new output
voltage, several time constants should be allowed (>7.6 time
constants for <1/2 LSB error @ 10 bits, for example).
VC*
HI
LO
HI
LO
C2
1F
V
(V)
OUT
5.0
3.3
4.5
5.0
+V
OUT
V
OUT
COMMON
REV. G
–21–
REF19x Series
S
Kelvin Connections
In many portable instrumentation applications where PC board
cost and area go hand-in-hand, circuit interconnects are very
often narrow. These narrow lines can cause large voltage drops
if the voltage reference is required to provide load currents to
various functions. In fact, a circuit’s interconnects can exhibit
a typical line resistance of 0.45 mΩ/square (1 oz. Cu, for
example). In those applications where these devices are configured as low dropout voltage regulators, these wiring voltage
drops can become a large source of error. To circumvent this
problem, force and sense connections can be made to the reference through the use of an operational amplifier, as shown in
Figure 10. This method provides a means by which the effects
of wiring resistance voltage drops can be eliminated. Load currents flowing through wiring resistance produce an I-R error
(I
LOAD
⫻ R
) at the load. However, the Kelvin connection
WIRE
overcomes the problem by including the wiring resistance within
the forcing loop of the op amp. Since the op amp senses the load
voltage, op amp loop control forces the output to compensate
for the wiring error and to produce the correct voltage at the
load. Depending on the reference device chosen, operational
amplifiers that can be used in this application are the OP295, the
OP292, and the OP183.
LEEP
V
IN
V
IN
REF19x
V
OUT
GND
1F
V
IN
2
A1
3
100k⍀
A1 = 1/2 OP295
R
LW
R
1
1/2 OP292
OP183
LW
+V
OUT
SENSE
+V
OUT
FORCE
R
L
Figure 10. A Low Dropout, Kelvin Connected
Voltage Reference
A Fail-Safe 5 V Reference
Some critical applications require a reference voltage to be maintained constant, even with a loss of primary power. The low standby
power of the REF19x series and the switched output capability
allow a fail-safe reference configuration to be implemented
rather easily. This reference maintains a tight output voltage
tolerance for either a primary power source (ac line derived) or
a standby (battery derived) power source, automatically switching
between the two as the power conditions change.
The circuit in Figure 11 illustrates the concept, which borrows
from the switched output idea of Figure 8, again using the REF19x
device family output wire-OR capability. In this case, since a
constant 5 V reference voltage is desired for all conditions, two
REF195 devices are used for U1 and U2, with their ON/OFF
switching controlled by the presence or absence of the primary
. V
dc supply source, V
plies power to the load only when V
power conditions, V
is a 6 V battery backup source that sup-
S
BAT
sees only the 15 µA (max) standby current
BAT
fails. For normal (VS present)
S
drain of U1 in its OFF state.
In operation, it is assumed that for all conditions either U1 or U2
is ON and a 5 V reference output is available. With this voltage
constant, a scaled down version is applied to the comparator IC
U3, providing a fixed 0.5 V input to the (–) input for all power
conditions. The R1 to R2
input proportional to V
upon the absolute level of V
divider provides a signal to the U3 (+)
, which switches U3 and U1/U2 dependent
S
. Op amp U3 is configured here as
S
a comparator with hysteresis, which provides for clean, noise-free
output switching. This hysteresis is important to eliminate rapid
switching at the threshold due to V
ripple. Further, the device
S
chosen is the AD820, a rail-to-rail output device that provides
HI and LO output states within a few mV of V
accurate thresholds and compatible drive for U2 for all V
and ground for
S
condi-
S
tions. R3 provides positive feedback for circuit hysteresis, changing
the threshold at the (+) input as a function of U3’s output.
+V
BAT
+V
, V
V
BAT
S
COMMON
S
R1
1.1M⍀
R2
100k⍀
C4
0.1F
R3
10M⍀
3
2
R5
100k⍀
4
7
6
U3
AD820
R6
100⍀
R4
900k⍀
Q1
2N3904
C2
0.1F
C1
0.1F
U1
REF195
U2
REF195
5.000V
C3
1F
V
OUT
COMMON
Figure 11. A Fail-Safe 5 V Reference
–22–
REV. G
For VS levels lower than the LOWER threshold, U3’s output is
500⍀
0.1%
57k⍀
1%
0.1F
10k⍀
1%
0.1F
1/4
OP492
10F
1F
REF195
1/4
OP492
1/4
OP492
1/4
OP492
2.21k⍀
20k⍀
1%
10k⍀
1%
20k⍀
1%
20k⍀
1%
0.01F
10F
100⍀
OUTPUT
2N2222
20k⍀
1%
10k⍀
1%
low, thus U2 and Q1 are OFF, while U1 is ON. For V
levels
S
higher than the UPPER threshold, the situation reverses, with
U1 OFF and both U2 and Q1 ON. In the interest of battery
power conservation, all of the comparison switching circuitry
is powered from V
and is arranged so that when VS fails, the
S
default output comes from U1.
For the R1 to R3
values as shown, the LOWER/UPPER VS switching thresholds are approximately 5.5 V and 6 V, respectively.
These can obviously be changed to suit other V
supplies, as can
S
the REF19x devices used for U1 and U2, over a range of 2.5 V
to 5 V of output. U3 can operate down to a V
of 3.3 V, which
S
is generally compatible with all family devices.
A Low Power, Strain Gage Circuit
As shown in Figure 12, the REF19x family of references can be
used in conjunction with low supply voltage operational amplifiers, such as the OP492 and the OP283, in a self-contained strain
gage circuit. In this circuit, the REF195 was used as the core of
this low power, strain gage circuit. Other references can be easily
accommodated by changing circuit element values. The references
play a dual role as the voltage regulator to provide the supply
voltage requirements of the strain gage and the operational
amplifiers as well as a precision voltage reference for the current
source used to stimulate the bridge. A distinct feature of the
circuit is that it can be remotely controlled ON or OFF by digital
means via the SLEEP pin.
REF19x Series
Figure 12. A Low Power, Strain Gage Circuit
REV. G
–23–
REF19x Series
8-Lead Plastic Dual In-Line Package [PDIP]
(N-8)
P-Suffix
Dimensions shown in inches and (millimeters)
0.375 (9.53)
0.365 (9.27)
0.355 (9.02)
8
1
0.100 (2.54)
0.180
(4.57)
MAX
0.150 (3.81)
0.130 (3.30)
0.110 (2.79)
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
COMPLIANT TO JEDEC STANDARDS MO-095AA
BSC
5
4
0.295 (7.49)
0.285 (7.24)
0.275 (6.98)
0.015
(0.38)
MIN
SEATING
PLANE
0.060 (1.52)
0.050 (1.27)
0.045 (1.14)
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
OUTLINE DIMENSIONS
8-Lead Thin Shrink Small Outline Package [TSSOP]
0.150 (3.81)
0.135 (3.43)
0.120 (3.05)
0.015 (0.38)
0.010 (0.25)
0.008 (0.20)
COPLANARITY
(RU-8)
Dimensions shown in millimeters
3.10
3.00
2.90
8
5
4.50
6.40 BSC
4.40
4.30
41
PIN 1
0.65
0.15
0.05
BSC
0.10
COMPLIANT TO JEDEC STANDARDS MO-153AA
0.30
0.19
1.20
MAX
SEATING
PLANE
0.20
0.09
8ⴗ
0ⴗ
0.75
0.60
0.45
8-Lead Standard Small Outline Package [SOIC]
Narrow Body
(R-8)
S-Suffix
Dimensions shown in millimeters and (inches)
5.00 (0.1968)
4.80 (0.1890)
4.00 (0.1574)
3.80 (0.1497)
0.25 (0.0098)
0.10 (0.0040)
COPLANARITY
0.10
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
85
1.27 (0.0500)
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MS-012AA
BSC
6.20 (0.2440)
5.80 (0.2284)
41
1.75 (0.0688)
1.35 (0.0532)
0.51 (0.0201)
0.31 (0.0122)
0.25 (0.0098)
0.17 (0.0067)
0.50 (0.0196)
0.25 (0.0099)
8ⴗ
0ⴗ
1.27 (0.0500)
0.40 (0.0157)
ⴛ 45ⴗ
–24–
REV. G
REF19x Series
Revision History
Location Page
7/04—Data Sheet Changed from REV. F to REV. G.
Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3/04—Data Sheet Changed from REV. E to REV. F.
Updated ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Updated ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
1/03—Data Sheet Changed from REV. D to REV. E.
Changes to TPCs 2 and 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Changes to Output Short Circuit Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Changes to Figure 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Changes to Figure 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
REV. G
–25–
–26–
–27–
C00371–0–7/04(G)
–28–
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