Page 1
RDA5802E
SINGLE-CHIP BROADCAST FM RADIO TUNER Rev.1.7–Jun.2009
1 General Description
The RDA5802E (RDA5802 Enhanced) is a
single-chip broadcast FM stereo radio tuner with
fully integrated synthesizer, IF selectivity and MPX
decoder. The tuner uses the CMOS process,
support multi-interface and require the least
external component. The package size is 4X4mm
and is completely adjustment-free. All these make
it very suitable for portable devices.
The RDA5802E has a powerful low-IF digital audio
processor, this make it have optimum sound quality
with varying reception conditions.
The RDA5802E can be tuned to the worldwide
frequency band.
Figure 1-1. RDA5802E Top View
1.1 Features
l
CMOS single-chip fully-integrated FM tuner
l
Low power consumption
Ø
Total current consumption lower than 22mA at 3.0V
power supply
l
Support worldwide frequency band
Ø
65 -108 MHz
l
Digital low-IF tuner
Ø
Image-reject down-converter
Ø
High performance A/D converter
Ø
IF selectivity performed internally
l
Fully integrated digital frequency synthesizer
Ø
Fully integrated on-chip RF and IF VCO
Ø
Fully integrated on-chip loop filter
l
Autonomous search tuning
l
Support 32.768KHz crystal oscillator
l
Digital auto gain control (AGC)
l
Digital adaptive noise cancellation
Ø
Mono/stereo switch
Ø
Soft mute
Copyright © RDA Microelectronics Inc. 2006. All rights are reserved.
The information contained herein is the exclusive property of RDA and shall not be distributed, reproduced, or disclosed in whole or in
part without prior written permission of RDA.
Ø
High cut
l
Programmable de-emphasis (50/75 µs)
l
Receive signal strength indicator (RSSI)
l
Bass boost
l
Volume control
l
I2S digital output interface
l
Line-level analog output voltage
l
32.768 KHz 12M,24M,13M,26M,19.2M,38.4MHz
Reference clock
l
2-wire and 3-wire serial control bus interface
l
Directly support 32Ω resistance loading
l
Integrated LDO regulator
Ø
1.8 to 5.5 V operation voltage
l
4X4mm 24 pin QFN package
1.2 Applications
l
Cellular handsets
l
MP3, MP4 players
l
Portable radios，PDAs, Notebook
Page 2
RDA Microelectronics, Inc. RDA5802E FM Tuner V1.7
2 Table of Contents
1 General Description....................................................................................................................................1
1.1 Features.........................................................................................................................................1
1.2
Applications
....................................................................................................................................1
2 Table of Contents........................................................................................................................................2
3 Functional Description...............................................................................................................................3
3.1 FM Receiver.................................................................................................................................3
3.2 Synthesizer....................................................................................................................................3
3.3 Power Supply................................................................................................................................3
3.4 RESET and Control Interface select.............................................................................................4
3.5 Control Interface...........................................................................................................................4
3.6 I
2
S Audio Data Interface...............................................................................................................4
3.7 GPIO Outputs...............................................................................................................................4
4 Electrical Characteristics...........................................................................................................................5
5 Receiver Characteristics.............................................................................................................................6
6 Serial Interface............................................................................................................................................7
6.1 Three-wire Interface Timing.........................................................................................................7
6.2 I
2
C Interface Timing.....................................................................................................................8
7 Register Definition......................................................................................................................................9
8 Pins Description........................................................................................................................................13
9 Application Diagram................................................................................................................................15
9.1 Audio Loading Resistance Larger than 32Ω & TCXO Application:..........................................15
9.1.1 Bill of Materials:.........................................................................................................................15
9.2 Audio Loading Resistance Lower than 32Ω & DCXO Application:..........................................16
9.2.1 Bill of Materials:.........................................................................................................................16
10 Package Physical Dimension....................................................................................................................17
11 PCB Land Pattern....................................................................................................................................18
12 Change List................................................................................................................................................21
13 Notes：.......................................................................................................................................................21
14 RDA5802E 与 RDA5802 对比..................................................................................................................22
15 Contact Information.................................................................................................................................23
The information contained herein is the exclusive property of RDA and shall not be distributed, reproduced, or disclosed in whole or in
part without prior written permission of RDA. Page 2 of 23
Page 3
RDA Microelectronics, Inc. RDA5802E FM Tuner V1.7
3 Functional Description
Figure 3-1. RDA5802E FM Tuner Block Diagram
3.1 FM Receiver
The receiver uses a digital low-IF architecture that
avoids the difficulties associated with direct
conversion while delivering lower solution cost
and reduces complexity, and integrates a low
noise amplifier (LNA) supporting the FM
broadcast band (65 to 108MHz), a quadrature
image-reject mixer, a programmable gain control
(PGA), a high resolution analog-to-digital
converters (ADCs), an audio DSP and a highfidelity digital-to-analog converters (DACs).
The LNA has differential input ports (LNAP and
LNAN) and supports any input port by set
according registers bits (LNA_PORT_SEL[1:0]). It
default input common mode voltage is GND.
The limiter prevents overloading and limits the
amount of intermodulation products created by
strong adjacent channels.
The quadrature mixer down converts the LNA
output differential RF signal to low-IF, it also has
image-reject function.
The DSP core finishes the channel selection, FM
demodulation, stereo MPX decoder and output
audio signal. The MPX decoder can autonomous
switch from stereo to mono to limit the output
noise.
The DACs convert digital audio signal to analog
and change the volume at same time. The DACs
has low-pass feature and -3dB frequency is about
30 KHz.
3.2 Synthesizer
The frequency synthesizer generates the local
oscillator signal which divide to quadrature, then
be used to downconvert the RF input to a
constant low intermediate frequency (IF). The
synthesizer reference clock is 32.768 KHz.
The synthesizer frequency is defined by bits
CHAN[9:0] with the range from 65MHz to
108MHz.
3.3 Power Supply
The PGA amplifies the mixer output IF signal and
then digitized with ADCs.
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part without prior written permission of RDA. Page 3 of 23
The RDA5802E integrated one LDO which
supplies power to the chip. The external supply
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RDA Microelectronics, Inc. RDA5802E FM Tuner V1.7
voltage range is 1.8-5.5 V.
3.4 RESET and Control Interface select
The RDA5802E is RESET itself When VIO is
Power up. And also support soft reset by trigger
02H BIT1 from 0 to 1. The control interface is
select by MODE Pin. The MODE Pin is low ,I2C
Interface is select. The MODE Pin is set to VIO,
SPI Interface is select.
3.5 Control Interface
The RDA5802E supports three- wire and I2C
control interface. User could select either of them
to program the chip.
The three-wire interface is a standard SPI
interface. It includes three pins: SEN, SCLK and
SDIO. Each register write is 25-bit long, including
4-bit high register address, a r/w bit, 4-bit low
register address, and 16-bit data (MSB is the first
bit). RDA5802E samples command byte and data
at posedge of SCLK. Each register read is also
25-bit long, including 4-bit high register address, a
r/w bit, 4-bit low register address, and 16-bit data
(MSB is the first bit) from RDA5802E. The turn
around cycle between command byte from MCU
and data from RDA5802E is a half cycle.
RDA5802E samples command byte at posedge of
SCLK, and output data also at posedge of SCLK.
The I2C interface is compliant to I2C Bus
Specification 2.1. It includes two pins: SCLK and
SDIO. A I2C interface transfer begins with START
condition, a command byte and data bytes, each
byte has a followed ACK (or NACK) bit, and ends
with STOP condition. The command byte includes
a 7-bit chip address (0010000b) and a R/W bit.
The ACK (or NACK) is always sent out by receiver.
When in write transfer, data bytes is written out
from MCU, and when in read transfer, data bytes
is read out from RDA5802E. There is no visible
register address in I2C interface transfers. The I2C
interface has a fixed start register address (0x02h
for write transfer and 0x0Ah for read transfer), and
an internal incremental address counter. If register
address meets the end of register file, 0x3Ah,
register address will wrap back to 0x00h. For write
transfer, MCU programs registers from register
0x02h high byte, then register 0x02h low byte,
then register 0x03h high byte, till the last register.
RDA5802E always gives out ACK after every byte,
and MCU gives out STOP condition when register
programming is finished. For read transfer, after
command byte from MCU, RDA5802E sends out
register 0x0Ah high byte, then register 0x0Ah low
byte, then register 0x0Bh high byte, till receives
NACK from MCU. MCU gives out ACK for data
bytes besides last data byte. MCU gives out
NACK for last data byte, and then RDA5802E will
return the bus to MCU, and MCU will give out
STOP condition.
Details refer to RDA5802E Programming Guide.
3.6 I2S Audio Data Interface
The RDA5802E supports I2S (Inter_IC Sound Bus)
audio interface. The interface is fully compliant
with I2S bus specification. When setting I2SEN bit
high, RDA5802E will output SCK, WS, SD signals
from GPIO3, GPIO1, GPIO2 as I2S master and
transmitter, the sample rate is 48Kbps ，
44.1kbps,32kbps….. RDA5802E also support as
I2S slaver mode and transmitter, the sample rate
is less than 100kbps.
Details refer to RDA5802E Programming Guide.
3.7 GPIO Outputs
The RDA5802E has three GPIOs. The function of
GPIOs could programmed with bits GPIO1[1:0],
GPIO2[1:0], GPIO3[1:0] and I2SEN.
If I2SEN is set to low, GPIO pins could be
programmed to output low or high or high-Z, or be
programmed to output interrupt and stereo
indicator with bits GPIO1[1:0], GPIO2[1:0],
GPIO3[1:0]. GPIO2 could be programmed to
output a low interrupt (interrupt will be generated
only with interrupt enable bit STCIEN is set to high)
when seek/tune process completes. GPIO3 could
be programmed to output stereo indicator bit ST.
Constant low, high or high-Z functionality is
available regardless of the state of VA and VD
supplies or the ENABLE bit.
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part without prior written permission of RDA. Page 4 of 23
Page 5
RDA Microelectronics, Inc. RDA5802E FM Tuner V1.7
SCK
WS
SD
1 SCK
MSB
LEFT CHANNEL
LSB MSB
1 SCK
RIGHT CHANNEL
LSB
Figure 3-2. I2S Digital Audio Format
4 Electrical Characteristics
Table 4-1 DC Electrical Specification (Recommended Operation Conditions):
SYMBOL DESCRIPTION MIN TYP MAX UNIT
AVDD
DVDD
VIO
T
amb
V
IL
VIH
VTH
Analog Supply Voltage 1.8 3.3 5.5 V
Digital Supply Voltage 1.8 3.3 5.5 V
Interface Supply Voltage 1.5 - 3.6 V
Ambient Temperature -20 27 +70 ℃
CMOS Low Level Input Voltage 0 0.3*DVDD
V
CMOS High Level Input Voltage 0.7*VDD DVDD V
CMOS Threshold Voltage 0.5*VDD V
Table 4-2 DC Electrical Specification (Absolute Maximum Ratings):
SYMBOL DESCRIPTION MIN TYP MAX UNIT
VIO
T
amb
I
IN
VIN
V
lna
Interface Supply Voltage -0.5 +4 V
Ambient Temperature -40 +90 °C
Input Current
Input Voltage
(1)
(1)
-0.3 VIO+0.3 V
-10 +10 mA
LNA FM Input Level -20 dBm
Notes:
1. For Pin: SCLK, SDIO, SEN, MODE
Table 4-3 Power Consumption Specification
(VDD = 1.8 to 5.5 V, TA = -25 to 85 ℃, unless otherwise specified)
SYMBOL DESCRIPTION CONDITION TYP UNIT
IA
ID
I
VIO
I
APD
I
DPD
I
VIO
Analog Supply Current ENABLE=1 18 mA
Digital Supply Current ENABLE=1 3 mA
Interface Supply Current SCLK and RCLK inactive 90
Analog Powerdown Current ENABLE=0 2
Digital Powerdown Current ENABLE=0 2
Interface Powerdown Current ENABLE=0 10
µA
µA
µA
µA
The information contained herein is the exclusive property of RDA and shall not be distributed, reproduced, or disclosed in whole or in
part without prior written permission of RDA. Page 5 of 23
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RDA Microelectronics, Inc. RDA5802E FM Tuner V1.7
5 Receiver Characteristics
Table 5-1 Receiver Characteristics
(VDD = 2.7 to 5.5 V, TA = -25 to 85 °C, unless otherwise specified)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNIT
General specifications
BAND=00 87 108 MHz
Fin
Vrf Sensitivity
Rin
Cin
IP3in
α
am
S
200
FM Input Frequency
1,2,3
LNA Input Resistance 7 150
LNA Input Capacitance 7 2 4 6 pF
Input IP34 AGCD=1 80 -
AM Suppression
1,2
Adjacent Channel Selectivity
Left and Right Audio
V
; V
AFL
AFR
Frequency Output Voltage
(Pins LOUT and ROUT)
Maximum Signal Plus Noise
(S+N)/N
α
SCS
to Noise Ratio
Stereo Channel Separation
1,2,3,5
Audio Total Harmonic
THD
α
AOI
Distortion
Audio Output L/R Imbalance
1,3,6
Audio Output Loading
RL
Resistance
Pins LNAN, LNAP, LOUT, ROUT and NC(22,23)
Pins LNAN and LNAP Input
V
com_rfin
Common Mode Voltage
Audio Output Common
V
com
Mode Voltage8
Pins NC (22, 23) Common
V
com_nc
Mode Voltage
! The NC(22, 23) pins SHOULD BE left floating.
Notes:
1. Fin=65 to 108MHz; F
2. ∆f=22.5KHz;
3. BAF = 300Hz to 15KHz, RBW <=10Hz;
4. |f2-f1|>1MHz, f0=2xf1-f2, AGC disable, Fin=76 to 108MHz;
5. PRF=60dBUV;
6. ∆f=75KHz.
7. Measured at V
8. At LOUT and ROUT pins
=1KHz; de-emphasis=75µs; MONO=1; L=R unless noted otherwise;
mod
= 1 m V, f RF = 65 to 108MHz
EMF
BAND=01 76 91 MHz
BAND=10 76 108 MHz
BAND=11 65 76 MHz
(S+N)/N=26dB 1 1.5
µV EMF
Ω
dBµV
m=0.3 40 - - dB
±200KHz
45 - dB
Volume [3:0] =1111 200 mV
55 60 - dB
35 - - dB
0.03 0.05 %
0.1 dB
Single-ended 32 - -
0
V
Ω
0.95 1. 1.05 V
Floating
V
The information contained herein is the exclusive property of RDA and shall not be distributed, reproduced, or disclosed in whole or in
part without prior written permission of RDA. Page 6 of 23
Page 7
RDA Microelectronics, Inc. RDA5802E FM Tuner V1.7
6 Serial Interface
6.1 Three-wire Interface Timing
Table 6-1 Three-wire Interface Timing Characteristics
(VDD = 2.7 to 5.5 V, TA = -25 to 85 °C, unless otherwise specified)
PARAMETER SYMBOL TEST CONDITION MIN TYP MAX UNIT
SCLK Cycle Time
SCLK Rise Time
SCLK Fall Time
SCLK High Time
SCLK Low Time
SDIO Input, SEN to SCLK↑ Setup t
SDIO Input, to SCLK↑ Hold t
SCLK↑ to SDIO Output Valid t
SEN↑ to SDIO Output High Z t
Digital Input Pin Capacitance
t
CLK
tR
tF
tHI
tLO
cdv
sdz
s
h
35 ns
50 ns
50 ns
10 ns
10 ns
10 - - ns
10 - - ns
Read 2 - 10 ns
Read 2 - 10 ns
5 pF
Figure 6-1. Three-wire Interface Write Timing Diagram
Figure 6-2. Three-wire Interface Read Timing Diagram
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part without prior written permission of RDA. Page 7 of 23
Page 8
RDA Microelectronics, Inc. RDA5802E FM Tuner V1.7
6.2 I2C Interface Timing
Table 6-2 I2C Interface Timing Characteristics
(VDD = 2.7 to 5.5 V, TA = -25 to 85 °C, unless otherwise specified)
PARAMETER SYMBOL TEST CONDITION
SCLK Frequency
SCLK High Time
SCLK Low Time
Setup Time for START Condition
Hold Time for START Condition
Setup Time for STOP Condition
SDIO Input to SCLK↑ Setup t
SDIO Input to SCLK↓ Hold t
STOP to START Time
SDIO Output Fall Time
SDIO Input, SCLK Rise/Fall Time
Input Spike Suppression
SCLK, SDIO Capacitive Loading
Digital Input Pin Capacitance
f
scl
t
high
t
low
t
su:sta
t
hd:sta
t
su:sto
su:dat
hd:dat
t
buf
t
f:out
t
r:in / tf:in
tsp
Cb
MIN TYP MAX UNIT
0 - 400 KHz
0.6 - -
1.3 - -
0.6 - -
0.6 - -
0.6 - 100 - - ns
0 - 900 ns
1.3 - 20+0.1C
20+0.1C
- - 50 ns
- - 50 pF
5 pF
- 250 ns
b
- 300 ns
b
µs
µs
µs
µs
µs
µs
Figure 6-3. I2C Interface Write Timing Diagram
Figure 6-4. I2C Interface Read Timing Diagram
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part without prior written permission of RDA. Page 8 of 23
Page 9
RDA Microelectronics, Inc. RDA5802E FM Tuner V1.7
7 Register Definition
REG BITS
00H 15:8 CHIPID[7:0]
02H 15 DHIZ
14 DMUTE
13 MONO
12 BASS
10 CLK_DIRECT_MODE
9 SEEKUP
8 SEEK
7 SKMODE Seek Mode
6:4 CLK_MODE[2:0] 000=32.768kHz
1 SOFT_RESET Soft reset.
0 ENABLE
03H 15:6 CHAN[9:0]
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part without prior written permission of RDA. Page 9 of 23
NAME FUNCTION DEFAULT
Chip ID.
Audio Output High-Z Disable.
0 = High impedance; 1 = Normal operation
Mute Disable.
0 = Mute; 1 = Normal operation
Mono Select.
0 = Stereo; 1 = Force mono
Bass Boost.
0 = Disabled; 1 = Bass boost enabled
Reference clk (32.768K,12M,…) direct input
mode.
0=clk_buffer mode;
1=clk directly input mode
Seek Up.
0 = Seek down; 1 = Seek up
Seek.
0 = Disable stop seek; 1 = Enable
Seek begins in the direction specified by
SEEKUP and ends when a channel is found with
RSSI level above SEEKTH[5:0], or the entire
band has been searched.
The SEEK bit is set low and the STC bit is set
high when the seek operation completes.
0 = wrap at the upper or lower band limit and
continue seeking
1 = stop seeking at the upper or lower band limit
001=12Mhz
101=24Mhz
010=13Mhz
110=26Mhz
011=19.2Mhz
111=38.4Mhz
If 0, not reset;
If 1, reset.
Power Up Enable.
0 = Disabled; 1 = Enabled
Channel Select.
BAND = 0
Frequency =
Channel Spacing (kHz) x CHAN+ 87.0 MHz
BAND = 1or 2
Frequency =
0x58
0
0
0
0
0
0
0
0
000
0
0
0x00
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RDA Microelectronics, Inc. RDA5802E FM Tuner V1.7
REG BITS
4 TUNE Tune
3:2 BAND[1:0] Band Select.
1:0 SPACE[1:0] Channel Spacing.
04H 14 STCIEN Seek/Tune Complete Interrupt Enable.
11 DE
9 SOFTMUTE_EN If 1, softmute enable 1
8 AFCD AFC disable.
6 I2S_ENABLED I2S bus enable
5:4 GPIO3[1:0]
3:2 GPIO2[1:0]
1:0 GPIO1[1:0]
NAME FUNCTION DEFAULT
Channel Spacing (kHz) x CHAN + 76.0 MHz
BAND = 3
Frequency =
Channel Spacing (kHz) x CHAN + 65.0 MHz
CHAN is updated after a seek operation.
0 = Disable
1 = Enable
The tune operation begins when the TUNE bit is
set high. The STC bit is set high when the tune
operation completes.
The tune bit is reset to low automatically when
the tune operation completes..
00 = 87–108 MHz (US/Europe)
01 = 76–91 MHz (Japan)
10 = 76–108 MHz (world wide)
11 = 65 –76 MHz （East Europe）
00 = 100 kHz
01 = 200 kHz
10 = 50kHz
0 = Disable Interrupt
1 = Enable Interrupt
Setting STCIEN = 1 will generate a low pulse on
GPIO2 when the interrupt occurs.
De-emphasis.
0 = 75 µs; 1 = 50 µs
If 0, afc work;
If 1, afc disabled.
If 0, disabled;
If 1, enabled.
General Purpose I/O 3.
00 = High impedance
01 = Mono/Stereo indicator (ST)
10 = Low
11 = High
General Purpose I/O 2.
00 = High impedance
01 = Interrupt (INT)
10 = Low
11 = High
General Purpose I/O 1.
0
00
00
0
0
0
0
00
00
00
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part without prior written permission of RDA. Page 10 of 23
Page 11
RDA Microelectronics, Inc. RDA5802E FM Tuner V1.7
REG BITS
05H 15 INT _MODE If 0, generate 5ms interrupt;
14:8 SEEKTH[6:0] Seek Threshold. RSSI scale is logarithmic.
7:6 LNA_PORT_SEL[1:0] LNA input port selection bit:
5:4 LNA_ICSEL_BIT[1:0] Lna working current bit:
3:0 VOLUME[3:0]
06H 12 I2s_mode_select If 0, master mode;
7:4 I2s_ws_cnt[4:0]
Only valid
in master mode
0AH 14 STC Seek/Tune Complete.
13 SF
10 ST
9:0 READCHAN[9:0] Read Channel.
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part without prior written permission of RDA. Page 11 of 23
NAME FUNCTION DEFAULT
00 = High impedance
01 = Reserved
10 = Low
11 = High
1
If 1, interrupt last until read reg0CH action
occurs.
0001000
0000000 = min RSSI
10
00: no input
01: LNAN
10: LNAP
11: dual port input
10
00=1.8mA
01=2.1mA
10=2.5mA
11=3.0mA
DAC Gain Control Bits (Volume).
0000=min; 1111=max
Volume scale is logarithmic
If 1, slave mode.
4'b1000: WS_STEP_48;
4'b0111: WS_STEP=44.1kbps;
4'b0110: WS_STEP=32kbps;
4'b0101: WS_STEP=24kbps;
4'b0100: WS_STEP=22.05kbps;
4'b0011: WS_STEP=16kbps;
4'b0010: WS_STEP=12kbps;
4'b0001: WS_STEP=11.025kbps;
4'b0000: WS_STEP=8kbps;
0 = Not complete
1 = Complete
The seek/tune complete flag is set when the seek
or tune operation completes.
Seek Fail.
0 = Seek successful; 1 = Seek failure
The seek fail flag is set when the seek operation
fails to find a channel with an RSSI level greater
than SEEKTH[5:0].
Stereo Indicator.
0 = Mono; 1 = Stereo
Stereo indication is available on GPIO3 by
setting GPIO1[1:0] =01.
BAND = 0
Frequency = Channel Spacing (kHz) x
READCHAN[9:0]+ 87.0 MHz
BAND = 1 or 2
1111
0
0000
0
0
1
8’h00
Page 12
RDA Microelectronics, Inc. RDA5802E FM Tuner V1.7
REG BITS
0BH 15:9 RSSI[6:0] RSSI.
8 FM TRUE 1 = the current channel is a station
7 FM_READY 1=ready
NAME FUNCTION DEFAULT
Frequency = Channel Spacing (kHz) x
READCHAN[9:0]+ 76.0 MHz
BAND = 3
Frequency = Channel Spacing (kHz) x
READCHAN[9:0]+ 65.0 MHz
READCHAN[9:0] is updated after a tune or seek
operation.
000000 = min
111111 = max
RSSI scale is logarithmic.
0 = the current channel is not a station
0=not ready
0
0
0
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part without prior written permission of RDA. Page 12 of 23
Page 13
RDA Microelectronics, Inc. RDA5802E FM Tuner V1.7
8 Pins Description
GND
NC
NC
GPIO1
GPIO2
GPIO3
18
AVDD
GND
24 23 22 21 20 19
1
LNAN
RFGND
LNAP
GND
GND
2
3
4
5
6
7
GND
PAD
RDA5802E
8 9 10 11 12
SEN
MODE
SCLK
SDIO
RCLK
17
GND
16
LOUT
15
ROUT
14
GND
13
DVDD
VIO
Figure 8-1. RDA5802E Top View
Table 8-1 RDA5802E Pins Description
SYMBOL PIN DESCRIPTION
GND 1,5,6,14,17,24 Ground. Connect to ground plane on PCB
LNAN,LNAP 2,4
LNA input port. For single-ended input, LNAN should
be connected to RFGND
RFGND 3 LNA ground. Connect to ground plane on PCB
Control Interface select
MODE 7
The MODE Pin is low ,I2C Interface is select.
The MODE Pin is set to VIO, SPI Interface is select.
SEN 8 Latch enable (active low) input for serial control bus
SCLK 9 Clock input for serial control bus
SDIO 10 Data input/output for serial control bus
RCLK 11 32.768KHz crystal oscillator and reference clock input
VIO 12 Power supply for I/O
AVDD 18 Power supply for analog section
ROUT,LOUT 15,16 Right/Left audio output
DVDD 14 Power supply for digital section
GPIO1,GPIO2,GPIO3
19,20,21 General purpose input/output
NC 22,23 No Connect
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part without prior written permission of RDA. Page 13 of 23
Page 14
RDA Microelectronics, Inc. RDA5802E FM Tuner V1.7
Table 8-2 Internal Pin Configuration
SYMBOL PIN DESCRIPTION
LNAN/LNAP 2/4
RCLK 11
SCLK/SDIO 9/10
GPIO1/GPIO2/GPIO3
19/20/21
SDIO\SCLK
MN1
47K
Sin
Sout
The information contained herein is the exclusive property of RDA and shall not be distributed, reproduced, or disclosed in whole or in
part without prior written permission of RDA. Page 14 of 23
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RDA Microelectronics, Inc. RDA5802E FM Tuner V1.7
9 Application Diagram
9.1 Audio Loading Resistance Larger than 32Ω & TCXO Application:
Notes:
1. J1: Common 32Ω Resistance
Headphone;
2. U1: RDA5802E Chip;
3. V1: Analog and Digital Power
19
7
Supply (1.8~5.5V);
4. FM Choke (L3 and C3) for Audio
Common and LNA Input
Common;
5. Pins NC(22, 23), Should be
Leaved Floating;
6.Set MODE to select control
interface(GND—I2C,VIO—SPI);
6. Place C6 Close to AVDD pin.
Figure 9-1. RDA5802E FM Tuner Application Diagram (TCXO Application)
9.1.1 Bill of Materials:
COMPONENT VALUE DESCRIPTION SUPPLIER
U1 RDA5802E Broadcast FM Radio Tuner RDA
J1 Common 32Ω Resistance Headphone
C2 100pF Couple CAP Murata
L3/C3 100nH/24pF LC Chock for LNA Input Murata
C4,C5 125µF Audio AC Couple Capacitors Murata
C6 24nF Power Supply Bypass Capacitor Murata
F1/F2 1.5K@100MHz FM Band Ferrite Murata
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part without prior written permission of RDA. Page 15 of 23
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RDA Microelectronics, Inc. RDA5802E FM Tuner V1.7
9.2 Audio Loading Resistance Lower than 32Ω & DCXO Application:
F1 1.5K@100MHz
J1
L3 100nH
C3 24pF
SCLK
SDIO VIO
F2
1.5K@100MHz
1
C4 125uF
C5 125uF
13
V1
24nF
C6
Notes:
1. J1: Common 32Ω Resistance
Headphone
2. U1: RDA5802E Chip
3. V1: Analog and Digital Power
Supply (1.8~5.5V)
5. Pins NC(22, 23),Should be
Leaved Floating;
6.Set MODE to select control
interface(GND—I2C,VIO—SPI);
7. Place C6 Close to AVDD pin
Figure 9-2. RDA5802E FM Tuner Application Diagram (32.768K crystal,I2C bus mode)
9.2.1 Bill of Materials:
COMPONENT VALUE DESCRIPTION SUPPLIER
U1 RDA5802E Broadcast FM Radio Tuner RDA
J1 Audio Amplifier
C4/C5 125uF Audio AC Couple Capacitors Murata
L3/C3 100nH/24pF LC Chock for LNA Input Murata
C6 24nF Power Supply Bypass Capacitor Murata
F1/F2 1.5K@100MHz FM Band Ferrite Murata
The information contained herein is the exclusive property of RDA and shall not be distributed, reproduced, or disclosed in whole or in
part without prior written permission of RDA. Page 16 of 23
Page 17
RDA Microelectronics, Inc. RDA5802E FM Tuner V1.7
10 Package Physical Dimension
Figure 10-1 illustrates the package details for the RDA5802E. The package is lead-free and
RoHS-compliant.
MIN NOM MAX
D
□
E
□
D2
E2
□
L
2.60 2.70 2.80
2.60 2.70 2.80
e
0.30 0.40 0.50
4.00 BSC
4.00 BSC
0.50 BSC
b 0.18 0.25 0.30
A
A1
A3
0.80 0.90 1.00
0.00 0.02 0.05
0.20 ref
Figure 10-2. 24-Pin 4x4 Quad Flat No-Lead (QFN)
The information contained herein is the exclusive property of RDA and shall not be distributed, reproduced, or disclosed in whole or in
part without prior written permission of RDA. Page 17 of 23
Page 18
RDA Microelectronics, Inc. RDA5802E FM Tuner V1.7
11 PCB Land Pattern
Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly
Average Ramp-Up Rate
(T
to Tp)
Smax
Preheat
-Temperature Min (T
-Temperature Max (T
-Time (t
smin
to t
Time maintained above:
-Temperature (TL)
-Time (tL)
Peak /Classification
Temperature(Tp)
smax
Figure 18.Classification Reflow Profile
3 oC/second max. 3 oC/second max.
smin
smax
)
)
)
100 oC
100 oC
60-120 seconds
183 oC
60-150seconds
See Table-II See Table-III
150 oC
200 oC
60-180 seconds
217oC
60-150 seconds
Time within 5 oC of actual
10-30 seconds 20-40 seconds
Peak Temperature (tp)
Ramp-Down Rate 6 oC/second max. 6 oC/seconds max.
Time 25 oC to Peak
6 minutes max. 8 minutes max.
Temperature
Table-I Classification Reflow Profiles
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part without prior written permission of RDA. Page 18 of 23
Page 19
RDA Microelectronics, Inc. RDA5802E FM Tuner V1.7
Package Thickness Volume mm
<350
3
Volume mm
≥350
3
＜2.5mm 240 + 0/-5 o C 225 + 0/-5 o C
≥2.5mm 225 + 0/-5 o C 225 + 0/-5 o C
Table – II SnPb Eutectic Process – Package Peak Reflow Temperatures
Package
Thickness
Volume mm3
＜350
Volume mm3
350-2000
Volume mm3
＞2000
＜1.6mm 260 + 0 o C * 260 + 0 o C * 260 + 0 o C *
1.6mm – 2.5mm 260 + 0 o C * 250 + 0 o C * 245 + 0 o C *
≥2.5mm 250 + 0 o C * 245 + 0 o C * 245 + 0 o C *
*Tolerance : The device manufacturer/supplier shall assure process compatibility up to and
including the stated classification temperature(this mean Peak reflow temperature + 0 o C. For
example 260+ 0 o C ) at the rated MSL Level.
Table – III Pb-free Process – Package Classification Reflow Temperatures
Note 1: All temperature refer topside of the package. Measured on the package body surface.
Note 2: The profiling tolerance is + 0 o C, - X o C (based on machine variation
capability)whatever
is required to control the profile process but at no time will it exceed - 5 o C. The
producer assures process compatibility at the peak reflow profile temperatures defined
in Table –III.
Note 3: Package volume excludes external terminals(balls, bumps, lands, leads) and/or non
integral heat sinks.
Note 4: The maximum component temperature reached during reflow depends on package the
thickness and volume. The use of convection reflow processes reduces the thermal
gradients between packages. However, thermal gradients due to differences in
thermal mass of SMD package may sill exist.
Note 5: Components intended for use in a “lead-free” assembly process shall be evaluated
using the “lead free” classification temperatures and profiles defined in Table-I II III
whether or not lead free.
The information contained herein is the exclusive property of RDA and shall not be distributed, reproduced, or disclosed in whole or in
part without prior written permission of RDA. Page 19 of 23
Page 20
RDA Microelectronics, Inc. RDA5802E FM Tuner V1.7
RoHS Compliant
The product does not contain lead, mercury, cadmium, hexavalent chromium, polybrominated biphenyls (PBB)
or polybrominated diphenyl ethers (PBDE), and are therefore considered RoHS compliant.
ESD Sensitivity
Integrated circuits are ESD sensitive and can be damaged by static electricity. Proper ESD
techniques should be used when handling these devices.
The information contained herein is the exclusive property of RDA and shall not be distributed, reproduced, or disclosed in whole or in
part without prior written permission of RDA. Page 20 of 23
Page 21
RDA Microelectronics, Inc. RDA5802E FM Tuner V1.7
12 Change List
REV DATE AUTHER CHANGE DESCRIPTION
V1.0 2009-03-03 ChunZhao Original Draft.
13 Notes：
1: 通过硬件电路设置芯片工作总线控制模式，详细电路如下图：
SEN
SCLK
SDIO
VIO
7
MODE
8
SEN
9
SCLK
10
SDIO
SCLK
SDIO
7
MODE
8
SEN
9
SCLK
10
SDIO
附图：I2C 总线电路接口电路 SPI 总线电路接口电路
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part without prior written permission of RDA. Page 21 of 23
Page 22
RDA Microelectronics, Inc. RDA5802E FM Tuner V1.7
14 RDA5802E 与 RDA5802 对比
1、5802E 的 0x0Ch＝5803、0x0Dh＝5804，可以通过读这两个寄存器的缺省值来区别 5800、5802 和
5802E;
2、FM 天线尽量用第 4 脚（LNAP），不要用第 2 脚（LNAN）。 5802E 的这两个输入脚电路结构是不一
样的，性能有差别；
3、需要给客户说明 5802E 的 I2C 地址有三个：0010000；0010001；1100000（测试模式）
4、RCLK 脚接 32.768K 晶体的时候，要注意尽量减小寄生电容，PCB 走线不能太长；否则容易造成
32.768K 晶体不起振现象。
5、LNAN & LANP 管脚电路做了修改，直流电平必须为 0；如果客户天线的直流电平不为 0（比如瑞
芯微的 MP3 芯片）， 则 需要加 100pF 电容隔直。
5802E 5802
ESD（静电）
5000V 2000V
I2C 缺省电平 不需要 sclk 触发 需要 sclk 下降沿触发
音量大小 大（250mV） 一般（200mV）
工作电压范围 1.8～5.5V (1.8~2V 性能略有下降)
信噪比（SNR）
灵敏度（SEN）
工作电流
RDS
57dB 54dB
-109dBm -107dBm
21.5mA 20mA
无 无
2.7~5.5V
多参考时钟 可以任意设置参考时钟（需改寄存器） 普通
I2C 口抗毛刺 有提高 一般
硬件兼容性 普通情况下，全兼容 5802
软件兼容性 普通情况下，全兼容 5802
32K 时钟输入性 对 32K 时钟电平特性要求小。如果输入时钟
信号幅度或者占空比小，可将 0x02h 寄存器
bit<10>设置成 1，这样参考时钟为直接输入模
如果 32K时钟信号幅度过小
或者占空比过小，会导致时
钟信号输入困难
式，保证可靠性
The information contained herein is the exclusive property of RDA and shall not be distributed, reproduced, or disclosed in whole or in
part without prior written permission of RDA. Page 22 of 23
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RDA Microelectronics, Inc. RDA5802E FM Tuner V1.7
15 Contact Information
RDA Microelectronics (Shanghai), Inc.
Suite 1108 Block A, e-Wing Center, 113 Zhichun Road Haidian District, Beijing
Tel: 86-10-62635360
Fax: 86-10-82612663
Postal Code: 100086
Suite 302 Building 2, 690 Bibo Road Pudong District, Shanghai
Tel: 86-21-50271108
Fax: 86-21-50271099
Postal Code: 201203
Copyright © RDA Microelectronics Inc. 2006. All rights are reserved.
Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
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part without prior written permission of RDA. Page 23 of 23
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