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RBHV7224DG
Datasheet (Supertex)
7 pgs477.75 Kb0

Datasheet RBHV7224DG Datasheet (Supertex)

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Page 1
HV7224
40-Channel Symmetric Row Driver
Ordering Information
Package Options
Device 80-Lead 64-Lead 3-Sided Die in waffle pack 80-Lead
HV7224 HV7224DG HV7224PG HV7224X RBHV7224DG
* For Hi-Rel process flows, refer to page 5-3 of the Databook.
Ceramic Gullwing Plastic Gullwing Ceramic Gullwing
Features
❏ Processed with HVCMOS® technology ❏ Symmetric row drive (reduces latent imaging
in ACTFEL displays)
❏ Output voltage up to 240V ❏ Low-power level shifting ❏ Source/Sink current 70mA (min.) ❏ Shift Register Speed 3MHz ❏ Pin-programmable shift direction (DIR, SHIFT) ❏ Hi-Rel processing available
Absolute Maximum Ratings
Supply voltage, V Supply voltage, V Logic input levels -0.5V to VDD +0.5V Continuous total power dissipation
Operating temperature range Plastic -40°C to +85°C
Storage temperature range -65°C to +150°C Lead temperature 1.6mm (1/16 inch) 260°C
from case for 10 seconds
Notes:
1. All voltages are referenced to GND.
2. For operation above 25°C ambient derate linearly to maximum operating tem- perature at 20mW/°C for plastic and at 19mW/°C for ceramic.
DD
PP
1
-0.5V to +7V
-0.5V to +260V
2
Plastic 1200mW Ceramic 1900mW
Ceramic -55°C to +125°C
General Description
The HV72 is a low-voltage serial to high-voltage parallel convert­ers with push-pull outputs. It is especially suitable for use as a symmetric row driver in AC thin-film electroluminescent (ACTFEL) displays.
When the data reset pin (DR outputs of the internal shift register to zero. At the same time, the output of the shift register will start shifting a logic high from the least significant bit to the most significant bit. The DR triggered at any time. The DIR and SHIFT pins control the direction of data shift through the device. When DIR is at logic high, DR grounded, DR Output Sequence Operation Table for output sequence. The
is the input and DR
IOA
is the input and the DR
IOB
POL and OE pins perform the polarity select and output enable function respectively. Data is loaded on the low to high transition of the clock. A logic high will cause the output to swing to V POL is high, or to GND if POL is low. All outputs will be in High­Z state if OE is at logic high. Data output buffers are provided for cascading devices.
) is at logic high, it will reset all the
IO
can be
IO
is the output. When DIR is
IOB
is the output. See the
IOA
PP
if
02/96/022
Supertex Inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability indemnification insurance agreement." Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of devices determined to be defective due to workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications, refer to the Supertex website: http://www.supertex.com. For complete liability information on all Supertex products, refer to the most current databook or to the Legal/Disclaimer page on the Supertex website.
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Page 2
Electrical Characteristics
(over recommended operating conditions of V
DC Characteristics
Symbol Parameter Min Max Units Conditions
I
DD
I
PP
I
DDQ
V
V
I I
I
SAT
Note:
1. Only one output can be turned on at a time.
VDD supply current 10 mA f High voltage supply current 2.0 mA Outputs low or High-Z
Quiescent VDD supply current 100 µA All VIN = GND or V High-level output HV
OH
Data out 4.5 V IO= -100µA
Low-level output HV
OL
Data out 0.5 V I
High-level logic input current 1.0 µAV
IH
Low-level logic input current -1.0 µAV
IL
Saturation current HV
OUT
P-Ch -80 mA N-Ch 75 mA
OUT
OUT
= 5V, V
DD
= 240V, and TA = 25°C unless noted)
PP
4.0 mA One Output High
190 V IO= -70mA
50 V IO= 70mA
= 3MHz
CLK
= 100µA
O
= V
IH
= 0V
IL
HV7224
1
DD
DD
AC Characteristics
Symbol Parameter Min Max Units Conditions
f
CLK
t
W (H/L)
t
SUD
t
HD
t
SUC
t
SUE
t
HC
t
HE
*
t
DHL
*
t
DLH
t
ONF
t
ONR
t
POW
t
OEW
* The delay is measured from the trailing edge of the clock but the data is triggered by the rising edge of the clock. There is an internal delay for the data output which is
equal to t
WH
Clock frequency 3.0 MHz Pulse width - clock high or low 150 ns Data set-up time before clock rises 50 ns Data hold time after clock rises 50 ns HV
delay from clock rises (Hi-Z to H or L) 1.0 µsCL = 330pF // RL = 10kΩ
OUT
HV
delay from Output Enable falls 600 ns CL = 330pF // RL = 10kΩ
OUT
HV
delay from clock rises (H or L to Hi-Z) 2.0 µsCL = 330pF // RL = 10kΩ
OUT
HV
delay from Output Enable rises 600 ns CL = 330pF // RL = 10kΩ
OUT
Delay time clock to data output falls 250 ns CL = 15pF Delay time clock to data output rises 250 ns CL = 15pF HV
fall time 2.0 µsCL = 330pF // RL = 10kΩ
OUT
HV
rise time 2.0 µsCL = 330pF // RL = 10kΩ
OUT
POL pulse width 3.0 µs Output Enable pulse width 3.0 µs Slew rate, VPP or GND 45 V/µs One active output driving
4.7nF load
. Therefore the delay is measured from the trailing edge of the clock.
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Page 3
Recommended Operating Conditions
Symbol Parameter Min Max Units
V
DD
V
PP
V
IH
V
IL
f
CLK
I
O
T
A
I
OD
Notes:
†
Output will not switch at VPP = 0V.
Power-up sequence should be the following:
1. Connect ground.
2. Apply V
3. Set all inputs (Data, CLK, Enable, etc.) to a known state.
4. Apply V
5. The V
Power-down sequence should be the reverse of the above.
.
DD
.
PP
should not drop below VDD or float during operation.
PP
Logic supply voltage 4.5 5.5 V High voltage supply High-level input voltage 0.7 V Low-level input voltage 0 0.2V
†
0 240 V
DD
V
DD
DD
Clock frequency 3 MHz High voltage output current ±70 mA Operating free-air temperature Plastic -40 +85 °C
Ceramic -55 +125 °C
Allowable pulse current through output diode ±300 mA
HV7224
V V
Input and Output Equivalent Circuits
V
DD
Input
GND (Logic)
Logic Inputs
V
DD
GND (Logic)
Logic Data Output
Data Out
V
PP
GND (Power)
High Voltage Outputs
HV
OUT
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Page 4
Switching Waveforms
CLK
t
Data Reset Input
(DR
/DR
/DR
IOB
IOB
)
)
IOA
Data Reset Output
(DR
IOA
SUD
50%
l/f
CLK
t
WH
50% 50%
t
HD
Data Valid
50%
t
DLH
Data Valid
t
WL
50%
50% 50%
t
DHL
HV7224
50%
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
HV
OUT
(POL = H)
HV
OUT
(POL = L)
POL
OE
HV
OUT
HV
OUT
High Impedance
t
SUC
t
SUC
50%
50%
t
SUE
t
SUE
10%
90%
10%
90%
t
90%
10%
t
ONF
t
90%
10%
t
ONF
ONR
t
POW
t
ONR
OEW
50%
50%
t
HE
t
HE
t
HC
90%
V
OH
High ImpedanceHigh Impedance
10%
t
HC
90%
V
OL
V
IH
V
IL
V
IH
V
IL
V
OH
High Impedance
10%
V
OL
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Page 5
Functional Block Diagram
V
PP
OE
Polarity
V
DD
D
IOA
SHIFT
LT
HV7224
P
HV
1
OUT
N
CLK
LT
S/R
DIR
LT
D
IOB
GND
LT = Level Translator
Function Table
I/O Relations
CLK DIR S/R Data POL OE HV Outputs O/P HIGH X X H H L H O/P OFF X X L X L HIGH-Z O/P LOW X X H L L L O/P OFF X X X X H All O/P HIGH-Z
Notes: H = logic high level, L = logic low level, X = irrelevant Data input (DRIO) loaded on the low-to-high transistion of the clock. Only one active output can be set at a time.
Inputs
HV
HV
OUT
OUT
2
40
Output Sequence Operation Table
DIR Shift Data Reset In Data Reset Out HV
LL DR
HL DR
LH DR
HH DR
* Reference to package outline or chip layout drawing.
1.DR
is DR
2. DR
IOA
IOB
delayed by 40 clock pulses.
IOB
is DR
delayed by 40 clock pulses.
IOA
IOB
IOA
IOB
IOA
DR DR DR DR
IOA
IOB
IOA
IOB
1
2
1
2
# Sequence Direction* Option (See pin-out on P. 12-158)
OUT
40 → 1A
1 → 40 A 20 → 1 → 40 → 21 B 21 → 40 → 1 → 20 B
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Page 6
Pin Configurations
HV7224
HV72 Option A: Pin Function Pin Function
1HV 2HV 3HV 4HV 5HV 6HV 7HV 8HV 9HV 10 HV 11 HV 12 HV 13 HV 14 HV 15 HV 16 HV 17 HV 18 HV 19 HV 20 HV 21 V 22 N/C 54 HV 23 GND (Power) 55 HV 24 GND (Logic) 56 HV 25 DIR 57 HV 26 V 27 CLK 59 HV 28 N/C 60 HV 29 SHIFT 61 HV 30 N/C 62 HV 31 DR 32 N/C 64 HV
Note:
Pin designation for DIR H/L, SHIFT = L.
Pins 65–80 are NC (ceramic only).
1/40 33 N/C
OUT
2/39 34 DR
OUT
3/38
OUT
4/37 36 NC
OUT
5/36 37 POL
OUT
6/35 38 N/C
OUT
7/34 39 V
OUT
8/33 40 N/C
OUT
9/32 41 GND (Logic)
OUT
10/31 42 GND (Power)
OUT
11/30 43 N/C
OUT
12/29 44 V
OUT
13/28 45 HV
OUT
14/27 46 HV
OUT
15/26 47 HV
OUT
16/25 48 HV
OUT
17/24 49 HV
OUT
18/23 50 HV
OUT
19/22 51 HV
OUT
20/21 52 HV
OUT
PP
DD
IOA
Example: For DIR = H, pin 1 is HV
35 OE
53 HV
58 HV
63 HV
For DIR = L, pin 1 is HV
IOB
DD
PP
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
21/20 22/19 23/18 24/17 25/16 26/15 27/14 28/13 29/12 30/11 31/10 32/9 33/8 34/7 35/6 36/5 37/4 38/3 39/2 40/1
OUT
OUT
1.
40.
HV72 Option B: Pin Function Pin Function
1HV 2HV 3HV 4HV 5HV 6HV 7HV 8HV 9HV 10 HV 11 HV 12 HV 13 HV 14 HV 15 HV 16 HV 17 HV 18 HV 19 HV 20 HV 21 V 22 N/C 54 HV 23 GND (Power) 55 HV 24 GND (Logic) 56 HV 25 DIR 57 HV 26 V 27 CLK 59 HV 28 N/C 60 HV 29 SHIFT 61 HV 30 N/C 62 HV 31 DR 32 N/C 64 HV
Note:
Pin designation for DIR L/H, SHIFT = H.
Pins 65–80 are NC (ceramic only).
20/21 33 N/C
OUT
19/22 34 DR
OUT
18/23
OUT
17/24 36 N/C
OUT
16/25 37 POL
OUT
15/26 38 N/C
OUT
14/27 39 V
OUT
13/28 40 N/C
OUT
12/29 41 GND (Logic)
OUT
11/30 42 GND (Power)
OUT
10/31 43 N/C
OUT
9/32 44 V
OUT
8/33 45 HV
OUT
7/34 46 HV
OUT
6/35 47 HV
OUT
5/36 48 HV
OUT
4/37 49 HV
OUT
3/38 50 HV
OUT
2/39 51 HV
OUT
1/40 52 HV
OUT
PP
DD
IOA
Example: For DIR = L, pin 1 is HV
35 OE
DD
PP
53 HV
58 HV
63 HV
For DIR = H, pin 1 is HV
IOB
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
40/1 39/2 38/3 37/4 36/5 35/6 34/7 33/8 32/9 31/10 30/11 29/12 28/13 27/14 26/15 25/16 24/17 23/18 22/19 21/20
OUT
OUT
20.
21.
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Page 7
Package Outline
HV7224
24
1
Index
25
40
64
41
top view
3-sided Plastic 64-pin Gullwing Package
64
65
Index
80
1
top view
80-pin Ceramic Gullwing Package
41
40
25
24
©2002 Supertex Inc. All rights reserved. Unauthorized use or reproduction prohibited.
02/06//02
1235 Bordeaux Drive, Sunnyvale, CA 94089
TEL: (408) 744-0100 • FAX: (408) 222-4895
7
www.supertex.com
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