R485-Type Lightwave Receiver with Clock
Recovery for 2.488 Gbits/s Applications
■
Agere Systems Inc. Reliability and Qualification
Program for built-in quality
■
SONET/SDH compatible for OC-48/STM-16 data
rate
Applications
■
Telecommunications
— Inter- and intraoffice SONET/SDH
— Subscribe r loo p
— Metropolitan area networks
Advance Data Sheet, Rev. 1
October 2001
Manufactured in a low-profile, 24-pin package, the R485-Type
Receiver features either an aval anche or PIN photodetector, a
transimpedance amplifier , a limiting ampli fier, and a clock and
data recovery IC.
Features
■
Multisourced footprint
■
Internal APD bias supply
■
Differential data and clock outputs
■
APD and PIN versions
■
Typical sensitivity:
—APD, –32 dBm
—PIN, –23 dBm
■
Operation at 1.3 µm or 1.55 µm
■
TTL link status flag
■
Wide operating case temperature range:
—APD, 0 °C to +70 °C
—PIN, –40 °C to +85 °C
■
Space-saving, self-contained, 24-pin DIP
■
High-speed data communications
Description
The R485-Type 2.5 Gbits/s lightwave receiver is
designed for use in SONET OC-48 and synchronous
digital hierarchy (SDH) STM-16 telecommunications
applications and high-speed data communications
applications. The receiver converts received optical
signals in the range of 1.2 µm to 1.6 µm wavelength
into differential data and clock outputs. The receiver
consists of either InGaAs APD or PIN photodetector
(depending on model selected), a transimpedance
amplifier, a limiting amplifier, and a clock and data
recovery IC (CDR). The CDR uses PLL technology to
extract the clock signal from the converted optical
signal. A TTL compatible link status flag signal indicates when there is a loss of optical signal.
The receiver is manufactured in a low-profile, pigtailed, 24-pin plastic DIP package. It requires a single, +5.0 V power supply. The APD version has the
added benefit of containing the high-voltage supply
internal to the receiver. This internal supply also provides the necessary temperature compensation for
the APD.
Page 2
R485-Type Lightwave Receiver with Clock
Recovery fo r 2.48 8 Gbits/s Appl ica ti ons
Advance Data Sheet, Rev. 1
October 2001
Flag Output
When the incoming optical signal falls below the linkstatus switching threshold, the FLAG output is asserted
and the FLAG output logic level changes from a TTL
low to a TTL high.
Pin Information
Table 1. Pin Information
PinNamePinName
1NIC24NUC*
2NUC*23NUC*
3LOS Flag
†
22V
CC
4Ground21NUC*
5CLOCK
20Ground
6CLOCK19Ground
7Ground18NIC
8V
CC
17Ground
9Ground16Ground
10DATA15Ground
11DATA
12Ground13DTV/NIC
* Pins designated as no user connect (NUC) are connected inter-
nally. The user should not make any connections to these pins.
† The loss of signal (LOS) FLAG output is a logic level that indicates
the presence or absence of a minimum acceptable level of optical
input. A TTL logic HIGH indicates the absence of a valid optical
input signal.
‡ This pin is not internally connected if the amplitude decision
threshold (DTV) is not made adjustable.
14Ground
‡
Handling Precautions
The R485-Type receiver is manufactured with a
39 in. ± 4 in. (100 cm ± 10 cm) single-mode fiber pigtail
with a 900 µm OD PVC outer jacket. Both SC and FC-
PC connectors are offered on standard versions. Other
optical connector options are available on special
order. Please contact an Agere Systems Account Manager for availability and ordering information.
Receiver Processing
The R485-Type receiver devices can withstand normal
wave soldering processes. The complete receiver module is not hermetically sealed; therefore, it should not
be immersed in, or sprayed with, any solutions. The
optical connector process cap deformation temperature
is 85 °C. The receiver pins can be wave soldered at
250 °C for 10 seconds.
Electrostatic Discharge
CAUTION: This device is susceptible to damage as
a result of electrostatic discharge (ESD).
Take proper precautions during both
handling and testing. Follow guidelines
such as JEDEC Publication No. 108-A
(Dec. 1988).
Although protection circuitry is designed into the
device, take proper precautions to avoid exposure to
ESD .
Agere employs a human-body model HBM) for ESDsusceptibility testing and protection design evaluation.
ESD voltage thresholds are dependent on the critical
parameters used to define the model. A standard HBM
(resistance = 1.5 kΩ, capacitance = 100 pF) is widely
used and, therefore, can be used for comparison purposes.
Installation Considerations
Although the receiver has been designed with ruggedness in mind, care should be used during handling.
The optical connector should be kept free from dust.
The optical connector process cap should be kept in
place as a dust cover when the device is not connected
to a cable. If contamination is present on the optical
connector, the use of canned air with a extension tube
should remove any loose debris. Other cleaning procedures are outlined in the
blies
Technical Note (TN95-010LWP).
The cable should be handled conservatively with no
excessive axial pulling or lateral tugging.
Cleaning Fiber Optic Assem-
The minimum fiber bending radius is 1.5 inches
(38 mm).
2Agere Systems Inc.
Page 3
Advance Data Sheet, Rev. 1
October 2001
R485-Type Lightwave Receiver with Clock
Recovery for 2.488 Gbits/s Applications
Absolute Maximum Ratings
Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess
of those given in the operational sections of the data sheet. Exposure to absolute maximum ratings for extended
periods can adversely affect device reliability.
ParameterSymbolMinMaxUnit
Operating Case Temperature Range:
APD
PIN
Storage TemperatureT
C
T
C
T
stg
0
–40
70
85
–4085°C
Optical Input Power—Biased:
APD
PIN
Supply VoltagesV
IN
P
IN
P
CC
—
—
0
8
06.5V
Lead Soldering Temperature/Time——250/10°C/s
°C
°C
dBm
dBm
Characteristics
Table 2. Optical Characteristics
–10
At 1.3 µm wavelength and 1 x 10
ParameterSymbolMin
Measured Average Sensitivity:
APD
PIN
Maximum Input Power:
APD
PIN
Link Status Switching Threshold
Decreasing Light Input:
APD
PIN
Flag Response Timet
Flag Hysteresis—1.2——dB
Optical Reflectance:
Single-mode Fiber
Multimode Fiber
* Over operating temperature range and at end of life.
†Typical values at room temperature and beginning of life.
BER with 223 – 1 NRZ pseudorandom data.
Typ
–32
–23
—
—
–40
–27
MIN
P
MIN
P
MAX
P
MAX
P
LSTD
LSTD
FLAG
*
—
—
–8
0
–45
–34
3—1000µs
—
—
—
—
—
†
Max
*
–30
–21
—
—
–35
–24
–27
–14
Unit
dBm
dBm
dBm
dBm
dBm
dBm
dB
dB
Agere Systems Inc.3
Page 4
R485-Type Lightwave Receiver with Clock
Recovery fo r 2.48 8 Gbits/s Appl ica ti ons
Advance Data Sheet, Rev. 1
October 2001
Characteristics
(continued)
Table 3. Electrical Characteristics
ParameterSymbolMinTyp
*
MaxUnit
Bit Rate—2488.072488.322488.57Mbits/s
dc Power Supply VoltagesV
CC
4.755.05.25 V
Power Consumption——1.32.0W
Output Data/Clock Voltage:
Single Output
Differential Output
Output Flag Voltage:
High
Low
Clock/Data Alignment (see Figure 1)t
†
SV
DV
‡
FOH
V
FOL
V
CDA
0.3
0.6
2.5
0
0.4
0.8
5.0
0.2
1.0
2.0
V
0.8
CC
Vp-p
Vp-p
V
V
—0±40ps
Clock Duty Cycle—455055%
Jitter GenerationJ
Jitter Transfer (see Figure 2)J
Jitter Tolerance (see Figure 3)
* Typical values measured at room temperature and beginning of life.
†Measured with a 50 Ω to ground. Outputs must be ac-coupled (see Figure 2).
‡TTL output.
G
P
—0.005<0.01Ul rms
——<0.1dB
Telcordia Technologies
™ GR-253-Core and ITU-T G.958 Compliant
4Agere Systems Inc.
Page 5
Advance Data Sheet, Rev. 1
October 2001
Characteristic Curves
DATA
CLOCK50%
R485-Type Lightwave Receiver with Clock
Recovery for 2.488 Gbits/s Applications
CLOCK/DATA ALIGNMENT
1-1313(F)
Figure 1. Clock/Data Alignment
10
0
–10
(dB)
–20
–30
1
101001k10k100k1M10M
(Hz)
Figure 2. Jitter Transfer
100
10
1
(UIp-p)
0.1
0.01
0.001
0.11101001k10k100k1M10M
(Hz)
1-1127(F)
1-1128(F)
Figure 3. Jitter Tolerance
Agere Systems Inc.5
Page 6
R485-Type Lightwave Receiver with Clock
Recovery fo r 2.48 8 Gbits/s Appl ica ti ons
Qualification and Reliability
Advance Data Sheet, Rev. 1
October 2001
The R485-type receiver is scheduled to complete the following qualification tests to meet the intent of
Technologies
Table 4. R485 Qualification Information
Mechanical Shock MIL-STD-883
Sine VibrationMIL-STD-883
Thermal ShockMIL-STD-883
Solder abilityMIL-STD-8 83
Integrity
Solvent
Resistance
Fiber PullGR-468-CORE
Acceleratin g
(HTOB)
High T emperature
Storag e
Temperature
Cycling
Temperature
Humidity Bias
Internal Water
GR-468-CORE.
TestReferenceConditions
Condition B
Method 2002
Method 2007
Method 1011
Method 2003
Lead
Aging
Vapor
ESDGR-468-CORE
MIL-STD-883
Method 2004
MIL-STD-883
Method 2015
Table 6
MIL-STD-883
Method 1005
GR-468-CORE
Table 6
GR-468-CORE
Section 5.20
GR-468-CORE
Table 6
MIL-STD-883
Method 1018
Section 5.22
5 times/axis
500 G, 1 ms
Condition A
20 G, 20 Hz—2000 Hz
4 min./cycle
4 cycles/axis
∆T = 100 °CR485
(Package Supplier Test)———Qualified by
(Package Supplier Test)———Qualified by
(Package Supplier Test)———Qualified by
1 kg; 3 times; 5 sR485
85 °C under bias,
2000 hours
85 °C storage,
2000 hours
–40 °C to +85 °C
100 Cycles for Pass/Fail
85 °C/85% RH
1000 hours
5000 ppm Water VaporR485
Human-Body ModelR485
Code
Type
R485
R480
R485
R480
R480
R480
R485
R480
R485
R480
R485
R480
R485
R480
R480
R4806 Pieces
Sample
Size
11
Pieces
11
Pieces
11
Pieces
11
Pieces
25
Pieces
11
Pieces
11
Pieces
11
Pieces
11
Pieces
Pass/Fail CriteriaNote
Change in Receiver
Sensitivity: –1.5 dB
Change in Receiver
Sensitivity: –1.5 dB
Physical Attributes
and Leak Check
Change in Receiver
Sensitivity: –1.5 dB
Change in Receiver
Sensitivity: –1.5 dB
Change in Receiver
Sensitivity: –1.5 dB
Change in Receiver
Sensitivity: –1.5 dB
Change in Receiver
Sensitivity: –1.5 dB
Change in Receiver
Sensitivity: –1.5 dB
Threshold
Minimum: 500 V
Telcordia
Qualified by
T48/P172
Qualified by
T48/P172
Qualified by
T48/P172
T48
T48
T48
Qualified by
P172
Qualified by
T48/P172;
Refer to
Chip Data
Qualified by
T48/P172
Qualified by
T48/P172
Qualified by
T48/P172
Qualified by
T48/P172
—
6Agere Systems Inc.
Page 7
Advance Data Sheet, Rev. 1
October 2001
R485-Type Lightwave Receiver with Clock
Recovery for 2.488 Gbits/s Applications
PWB Layout Guidelines
■
The data and clock outputs are designed to drive 50 Ω loads.
■
Clock and data output traces must be controlled-impedance lines and the termination impedance must match
the line impedance. Avoid 90° bends in the traces. Paired lines (i.e., DATA and DATA
■
Data and clock output lines should be as short and straight as possible and should be shielded from noise
sources to prevent noise from feeding back into the receiver.
■
Use high-quality multilayer printed-wiring boards. A ground plane should occupy the area directly beneath the
receiver.
1 µH
+
4, 7, 9, 12,
14—17, 19, 20
8, 22
0.1 µF
NOTE 2
CC
V
2.2 µF15 µF
) must be equal in length.
+5 V
50 Ω TRANSMISSION
1
NIC
0.1 µF
3
LOS (FLAG)
0.1 µF
Note 1: Data and clock outputs must be ac-coupled on customer board. Use a 0.1 µF chip capacitor with a low ESR. For optimum receiver per-
formance, all four outputs must be terminated in equivalent loads, even if some of the outputs are not being used.
CC
Note 2: The 0.1 µF V
the appropriate power supply leads and should provide a low inductance path to the ground plane.
power supply bypass capacitors should be high-quality, low ESR chip capacitors that are located as close as possible to
CLOCK
CLOCK
DATA
DATA
5
6
10
11
LINE (4X)
0.1 µF
NOTE 1
50
Ω
1-934(F)xxx
Figure 4. Biasing and Interfacing to the R485-Type 2.5 Gbits/s Receiver
Agere Systems Inc.7
Page 8
R485-Type Lightwave Receiver with Clock
Recovery fo r 2.48 8 Gbits/s Appl ica ti ons
Outline Diagrams
Dimensions are in inches and (millimeters).
Advance Data Sheet, Rev. 1
October 2001
0.014
(0.36)
0.122
(3.10)
0.495
(12.57)
0.018
(0.48)
1324
121
BOTTOM VIEW
2.305
(58.55)
0.100
(2.54)
1.100
(27.94)
0.710
(18.03)
0.950
(24.13)
0.144
(3.36)
0.350
(8.89)
1.000
(25.40)
1.400
(35.56)
1-999(F)
8Agere Systems Inc.
Page 9
Advance Data Sheet, Rev. 1
October 2001
R485-Type Lightwave Receiver with Clock
Recovery for 2.488 Gbits/s Applications
Ordering Information
Table 5. Ordering Information for the R485-Type Receiver
R485-Type Lightwave Receiver with ClockRecovery for 2.488 Gbits/s Applications
Advance Data Sheet, Rev.1
October 2001
Telcordia Technologies
For additional information, contact your Agere Systems Account Ma na ger or the following:
INTERNET:
E-MAIL:
N. AMERICA: Agere Systems Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18109-3286
ASIA:Agere Systems Hong Kong Ltd., Suites 3201 & 3210-12, 32/F, Tower 2, The Gateway, Harbour City, Kowloon
EUROPE:
Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application.