Datasheet R2J20656ANP Datasheet (Renesas)

Preliminary Datasheet

R2J20656ANP

R07DS0201EJ0100

Rev.1.00

Integrated Driver - MOS FET (DrMOS)

Jan 25, 2011

Description

The R2J20656ANP multi-chip module incorporates a high-side MOS FET, low-side MOS FET, and MOS-FET driver
in a single QFN package. The on and off timing of the power MOS FET is optimized by the built-in driver, making this
device suitable for large-current buck converters. The chip also incorporates a high-side bootstrap switch, eliminating
the need for an external SBD for this purpose.

Features

 Compliant with Intel 6  6 DrMOS Specification.
 Built-in power MOS FET suitable for Notebook, Desktop, Server application.
 Low-side MOS FET with built-in SBD for lower loss and reduced ringing.
 Built-in driver circuit which matches the power MOS FET
 Built-in tri-state input function which can support a number of PWM controllers
 High-frequency operation (above 1 MHz) possible
 VIN operating-voltage range: 27 Vmax
 Large average output current (Max. 3 5 A)
 Achieve low power dissipation
 Controllable driver: Remote on/off
 Zero current detection for a diode emulation operation
 Double thermal protection: Thermal Warning & Thermal Shutdown
 Built-in bootstrapping Switch
 Small package: QFN40 (6 mm  6 mm  0.95 mm)
 Pb-free/Halogen-Free

Outline

THWN

DISBL#

ZCD_EN#

PWM

Integrated Driver-MOS FET (DrMOS)

QFN40 package 6 mm × 6 mm

VINGHBOOTVCIN

MOS FET Driver

CGND VDRV GL PGND

VSWH

110

40

Driver
Pad

Low-side MOS Pad

31

30 21

(Bottom view)

High-side
MOS Pad

11

20

R07DS0201EJ0100 Rev.1.00 Page 1 of 15
Jan 25, 2011

R2J20656ANP Preliminary

Block Diagram

Driver Chip

THWN

DISBL#

ZCD_EN#

PWM

THWN THDN

2 μA

CGND

CGND

VCIN

160 k

VCIN

Input Logic
(TTL Level)
(3 state in)

Zero
Current
Det.

VCIN

UVL

VDRV

Level Shifter

Overlap
Protection.
& Logic

BOOT GH

Boot

SW

VDRV

VIN

High Side
MOS FET

20 k

VSWH

Low Side
MOS FET

35 k

PGND

GLCGND

Notes: 1. Truth table for the DISBL# pin 2. Truth table for the ZCD_EN# pin

DISBL# Input Driver Chip Status

"L" Shutdown (GL, GH = "L")
"Open" Shutdown (GL, GH = "L")
"H" Enable (GL, GH = "Active")

ZCD_EN# Input Driver Chip Status

"L" "Diode Emulation Mode"
"Open"

"Continuous Conduction
Mode"

"H"

"Continuous Conduction
Mode"

3. Output signal from the UVL block 4. Output signal from the THWN block

VHVL

For active

VCIN

Thermal Warning
Logic Level

"H"

"L"

Normal
operating

Thermal
Warning

T

(°C)

IC

TwarnHTwarnL

UVL output
Logic Level

"H"

For shutdown

"L"

5. Truth table for the THDN block

Driver IC Temp. Driver Chip Status

< 150°C Enable (GL, GH = "Active")
> 150°C

Shutdown (GL, GH = "L")
(latch-off)

R07DS0201EJ0100 Rev.1.00 Page 2 of 15
Jan 25, 2011

R2J20656ANP Preliminary

Pin Arrangement

VIN

VIN

VIN

VSWHGHCGND

1098765432

11

VIN PWM

12

VIN

13

VIN

14

VIN

VSWH

PGND
PGND
PGND
PGND
PGND VSWH

15
16
17
18
19
20

VIN

VSWH

21 22 23 24 25 26 27 28 29 30

PGND

PGND

PGND

PGND

PGND

PGND

BOOT

VDRV

CGND

PGND

PGND

VCIN

VSWH

(Top view)

Note: All die-pads (three pads in total) should be soldered to PCB.

Pin Description

ZCD_EN#

1

40
39
38
37
36
35
34
33
32
31

VSWH

DISBL#
THWN
CGND
GL
VSWH
VSWH
VSWH
VSWH

Pin Name Pin No. Description Remarks

ZCD_EN# 1 Zero current detection enable

When asserted "L" signal, zero crossing

detection is enabled
VCIN 2 Control input voltage (+5 V input) Driver Vcc input
VDRV 3 Gate supply voltage (+5 V input) 5 V gate drive
BOOT 4 Bootstrap voltage pin To be supplied +5 V through internal switch
CGND 5, 37, Pad Control signal ground Should be connected to PGND externally
GH 6 High-side gate signal Pin for monitor
VIN 8 to 14, Pad Input voltage
VSWH 7, 15, 29 to 35, Pad Phase output/Switch output
PGND 16 to 28 Power ground
GL 36 Low-side gate signal Pin for monitor
THWN 38 Thermal warning Thermal warning when over 115°C
DISBL# 39 Signal disable

Disabled when DISBL# is "L".

This Pin is pulled low when internal IC over the

thermal shutdown level, 150°C.
PWM 40 PWM drive logic input 5 V logic input

R07DS0201EJ0100 Rev.1.00 Page 3 of 15
Jan 25, 2011

R2J20656ANP Preliminary

Absolute Maximum Ratings

(Ta = 25°C)

Item Symbol Rating Units Note

Pt(25) 25 Power dissipation
Pt(110) 8

Average output current Iout 35 A

VIN(DC) –0.3 to +27 2 Input voltage
VIN(AC) 30

Supply voltage & Drive voltage VCIN & VDRV –0.3 to +6 V 2

VSWH(DC) 27 2 Switch node voltage
VSWH(AC) 30
VBOOT(DC) 32 2 BOOT voltage
VBOOT(AC) 36

I/O voltage

THWN/THDN current Ithwn, Ithdn 0 to 1.0 mA
Operating junction temperature Tj-opr –40 to +150 °C
Storage temperature Tstg –55 to +150 °C
Notes: 1. Pt(25) represents a PCB temperature of 25°C, and Pt(110) represents 110C.

2. Rated voltages are relativ e to voltages on the CGND and PGND pins.

3. For rated current, (+) indicates inflow.

4. The specification values indicated "AC" are limited within 10 ns.

5. VCIN + 0.3 V < 6 V

Vpwm, Vdisble,
Vlsdbl, Vthwn

–0.3 to VCIN + 0.3 V 2, 5

W 1

V

2, 4

V

2, 4

V

2, 4

Safe Operating Area

45
40
35
30
25
20

VOUT = 1.3 V

15

VIN = 12 V

10

VCIN = 5 V
L = 0.45 μH

Average Output Current (A)

5

Fsw = 1 MHz

0

0 25 50 75 100 125 150 175

PCB Temperature (°C)

R07DS0201EJ0100 Rev.1.00 Page 4 of 15
Jan 25, 2011

R2J20656ANP Preliminary

Recommended Operating Condition

Item Symbol Rating Units Note

Input voltage VIN 4.5 to 22 V
Supply voltage & Drive voltage VCIN & VDRV 4.5 to 5.5 V

Electrical Characteristics

(Ta = 25°C, VCIN = 5 V, VDRV = 5 V, VSWH = 0 V, unless otherwise specified)

Item Symbol Min Typ Max Units Test Conditions

Supply

PWM
input

DISBL#
input

ZCD_EN#

Thermal
warning

Thermal
shutdown

Note: 1. Reference values for design. Not 100% tested in production.

VCIN start threshold VH 4.1 4.3 4.5 V
VCIN shutdown threshold VL 3.6 3.8 4.0 V
UVLO hysteresis dUVL — 0.5 — V VH – VL
VCIN operating current I

— 49 — mA

CIN

f

PWM

= 1 MHz,

Ton_pwm = 120 ns

VCIN disable current I

— — 150 A

CIN-DISBL

DISBL# = 0 V,

PWM = ZCD_EN# = Open
PWM input high level V
PWM input low level V
PWM input resistance R
PWM input tri-state range V
Shutdown hold-off time t
Enable level V
Disable level V
Input current I
THDN on resistance R

4.0 — — V 5.0 V PWM interface

H-PWM

— — 0.8 V

L-PWM

6.5 12.5 25 k PWM = 1 V

IN-PWM

1.5 — 3.2 V 5.0 V PWM interface

IN-tri

HOLD-OFF

ENBL
DISBL

DISBL

THDN

1

*

— 150 — ns

2.0 — — V
— — 0.8 V

— 2.0 5.0 A DISBL# = 1 V

*1 0.2 0.5 1.0 k DISBL# = 0.2 V

ZCD disable level Vzcddisbl 2.0 — — V
ZCD enable level Vzcden — — 0.8 V
Input current Izcden –52 –25 –12 A ZCD_EN# = 1 V
Warning temperature T
Temperature hysteresis T
THWN on resistance R
THWN leakage current I
Shutdown temperature Tstdn *

*1 100 115 130 °C Driver IC temperature

THWN

*1 — 15 — °C

HYS

*1 0.2 0.5 1.0 k THWN = 0.2 V

THWN

— — 1.0 A THWN = 5 V

LEAK

1

130 150 — °C Driver IC temperature

R07DS0201EJ0100 Rev.1.00 Page 5 of 15
Jan 25, 2011

R2J20656ANP Preliminary

Typical Application

4.5 to 22 V
+5 V

PWM

Control

Circuit

PWM1

PWM2

PWM3

PWM4

VCIN

THWN

DISBL#

ZCD_EN#

PWM

CGND GL

VCIN

THWN

DISBL#

ZCD_EN#

PWM

CGND GL

VCIN

THWN

DISBL#

ZCD_EN#

PWM

CGND GL

BOOT

R2J20656

ANP

BOOT GHVDRV

R2J20656

ANP

BOOT

R2J20656

ANP

GHVDRV

VIN

VSWH

PGND

VIN

VSWH

PGND

+1.3 V

GHVDRV

VIN

VSWH

Power GND Signal GND

PGND

VCIN

THWN

DISBL#

ZCD_EN#

PWM

CGND GL

BOOT

R2J20656

ANP

GHVDRV

VIN

VSWH

PGND

R07DS0201EJ0100 Rev.1.00 Page 6 of 15
Jan 25, 2011

R2J20656ANP Preliminary

Pin Connection

+5 V

(4.5 to 22 V)

10 μF × 4

VIN

PGND

0.1 μF

0 to 10 Ω

10 9 8 7 654321

11
12
13
14

VIN

15

VSWH GL

16

PGND

17
18
19
20

VIN

VIN

PAD

R2J20656ANP

GH

VSWH

VSWH

PAD

BOOT

CGND

CGND

PAD

VDRV

PGND

21 22 23 24 25 26 27 28 29 30

1.0 μF

VCIN

CGND

VSWH

VSWH

CGND

ZCD_EN#able Signal INPUT

40
39

ZCD_EN#

38
37
36

35
34
33
32
31

CGND

PWM
DISBL#
THWN

0.45 μH

PWM INPUT

10 kΩ

+5 V

10 kΩ

+5 V

Thermal Shutdown

Thermal Warning

Vout

Power GND Signal GND

PGND

PGND

R07DS0201EJ0100 Rev.1.00 Page 7 of 15
Jan 25, 2011

R2J20656ANP Preliminary

Test Circuit

I

IN

Vinput

Vcont

5 V pulse

A

V

V

IN

I

CIN

A

V

V

CIN

VCIN

DISBL#

BOOT

VIN

R2J20656ANP

VDRV
ZCD_EN#

PWM

CGND

GH

VSWH

PGND

GL

Electric
load

I

O

Note: P

= IIN × VIN + I

IN

P

= IO × V

OUT

Efficiency = P
P

(DrMOS) = PIN – P

LOSS

Ta = 27°C

O
OUT

CIN

/ P

× V

IN

CIN

OUT

Averaging
circuit

Average Output Voltage

V

V

O

R07DS0201EJ0100 Rev.1.00 Page 8 of 15
Jan 25, 2011

R2J20656ANP Preliminary

Typical Data

Power Loss vs. Output Current

9

VIN = 12 V
VCIN = VDRV = 5 V

8

VOUT = 1.3 V
f

7

= 600 kHz

PWM

L = 0.45 μH

6
5
4
3

Power Loss (W)

2
1
0

0 5 10 15 20 25 30 35

Output Current (A)

Power Loss vs. Output Voltage

1.7

VIN = 12 V
VCIN = VDRV = 5 V

1.6

f

= 600 kHz

PWM

L = 0.45 μH

1.5

IOUT = 25 A

1.4

Power Loss vs. Input Voltage

1.7

VCIN = VDRV = 5 V
VOUT = 1.3 V

1.6

f

= 600 kHz

PWM

L = 0.45 μH

1.5

IOUT = 25 A

1.4

1.3

1.2

@ VIN = 12 V

1.1

Normalized Power Loss

1.0

0.9

0.8
4 6 8 10 2012 14 2216 18

Input Voltage (V)

Power Loss vs. Switching Frequency

1.7

VIN = 12 V
VCIN = VDRV = 5 V

1.6

VOUT = 1.3 V
L = 0.45 μH

1.5

IOUT = 25 A

1.4

1.3

1.2

1.1

@ VOUT = 1.3 V

Normalized Power Loss

1.0

0.9

0.8

0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 4.4
Output Voltage (V)

1.3

= 600 kHz

1.2

PWM

1.1

@ f

Normalized Power Loss

1.0

0.9

0.8
250 500 750 1000 1250

Switching Frequency (kHz)

R07DS0201EJ0100 Rev.1.00 Page 9 of 15
Jan 25, 2011

R2J20656ANP Preliminary

Power Loss vs. Output Inductance

1.7

VIN = 12 V
VCIN = VDRV = 5 V

1.6

VOUT = 1.3 V
f

1.5

= 600 kHz

PWM

IOUT = 25 A

1.4

1.3

1.2

@ L = 0.45 μH

1.1

Normalized Power Loss

1.0

0.9

0.8

0.10.20.30.40.50.60.70.80.91.0
Output Inductance (μH)

Average ICIN vs. Switching Frequency

70

VIN = 12 V
VCIN = VDRV = 5 V
VOUT = 1.3 V

60

L = 0.45 μH
IOUT = 0 A

50

Power Loss vs. VCIN

1.7

VIN = 12 V
VOUT = 1.3 V

1.6

f

= 600 kHz

PWM

L = 0.45 μH

1.5

IOUT = 25 A

1.4

1.3

1.2

1.1

@ VCIN = VDRV = 5 V

Normalized Power Loss

1.0

0.9

0.8

4.5 5.0 5.5 6.0
VCIN = VDRV (V)

40

30

Average ICIN (mA)

20

10

250 500 750 1000 1250

Switching Frequency (kHz)

R07DS0201EJ0100 Rev.1.00 Page 10 of 15
Jan 25, 2011

R2J20656ANP Preliminary

Description of Operation

The DrMOS multi-chip module incorporates a high-side MOS FET, low-side MOS FET, and MOS-FET driver in a
single QFN package. Since the parasitic inductance between each chip is extremely small, the module is highly suitable
for use in buck converters to be operated at high frequencies. The control timing between the high-side MOS FET, low­side MOS FET, and driver is optimized so that high efficiency can be obtained at low output-voltage.

VCIN & DISBL#

The VCIN pin is connected to the UVL (under-voltage lockout) module, so that the driver is disabled as long as VCIN
is 4.3 V or less. On cancellation of UVL, the driver remains enabled until the UVL input is driven to 3.8 V or less. The
signal on pin DISBL# also enables or disables the circuit.

Voltages from –0.3 V to VCIN can be applied to the DISBL# pin, so on/off control by a logic IC or the use of a resistor,
etc., to pull the DISBL# line up to VCIN are both possible.

VCIN DISBL# Driver State

L  Disable (GL, GH = L)
H L Disable (GL, GH = L)
H H Active
H Open Disable (GL, GH = L)

The pulled-down MOS FET, which is turned on when internal IC temperature becomes over thermal shutdown level, is
connected to the DISBL# pin. The detailed function is described in THDN section.

PWM & ZCD_EN#

The PWM pin is the signal input pin for the driver chip. The input-voltage range is –0.3 V to (VCIN + 0.3 V). When the
PWM input is high, the gate of the high-side MOS FET (GH) is high and the gate of the low-side MOS FET (GL) is
low.

PWM GH GL

L L H
H H L

The ZCD_EN# pin is the Zero Current Detection Operation Enable pin for "Diode Emulation Mode (DEM)" when
ZCD_EN# is low. This function improves light load efficiency by preventing negative inductor current from output
capacitor. Driver IC monitors inductor current and when inductor current crosses zero, driver IC turn off Low side MOS
FET automatically.

Figure 1.1 shows the Typical high side and low side gate switching and Inductor current (IL) during Continuous
Conduction Mode (CCM), and figure 1.2 shows DEM when asserting Zero Current Detection Enable signal.

ZCD_EN# pin is internally pulled up to VCIN with 160 k resistor. When Zero current detection function is not used,
keep this pin open or pulled up to VCIN.

CCM Operation (ZCD_EN# = "H" or Open mode)

IL

PWM

GH

GL

Figure 1.1 Typical Signals during CCM

R07DS0201EJ0100 Rev.1.00 Page 11 of 15
Jan 25, 2011

R2J20656ANP Preliminary

DEM Operation (ZCD_EN# = "L" in Light load condition)

IL

0 A

PWM

GH

GL

Figure 1.2 Typical Signals during DEM

The PWM input is TTL level and has hysteresis. When the signal route from the control IC is high impedance, the tri­state function turns off the high- and low-side MOS FETs. This function operates when the PWM input signal stays in
the input hysteresis window for 150 ns (typ.). Afte r the tri- st at e mode has been ente red a nd GH an d GL ha ve become
low, a PWM input voltage of 4.0 V or more is required to make the circuit return to normal operation.

150 ns (t

HOLD-OFF

)

PWM

GH

GL

3.2 V

1.5 V

150 ns (t

HOLD-OFF

)

PWM

GH

GL

3.2 V

1.5 V

150 ns (t

HOLD-OFF

)

150 ns (t

HOLD-OFF

Figure 2 PWM Shutdown-Hold Time Signal

)

R07DS0201EJ0100 Rev.1.00 Page 12 of 15
Jan 25, 2011

R2J20656ANP Preliminary

The equivalent circuit for the PWM-pin input is shown in the next figure. M1 is in the ON state during normal
operation; after the PWM input signal has stayed in the hysteresis window for 150 ns (typ.) and the tri-state detection
signal has been driven high, the transistor M1 is turned off.

When VCIN is powered up, M1 is started in the OFF state regardless of PWM Low or Open state. After PWM is
asserted high signal, M1 becomes ON and shifts to normal operation.

VCIN

M1

14.5 k
Tri-state

PWM Pin

Input

Logic

12.5 k

detection signal

To internal control

Figure 3 Equivalent Circuit for the PWM-pin Input

THWN & THDN

This device has two level thermal detection, one is thermal warning and the other is thermal shutdown function.
This Thermal Warning feature is the indication of the high temperature status.

THWN is an open drain logic output signal and need to connect a pull-up resistor (ex.51 k) to THWN for Systems
with the thermal warning implementation.

When the chip temperature of the internal driver IC becomes over 115°C, Thermal warning function operates.
This signal is only indication for the system controller and does not disable DrMOS operation.

When thermal warning function is not used, keep this pin open.

115100

Thermal
warning

TIC (°C)

THWN output
Logic Level

"H"

Normal
operating

"L"

Figure 4 THWN Trigger Temperature

R07DS0201EJ0100 Rev.1.00 Page 13 of 15
Jan 25, 2011

R2J20656ANP Preliminary

r

THDN is an internal thermal shutdown signal when driver IC becomes over 150°C.
This function makes High Side MOS FET and Low Side MOS FET turn off for the device protection from abnormal

high temperature situation and at the same time DISBL# pin is pulled low internally to give notice to the system
controller. Once thermal shutdown function operates, driver IC keeps DISBL# pin pulled low until VCIN becomes
under UVL level (3.8 V).

Figure 5 shows the example of two types of DISBL# connection with the system controller signal.

Driver IC Temp. Driver Chip Status

< 150°C Enable (GL, GH = "Active")
> 150°C Shutdown (GL, GH = "L")

5 V

10 k

To shutdown signal

DISBL#

2 μA

To Internal
Logic

Thermal

Shutdown

Detection

ON/OFF signal

10 k

DISBL#

2 μA

To Internal
Logic

Thermal

Shutdown

Detection

Figure 5.1 THDN Signal to the System Controller Figure 5.2 ON/OFF Signal from the System Controlle

MOS FET

The MOS FETs incorporated in R2J20656ANP are highly suit abl e fo r sy nch r on ous- rect i fi cati on buck conversion. For
the high-side MOS FET, the drain is connected to the VIN pin and the source is connected to the VSWH pin. For the
low-side MOS FET, the drain is connected to the VSWH pin and the source is connected to the PGND pin.

R07DS0201EJ0100 Rev.1.00 Page 14 of 15
Jan 25, 2011

R2J20656ANP Preliminary

Package Dimensions

P-HVQFN40-p-0606-0.50 ——PVQN0040KE-A

X 4

4-(0.139)

t S AB

HE

E

HE/2 E /2

20°

HD/2 D /2

2-A section

CAV No.
Die No.

1.95

e

HD

D

1.95

INDEX

y1

B

1.95

S

1pin

1.95

ZD

20°

4-C0.50

40

ZE

X 4

f S AB

MASS[Typ.]RENESAS CodeJEITA Package Code Previous Code

0.2

2.2

1pin

40

A

2.2

b

S

A

A2

0.69

Lp

0.2

C0.3

x S AB

L1

c2

A1

2.2

B

2.2

0.7

0.2

2.05

2.05

y

S

Dimension in Millimeters

Reference

Symbol

Min Nom Max

5.95 6.00 6.05

D

5.95 6.00 6.05

E

0.87 0.89 0.91

A2

f

0.865 0.91 0.95

A

0.005 0.02 0.04

A1

0.17 0.22 0.27

b

0.16 0.20 0.24

b1

e

0.40 0.50 0.60

Lp

x

y1

t

6.15 6.20 6.25HD

6.15 6.20 6.25

HE
ZD

0.06 0.10 0.14

L1

0.17 0.20 0.23

c1

0.17 0.22 0.27

c2

— — 0.20

— 0.50 —

— — 0.05
— — 0.05y
— — 0.20
— — 0.20

— 0.75 —
— 0.75 —ZE

Ordering Information

Part Name Quantity Shipping Container

R2J20656ANP#G0 2500 pcs Taping Reel

R07DS0201EJ0100 Rev.1.00 Page 15 of 15
Jan 25, 2011

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use of any Renesas Electronics product for an application categorized as "Specific" or for which the product is not intended where you have failed to obtain the prior written consent of Renesas Electronics.
The quality grade of each Renesas Electronics product is "Standard" unless otherwise expressly specified in a Renesas Electronics data sheets or data books, etc.

"Standard": Computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools;
personal electronic equipment; and industrial robots.
"High Quality": Transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anti-crime systems; safety equipment; and medical equipment not specifically

designed for life support.

"Specific": Aircraft; aerospace equipment; submersible repeaters; nuclear reactor control systems; medical equipment or systems for life support (e.g. artificial life support devices or systems), surgical

implantations, or healthcare intervention (e.g. excision, etc.), and any other applications or purposes that pose a direct threat to human life.

8. You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics, especially with respect to the maximum rating, operating supply voltage
range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas Electronics shall have no liability for malfunctions or damages arising out of the
use of Renesas Electronics products beyond such specified ranges.

9. Although Renesas Electronics endeavors to improve the quality and reliability of its products, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and
malfunctions under certain use conditions. Further, Renesas Electronics products are not subject to radiation resistance design. Please be sure to implement safety measures to guard them against the
possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas Electronics product, such as safety design for hardware and software including but not limited to
redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because the evaluation of microcomputer software alone is very difficult,
please evaluate the safety of the final products or system manufactured by you.

10. Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product. Please use Renesas Electronics
products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive. Renesas Electronics assumes
no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations.

11. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of Renesas Electronics.

12. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products, or if you have any other inquiries.

(Note 1) "Renesas Electronics" as used in this document means Renesas Electronics Corporation and also includes its majority-owned subsidiaries.
(Note 2) "Renesas Electronics product(s)" means any product developed or manufactured by or for Renesas Electronics.

SALES OFFICES

Refer to "http://www.renesas.com/" for the latest and detailed information.

Renesas Electronics America Inc.

2880 Scott Boulevard Santa Clara, CA 95050-2554, U.S.A.
Tel: [phone], Fax: [phone]

Renesas Electronics Canada Limited

1101 Nicholson Road, Newmarket, Ontario L3Y 9C3, Canada
Tel: [phone], Fax: [phone]

Renesas Electronics Europe Limited

Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K
Tel: [phone], Fax: [phone]

Renesas Electronics Europe GmbH

Arcadiastrasse 10, 40472 Düsseldorf, Germany
Tel: [phone], Fax: [phone]

Renesas Electronics (China) Co., Ltd.

7th Floor, Quantum Plaza, No.27 ZhiChunLu Haidian District, Beijing 100083, P.R.China
Tel: [phone], Fax: [phone]

Renesas Electronics (Shanghai) Co., Ltd.

Unit 204, 205, AZIA Center, No.1233 Lujiazui Ring Rd., Pudong District, Shanghai 200120, China
Tel: [phone], Fax: [phone] / -7898

Renesas Electronics Hong Kong Limited

Unit 1601-1613, 16/F., Tower 2, Grand Century Place, 193 Prince Edward Road West, Mongkok, Kowloon, Hong Kong
Tel: [phone], Fax: [phone]

Renesas Electronics Taiwan Co., Ltd.

7F, No. 363 Fu Shing North Road Taipei, Taiwan
Tel: [phone], Fax: [phone]

Renesas Electronics Singapore Pte. Ltd.

1 harbourFront Avenue, #06-10, keppel Bay Tower, Singapore 098632
Tel: [phone], Fax: [phone]

Renesas Electronics Malaysia Sdn.Bhd.

Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No. 18, Jln Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia
Tel: [phone], Fax: [phone]

Renesas Electronics Korea Co., Ltd.

11F., Samik Lavied' or Bldg., 720-2 Yeoksam-Dong, Kangnam-Ku, Seoul 135-080, Korea
Tel: [phone], Fax: [phone]

© 2011 Renesas Electronics Corporation. All rights reserved.

http://www.renesas.com

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