Datasheet R2J20655NP Datasheet (Mosfet)

Preliminary Datasheet

R2J20655NP

R07DS0200EJ0100

Rev.1.00

Integrated Driver - MOS FET (DrMOS)

Jan 25, 2011

Description

The R2J20655NP multi-chip module incorporates a high-side MOS FET, low-side MOS FET, and MOS-FET driver in
a single QFN package. The on and off timing of the power MOS FET is optimized by the built-in driver, making this
device suitable for large-current buck converters. The chip also incorporates a high-side bootstrap switch, eliminating
the need for an external SBD for this purpose.

Features

 Based on Intel 6  6 DrMOS Specification.
 Built-in power MOS FET suitable for Desktop, Server application.
 Low-side MOS FET with built-in SBD for lower loss and reduced ringing.
 Built-in driver circuit which matches the power MOS FET
 Built-in tri-state input function which can support a number of PWM controllers
 High-frequency operation (above 1 MHz) possible
 VIN operating-voltage range: 27 Vmax
 Large average output current (Max. 3 5 A)
 Achieve low power dissipation
 Controllable driver: Remote on/off
 Low side MOS FET disabled function for DCM operation
 Double thermal protection: Thermal Warning & Thermal Shutdown
 Built-in bootstrapping Switch
 Small package: QFN40 (6 mm  6 mm  0.95 mm)
 Pb-free/Halogen-Free

Outline

THWN

DISBL#

LSDBL#

PWM

MOS FET Driver

CGND

Integrated Driver-MOS FET (DrMOS)

QFN40 package 6 mm × 6 mm

VINGHBOOTVCIN Reg5V

VSWH

GL PGND

110

40

Driver
Pad

Low-side MOS Pad

31

30 21

(Bottom view)

High-side
MOS Pad

11

20

R07DS0200EJ0100 Rev.1.00 Page 1 of 17
Jan 25, 2011

R2J20655NP Preliminary

Block Diagram

Driver Chip

THWN

DISBL#

LSDBL#

PWM

THWN THDN

2 μA

CGND

CGND

160 k

Reg5V

Input Logic
(TTL Level)
(3 state in)

Reg5V

VCIN

UVL

Reg5V

Supervisor

Reg5V

Level Shifter

Overlap
Protection.
& Logic

BOOT GH

Boot

SW

Reg5V

VIN

High Side
MOS FET

20 k

VSWH

Low Side
MOS FET

35 k

PGND

GLCGND

Notes: 1. Truth table for the DISBL# pin 2. Truth table for the LSDBL# pin

DISBL# Input Driver Chip Status

"L" Shutdown (GL, GH = "L")
"Open" Shutdown (GL, GH = "L")
"H" Enable (GL, GH = "Active")

LSDBL# Input GL Status

"L" "L"
"Open" "Active"
"H" "Active"

3. Output signal from the UVL block 4. Output signal from the THWN block

VHVL

For active

VCIN

Thermal Warning
Logic Level

"H"

"L"

Normal
operating

Thermal
Warning

T

(°C)

IC

TwarnHTwarnL

UVL output
Logic Level

"H"

For shutdown

"L"

5. Truth table for the THDN block

Driver IC Temp. Driver Chip Status

< 150°C Enable (GL, GH = "Active")
> 150°C

Shutdown (GL, GH = "L")
(latch-off)

R07DS0200EJ0100 Rev.1.00 Page 2 of 17
Jan 25, 2011

R2J20655NP Preliminary

Pin Arrangement

VIN

VIN

VIN

VSWHGHCGND

1098765432

11

VIN PWM

12

VIN

13

VIN

14

VIN

VSWH

PGND
PGND
PGND
PGND
PGND VSWH

15
16
17
18
19
20

VIN

VSWH

21 22 23 24 25 26 27 28 29 30

PGND

PGND

PGND

PGND

PGND

PGND

BOOT

VCIN

CGND

PGND

PGND

Reg5V

VSWH

(Top view)

Note: All die-pads (three pads in total) should be soldered to PCB.

Pin Description

LSDBL#

1

40
39
38
37
36
35
34
33
32
31

VSWH

DISBL#
THWN
CGND
GL
VSWH
VSWH
VSWH
VSWH

Pin Name Pin No. Description Remarks

LSDBL# 1 Low-side gate disable When asserted "L" signal, Low-side gate disable
Reg5V 2 +5 V logic power supply output
VCIN 3 Control input voltage Driver Vcc input
BOOT 4 Bootstrap voltage pin To be supplied +5 V through internal switch
CGND 5, 37, Pad Control signal ground Should be connected to PGND externally
GH 6 High-side gate signal Pin for monitor
VIN 8 to 14, Pad Input voltage
VSWH 7, 15, 29 to 35, Pad Phase output/Switch output
PGND 16 to 28 Power ground
GL 36 Low-side gate signal Pin for monitor
THWN 38 Thermal warning Thermal warning when over 115°C
DISBL# 39 Signal disable

Disabled when DISBL# is "L".
This Pin is pulled low when internal IC over the
thermal shutdown level, 150°C.

PWM 40 PWM drive logic input Capable of both 3.3 V and 5 V logic input

R07DS0200EJ0100 Rev.1.00 Page 3 of 17
Jan 25, 2011

R2J20655NP Preliminary

Absolute Maximum Ratings

(Ta = 25°C)

Item Symbol Rating Units Note

Pt(25) 25 Power dissipation
Pt(110) 8

Average output current Iout 35 A

VIN(DC) –0.3 to +27 2 Input voltage
VIN(AC) 30
VSWH(DC) 27 2 Switch node voltage
VSWH(AC) 30
VBOOT(DC) 32 2 BOOT voltage

VBOOT(AC) 36
Supply voltage VCIN –0.3 to +27 V 2
PWM voltage Vpwm

Other I/O voltage Vdisbl, Vlsdbl –0.3 to VCIN + 0.3 V 2
Reg5V voltage Vreg5V –0.3 to +6 V 2, 7
Reg5V current Ireg5V –20 to +0.1 mA 3
THWN/THDN current Ithwn, Idisbl 0 to 1.0 mA 3
Operating junction temperature Tj-opr –40 to +150 °C
Storage temperature Tstg –55 to +150 °C
Notes: 1. Pt(25) represents a PCB temperature of 25°C, and Pt(110) represents 110C.

2. Rated voltages are relative to voltages on the CGND and PGND pins.

3. For rated current, (+) indicates inflow to the chip and (–) indicates outflow.

4. This rating is when UVL (Under Voltage Lock out) is ineffective (normal operation mode).

5. This rating is when UVL (Under Voltage Lock out) is effective (lock out mode).

6. The specification values indicated "AC" are limited within 10 ns.

7. This rating is when the external power-source is applied to Reg5V pin.

8. Reg5V + 0.3 V < 6 V

–0.3 to +5.5 @UVL OFF

–0.3 to +0.3 @UVL ON

–0.3 to Reg5V + 0.3

W 1

V

2, 4, 6

V

2, 4, 6

V

2, 4, 6

V

2, 4
2, 5

2, 7, 8

Safe Operating Area

45
40
35
30
25
20

VOUT = 1.3 V

15

VIN = 12 V

10

VCIN = 5 V
L = 0.45 μH

Average Output Current (A)

5

Fsw = 1 MHz

0

0 25 50 75 100 125 150 175

PCB Temperature (°C)

R07DS0200EJ0100 Rev.1.00 Page 4 of 17
Jan 25, 2011

R2J20655NP Preliminary

Recommended Operating Condition

Item Symbol Rating Units Note

Input voltage VIN 4.5 to 22 V
Supply voltage &

Drive voltage

VCIN

4.5 to 5.5
or

V

When the usage of VCIN = 4.5 V to 5.5 V,
VCIN should be connected to Reg5V
(Refer to "Pin Connection")

8 to 22

Electrical Characteristics

(Ta = 25°C, VCIN = 12 V, VSWH = 0 V, unless otherwise specified)

Item Symbol Min Typ Max Units Test Conditions

Supply

PWM
input

DISBL#
input

LSDBL#
input

Thermal
warning

Thermal
shutdown

5 V
regulator

Note: 1. Reference values for design. Not 100% tested in production.

VCIN start threshold VH 7.0 7.4 7.8 V
VCIN shutdown threshold VL 6.6 7.0 7.4 V
UVLO hysteresis dUVL — 0.4 — V VH – VL
VCIN operating current I

— 49 — mA

CIN

f

PWM

= 1 MHz,

Ton_pwm = 120 ns

VCIN disable current I

— — 800 A

CIN-DISBL

DISBL# = 0 V,

PWM = LSDBL# = Open
PWM input high level V
PWM input low level V
PWM input resistance R
PWM input tri-state range V
Shutdown hold-off time t
Enable level V
Disable level V
Input current I
THDN on resistance R
Low-side activation level V
Low-side disable level V
Input current I
Warning temperature T
Temperature hysteresis T
THWN on resistance R
THWN leakage current I
Shutdown temperature Tstdn *

2.6 — — V 3.3 V/5.0 V PWM interface

H-PWM

— — 0.8 V

L-PWM

6.5 12.5 25 k PWM = 1 V

IN-PWM

1.4 — 2.0 V 3.3 V/5.0 V PWM interface

IN-tri

HOLD-OFF

ENBL
DISBL

DISBL

THDN
LSDBLH
LSDBLL

LSDBL

THWN
HYS

THWN

LEAK

1

*

— 150 — ns

2.0 — — V
— — 0.8 V

— 2.0 5.0 A DISBL# = 1 V

*1 0.2 0.5 1.0 k DISBL# = 0.2 V

2.0 — — V

— — 0.8 V

–52 –26 –12 A LSDBL# = 1 V

*1 100 115 130 °C Driver IC temperature

*1 — 15 — °C

*1 0.2 0.5 1.0 k THWN = 0.2 V

— — 1.0 A THWN = 5 V

1

130 150 — °C Driver IC temperature

Output voltage Vreg 4.95 5.2 5.45 V
Line regulation Vreg-line –10 0 10 mV VCIN = 12 V to 16 V
Load regulation Vreg-load –10 0 10 mV Ireg = 0 to 10 mA

R07DS0200EJ0100 Rev.1.00 Page 5 of 17
Jan 25, 2011

R2J20655NP Preliminary

Typical Application

(1) Desktop/Server Application

+12 V

+5 V

PWM
Control
Circuit

PWM1

PWM2

PWM3

PWM4

VCIN

THWN
DISBL#
Reg5V

R2J20655NP

PWM

CGND GL

VCIN

THWN
DISBL#
Reg5V

R2J20655NP

PWM

CGND GL

LSDBL#

LSDBL#

GH

GH

BOOT

VIN

VSWH

PGND

BOOT

VIN

VSWH

PGND

+1.3 V

VCIN

THWN
DISBL#
Reg5V

R2J20655NP

PWM

LSDBL#

CGND GL

VCIN

THWN
DISBL#
Reg5V

R2J20655NP

PWM

CGND GL

LSDBL#

GH

GH

BOOT

VSWH

PGND

BOOT

VSWH

PGND

VIN

Power GND Signal GND

VIN

R07DS0200EJ0100 Rev.1.00 Page 6 of 17
Jan 25, 2011

R2J20655NP Preliminary

Typical Application (cont.)

(2) Notebook Application

+19 V

+5 V

PWM
Control
Circuit

PWM1

PWM2

PWM3

VCIN

THWN
DISBL#
Reg5V

R2J20655NP

PWM

CGND GL

VCIN

THWN
DISBL#
Reg5V

R2J20655NP

PWM

CGND GL

LSDBL#

LSDBL#

GH

GH

BOOT

VIN

VSWH

PGND

BOOT

VIN

VSWH

PGND

+1.1 V

VCIN

THWN
DISBL#
Reg5V

R2J20655NP

PWM

CGND GL

LSDBL#

BOOT

VIN

VSWH

PGND

GH

Power GND Signal GND

R07DS0200EJ0100 Rev.1.00 Page 7 of 17
Jan 25, 2011

R2J20655NP Preliminary

Pin Connection

(1) Single 12 V Application

VIN

12 V

10 μF × 4

PGND

Power GND Signal GND

PGND

0.1 μF

GH

11
12
13

VIN

14

15

VSWH

16

PGND
17
18
19
20

VIN

VIN

PAD

R2J20655NP

VSWH

VSWH

CGND

PAD

0 to 10 Ω

BOOT

CGND

PAD

1.0 μF

VCIN

PGND

1.0 μF

12345678910

Reg5V

DISBL#

THWN
CGND

VSWH

VSWH

30292827262524232221

CGND

PWM

LSDBL#

GL

Low Side Disable Signal INPUT

CGND

40
39
38
37
36

35
34
33
32
31

Thermal Warning

10 kΩ

10 kΩ

PWM INPUT

Thermal Shutdown

VCIN

VCIN

0.45 μH
Vout

PGND

(2) VCIN 5 V Application

VIN

12 V

10 μF × 4

PGND

Power GND Signal GND

PGND

0.1 μF

1.0 μF

0 to 10 Ω

Low Side Disable Signal INPUT

5.0 V

12345678910

GH

VIN

11
12
13

VIN

14

15

VSWH

16

PGND
17
18
19
20

VSWH

VIN

PAD

R2J20655NP

VSWH

PAD

CGND

VCIN

BOOT

CGND

PAD

PGND

Reg5V

DISBL#

THWN
CGND

VSWH

VSWH

30292827262524232221

PWM

LSDBL#

GL

40
39
38
37
36

35
34
33
32
31

CGND

Thermal Warning

0.45 μH

External
Power Supply

Thermal Shutdown

10 kΩ

10 kΩ

PWM INPUT

5 V

5 V

Vout

PGND

R07DS0200EJ0100 Rev.1.00 Page 8 of 17
Jan 25, 2011

R2J20655NP Preliminary

Test Circuit

I

IN

Vinput

Vcont

5 V pulse

A

V

V

IN

I

CIN

A

V

V

CIN

VCIN

DISBL#

R2J20655NP

Reg5V
LSDBL#

PWM

CGND

GH

GL

BOOT

VSWH

PGND

VIN

Electric
load

I

O

Note: P

= IIN × VIN + I

IN

P

= IO × V

OUT

Efficiency = P
P

(DrMOS) = PIN – P

LOSS

Ta = 27°C

O
OUT

CIN

/ P

× V

IN

CIN

OUT

Averaging
circuit

Average Output Voltage

V

V

O

R07DS0200EJ0100 Rev.1.00 Page 9 of 17
Jan 25, 2011

R2J20655NP Preliminary

Typical Data

Power Loss vs. Output Current

9

VIN = 12 V
VCIN = Reg5V = 5 V

8

VOUT = 1.3 V
f

= 600 kHz

7

PWM

L = 0.45 μH

6
5
4
3

Power Loss (W)

2
1
0

0 5 10 15 20 25 30 35

Output Current (A)

Power Loss vs. Output Voltage

1.7

VIN = 12 V
VCIN = Reg5V = 5 V

1.6

f

= 600 kHz

PWM

L = 0.45 μH

1.5

IOUT = 25 A

1.4

Power Loss vs. Input Voltage

1.7

VCIN = Reg5V = 5 V
VOUT = 1.3 V

1.6

f

= 600 kHz

PWM

L = 0.45 μH

1.5

IOUT = 25 A

1.4

1.3

1.2

@ VIN = 12 V

1.1

Normalized Power Loss

1.0

0.9

0.8
4 6 8 10 2012 14 2216 18

Input Voltage (V)

Power Loss vs. Switching Frequency

1.7

VIN = 12 V
VCIN = Reg5V = 5 V

1.6

VOUT = 1.3 V
L = 0.45 μH

1.5

IOUT = 25 A

1.4

1.3

1.2

1.1

@ VOUT = 1.3 V

Normalized Power Loss

1.0

0.9

0.8

0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 4.4
Output Voltage (V)

1.3

= 600 kHz

1.2

PWM

1.1

@ f

Normalized Power Loss

1.0

0.9

0.8
250 500 750 1000 1250

Switching Frequency (kHz)

R07DS0200EJ0100 Rev.1.00 Page 10 of 17
Jan 25, 2011

R2J20655NP Preliminary

Typical Data (cont.)

Power Loss vs. Output Inductance

1.7

VIN = 12 V
VCIN = Reg5V = 5 V

1.6

VOUT = 1.3 V
f

1.5

= 600 kHz

PWM

IOUT = 25 A

1.4

1.3

1.2

@ L = 0.45 μH

1.1

Normalized Power Loss

1.0

0.9

0.8

0.10.20.30.40.50.60.70.80.91.0
Output Inductance (μH)

Average ICIN vs. Switching Frequency

70

VIN = 12 V
VCIN = Reg5V = 5 V
VOUT = 1.3 V

60

L = 0.45 μH
IOUT = 0 A

50

Power Loss vs. VCIN

1.7

VIN = 12 V
VOUT = 1.3 V

1.6

f

= 600 kHz

PWM

L = 0.45 μH

1.5

IOUT = 25 A

1.4

1.3

1.2

1.1

@ VCIN = Reg5V = 5 V

Normalized Power Loss

1.0

0.9

0.8

4.5 5.0 5.5 6.0
VCIN = Reg5V (V)

40

30

Average ICIN (mA)

20

10

250 500 750 1000 1250

Switching Frequency (kHz)

R07DS0200EJ0100 Rev.1.00 Page 11 of 17
Jan 25, 2011

R2J20655NP Preliminary

Description of Operation

The DrMOS multi-chip module incorporates a high-side MOS FET, low-side MOS FET, and MOS-FET driver in a
single QFN package. Since the parasitic inductance between each chip is extremely small, the module is highly suitable
for use in buck converters to be operated at high frequencies. The control timing between the high-side MOS FET, low­side MOS FET, and driver is optimized so that high efficiency can be obtained at low output-voltage.

VCIN & DISBL#

The VCIN pin is connected to the UVL (under-voltage lockout) module, so that the built-in 5 V regulator is disabled as
long as VCIN is 7.4 V or less. On cancellation of UVL, the built-in 5 V regulator remains enabled until the UVL input
is driven to 7.0 V or less.

The built-in 5 V regulator is a series regulator with temperature compensation. A ceramic capacitor with a value of 0.1
F or more must be connected between the CGND plane and the Reg5V pin.

The output of 5 V regulator is monitored by the internal Supervisor circuits. When the Supervisor detects this output is
more than 4.3 V (typ.), the driver state becomes active (figure 1.1). Supervisor circuit has hysteresis and its shutdown
level of Supervisor is 3.8 V (typ.).

Figure 1.2 shows the application when the external 5 V regulator is used. When the Reg5V pin is applied into external 5
V, the Supervisor can activate the driver. In this application usage, VCIN should be connected to Reg5V.

The signal on pin DISBL# also enables or disables the circuit. When UVL disables the circuit , the built-in 5 V
regulator does not operate, but when the signal on DISBL# disables the circuit, only output-pulse generation is
terminated, and the 5 V regulator is not disabled.

Voltages from –0.3 V to VCIN+0.3 V can be applied to the DISBL# pin, so on/off control by a logic IC or the use of a
resistor, etc., to pull the DISBL# line up to VCIN are both possible.

VCIN DISBL# REG5V Driver State

L  0 Disable (GL, GH = L)
H L Active Disable (GL, GH = L)
H H Active Active
H Open Active Disable (GL, GH = L)

12 V

VCIN

VCIN > 7.4 V

VCIN

5 V

IN

UVL &

5 V Regulator

To Internal

Logic

Supervisor

Reg5V

OUT

Figure 1.1 Typical 12 V Input Application

To Internal

Logic

IN

UVL &

5 V Regulator

Supervisor

OUT

Reg5V

External 5 V

Figure 1.2 External 5 V Application

(Activate Built-in 5 V Regulator)

R07DS0200EJ0100 Rev.1.00 Page 12 of 17
Jan 25, 2011

R2J20655NP Preliminary

PWM & LSDBL#

The PWM pin is the signal input pin for the driver chip. When the PWM input is high, the gate of the high-side MOS
FET (GH) is high and the gate of the low-side MOS FET (GL) is low.

PWM GH GL

L L H
H H L

The LSDBL# pin is the Low Side Gate Disable pin for "Discontinuous Conduction Mode (DCM)" when LSDBL# is
low.

Figure 2 shows the Typical high side and low side gate switching and Inductor current (IL) during "Continuous
Conduction Mode (CCM)" and low side gate disabled when asserting LSDBL# signal.
This pin is internally pulled up to Reg5V with 160 k resistor.

When low side disable function is not used, keep this pin open or pulled up to VCIN.

CCM Operation (LSDBL# = "H" or Open mode)

IL

GH

GL

Figure 2.1 Typical Signals during CCM

DCM Operation (LSDBL# = "L")

IL

0 A

GH

GL

Figure 2.2 Typical Signals during DCM

R07DS0200EJ0100 Rev.1.00 Page 13 of 17
Jan 25, 2011

R2J20655NP Preliminary

The PWM input is TTL level and has hysteresis. When the signal route from the control IC is high impedance, the tri­state function turns off the high- and low-side MOS FETs. This function operates when the PWM input signal stays in
the input hysteresis window for 150ns (typ.). After the tri-state mode has been entered and GH and GL have become
low, a PWM input voltage of 2.6 V or more is required to make the circuit return to normal operation.

PWM

GH

GL

PWM

2.0 V

1.4 V

2.0 V

1.4 V

150 ns (t

150 ns (t

HOLD-OFF

HOLD-OFF

)

)

150 ns (t

150 ns (t

HOLD-OFF

HOLD-OFF

)

)

GH

GL

Figure 3 PWM Shutdown-Hold Time Signal

R07DS0200EJ0100 Rev.1.00 Page 14 of 17
Jan 25, 2011

R2J20655NP Preliminary

The equivalent circuit for the PWM-pin input is shown in the next figure. M1 is in the ON state during normal
operation; after the PWM input signal has stayed in the hysteresis window for 150 ns (typ.) and the tri-state detection
signal has been driven high, the transistor M1 is turned off.

When VCIN is powered up, M1 is started in the OFF state regardless of PWM Low or Open state. After PWM is
asserted high signal, M1 becomes ON and shifts to normal operation.

Reg5V

M1

25 k

Tri-state

PWM Pin

Input

Logic

12.5 k

detection signal

To internal control

Figure 4 Equivalent Circuit for the PWM-pin Input

THWN & THDN

This device has two level thermal detection, one is thermal warning and the other is thermal shutdown function.
This Thermal Warning feature is the indication of the high temperature status.

THWN is an open drain logic output signal and need to connect a pull-up resistor (ex.51 k) to THWN for Systems
with the thermal warning implementation.

When the chip temperature of the internal driver IC becomes over 115°C, Thermal warning function operates.
This signal is only indication for the system controller and does not disable DrMOS operation.

When thermal warning function is not used, keep this pin open.

115100

Thermal
warning

TIC (°C)

THWN output
Logic Level

"H"

Normal
operating

"L"

Figure 5 THWN Trigger Temperature

R07DS0200EJ0100 Rev.1.00 Page 15 of 17
Jan 25, 2011

R2J20655NP Preliminary

r

THDN is an internal thermal shutdown signal when driver IC becomes over 150°C.
This function makes High Side MOS FET and Low Side MOS FET turn off for the device protection from abnormal

high temperature situation and at the same time DISBL# pin is pulled low internally to give notice to the system
controller. Once thermal shutdown function operates, driver IC keeps DISBL# pin pulled low until VCIN becomes
under UVL level (or under supervisor shutdown level).

Figure 6 shows the example of two types of DISBL# connection with the system controller signal.

Driver IC Temp. Driver Chip Status

< 150°C Enable (GL, GH = "Active")
> 150°C Shutdown (GL, GH = "L")

5 V

10 k

To shutdown signal

DISBL#

2 μA

To Internal
Logic

Thermal

Shutdown

Detection

ON/OFF signal

10 k

DISBL#

2 μA

To Internal
Logic

Thermal

Shutdown

Detection

Figure 6.1 THDN Signal to the System Controller Figure 6.2 ON/OFF Signal from the System Controlle

MOS FET

The MOS FETs incorporated in R2J20655NP are highly suitable for synchronous-rectification buck conversion. For the
high-side MOS FET, the drain is connected to the VIN pin and the source is connected to the VSWH pin. For the low­side MOS FET, the drain is connected to the VSWH pin and the source is connected to the PGND pin.

R07DS0200EJ0100 Rev.1.00 Page 16 of 17
Jan 25, 2011

R2J20655NP Preliminary

Package Dimensions

P-HVQFN40-p-0606-0.50 ——PVQN0040KE-A

X 4

4-(0.139)

t S AB

HE

E

HE/2 E /2

20°

HD/2 D /2

2-A section

CAV No.
Die No.

1.95

e

HD

D

1.95

INDEX

y1

B

1.95

S

1pin

1.95

ZD

20°

4-C0.50

40

ZE

X 4

MASS[Typ.]RENESAS CodeJEITA Package Code Previous Code

f S AB

0.2

2.2

1pin

40

A

2.2

b

S

A

A2

0.69

Lp

0.2

C0.3

x S AB

L1

c2

A1

2.2

B

2.2

0.7

0.2

2.05

2.05

y

S

Dimension in Millimeters

Reference

Symbol

Min Nom Max

5.95 6.00 6.05

D

5.95 6.00 6.05

E

0.87 0.89 0.91

A2

f

0.865 0.91 0.95

A

0.005 0.02 0.04

A1

0.17 0.22 0.27

b

0.16 0.20 0.24

b1

e

0.40 0.50 0.60

Lp

x

y1

t

6.15 6.20 6.25HD

6.15 6.20 6.25

HE
ZD

0.06 0.10 0.14

L1

0.17 0.20 0.23

c1

0.17 0.22 0.27

c2

— — 0.20

— 0.50 —

— — 0.05
— — 0.05y
— — 0.20
— — 0.20

— 0.75 —
— 0.75 —ZE

Ordering Information

Part Name Quantity Shipping Container

R2J20655NP#G0 2500 pcs Taping Reel

R07DS0200EJ0100 Rev.1.00 Page 17 of 17
Jan 25, 2011

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