Datasheet R2033K, R2033T Datasheet (RICOH)

Page 1

R2033K/T

3 wire interface Real-Time Clock ICs

NO.EA-120-070221

OUTLINE

The R2033K/T is a CMOS real-time clock IC connected to the CPU by three signal lines, CE, SCLK, SIO, and configured to perform serial transmission of time and calendar data to the CPU. The periodic interrupt circuit is configured to generate interrupt signals with six selectable interrupts ranging fro m 0.5 seconds to 1 month. The 2 alarm interrupt circuits generate interrupt signals at preset times. As the oscillation circuit is driven under constant voltage, fluctuation of the oscillator frequency due to supply voltage is small, and the time keeping current is small (TYP. 0.45µA at 3V). The oscillation halt sensing circuit can be used to judge the validity of internal data in such events as power-on; The supply voltage monitoring circuit is configured to record a drop in supply voltage below two selectable supply voltage monitoring threshold settings. The 32.768kHz clock output function (CMOS output with control pin) is intended to output sub-clock pulses for the external microcomputer. The oscillation adjustment circuit is intended to adjust time counts with high precision by correcting deviations in the oscillation frequency of the crystal oscillator. Since the package for these ICs are TSSOP10G (4.0x2.9x1.0: R2033T) or FFP12 (2.0x2.0x1.0: R2033K), high density mounting of ICs on boards is possibl e.

FEATURES

• Minimum Timekeeping supply voltage TYP:0.66 to 5.5v (Worst: 1.00V to 5.5v); VDD pin

• Low power consumption 0.45µA TYP at VDD=3V (1.00µA MAX.)

• Three signal lines (CE, SCLK, SIO) required for connection to the CPU.

(Maximum clock frequency of 1MHz (with V

• Time counters (counting hours, minutes, and seconds) and calendar counters (counting years, months, days, and weeks) (in BCD format)

• Interrupt circuit configured to generate interrupt signals (with interrupts ranging from 0.5 seconds to 1 month) to the CPU and provided with an interrupt flag and an interrupt halt

• 2 alarm interrupt circuits (Alarm_W for week, hour, and minute alarm settings and Alarm_D for hour and minute alarm settings)

• With Power-on flag to prove that the power supply starts from 0V

• 32-kHz clock output pin (CMOS push-pull output with control pin)

• Supply voltage monitoring circuit with two supply voltage monitoring threshold settings

• Automatic identification of leap years up to the year 2099

• Selectable 12-hour and 24-hour mode settings

• High precision oscillation adjustment circuit

• Built-in oscillation stabilization capacitors (CG and CD)

• Package TSS OP10G (4.0 mm x 2.9mm x 1.0mm: R2033T) FFP12 (2.0mm x 2.0mm x 1.0mm: R2033K)

• CMOS process

DD = 3V) )

Page 2

R2033K/T

PIN CONFIGURATION

R2033T(TSSOP10G)

32KOUT

SCLK

SIO

BLOCK DIAGRAM

32KOUT

CLKC

OSCIN

OSCOUT

INTR

32kHz

OUTPUT

CONTROL

OSC

DETECT

DIVIDER

CORREC

-TION

INTERRUPT CONTROL

9 8 7

VDD OSCIN OSCOUT CLKC

INTR VSS

1 2

3 4 56

TOP VIEW

COMPARATOR_W

COMPARATOR_D

DIV

(SEC,MIN,HOUR,WEEK,DAY,MONTH,YEAR)

ADDRESS DECODER

INTR

VSS

TIME COUNTER

ADDRESS

SHIFT REGISTER

R2033K(FFP12)

OSCOUT

OSCIN

CLKC

10 11 12

SIO

SCL

TOP VIEW

ALARM_W REGISTER

(MIN,HOUR, WEEK)

ALARM_D REGISTER

(MIN,HOUR)

VDD

(VSS)

32KOUT

I/O

CONTROL

VDD

VOLTAGE

DETECT

POWER_ON

RESET

VSS

SCLK SIO

SELECTION GUIDE

Part Number is designated as follows: R2033K-E2 ←Part Number ↑ ↑ R2033a-cc

Code Description

Designation of the package.

a bb Designation of the taping type. Only E2 is available.

K: FFP12 T: TSSOP10G

Page 3

R2033K/T

PIN DESCRIPTION

Symbol Item Description

CE Chip enable

Input

SCLK Serial Clock

Input

SIO Serial Input /

Output

INTR

32KOUT 32kHz Clock

CLKC Clock Control The CLKC pin is used to control output of the 32KOUT pin. The clock

OSCIN OSCOUT

VDD VSS

(VSS) Please connect to ground line, or do not connect any lines.

Interrupt Output

Output

Oscillation Circuit Input / Output Positive/Negative Power Supply Input

The CE pin is used for interfacing with the CPU. Should be held high to allow access to the CPU. Incorporates a pull-down resistor. Should be held low or open when the CPU is powered off. Allows a maximum input voltage of 5.5v regardless of supply voltage. The SCLK pin is used to input clock pulses synchronizing the input and output of data to and from the SIO pin. Allows a maximum input voltage of

5.5v regardless of supply voltage. The SIO pin is used to input and output data intended for writing and reading in synchronization with the SCLK pin. CMOS input / output.

INTR

The interrupt (Alarm_D) and output periodic interrupt signals to the CPU. Disabled at power-on from 0V. N-channel open drain output. Allows a maximum pull-up voltage of 5.5v regardless of supply voltage. The 32KOUT pin is used to output 32.768-kHz clock pulses. The pin is CMOS push-pull output. The output is disabled and held “L” when CLKC pin is set to “L” or open, or certain register setting. This pin is enabled at power-on from 0v.

output is disabled and held “L” when this pin is set to “L” or open. Incorporated pull down register. The OSCIN and OSCOUT pins are used to connect the 32.768-kHz crystal oscillator (with all other oscillation circuit components built into the R2033K/T). The VDD pin is connected to the power supply. The VSS pin is grounded.

pin is used to output alarm interrupt (Alarm_W) and alarm

Page 4

R2033K/T

ABSOLUTE MAXIMUM RATINGS

(VSS=0V)

Symbol Item Pin Name Description Unit

VDD Supply Voltage VDD -0.3 to +6.5 V

Input Voltage 1 CE, SCLK, CLKC -0.3 to +6.5 VI Input Voltage 2 SIO -0.3 to V Output Voltage 1 SIO, 32KOUT -0.3 to VDD + 0.3 VO

Output Voltage 2 PD Power Dissipation Topt Operating Temperature -40 to +85 Tstg Storage Temperature -55 to +125

INTR

Topt = 25°C

DD + 0.3

-0.3 to +6.5 300 mW

°C °C

RECOMMENDED OPERATING CONDITIONS

(VSS=0V, Topt=-40 to +85°C)

Symbol Item Pin Name Min, Typ. Max. Unit

Vaccess Supply Voltage Power supply voltage

for interfacing with CPU

VCLK Time keeping Voltage VCLKL Minimum Time keeping

Voltage fXT Oscillation Frequency 32.768 kHz VPUP Pull-up Voltage

*1) CGout is connected between OSCIN and VSS, CDout is connected between OSCOUT and VSS. R2033K/T incorporates the capacitors between OSCIN and VSS, between OSCOUT and VSS. Then normally, CGout and CDout are not necessary. For more detail, see “P.32 •Oscillation Adjustment Circuit” *2) Crystal oscillator: CL=6-9pF, R1=50KΩ

CGout,CDout=0pF *1), *2) CGout,CDout=0pF *1), *2)

INTR

32KOUT V

1.7 5.5 V

1.00 5.50

0.66 1.00

5.5

+0.3

Page 5

R2033K/T

DC ELECTRICAL CHARACTERISTICS

• R2033K/T

(Unless otherwise specified:

SS=0V, VDD=3.0V, Topt=-40 to +85°C, Crystal oscillator 32768Hz,CL=7pF,R1=50kΩ)

Symbol Item Pin Name Conditions Min. Typ. Max. Unit

VIH1 CE, SCLK, VIH2 VIL “L” Input Voltage CE, SCLK, IOH “H” Output IOL1

IOL2 IIL Input Leakage RDNCE Pull-down Resistance CE 40 120 400

ICLKC Pull-down Resister

IOZ1 SIO VO=5.5V or VSS IOZ2 IDD Time Keeping Current VDD VDD=3V,

VDETH Supply Voltage VDETL Supply Voltage

*1) For time keeping current when outputting 32.768kHz from the 32KOUT pin, see “P.44 TYPICAL CHARACTERISTICS”. For time keeping current when CGOUT, CDOUT is not equal to 0pF, see “P.29

•Adjustment of oscillation frequency”.

“H” Input Voltage

Current “L” Output Current

Current

Input Leakage Current

Output Off-state Current

Monitoring Voltage “H” Monitoring Voltage “L”

DD=1.7 to 5.5V

V CLKC SIO 0.8x

0.8x VDD

VDD

5.5 VDD+0.

-0.3 0.2x CLKC, SIO SIO,

VOH=VDD-0.5V -0.5 mA

32KOUT

INTR

SIO,

OL=0.4V

2.0

0.5

mA 32KOUT SCLK VI=5.5V or VSS

-1.0 1.0

µA

VDD=5.5V

kΩ CLKC VI=5.5V 0.30 1.00

-1 1 VDD=5.5V V

INTR

O=5.5V

DD=5.5V

CE=SCLK=SIO=CLKC

INTR

=0V

-1 1

0.45 1.00

µA

32KOUT=OFF Output = OPEN CGout=CDout=0pF *1)

VDD VDD

Topt=-30 to +70°C Topt=-30 to +70°C

1.45 1.60 1.75 V

1.15 1.30 1.45 V

Page 6

R2033K/T

AC ELECTRICAL CHARACTERISTICS

Unless otherwise specified: VSS=0V,Topt=-40 to +85°C Input and Output Conditions: V

Sym

-bol

CE Set-up Time 400 ns

CES

CE Hold Time 400 ns

CEH

tCR CE Recovery Time 62 f

SCLK Clock Frequency 1.0 MHz

SCLK

SCLK Clock ”H” Time 400 ns

CKH

SCLK Clock ”L” Time 400 ns

CKL

SCLK Set-up Time 200 ns

CKS

tRD Data Output Delay Time 300 ns tRZ Data Output Floating Time 300 ns t

Data Output Delay Time After

CEZ

Falling of CE tDS Input Data Set-up Time 200 ns tDH Input Data Hold Time 200 ns t

Output Delay Time of Voltage

DELAY

Detector

IH=0.8×VDD,VIL=0.2×VDD,VOH=0.8×VDD,VOL=0.2×VDD,CL=50pF

Item Condi-

Tions

300 ns

Time Keeping

CKH

CKL

DD≥1.7V

Unit

Min. Typ. Max.

µs

100 105 110 ms

CEH

CKS

CES

tCR

SCLK

SIO(write cycle)

CEZ

SIO(read cycle)

tRD

*) For reading/writing timing, see “P.26 •Considerations in Reading and Writing Time Data under special condition”.

Page 7

PACKAGE DIMENSIONS

• R2033K

9 7

R2033K/T

0.103

0.5

1PIN INDEX

0.15

0.3

0.2±0.15

(BOTTOM VIEW)

2PIN INDEX

0.35

0.1

2.0

0.05

0.35

0.25

1.0Max

0.17±0.1

0.27±0.15

2.0±0.1

unit: mm

Page 8

R2033K/T

• R2033T

0.2

4.0

0 to 10°

0.13

2.9±0.2

2.8±0.2

0.5

(0.75)

0.1

0.2±0.1

0.15

-0.05

+0.1

0.1

TAPING SPECIFICATION

+0.1

-0.05

0.85±0.15

0.55±0.2

unit: mm

The R2033K/T have one designated taping direction. The product designation for the taping components is "R2033K/T-E2".

Page 9

R2033K/T

GENERAL DESCRIPTION

• Interface with CPU

The R2033K/T is connected to the CPU by three signal lines CE (Chip Enable), SCLK (Serial Clock), and SIO (Serial Input and Output), through which it reads and writes data from and to the CPU. The CPU can be accessed when the CE pin is held high. Access clock pulses have a maximum frequency of 1 MHz allowing high-speed data transfer to the CPU.

• Clock and Calendar Function

The R2033K/T reads and writes time data from and to the CPU in units ranging from seconds to the last two digits of the calendar year. The calendar year will automatically be identified as a leap year when its last two digits are a multiple of 4. Consequently, leap years up to the year 2099 can automatically be identified as such.

*) The year 2000 is a leap year while the year 2100 is not a leap year.

• Alarm Function

The R2033K/T incorporates the alarm interrupt circuit configured to generate interrupt signals to the CPU at preset times. The alarm interrupt circuit allows two types of alarm settings specified by the Alarm_W registers and the Alarm_D registers. The Alarm_W registers allow week, hour, and minute alarm settings including combinations of multiple day-of-week settings such as "Monday, Wednesday, and Friday" and "Saturday and Sunday". The Alarm_D registers allow hour and minute alarm settings. The Alarm_W outputs from and the Alarm_D outputs also from /INTR pin. Each alarm function can be checked from the CPU by using a polling function.

• High-precision Oscillation Adjustment Function

INTR

pin,

The R2033K/T has built-in oscillation stabilization capacitors (CG and CD), which can be connected to an external crystal oscillator to configure an oscillation circuit. Two kinds of accuracy for this function are alternatives. To correct deviations in the oscillator frequency of the crystal, the oscillation adjustment circuit is configured to allow correction of a time count gain or loss (up to ±1.5ppm or ±0.5ppm at 25°C) from the CPU. The maximum range is approximately ±189ppm (or ±63ppm) in increments of approximately 3ppm (or 1ppm). Such oscillation frequency adjustment in each system has the following advantages: * Allows timekeeping with much higher precision than conventional RTCs while using a crystal oscillator with a wide range of precision variations. * Corrects seasonal frequency deviations through seasonal oscillation adjustme nt. * Allows timekeeping with higher precision particularly with a temperature sensing function out of RTC, through oscillation adjustment in tune with temperature fluctuations.

• Power-on Reset, Oscillation Halt Sensing Function and Supply Voltage Monitoring Function

The R2033K/T incorporates an oscillation halt sensing circuit equipped with internal registers configured to record any past oscillation halt. Power on reset function reset the control resisters when the system is powered on from 0V. At the same time, the fact is memorized to the resister as a flag, thereby identifying whether they are powered on from 0V or battery backed-up. The R2033K/T also incorporates a supply voltage monitoring circuit equipped with internal registers configured to record any drop in supply voltage below a certain threshold value. Supply voltage monitoring threshold

Page 10

R2033K/T

settings can be selected between 1.6V and 1.3V through internal register settings. The sampling rate is normally 1s. The oscillation halt sensing circuit and the power-on reset flag are configured to confirm the established invalidation of time data in contrast to the supply voltage monitoring circuit intended to confirm the potential invalidation of time data. Further, the supply voltage monitoring circuit can be applied to battery supply voltage monitoring.

• Periodic Interrupt Function

The R2033K/T incorporates the periodic interrupt circuit configured to generate periodic interrupt signals aside from interrupt signals generated by the alarm interrupt circuit for output from the signals have five selectable frequency settings of 2 Hz (once per 0.5 seconds), 1 Hz (once per 1 second), 1/60 Hz (once per 1 minute), 1/3600 Hz (once per 1 hour), and monthly (the first day of every month). Further, periodic interrupt signals also have two selectable waveforms, a normal pulse form (with a frequency of 2 Hz or 1 Hz) and special form adapted to interruption from the CPU in the level mode (with second, minute, hour, and month interrupts). The condition of periodic interrupt signals can be monitored with using a pol ling function.

INTR

pin. Periodic interrupt

• 32kHz Clock Output

The R2033K/T incorporates a 32-kHz clock circuit configured to generate clock pulses with the oscillation frequency of a 32.768kHz crystal oscillator for output from the 32KOUT pin. The 32KOUT pin is CMOS push-pull output and the output is enabled and disabled when the CLKC pin is held high, and low or open, respectively. The 32-kHz clock output can be disabled by certain register settings but cannot be disabled without manipulation of any two registers with different addresses to prevent disabling in such events as the runaway of the CPU. The 32-kHz clock circuit is enabled at power-on, when the CLKC pin is held high.

Page 11

R2033K/T

Address Mapping

Address Register Name D a t a A3A2A1A0 D7 D6 D5 D4 D3 D2 D1 D0

0 0 0 0 0 Second Counter -

*2) 1 0 0 0 1 Minute Counter - M40 M20 M10 M8 M4 M2 M1 2 0 0 1 0 Hour Counter - - H20

3 0 0 1 1 Day-of-week Counter - - - - - W4 W2 W1 4 0 1 0 0 Day-of-month Counter - - D20 D10 D8 D4 D2 D1 5 0 1 0 1 Month Counter and

Century Bit 6 0 1 1 0 Year Counter Y80 Y40 Y20 Y10 Y8 Y4 Y2 Y1 7 0 1 1 1 Oscillation Adjustment

(Minute Register) 9 1 0 0 1 Alarm_W

(Hour Register) A 1 0 1 0 Alarm_W

(Day-of-week Register)

B 1 0 1 1 Alarm_D

(Minute Register) C 1 1 0 0 Alarm_D

(Hour Register) D 1 1 0 1 - - - - - - - -

E 1 1 1 0 Control Register 1 *3) WALE DALE F 1 1 1 1 Control Register 2 *3) VDSL VDET

Notes: * 1) All the data listed above accept both reading and writing. * 2) The data marked with "-" is invalid for writing and reset to 0 for reading. * 3) When the PON bit is set to 1 in Control Register 2, all the bits are reset to 0 in Oscillation Adjustment Register, Control Register 1 and Control Register 2 excluding the * 4) When DEV=0, the oscillation adjustment circuit is configured to allow correction of a time count gain

or loss up to ±1.5ppm.

When DEV=1, the oscillation adjustment circuit is configured to allow correction of a time count gain

or loss up to or ±0.5ppm.

* 5) PON is a power-on-reset flag.

/20

DEV

*4)

- WM40 WM20 WM10 WM8 WM4 WM2 WM1

- - WH20

- WW6 WW5 WW4 WW3 WW2 WW1 WW0

- DM40 DM20 DM10 DM8 DM4 DM2 DM1

- - DH20

S40 S20 S10 S8 S4 S2 S1

H10 H8 H4 H2 H1

- - MO10 MO8 MO4 MO2 MO1

F6 F5 F4 F3 F2 F1 F0

WH10 WH8 WH4 WH2 WH1

WP/

DH10 DH8 DH4 DH2 DH1

DP/

XST

/24

CLEN2

PON

*5)

TEST CT2 CT1 CT0

CTFG WAFG DAFG

XST

CLEN1

bit.

Page 12

R2033K/T

• Control Register 1 (ADDRESS Eh)

D7 D6 D5 D4 D3 D2 D1 D0

WALE DALE WALE DALE

0 0 0 0 0 0 0 0 Default Settings *) *) Default settings: Default value means read / written values when the PON bit is set to “1” due to VDD power-on from 0 volts.

12 12

/24 /24

CLEN2 CLEN2

(1) WALE, DALE Alarm_W Enable Bit, Alarm_D Enable Bit

WALE,DALE Description

0 Disabling the alarm interrupt circuit (under the control of the settings

of the Alarm_W registers and the Alarm_D registers).

1 Enabling the alarm interrupt circuit (under the control of the settings

of the Alarm_W registers and the Alarm_D registers)

(2)

(3)

/24

0 Selecting the 12-hour mode with a.m. and p.m. indications. (Default) 1 Selecting the 24-hour mode

Setting the

CLEN2

Setting the specifies generating clock pulses with the oscillation frequency of the 32.768-kHz crystal oscillator for output from the 32KOUT pin. Conversely, setting both the low specifies disabling (”L”) such output.

/24 bit to 0 and 1 specifies the 12-hour mode and the 24-hour mode, respectively.

24-hour mode 12-hour mode 24-hour mode 12-hour mode

00 12 (AM12) 12 32 (PM12) 01 01 (AM 1) 13 21 (PM 1) 02 02 (AM 2) 14 22 (PM 2) 03 03 (AM 3) 15 23 (PM 3) 04 04 (AM 4) 16 24 (PM 4) 05 05 (AM 5) 17 25 (PM 5) 06 06 (AM 6) 18 26 (PM 6) 07 07 (AM 7) 19 27 (PM 7) 08 08 (AM 8) 20 28 (PM 8) 09 09 (AM 9) 21 29 (PM 9) 10 10 (AM10) 22 30 (PM10) 11 11 (AM11) 23 31 (PM11)

/24 bit should precede writing time data

32kHz Clock Output Bit 2

CLEN2

0 Enabling the 32-kHz clock circuit (Default) 1 Disabling the 32-kHz clock circuit

bit or the

/24-hour Mode Selection Bit

CLEN1

bit (D3 in the control register 2) to 0, and the CLKC pin to high

TEST CT2 CT1 CT0 (For Writing) TEST CT2 CT1 CT0 (For Reading)

(Default)

Description

CLEN1

and

CLEN2

bit to 1 or CLKC pin to

Page 13

R2033K/T

(4) TEST Test Bit

TEST Description

0 Normal operation mode. (Default) 1 Test mode.

The TEST bit is used only for testing in the factory and should normally be set to 0.

(5) CT2,CT1, and CT0 Periodic Interrupt Selection Bits

Description CT2 CT1 CT0

Wave form

mode

0 0 0 - OFF(H) (Default) 0 0 1 - Fixed at “L” 0 1 0 Pulse Mode

*1)

0 1 1 Pulse Mode

*1)

1 0 0 Level Mode

*2)

1 0 1 Level Mode

*2)

1 1 0 Level Mode

*2)

1 1 1 Level Mode

*2)

* 1) Pulse Mode: 2-Hz and 1-Hz clock pulses are output in synchronization with the increment of the

second counter as illustrated in the timing chart below.

Interrupt Cycle and Falling Timing

2Hz(Duty50%) 1Hz(Duty50%) Once per 1 second (Synchronized with

second counter increment) Once per 1 minute (at 00 seconds of every minute) Once per hour (at 00 minutes and 00 seconds of every hour) Once per month (at 00 hours, 00 minutes, and 00 seconds of first day of every month)

CTFG Bit

INTR Pin

pprox. 92µs

(Increment of second counter)

Rewriting of the second counter

In the pulse mode, the increment of the second counter is delayed by approximately 92 µs from the falling edge of clock pulses. Consequently, time readings immediately after the falling edge of clock pulses may appear to lag behind the time counts of the real-time clocks by approximately 1 second. Rewriting the second counter will reset the other time counters of less than 1 second, driving the

INTR

pin low.

* 2) Level Mode: Periodic interrupt signals are output with selectable interrupt cycle settings of 1 second,

1 minute, 1 hour, and 1 month. The increment of the second counter is synchronized with the falling edge of periodic interrupt signals. For example, periodic interrupt signals with an interrupt cycle setting of 1 second are output in synchronization with the increment of the second counter as illustrated in the timing chart below.

Page 14

R2033K/T

CTFG Bit

INTR Pin

Setting CTFG bit to 0

(Increment of second counter)

Setting CTFG bit to 0

(Increment of second counter)

*1), *2) When the oscillation adjustment circuit is used, the interrupt cycle will fluctuate once per 20sec. or

60sec. as follows: Pulse Mode: The “L” period of output pulses will increment or decrement by a maximum of ±3.784 ms. For example, 1-Hz clock pulses will have a duty cycle of 50 ±0.3784%. Level Mode: A periodic interrupt cycle of 1 second will increment or decrement by a maximum of

±3.784 ms.

Page 15

R2033K/T

• Control Register 2 (Address Fh)

D7 D6 D5 D4 D3 D2 D1 D0

VDSL VDET VDSL VDET

0 0 *) Default settings: Default value means read / written values when the PON bit is set to “1” due to VDD power-on from 0 volts.

XST XST

Indefinite

PON PON

1 0 0 0 0 Default Settings *)

CLEN1 CLEN1

(1) VDSL VDD Supply Voltage Monitoring Threshold Selection Bit

VDSL Description

0 Selecting the VDD supply voltage monitoring threshold setting of 2.1v. (Default) 1 Selecting the VDD supply voltage monitoring threshold setting of

1.35v.

The VDSL bit is intended to select the VDD supply voltage monitoring threshold settings.

(2) VDET Supply Voltage Monitoring Result Indication Bit

VDET Description

0 Indicating supply voltage above the supply voltage monitoring

threshold settings.

1 Indicating supply voltage below the supply voltage monitoring

threshold settings. Once the VDET bit is set to 1, the supply voltage monitoring circuit will be disabled while the VDET bit will hold the setting of 1. The VDET bit accepts only the writing of 0, which restarts the supply voltage monitoring circuit. Conversely, setting the VDET bit to 1 causes no event.

XST

(3)

The halt sensing. The

Oscillation Halt Sensing Monitor Bit

XST

0 Sensing a halt of oscillation 1 Sensing a normal condition of oscillation

XST

accepts the reading and writing of 0 and 1. The

XST

bit will hold 0 even after the restart of oscillation.

(4) PON Power-on-reset Flag Bit

PON Description

0 Normal condition 1 Detecting VDD power-on -reset (Default)

The PON bit is for sensing power-on reset condition.

* The PON bit will be set to 1 when VDD power-on from 0 volts. The PON bit will hold the setting of 1 even after power-on. * When the PON bit is set to 1, all bits will be reset to 0, in the Oscillation Adjustment Register, Control Register 1, and Control Register 2, except * The PON bit accepts only the writing of 0. Conversely, setting the PON bit to 1 causes no event.

XST

and PON. As a result,

CTFG WAFG DAFG (For Writing) CTFG WAFG DAFG (For Reading)

(Default)

Description

XST

bit will be set to 0 when the oscillation

INTR

pin stops outputting.

Page 16

R2033K/T

CLEN1

(5)

(6) CTFG Periodic Interrupt Flag Bit

The CTFG bit is set to 1 when the periodic interrupt signals are output from the CTFG bit accepts only the writing of 0 in the level mode, which disables (“H”) the enabled (“L”) again in the next interrupt cycle. Conversely, setting the CTFG bit to 1 causes no event.

(7) WAFG,DAFG Alarm_W Flag Bit and Alarm_D Flag Bit

The WAFG and DAFG bits are valid only when the WALE and DALE have the setting of 1, which is caused approximately 61µs after any match between current time and preset alarm time specified by the Alarm_W registers and the Alarm_D registers. The WAFG (DAFG) bit accepts only the writing of 0. outputs off (“H”) when this bit is set to 0. And Conversely, setting the WAFG and DAFG bits to 1 causes no event. The WAFG and DAFG bits will have the reading of 0 when the alarm interrupt circuit is disabled with the WALE and DALE bits set to 0. The settings of the WAFG and DAFG bits are synchronized with the output of the timing chart below.

32kHz Clock Output Bit 1

CLEN1

0 Enabling the 32-kHz clock circuit (Default) 1 Disabling the 32-kHz clock circuit

CLEN1

bit or the

CLEN2

bit (D4 in the control register 1) to 0, and the CLKC pin to high

CTFG Description

0 Periodic interrupt output = “H” (Default) 1 Periodic interrupt output = “L”

WAFG,DAFG Description

0 Indicating a mismatch between current time and preset alarm time (Default) 1 Indicating a match between current time and preset alarm time

INTR

Description

CLEN1

and

CLEN2

bit to 1 or CLKC pin to

INTR

pin (“L”). The

INTR

pin until it is

INTR

pin outputs “L” again at the next preset alarm time.

INTR

pin as shown in the

pprox. 61µs

WAFG(DAFG) Bit

INTR Pin

Writing of 0 to

WAFG(DAFG) bit (Match between current time and preset alarm time)

(Match between current time and preset alarm time)

Writing of 0 to

WAFG(DAFG) bit (Match between current time and preset alarm time)

Page 17

R2033K/T

• Time Counter (Address 0-2h)

Second Counter (Address 0h)

D7 D6 D5 D4 D3 D2 D1 D0

- S40 S20 S10 S8 S4 S2 S1 (For Writing) 0 S40 S20 S10 S8 S4 S2 S1 (For Reading) 0 Indefi

nite

Minute Counter (Address 1h)

D7 D6 D5 D4 D3 D2 D1 D0

- M40 M20 M10 M8 M4 M2 M1 (For Writing) 0 M40 M20 M10 M8 M4 M2 M1 (For Reading) 0 Indefi

nite

Hour Counter (Address 2h)

D7 D6 D5 D4 D3 D2 D1 D0

- -

0 0

0 0 Indefi

*) Default settings: Default value means read / written values when the PON bit is set to “1” due to VDD

* Time digit display (BCD format) as follows: The second digits range from 00 to 59 and are carried to the minute digit in transition from 59 to 00. The minute digits range from 00 to 59 and are carried to the hour digits in transition from 59 to 00. The hour digits range as shown in "P12 • Control Register 1 (ADDRESS Eh) (2)

Mode Selection Bit" and are carried to the day-of-month and day-of-week digits in tran sition from PM11 to

AM12 or from 23 to 00. * Any writing to the second counter resets divider units of less than 1 second. * Any carry from lower digits with the writing of non-existent time may cause the time counters to

malfunction. Therefore, such incorrect writing should be replaced with the writing of existent time data.

Indefi nite

P/ or H20

nite

power-on from 0 volts.

Indefi nite

H10 H8 H4 H2 H1 (For Writing)

H10 H8 H4 H2 H1 (For Reading)

Indefi nite

Default Settings *)

/24: 12/24-hour

Page 18

R2033K/T

• Day-of-week Counter (Address 3h)

D7 D6 D5 D4 D3 D2 D1 D0

- - - - - W4 W2 W1 (For Writing) 0 0 0 0 0 W4 W2 W1 (For Reading) 0 0 0 0 0 Indefi

nite

*) Default settings: Default value means read / written values when the PON bit is set to “1” due to VDD

power-on from 0 volts.

* The day-of-week counter is incremented by 1 when the day-of-week digits are carried to the day-of-month

digits. * Day-of-week display (incremented in septimal notation): (W4, W2, W1) = (0, 0, 0) → (0, 0, 1)→…→(1, 1, 0) → (0, 0, 0) * Correspondences between days of the week and the day-of-week digits are user-definable (e.g. Sunday = 0, 0, 0) * The writing of (1, 1, 1) to (W4, W2, W1) is prohibited except when days of the week are unused.

Indefi nite

Default Settings *)

• Calendar Counter (Address 4-6h)

Day-of-month Counter (Address 4h)

D7 D6 D5 D4 D3 D2 D1 D0

- - D20 D10 D8 D4 D2 D1 (For Writing) 0 0 D20 D10 D8 D4 D2 D1 (For Reading) 0 0 Indefi

nite

Month Counter + Century Bit (Address 5h)

D7 D6 D5 D4 D3 D2 D1 D0

/20

/20 Indefin ite

Year Counter (Address 6h)

D7 D6 D5 D4 D3 D2 D1 D0

Y80 Y40 Y20 Y10 Y8 Y4 Y2 Y1 (For Writing) Y80 Y40 Y20 Y10 Y8 Y4 Y2 Y1 (For Reading) Indefi nite

*) Default settings: Default value means read / written values when the PON bit is set to “1” due to VDD power-on from 0 volts.

* The calendar counters are configured to display the calendar digits in BCD format by using the automatic

calendar function as follows:

The day-of-month digits (D20 to D1) range from 1 to 31 for January, March, May, July, August, October,

and December; from 1 to 30 for April, June, September, and November; from 1 to 29 for February in leap years; from 1 to 28 for February in ordinary years. The day-of-month digits are carried to the month

- - MO10 MO8 MO4 MO2 MO1 (For Writing) 0 0 MO10 MO8 MO4 MO2 MO1 (For Reading) 0 0 Indefi

Indefi nite

nite

Indefi nite

Default Settings *)

Page 19

R2033K/T

,F4,F3,F2,F1,

digits in reversion from the last day of the month to 1. The month digits (MO10 to MO1) range from 1 to 12 and are carried to the year digits in reversion from 12 to 1.

The year digits (Y80 to Y1) range from 00 to 99 (00, 04, 08, …, 92, and 96 in leap years) and are carried to

the The * Any carry from lower digits with the writing of non-existent calendar data may cause the calendar

counters to malfunction. Therefore, such incorrect writing should be replaced with the writing of existent

calendar data.

/20 digits in reversion from 99 to 00.

/20 digits cycle between 0 and 1 in reversion from 99 to 00 in the year digits.

• Oscillation Adjustment Register (Address 7h)

D7 D6 D5 D4 D3 D2 D1 D0

DEV F6 F5 F4 F3 F2 F1 F0 (For Writing) DEV F6 F5 F4 F3 F2 F1 F0 (For Reading)

0 0 0 0 0 0 0 0 Default Settings *) *) Default settings: Default value means read / written values when the PON bit is set to “1” due to VDD power-on from 0 volts.

DEV bit When DEV is set to 0, the Oscillation Adjustment Circuit operates 00, 20, 40 seconds. When DEV is set to 1, the Oscillation Adjustment Circuit operates 00 seconds. F6 to F0 bits The Oscillation Adjustment Circuit is configured to change time counts of 1 second on the basis of

the settings of the Oscillation Adjustment Register at the timing set by DEV. * The Oscillation Adjustment Circuit will not operate with the same timing (00, 20, or 40 seconds) as the timing of writing to the Oscillation Adjustment Register. * The F6 bit setting of 0 causes an increment of time counts by ((F5, F4, F3, F2, F1, F0) - 1) x 2.

The F6 bit setting of 1 causes a decrement of time counts by (( The settings of "*, 0, 0, 0, 0, 0, *" ("*" representing either "0" or "1") in the F6, F5, F4, F3, F2, F1, and

F0 bits cause neither an increment nor decrement of time counts.

Example: If (DEV, F6, F5, F4, F3, F2, F1, F0) is set to (0, 0, 0, 0, 0, 1, 1, 1), when the second digits read 00, 20, or

40, an increment of the current time counts of 32768 + (7 - 1) x 2 to 32780 (a current time count loss).

If (DEV, F6, F5, F4, F3, F2, F1, F0) is set to (0, 0, 0, 0, 0, 0, 0, 1), when the second digits read 00, 20, 40,

neither an increment nor a decrement of the current time counts of 32768.

If (DEV, F6, F5, F4, F3, F2, F1, F0) is set to (1, 1, 1, 1, 1, 1, 1, 0), when the second digits read 00, a

decrement of the current time counts of 32768 + (- 2) x 2 to 32764 (a current time count gain).

An increase of two clock pulses once per 20 seconds causes a time count loss of approximately 3 ppm (2 /

(32768 x 20 = 3.051 ppm). Conversely, a decrease of two clock pulses once per 20 seconds causes a time count gain of 3 ppm. Consequently, when DEV is set to “0”, deviations in time counts can be corrected with a precision of ±1.5 ppm. In the same way, when DEV is set to “1”, deviations in time counts can be corrected with a precision of ±0.5 ppm. Note that the oscillation adjustment circuit is configured to correct deviations in time counts and not the oscillation frequency of the 32.768-kHz clock pulses. For further details, see "P32 Configuration of Oscillation Circuit and Correction of Time Count Deviations • Oscillation Adjustment Circuit".

) + 1) x 2.

Page 20

R2033K/T

• Alarm_W Registers (Address 8-Ah)

Alarm_W Minute Register (Address 8h)

D7 D6 D5 D4 D3 D2 D1 D0

- WM40 WM20 WM10 WM8 WM4 WM2 WM1 (For Writing) 0 WM40 WM20 WM10 WM8 WM4 WM2 WM1 (For Reading) 0 Indefi

nite

Alarm_W Hour Register (Address 9h)

D7 D6 D5 D4 D3 D2 D1 D0

- - WH20

0 0 WH20

0 0 Indefi

Alarm_W Day-of-week Register (Address Ah)

D7 D6 D5 D4 D3 D2 D1 D0

- WW6 WW5 WW4 WW3 WW2 WW1 WW0 (For Writing) 0 WW6 WW5 WW4 WW3 WW2 WW1 WW0 (For Reading) 0 Indefi

nite *) Default settings: Default value means read / written values when the PON bit is set to “1” due to VDD power-on from 0 volts.

* The D5 bit of the Alarm_W Hour Register represents WP/

a.m. and 1 for p.m.) and WH20 when the 24-hour mode is selected (tens in the hour digits). * The Alarm_W Registers should not have any non-existent alarm time settings. (Note that any mismatch between current time and preset alarm time specified by the Alarm_W registers may disable the alarm interrupt circuit.) * When the 12-hour mode is selected, the hour digits read 12 and 32 for 0 a.m. and 0 p.m., respectively.

(See "P12 •Control Register 1 (ADDRESS Eh) (2) * WW0 to WW6 correspond to W4, W2, and W1 of the day-of-week counter with settings ranging from (0, 0,

0) to (1, 1, 0).

* WW0 to WW6 with respective settings of 0 disable the outputs of the Alarm_W Registers.

Indefi nite

WP/

nite

Indefi nite

WH10 WH8 WH4 WH2 WH1 (For Writing)

WH10 WH8 WH4 WH2 WH1 (For Reading)

Indefi nite

/24: 12/24-hour Mode Selection Bit")

Indefi nite

when the 12-hour mode is selected (0 for

Indefi nite

Default Settings *)

Page 21

R2033K/T

Example of Alarm Time Setting

Alarm Day-of-week 12-hour mode 24-hour mode

Preset alarm time Sun. Mon. Tue. Wed. Th. Fri. Sat. 10

hr. 1 hr.

WW0 WW1 WW2 WW3 WW4 WW5 WW6 00:00 a.m. on all days 1 1 1 1 1 1 1 1 2 0 0 0 0 0 0 01:30 a.m. on all days 1 1 1 1 1 1 1 0 1 3 0 0 1 3 0 11:59 a.m. on all days 1 1 1 1 1 1 1 1 1 5 9 1 1 5 9 00:00 p.m. on Mon. to Fri. 01:30 p.m. on Sun. 1 0 0 0 0 0 0 2 1 3 0 1 3 3 0 11:59 p.m. on Mon. ,Wed., and Fri.

0 1 1 1 1 1 0 3 2 0 0 1 2 0 0

0 1 0 1 0 1 0 3 1 5 9 2 3 5 9

10 min. 1 min.

10 hr. 1 hr.

10 min.1 min.

Note that the correspondence between WW0 to WW6 and the days of the week shown in the above table is only an example and not mandatory.

• Alarm_D Register (Address B-Ch)

Alarm_D Minute Register (Address Bh)

D7 D6 D5 D4 D3 D2 D1 D0

- DM40 DM20 DM10 DM8 DM4 DM2 DM1 (For Writing) 0 DM40 DM20 DM10 DM8 DM4 DM2 DM1 (For Reading) 0 Indefi

nite

Alarm_D Hour Register (Address Ch)

D7 D6 D5 D4 D3 D2 D1 D0

- - DH20

0 0 DH20

0 0 Indefi

*) Default settings: Default value means read / written values when the PON bit is set to “1” due to VDD power-on from 0 volts.

* The D5 bit represents DP/

when the 24-hour mode is selected (tens in the hour digits). * The Alarm_D registers should not have any non-existent alarm time settings. (Note that any mismatch between current time and preset alarm time specified by the Alarm_D registers

may disable the alarm interrupt circuit.) * When the 12-hour mode is selected, the hour digits read 12 and 32 for 0a.m. and 0p.m., respectively. (See "P12 •Control Register 1 (ADDRESS Eh) (2)

Indefi nite

DP/

nite

Indefi nite

Default Settings *)

DH10 DH8 DH4 DH2 DH1 (For Writing)

DH10 DH8 DH4 DH2 DH1 (For Reading)

Indefi nite

when the 12-hour mode is selected (0 for a.m. and 1 for p.m.) and DH20

Indefi nite

/24: 12/24-hour Mode Selection Bit")

Indefi nite

Default Settings *)

Page 22

R2033K/T

Interfacing with the CPU

• DATA TRANSFER FORMATS

(1) Timing Between CE Pin Transition and Data Input / Output

The R2033K/T adopts a 3-wire serial interface by which they use the CE (Chip Enable), SCLK (Serial Clock), and SIO (Serial Input/Output) pins to receive and send data to and from the CPU. The 3-wire serial interface provides two types of input/output timings with which the SIO pin output and input are synchronized with the rising or falling edges of the SCLK pin input, respectively, and vice versa. The R2033K/T is configured to select either one of two different input/output timings depending on the level of the SCLK pin in the low to high transition of the CE pin. Namely, when the SCLK pin is held low in the low to high transition of the CE pin, the models will select the timing with which the SIO pin output is synchronized with the rising edge of the SCLK pin input, and the input is synchronized with the falling edge of the SCLK pin input, as illustrated in the timing chart below.

SCLK

SIO (for writing)

SIO (for reading)

CES

Conversely, when the SCLK pin is held high in the low to high transition of the CE pin, the models will select the timing with which the SIO pin output is synchronized with the falling edge of the SCLK pin input, and the input is synchronized with the rising edge of the SCLK pin input, as illustrated in the timing chart below.

SCLK

SIO (for writing)

CES

SIO (for reading)

Page 23

R2033K/T

(2) Data Transfer Formats

Data transfer is commenced in the low to high transition of the CE pin input and completed in its high to low transition. Data transfer is conducted serially in multiple units of 1 byte (8 bits). The former 4 bits are used to specify in the Address Pointer a head address with which data transfer is to be commenced from the host. The latter 4 bits are used to select either reading data transfer or writing data transfer, and to set the Transfer Format Register to specify an appropriate data transfer format. All data transfer formats are designed to transfer the most significant bit (MSB) first.

7582312314

SCL

SIO

A1 A0 C3 C2 C1 C0

Setting

the Address Pointer

Format Register

D7 D6 D3 D2 D1 D0

Writing or Reading data transferSetting the Transfer

Two types of data transfer formats are available for reading data transfer and writing data tran sfer each.

• Writing Data Transfer Formats

(1) 1-byte Writing Data Transfer Format

The first type of writing data transfer format is designed to transfer 1-byte data at a time and can be selected by specifying in the address pointer a head address with which writing data transfer is to be commenced and then writing the setting of 8h to the transfer format register. This 1-byte writing data transfer can be completed by driving the CE pin low or continued by specifying a new head address in the address pointer and setting the data transfer format.

Example of 1-byte Wr i t ing Data Transfer (For Writi ng Dat a t o Addr esses Fh and 7h)

SIO

1 1

Specifying Fh in the

ddress

Pointer

01 0 01 1

Setting 8h in the Transfer Format

Data transfer from the host

Data Data

Writing data to address Fh

0 11 0 0 01 1

Specifying 7h in the

ddress

Pointer

Setting 8h in the Transfer Format

Data transfer from the RTCs

Writing data to address 7h

Page 24

R2033K/T

(2) Burst Writing Data Transfer Format

The second type of writing data transfer format is designed to transfer a sequence of data serially and can be selected by specifying in the address pointer a head address with which writing data transfer is to be commenced and then writing the setting of 0h to the transfer format register. The address pointer is incremented for each transfer of 1-byte data and cycled from Fh to 0h. This burst writing data transfer can be completed by driving the CE pin low.

Example of Burst Writing Data Transfer (For W riting Data to Addresses Eh, Fh, and 0h)

SIO

1 0

Specifying Eh in the

ddress

Pointer

00 0 01 1

Setting 0h in the Transfer Format

Data

Writing data to address Eh

Data

Writing data to address Fh

Data transfer from the host Data transfer from the RTCs

Data

Writing data to address 0h

• Reading Data Transfer Formats

(1) 1-byte Reading Data Transfer Format

The first type of reading data transfer format is designed to transfer 1-byte d ata a t a time and can be sel ecte d by specifying in the Address Pointer a head address with which reading data transfer is to be commenced a nd then the setting of writing Ch to the Transfer Format Register. This 1-byte reading data transfer can be completed by driving the CE pin low or continued by specifying a new head address in the Address Pointer and selecting this type of reading data Transfer Format.

Example of 1-byte Reading Data Transfer (For Readi ng Dat a f r om Addr esses Eh and 2h)

SIO

1 0

11 0 01 1 0 10 1 0 00 1

Data Data

Specifying Eh in the

ddress

Pointer

Setting Ch in the Transfer Format

Reading data from address Eh

Specifying 2h in the

ddress

Pointer

Setting Ch in the Transfer Format

Reading data from address 2h

Data transfer from the host Data transfer from the RTCs

Page 25

R2033K/T

(2) Burst Reading Data Transfer Format

The second type of reading data transfer format is designed to transfer a sequence of data serially and can be selected by specifying in the address pointer a head address with which reading data transfer is to be commenced and then writing the setting of 4h to the transfer format register. The address pointer is incremented for each transfer of 1-byte data and cycled from Fh to 0h. This burst reading data transfer can be completed by driving the CE pin low.

Example of Burst Reading Data Transfer (For Reading Data from Addresses Fh, 0h, and 1h)

1 1

Specifying Fh in the

ddress

Pointer

10 0 01 1

Setting 4h in the Transfer Format

Data transfer from the host Data transfer from the RTCs

DATASIO

Reading data from address Fh

DATA DATA

Reading data from address 0h

Reading data from address 1h

(3) Combination of 1-byte Reading and writing Data Transfer Formats

The 1-byte reading and writing data transfer formats can be combined together and further followe d by any other data transfer format.

Example of Reading Modify Writing Data Transfer

(For Reading and Writing Data from and to Address Fh)

1 1

Specifying Fh in the

ddress

Pointer

11 0 01 1 1 11 0 0 01 1

Setting Ch in the Transfer Format

DATA

Reading data from address Fh

Specifying Fh in the

ddress

Pointer

Setting 8h in the Transfer Format

DATASIO

Writing data to address Fh

Data transfer from the host Data transfer from the RTCs

The reading and writing data transfer formats correspond to the settings in the transfer format register as shown in the table below.

1 Byte Burst

Writing data transfer Reading data transfer

8h (1,0,0,0) Ch (1,1,0,0)

0h (0,0,0,0) 4h (0,1,0,0)

Page 26

R2033K/T

• Considerations in Reading and Writing Time Data under special condition

Any carry to the second digits in the process of reading or writing time data may cause reading or writing erroneous time data. For example, suppose a carry out of 13:59:59 into 14:00:00 occurs in the process of reading time data in the middle of shifting from the minute digits to the hour digits. At this moment, the second digits, the minute digits, and the hour digits read 59 seconds, 59 minutes, and 14 hours, respectively (indicating 14:59:59) to cause the reading of time data deviating from actual time virtually 1 hour. A similar error also occurs in writing time data. To prevent such errors in reading and writing time data, the R2033K/T has the function of temporarily locking any carry to the second digits during the high interval of the CE pin and unlocking such a carry in its high to low transition. Note that a carry to the second digits can be locked for only 1 second, during which time the CE pin should be driven low.

Actual time

Time counts within RTC

The effective use of this function requires the following considerations in reading and writing time data: (1) Hold the CE pin high in each session of reading or writing time data. (2) Ensure that the high interval of the CE pin lasts within 1 second. Should there be any possibility of the host going down in the process of reading or writing time data, make arrangements in the peripheral circuitry as to drive the CE pin low or open at the moment that the host actually goes down. (3) Leave a time span of 31µs or more from the low to high transition of the CE pin to the start of access to addresses 0h to 6h in order that any ongoing carry of the time digits may be completed within this time span. (4) Leave a time span of 62µs or more from the high to low transition of the CE pin to its low to high transition in order that any ongoing carry of the time digits during the high interval of the CE pin may be adjusted within this time span.

The considerations listed in (1), (3), and (4) above are not required when the process of reading or writing time data is obviously free from any carry of the time digits. (e.g. reading or writing time data in synchronization with the periodic interrupt function in the level mode or the alarm interrupt function).

Good and bad examples of reading and writing time data are illustrated on the next page.

13:59:59 14:00:00 14:00:01

Max.62µs

13:59:59

14:00:00

14:00:01

Page 27

R2033K/T

Good Example

Time span of 31µs or more

ny address other than addresses 0h to 6h permits of immediate reading or writing withou requiring a time span of 31 µs.

SIO

ddress Pointer = Fh Transfer Format Register = 4h

DATA

Reading from

ddress Fh

(control2)

DATA F4h

Reading from

ddress 0h

(sec.)

DATA

Reading from

ddress 1h

(min.)

DATA

Reading from

ddress 2h

(hr.)

Bad Example (1) (Where the CE pin is once driven low in the proc es s of reading time data)

31µs or more

CE SIO

0Ch Data Data

ddress Pointer = 0h Transfer Format Register = Ch

Reading from

ddress 0h

(sec.)

14h

ddress Pointer = 1h Transfer Format Register = 4h

Data

Reading from

ddress 1h

(min.)

Reading from

ddress 2h

(hr.)

Bad Example (2) (Where a time span of less than 31µs is left until the start of the process of writing time data)

Time span of less than 31µs

CE SIO

= Fh Transfer Format Register = 0h

Bad Example (3)

F0h

ddress Pointer

Writing to

ddress Fh

(contorl2)

Data Data Data Data

Writing to

ddress 0h

(sec.)

Writing to

ddress 1h

(min.)

Writing to

ddress 2h

(hr.)

(Where a time span of less than 62µs is left between the adjacent processes of reading time data)

Less than 62µs

CE SIO

= 0h Transfer Format Register = Ch

0Ch

ddress Pointer

Data

Reading from

ddress 0h

(sec.)

Data transfer from the host

0Ch

ddress Pointer

= 0h

Data

Transfer Format Register = Ch

Data transfer from RTCs

Data

Reading from

ddress 0h

(sec.)

Page 28

R2033K/T

Configuration of Oscillation Circuit and Correction of Time Count Deviations

• Configuration of Oscillation Circuit

Typical externally-equipped element X’tal : 32.768kHz

OSCIN

Oscillator

Circuit

The oscillation circuit is driven at a constant voltage of approximately 1.2 volts relative to the level of the VSS pin input. As such, it is configured to generate an oscillating waveform with a peak-to-peak voltage on the order of

1.2 volts on the positive side of the VSS pin input.

< Considerations in Handling quartz crystal unit > Generally, quartz crystal units have basic characteristics including an equivalent series resistance (R1) indicating the ease of their oscillation and a load capacitance (CL) indicating the degree of th eir center frequ ency. Particularly, quartz crystal units intended for use in the R2033K/T are recommended to have a typical R1 value of 50kΩ and a typical CL value of 6 to 9pF. To confirm these recommended values, contact the manufacturers of quartz crystal units intended for use in these particular models.

< Considerations in Installing Components around the Oscillation Circuit >

1) Install the quartz crystal unit in the closest possible vicinity to the real-time clock ICs.

2) Avoid laying any signal lines or power lines in the vicinity of the oscillation circuit (particularly in the area marked "A" in the above figure).

3) Apply the highest possible insulation resistance between the OSCIN and OSCOUT pins and the printed circuit board.

4) Avoid using any long parallel lines to wire the OSCIN and OSCOUT pins.

5) Take extreme care not to cause condensation, which leads to various problems such as oscillation halt.

< Other Relevant Considerations >

1) We cannot recommend connecting the external input of 32.768-kHz clock pulses to the OSCIN pin.

2) To maintain stable characteristics of the quartz crystal unit, avoid driving any other IC through 32.768-kHz clock pulses output from the OSCOUT pin.

OSCOUT

32kHz

(R1=30kΩ typ) (CL=6pF to 8pF) Standard values of internal elements CG,CD 10pF typ

Page 29

• Measurement of Oscillation Frequency

R2033K/T

VDD

CLKC

OSCIN

OSCOUT

32KOUT

VSS

32768Hz

Frequency

Counter

* 1) The R2033K/T is configured to generate 32.768-kHz clock pulses for output from the 32KOUT pin. * 2) A frequency counter with 6 (more preferably 7) or more digits on the ord er of 1ppm is re commended for use in the measurement of the oscillation frequency of the oscillation circuit.

• Adjustment of Oscillation frequency

The oscillation frequency of the oscillation circuit can be adjusted by varying procedures depending on the usage of Model R2033K/T in the system into which they are to be built and on the allowable degree of time count errors. The flow chart below serves as a guide to selecting an optimum oscillation frequency adjustment procedure for the relevant system.

Start

Use 32-kHz

YES

clock output?

Use 32-kHz clock output without regard

to its frequency precision

llowable time count precision on order of oscillation frequency variations of crystal oscillator (*1) plus frequency variations of RTC (*2)? (*3)

llowable time count precision on order of oscillation

frequency variations of crystal oscillator (*1) plus frequency variations of RTC (*2)? (*3)

YES

Course (A)

Course (B)

Course (C)

Course (D)

* 1) Generally, quartz crystal units for commercial use are classified in terms of their center frequency depending on their load capacitance (CL) and further divided into ranks on the order of ±10, ±20, and ±50ppm depending on the degree of their oscillation frequency variations. * 2) Basically, Model R2033K/T is configured to cause frequency variations on the order of ±5 to ±10ppm at 25°C. * 3) Time count precision as referred to in the above flow chart is applicable to no rmal temperature an d actually affected by the temperature characteristics and other properties of quartz crystal units.

Page 30

R2033K/T

Course (A) When the time count precision of each RTC is not to be adjusted, the quartz crystal unit intended for use in that RTC may have any CL value requiring no presetting. The quartz crystal unit may be subject to frequency variations which are selectable within the allowable range of time count precision. Several quartz crystal units and RTCs should be used to find the center frequency of the quartz crystal units by the method described in "P29 • Measurement of Oscillation Frequency" and then calculate an appropriate oscillation adjustment value by the method described in "P32 • Oscillation Adjustment Circuit" for writing this value to the R2033K/T.

Course (B) When the time count precision of each RTC is to be adjusted within the oscillation frequency variations of the quartz crystal unit plus the frequency variations of the real-time clock ICs, it becomes necessary to correct deviations in the time count of each RTC by the method described in " P29 • Oscillation Adjustment Circuit". Such oscillation adjustment provides quartz crystal units with a wider range of allowable settings of their oscillation frequency variations and their CL values. The real-time clock IC and the quartz crystal unit intended for use in that real-time clock IC should be used to find the center frequency of the quartz crystal unit by the method described in " P29 • Measurement of Oscillation Frequency" and then confirm the center frequency thus found to fall within the range adjustable by the oscillation adjustment circuit before adjusting the oscillation frequency of the oscillation circuit. At normal temperature, the oscillation frequency of the oscillator circuit can be adjusted by up to approximately ±0.5ppm.

Course (C) Course (C) together with Course (D) requires adjusting the time count precision of each RTC as well as the frequency of 32.768-kHz clock pulses output from the 32KOUT pin. Normally, the oscillation frequency of the crystal oscillator intended for use in the RTCs should be adjusted by adjusting the oscillation stabilizing capacitors CG and CD connected to both ends of the crystal oscillator. The R2033K/T, which incorporate the CG and the CD, require adjusting the oscillation frequency of the crystal oscillator through its CL value. Generally, the relationship between the CL value and the CG and CD values can be repre sented by the following equation: CL = (CG × CD)/(CG + CD) + CS where "CS" represents the floating capacity of the printed circuit board. The crystal oscillator intended for use in the R2033K/T is recommended to have the CL value on the ord er of 6 to 9pF. Its oscillation frequency should be measured by the method described in " P.29 • Measurement of Oscillation Frequency ". Any crystal oscillator found to have an excessively high or low oscillation frequency (causing a time count gain or loss, respectively) should be replaced with another one having a smaller and greater CL value, respectively until another one having an optimum CL value is selected. In this case, the bit settings disabling the oscillation adjustment circuit (see " P.32 • Oscillation Adjustment Circuit") should be written to the oscillation adjustment register. Incidentally, the high oscillation frequency of the crystal oscillator can also be adjusted by adding an external oscillation stabilization capacitor CGOUT or/and CDOUT as illustrated in the diagram below.

Page 31

Oscillator

Circuit

CG RD

OSCIN

32kHz

OSCOUT

CDOUT

R2033K/T

*1) The CGOUT or/and CDOUT should have a

capacitance ranging from 0 to 6 pF.

CGOUT

However, if adding CGOUT and/or CDOUT, Time keeping Voltage and Current will be worse, and it will be hard to oscillate. For reference, the data of Time keeping voltage and current when adding CGOUT=CDOUT=5pF are shown in the table below.

(Topt=-40 to 85°C, V

SS=0v)

PIN Item Condition Min. TYP. MAX. UNITS

Vclk Time Keeping

CGout=CDout=5pF 1.15 5.5 V

Voltage

IDD Time Keeping

Current

VDD=3V, CE, SCLK, SIO, CLKC,

INTR

=0v

0.55

1.20

µA

32KOUT=OFF CGout=CDout=0pF

Course (D) It is necessary to select the crystal oscillator in the same manner as in Course (C) as well as correct errors in the time count of each RTC in the same manner as in Course (B) by the method described in " P.32 • Oscillation Adjustment Circuit ".

Page 32

R2033K/T

• Oscillation Adjustment Circuit

The oscillation adjustment circuit can be used to correct a time count gain or loss with high precision by varying the number of 1-second clock pulses once per 20 seconds or 60 seconds. When DEV bit in the Oscillation Adjustment Register is set to 0, R2033K/T varies number of 1-second clock pulses once per 20 seconds. When DEV bit is set to 1, R2033K/T varies number of 1-second clock pulses once per 60 seconds. The oscillation adjustment circuit can be disabled by writing the settings of "*, 0, 0, 0, 0, 0, *" ("*" representing "0" or "1") to the F6, F5, F4, F3, F2, F1, and F0 bits in the oscillation adjustment circuit. Conversely, when such oscillation adjustment is to be made, an appropriate oscillation adjustment value can be calculated by the equation below for writing to the oscillation adjustment circuit.

(1) When Oscillation Frequency (* 1) Is Higher Than Target Frequency (* 2) (Causing Time Count Gain) When DEV=0: Oscillation adjustment value (*3) = (Oscillation frequency - Target Frequency + 0.1) Oscillation frequency × 3.051 × 10

-6

≈ (Oscillation Frequency – Target Frequency) × 10 + 1 When DEV=1: Oscillation adjustment value (*3) = (Oscillation frequency - Target Frequency + 0.0333) Oscillation frequency × 1.017 × 10

-6

≈ (Oscillation Frequency – Target Frequency) × 30 + 1

* 1) Oscillation frequency: The clock frequency output from the 32KOUT pin at normal temperature in the manner described in "

P29 • Measurement of Oscillation Frequency".

* 2) Target frequency:

Desired frequency to be set. Generally, a 32.768-kHz quartz crystal unit has such temperature

characteristics as to have the highest oscillation frequency at normal temperature. Consequently, the quartz crystal unit is recommended to have target frequency settings on the order of 32.768 to

32.76810 kHz (+3.05ppm relative to 32.768 kHz). Note that the target frequency differs depending on the environment or location where the equipment incorporating the RTC is expected to be operated.

* 3) Oscillation adjustment value:

Value that is to be finally written to the F0 to F6 bits in the Oscillation Adjustment Register and is represented in 7-bit coded decimal notation.

(2) When Oscillation Frequency Is Equal To Target Frequency (Causing Time Count neither Gain nor Loss) Oscillation adjustment value = 0, +1, -64, or –63

Page 33

R2033K/T

(3) When Oscillation Frequency Is Lower Than Target Frequency (Causing Time Count Loss) When DEV=0: Oscillation adjustment value = (Oscillation frequency - Target Frequency) Oscillation frequency × 3.051 × 10 ≈ (Oscillation Frequency – Target Frequency) × 10 When DEV=1: Oscillation adjustment value = (Oscillation frequency - Target Frequency) Oscillation frequency × 1.017 × 10 ≈ (Oscillation Frequency – Target Frequency) × 30

Oscillation adjustment value calculations are exemplified below

(A) For an oscillation frequency = 32768.85Hz and a target frequency = 32768.05Hz When setting DEV bit to 0: Oscillation adjustment value = (32768.85 - 32768.05 + 0.1) / (32768.85 × 3.051 × 10 ≈ (32768.85 - 32768.05) × 10 + 1 = 9.001 ≈ 9 In this instance, write the settings (DEV,F6,F5,F4,F3,F2,F1,F0)=(0,0,0,0,1,0,0,1) in the oscillation adjustment register. Thus, an appropriate oscillation adjustment value in the presence of any time count gain represents a distance from 01h.

When setting DEV bit to 1: Oscillation adjustment value = (32768.85 - 32768.05 + 0.0333) / (32768.85 × 1.017 × 10 ≈ (32768.85 - 32768.05) × 30 + 1 = 25.00 ≈ 25 In this instance, write the settings (DEV,F6,F5,F4,F3,F2,F1,F0)=(1,0,0,1,1,0,0,1) in the oscillation adjustment register.

(B) For an oscillation frequency = 32762.22Hz and a target frequency = 32768.05Hz

When setting DEV bit to 0: Oscillation adjustment value = (32762.22 - 32768.05) / (32762.22 × 3.051 × 10 ≈ (32762.22 - 32768.05) × 10 = -58.325 ≈ -58 To represent an oscillation adjustment value of - 58 in 7-bit coded decimal notation, subtract 58 (3Ah) from 128 (80h) to obtain 46h. In this instance, write the settings of (DEV,F6,F5,F4,F3,F2,F1,F0) = (0,1,0,0,0,1,1,0) in the oscillation adjustment register. Thus, an appropriate oscillation adjustment value in the presence of any time count loss represents a distance from 80h.

When setting DEV bit to 1: Oscillation adjustment value = (32762.22 - 32768.05) / (32762.22 × 1.017 × 10 ≈ (32762.22 - 32768.05) × 30 = -174.97 ≈ -175

Oscillation adjustment value can be set from -62 to 63. Then, in this case, Oscillation adjustment value is out of range.

-6

)

-6

)

-6

)

-6

)

Page 34

R2033K/T

(4) Difference between DEV=0 and DEV=1 Difference between DEV=0 and DEV=1 is following,

DEV=0 DEV=1

Maximum value range -189.2ppm to 189.2ppm -62ppm to 63ppm Minimum resolution 3ppm 1ppm

Notes: If following 3 conditions are completed, actual clock adjustment value could be different from target

adjustment value that set by oscillator adjustment function.

1. Using oscillator adjustment function

2. Access to R2033K/T at random, or synchronized with external clock that has no relatio n to R2033K/T, or synchronized with periodic interrupt in pulse mode.

3. Access to R2033K/T more than 2 times per each second on average.

For more details, please contact to Ricoh.

• How to evaluate the clock gain or loss

The oscillator adjustment circuit is configured to change time counts of 1 second on the basis of the settings of the oscillation adjustment register once in 20 seconds or 60 seconds. The oscillation adjustment circuit does not effect the frequency of 32768Hz-clock pulse output from the 32KOUT pin. Therefore, after writing the oscillation adjustment register, we cannot measure the clock error with probing 32KOUT clock pulses. The way to measure the clock error as follows:

(1) Output a 1Hz clock pulse of Pulse Mode with interrupt pin Set (0,0,x,x,0,0,1,1) to Control Register 1 at address Eh.

(2) After setting the oscillation adjustment register, 1Hz clock period changes every 20seconds ( or every 60 seconds) like next page figure.

1Hz clock pulse

T0 T0 T0 T1

1 time19 times

Measure the interval of T0 and T1 with frequency counter. A frequency counter with 7 or more digits is recommended for the measurement.

(3) Calculate the typical period from T0 and T1 T = (19×T0+1×T1)/20 Calculate the time error from T.

Page 35

Power-on Reset, Oscillation Halt Sensing, and Supply Voltage Monitoring

R2033K/T

• PON,

The power-on reset circuit is configured to reset control register1, 2, and clock adjustment register when VDD power up from 0v. The oscillation halt sensing circuit is configured to record a halt on oscillation by 32.768-kHz clock pulses. The supply voltage monitoring circuit is configured to record a drop in supply voltage below a threshold voltage of 1.6 or 1.3v. Each function has a monitor bit. I.e. the PON bit is for the power-on reset circuit, and oscillation halt sensing circuit, and VDET is for the supply voltage monitoring circuit. PON and VDET bits are activated to “H”. However,

XST

0, and The functions of these three monitor bits are shown in the table below.

The relationship between the PON,

XST

, and VDET

XST

bit is for the

XST

bit is activated to “L”. The PON and VDET accept only the writing of 0, but

accepts the writing of 0 and 1. The PON bit is set to 1, when VDD power-up from 0V, but VDET is set to

XST

is indefinite.

PON

Function Monitoring for the

power-on reset function

Address D4 in Address Fh D5 in Address Fh D6 in Address Fh Activated High Low High When VDD power up from 0v accept the writing 0 only Both 0 and 1 0 only

PON

0 0 0 Halt on oscillation, but no drop in

0 0 1 Halt on oscillation and drop in VDD

0 1 0 No drop in VDD supply voltage

0 1 1 Drop in VDD supply voltage below

1 * * Drop in supply voltage to 0v Power-up from 0v,

XST

1 indefinite 0

XST

, and VDET is shown in the table below.

VDET Conditions of supply voltage and

oscillation

VDD supply voltage below threshold voltage

supply voltage below threshold voltage, but no drop to 0V

below threshold voltage and no halt in oscillation

threshold voltage and no halt on oscillation

Monitoring for the oscillation halt sensing function

a drop in supply voltage below a threshold voltage of 1.6 or 1.3v

Condition of oscillator, and

back-up status

Halt on oscillation cause of condensation etc.

Halt on oscillation cause of drop in back-up battery voltage

Normal condition

No halt on oscillation, but drop in back-up battery voltage

VDET

Page 36

R2033K/T

)

32768Hz Oscillation

Power-on reset flag

(PON)

Oscillation halt

sensin

monitor flag (VDET)

flag (XST

Supply voltage

Threshold voltage (1.6v or 1.3v)

VDD

Internal initialization

period (1 to 2 sec.)

VDET←0 XST←1 PON←0

VDET←0 XST←1 PON←1

Internal initialization

period (1 to 2 sec.)

VDET←0 XST←1 PON←0

When the PON bit is set to 1 in the control register 2, the DEV, F6 to F0, WALE, DALE, CT2, CT1, CT0, VDSL, VDET,

CLEN1

, CTFG, WAFG, and DAFG bits are reset to 0 in the oscillation

/24,

CLEN2

, TEST,

adjustment register, the control register 1, and the control register 2. The PON bit is also set to 1 at power-on from 0v.

< Considerations in Using Oscillation Halt Sensing Circuit > Be sure to prevent the oscillation halt sensing circuit from malfunctioning by preventing the following:

1) Instantaneous power-down on the VDD

2) Condensation on the crystal oscillator

3) On-board noise to the crystal oscillator

4) Applying to individual pins voltage exceeding their respective maximum ratings

In particular, note that the

XST

bit may fail to be set to 0 in the presence of any applied supply voltage as illustrated below in such events as backup battery installation. Further, give special considerations to prevent excessive chattering in the oscillation halt sensing circuit.

VDD

Page 37

R2033K/T

(

)

(

)

• Voltage Monitoring Circuit

The supply monitoring circuit is configured to conduct a sampling operation during an interval of 7.8ms per second to check for a drop in supply voltage below a threshol d voltage of 1.6 or 1.3v for the V DSL bit setting of 0 (the default setting) or 1, respectively, in the Control Register 2, thus minimizing supply current requirements as illustrated in the timing chart below. This circuit suspends a sampling operation once the VDET bit is set to 1 in the Control Register 2. The supply voltage monitor is useful for back-up battery checking.

Sampling timing for

VDD supply voltage

D6 in Address Fh

VDD

PON

VDET

Internal initialization period

1 to 2sec.

PON←0 VDET

←0

1.6v or 1.3v

7.8ms

VDET←0

Page 38

R2033K/T

Alarm and Periodic Interrupt

The R2033K/T incorporates the alarm interrupt circuit and the periodic interrupt circuit that are configured to generate alarm signals and periodic interrupt signals for output from the

(1) Alarm Interrupt Circuit The alarm interrupt circuit is configured to generate alarm signals for output from the (enabled) upon the occurrence of a match between current time read by the time counters (the day-of-week, hour, and minute counters) and alarm time preset by the alarm registers (the Ala rm_W regi sters intend ed for the day-of-week, hour, and minute digit settings and the Alarm_D registers intended for the hour and minute digit settings).

(2) Periodic Interrupt Circuit The periodic interrupt circuit is configured to generate either clock p ulses in the pulse mode o r interrupt signals in the level mode for output from the register 1.

The above two types of interrupt signals are monitored by the flag bits (i.e. the WAFG, DAFG, and CTFG bits in the Control Register 2) and enabled or disabled by the enable bits (i.e. the WALE, DALE, CT2, CT1, and CT0 bits in the Control Register 1) as listed in the table below.

Flag bits Enable bits

Alarm_W WAFG

(D1 at Address Fh)

Alarm_D DAFG

(D0 at Address Fh)

Peridic interrupt CTFG

(D2 at Address Fh)

* At power-on, when the WALE, DALE, CT2, CT1, and CT0 bits are set to 0 in the Control Register 1, the * When two types of interrupt signals are output simultaneously from the

INTR

pin is driven high (disabled).

INTR

pin becomes an OR waveform of their negative logic.

INTR

pin depending on the CT2, CT1, and CT0 bit settings in the control

WALE (D7 at Address Eh) DALE (D6 at Address Eh) CT2=CT1=CT0=0 (These bit setting of “0” disable the Periodic Interrupt) (D2 to D0 at Address Eh)

INTR

pin as described below.

INTR

pin, the output from the

, which is driven low

Example: Combined Output to INTR Pin Under Control of Alarm_D and Periodic Interrupt

Alarm_D

Periodic Interrupt

In this event, which type of interrupt signal is output from the DAFG, and CTFG bit settings in the Control Register 2.

INTR

pin can be confirmed by reading the

Page 39

R2033K/T

• Alarm Interrupt

The alarm interrupt circuit is controlled by the enable bits (i.e. the WALE and DALE bits in the Control Register 1) and the flag bits (i.e. the WAFG and DAFG bits in the Control Register 2). The enable bits can be used to enable this circuit when set to 1 and to disable it when set to 0. When intended for reading, the flag bits can be used to monitor alarm interrupt signals. When intended for writing, the flag bits will cause no event when set to 1 and will drive high (disable) the alarm interrupt circuit when set to 0. The enable bits will not be affected even when the flag bits are set to 0. In this event, therefore, the alarm interrupt circuit will continue to function until it is driven low (enabled) upon the next occurrence of a match between current time and preset alarm time.

The alarm function can be set by presetting desired alarm time in the alarm registers (the Alarm_W Regist ers for the day-of-week digit settings and both the Alarm_W Registers and the Alarm_D Registers for the hour and minute digit settings) with the WALE and DALE bits once set to 0 and then to 1 in the Control Register 1. Note that the WALE and DALE bits should be once set to 0 in order to disable the alarm interrupt circuit upon the coincidental occurrence of a match between current time and preset alarm time in the process of setting the alarm function.

Interval (1min.) during which a match between current time and preset alarm time occurs

INTR

WALE←1 (DALE)

current time = preset alarm time

WALE←0 (DALE)

WAFG←0 (DAFG)

WALE←1 (DALE)

current time = preset alarm time

After setting WALE(DALE) to 0, Alarm registers is set to current time, and WALE(DALE) is set to 1, be not driven to “L” immediately,

INTR

will be driven to “L” at next alarm setting time.

INTR

will

Page 40

R2033K/T

• Periodic Interrupt

Setting of the periodic selection bits (CT2 to CT0) enables periodic interrupt to the CPU. There are two waveform modes: pulse mode and level mode. In the pulse mode, the output has a waveform duty cycle of around 50%. In the level mode, the output is cyclically driven low and, when the CTFG bit is set to 0, the output is return to High (OFF).

CT2 CT1 CT0

Wave form

mode

0 0 0 - OFF(H) (Default) 0 0 1 - Fixed at “L” 0 1 0 Pulse Mode *1) 2Hz(Duty50%) 0 1 1 Pulse Mode *1) 1Hz(Duty50%) 1 0 0 Level Mode *2) Once per 1 second (Synchronized with

1 0 1 Level Mode *2) Once per 1 minute (at 00 seconds of every 1 1 0 Level Mode *2) Once per hour (at 00 minutes and 00 1 1 1 Level Mode *2) Once per month (at 00 hours, 00 minutes,

*1) Pulse Mode: 2-Hz and 1-Hz clock pulses are output in synchronization with the increment of the second counter as illustrated in the timing chart below.

Description

Interrupt Cycle and Falling Timing

Second counter increment) Minute) Seconds of every hour) and 00 seconds of first day of every month)

*2) Level Mode: Periodic interrupt signals are output with selectable interrupt cycle settings of 1 second, 1 minute, 1 hour, and 1 month. The increment of the second counter is synchronized with the falling edge of periodic interrupt signals. For example, periodic interrupt signals with an interrupt cycle setting of 1 second are output in synchronization with the increment of the second counter as illustrated in the timing chart below.

CTFG Bit

INTR Pin

pprox. 92µs

(Increment of second counter)

INTR

pin low.

Rewriting of the second counter

Page 41

R2033K/T

CTFG Bit

INTR Pin

Setting CTFG bit to 0

(Increment of second counter)

Setting CTFG bit to 0

(Increment of second counter)

*1), *2) When the oscillation adjustment circuit is used, the interrupt cycle will fluctuate once per 20sec. as follows: Pulse Mode: The “L” period of output pulses will increment or decrement by a maximum of ±3.784ms. For example, 1-Hz clock pulses will have a duty cycle of 50 ±0.3784%. Level Mode: A periodic interrupt cycle of 1 second will increment or decrement by a maximum of ±3.784ms.

• 32-kHz CLOCK OUTPUT

For the R2033K/T, 32.768-kHz clock pulses are output from the 32KOUT pin when either the Control Register 2 or the

CLEN2

bit in the Control Register 1 is set to 0 when the CLKC pin is set to high. If

the condition is not satisfied, the output is set to low.

CLEN1

(D3 at Address Fh)

CLEN2

(D4 at Address Eh)

CLKC pin input 32KOUT PIN

(CMOS push-pull output)

1 1 *

* * 0

0(Default) * 1

* 0(Default) 1

The 32KOUT pin output is synchronized with the

CLEN1

and

CLEN2

bit and CLKC pin settings as

illustrated in the timing chart below.

CLEN1

“L”

Clock pulses

bit in the

CLKC pin or CLEN1 or

CLEN2 bit setting

32KOUT PIN

Max.62.0µs

Page 42

R2033K/T

Typical Applications

• Typical Power Circuit Configurations

Sample circuit configuration 1 R1163xxx1B is a series regulator with the reverse current protection circuit. The CE pin should be pull-up to system power supply voltage, and ECO pin should be connect to system power supply or VSS. Please select VOUT voltage equal to the CPU power supply voltage that interfaces to R2033K/T and SRAM.

VDD

Primary

VSS

Battery

Sample circuit configuration 2

OSCOUT

OSCIN

VDD

32768Hz

System Power Supply

SRAM

etc.

System power supply

VOUT VDD

R1163xxx1B

ECO

VSS

*1) Install bypass capacitors fo high-frequency and low-frequenc applications in parallel in close vicinity to the R2033K/T.

VSS

OSCIN

OSCOUT

VDD

VSS

Primary Battery

32768Hz

System power supply

Secondary Battery

Page 43

R2033K/T

• Connection of

INTR

The

pin follows the N-channel open drain output logic and contains no protective diode on the power

INTR

supply side. As such, it can be connected to a pull-up resistor of up to 5.5v regardless of supply voltage.

System power supply

*1) Depending on whether the

INTR used during battery backup, it should be connected to a pull-up resistor at the following different positions:

(1) Position A in the left diagram when it is not to

be used during battery backup.

(2) Position B in the left diagram when it is to be

used during battery backup.

INTR

OSCIN

OSCOUT

VDD

VSS

*1)

32768Hz

Backup power supply

• Connection of 32KOUT Pin

pin is

As the 32KOUT pin is CMOS output, the supply voltage of the R2033K/T and any devices to be connected should be the same. When the device is powered down, the 32KOUT output pin should be disabled. When the CLKC pin is connected to the system power supply through the pull-up resistor, the pull-up resistor should be 0Ω to 10kΩ, and the 32KOUT pin should be connect to the host device through the resistor (approx. 10kΩ)

CLKC

32KOUT

VDD

VSS

R3111

XXXXC

Back-up Power Supply

CPU Power Supply

CLKC

32KOUT

VDD

VSS

CPU Power Supply

0 to 10K

Approx.10K

Ω

Back-up Power supply

CPU

Page 44

R2033K/T

Typical Characteristics

Test circuit

OSCOUT

VDD

OSCIN

32KOUT

VSS

CGOUT

32768Hz

CDOUT

Frequency

Counter

X’tal : 32.768kHz (R1=50kΩ typ) (CL=6pF to 9pF) Topt : 25°C Output pins : Open

Timekeeping Current vs. Supply Voltage Timekeeping Current vs. Supply Voltage (with no 32kHz clock output) (with 32kHz clock output) (Output=Open, Topt=25°C) (Output=Open, Topt=25°C)

0.8

0.6

0.4

0.2

(CGout, CDout)=(5pF, 5pF)

(CGout, CDout)=(0pF, 0pF)

2.5

(CGout, CDout)=(5pF, 5pF)

1.5 1

0.5

(CGout, CDout)=(0pF, 0pF)

Timekeeping Current IDD(uA)

0123456

Supply Vlotage VDD(v)

Timekeeping Current IDD(uA)

0123456

Supply Voltage VDD(v)

CPU Access Current vs. SCLK Clock Frequency Timekeeping Current vs. Operating Temperature (Output pins=Open, Topt=25°C, CGout=CDout=0pF) (Output pins=Open, CGout=CDout=0pF)

80 70 60 50 40 30 20 10

CPU Access Current IDD(uA)

0 200 400 600 800 1000

SCL Clock Frequency (kHz)

DD=5v

DD=3v

1.8

1.6

1.4

1.2

0.8

0.6

0.4

0.2

Timekeeping Current IDD(uA)

with 32kHz clock output

with no 32kHz clock outpu

-50 -25 0 25 50 75 100

Operating Temperature Topt(Celcius)

Page 45

R2033K/T

Oscillation Frequency Deviation vs. External CGout Oscillation Frequency Deviation vs. Supply Voltage

DD=3v, Topt=25°C, CGout=CDout=0pF as standard) (Topt=25°C,VDD=3v as standard)

-10

-20

-30

-40

-50

(ppm)

-60

-70

-80

-90

-100

Oscillation Frequency Deviation

0 5 10 15 20

External CGout (pF)

CDout=0pF

CDout=5pF

5 4 3 2 1 0

(ppm)

-1

-2

-3

-4

-5

Oscillation Frequency Deviation

0123456

Supply Voltage VDD (v)

Oscillation Frequency Deviation vs. V

OL vs. IOL (

INTR Operating Temperature (Topt=25°C) (V

DD=3V, Topt=25°C as standard)

-20

-40

-60

(ppm)

-80

-100

-120

Oscillation Frequency Deviation

-60 -40 -20 0 20 40 60 80 10

Operating TemperatureTopt(Celsius)

30 25 20 15

IOL (mA)

5 0

0 0.1 0.2 0.3 0.4 0.5

pin)

VOL (v)

DD=5v

DD=3v

DD=1.5v

Page 46

R2033K/T

Typical Software-based Operations

• Initialization at Power-on

Start

*1)

Power-on

*2)

PON=1?

Yes

*4)

Set Oscillation Adju stment

*1) After power-on from 0 volt, the start of oscillation and the process of internal initialization require a time span on 1to 2seconds, so that access should be done after the lapse of this time span or more. *2) The PON bit setting of 0 in the Control Register 1 indicates power-on from backup battery and not from 0v. For further details, see "P.35 • PON, *3) This step is not required when the supply voltage monitoring circuit is not used. *4) This step involves ordinary initialization including the Oscillation Adjustment Register and i nterrupt cycle settings, etc.

VDET=0?

Yes

XST

*3)

, VDET".

Warning Back-up

Run-down

Batter

• Writing of Time and Calendar Data

CE←H

Write to Time Counter and

Calendar Counter

CE←L

*1)

*2)

*3)

*1) When writing to clock and calendar counters, do not insert CE=L

until all times from second to year have been written to prevent error in writing time. (Detailed in "P.24 •Considerations in Reading and Writing Time Data under special condition".

*2) Any writing to the second counter will reset divider units lower

than the second digits.

The R2033K/T may also be initialized not at power-on but in the

process of writing time and calendar data.

Page 47

• Reading Time and Calendar Data

(1) Ordinary Process of Reading Time and Calendar Data

CE←H

Read from Time Counter

and Calendar Counter

*1)

*1) When reading to clock and calendar counters, do not insert

CE=L until all times from second to year have been read to prevent error in reading time. (Detailed in "P.24

•Considerations in Reading and Writing Time Data under

special condition".

R2033K/T

CE←L

*1)

(2) Basic Process of Reading Time and Calendar Data with Periodic Interrupt Function

Set Periodic Interrupt

Cycle Selection Bits

Generate Interrupt in CPU

CTFG=1?

Yes

Read from Time Counter

and Calendar Counter

Control Register 2

(X1X1X011)

←

*2)

*3)

*1)

Other Interrupt

Processes

*1) This step is intended to select the level mode

as a waveform mode for the periodic interrupt function.

*2) This step must be completed within 0.5

second.

*3) This step is intended to set the CTFG bit to 0

in the Control Register 2 to cancel an interrupt to the CPU.

Page 48

R2033K/T

(3) Applied Process of Reading Time and Calendar Data with Periodic Interrupt Function

Time data need not be read from all the time counters when used for such ordinary purposes as time count indication. This applied process can be used to read time and calendar data with substantial reductions in the load involved in such reading.

For Time Indication in "Day-of-Month, Day-of-week, Hour, Minute, and Second" Format:

Control Register 1

(XXXX0100)

Control Register 2

(X1X1X011)

Generate interrupt to CPU

CTFG=1?

Yes

Sec.=00?

Yes

Read Min.,Hr.,Day,

and Day-of-week

←

*2)

*1)

Other interrupts

*3)

Use Previous Min.,Hr.,

Day,and Day-of-week data

Processes

*1) This step is intended to select the

level mode as a waveform mode for the periodic interrupt function.

*2) This step must be completed within

0.5 sec.

*3) This step is intended to read time

data from all the time counters only in the first session of reading time data after writing time data.

*4) This step is intended to set the

CTFG bit to 0 in the Control Register 2 to cancel an interrupt to the CPU.

Control Register 2

(X1X1X011)

←

*4)

Page 49

• Interrupt Process

(1) Periodic Interrupt

Set Periodic Interrupt

Cycle Selection Bits

Generate Interrupt to CPU

CTFG=1?

Yes

Conduct

Periodic Interru

Control Register 2

(X1X1X011)

←

*2)

*1)

Other Interrupt

Processes

R2033K/T

*1) This step is intended to select the level mode

as a waveform mode for the periodic interrupt function.

*2) This step is intended to set the CTFG bit to 0

in the Control Register 2 to cancel an interrupt to the CPU.

Page 50

R2033K/T

(2) Alarm Interrupt

WALE or DALE←0

*1)

Set Alarm Min., Hr ., and

Day-of- week Regi ster s

WALE or DALE←1

Generate Interrupt to CPU

WAFG or DAFG=1?

Yes

Conduct Alarm Interrupt

*3)

Control Register 2 ←

(X1X1X101)

*2)

Other Interrupt

Processes

*1) This step is intended to once disable the alarm

interrupt circuit by setting the WALE or DALE bits to 0 in anticipation of the coincidental occurrence of a match between current time and preset alarm time in the process of setting the alarm interrupt function.

*2) This step is intended to enable the alarm

interrupt function after completion of all alarm interrupt settings.

*3) This step is intended to once cancel the alarm

interrupt function by writing the settings of "X,1,X, 1,X,1,0,1" and "X,1,X,1,X,1,1,0" to the Alarm_W Registers and the Alarm_D Registers, res

ectively.

Datasheet R2033K, R2033T Datasheet (RICOH)

Specifications and Main Features

Frequently Asked Questions

User Manual