Datasheet R1LP0408-70, R1LP0408-55 Specification

R1LP0408C-I Series

Wide Temperature Range Version
4M SRAM (512-kword × 8-bit)

REJ03C0067-0200Z

Rev. 2.00

May.26.2004

Description

The R1LP0408C-I is a 4-Mbit static RAM organized 512-kword × 8-bit. R1LP0408C-I Series has realized
higher density, higher performance and low power consumption by employing CMOS process technology
(6-transistor memory cell). The R1LP0408C-I Series offers low power standby power dissipation;
therefore, it is suitable for battery backup systems. It has packaged in 32-pin SOP, 32-pin TSOP II.

Features

• Single 5 V supply: 5 V ± 10%

• Access time: 55/70 ns (max)

• Power dissipation:
 Active: 10 mW/MHz (typ)
 Standby: 4 µW (typ)

• Completely static memory.
 No clock or timing strobe required

• Equal access and cycle times

• Common data input and output.
 Three state output

• Directly TTL compatible.
 All inputs and outputs

• Battery backup operation.

• Operating temperature: −40 to +85°C

Rev.2.00, May.26.2004, page 1 of 12

R1LP0408C-I Series

Ordering Information

Type No. Access time Package

R1LP0408CSP-5SI 55 ns 525-mil 32-pin plastic SOP (32P2M-A)
R1LP0408CSP-7LI 70 ns
R1LP0408CSB-5SI 55 ns 400-mil 32-pin plastic TSOP II (32P3Y-H)
R1LP0408CSB-7LI 70 ns
R1LP0408CSC-5SI 55 ns 400-mil 32-pin plastic TSOP II reverse (32P3Y-J)
R1LP0408CSC-7LI 70 ns

Rev.2.00, May.26.2004, page 2 of 12

R1LP0408C-I Series

Pin Arrangement

32-pin SOP
32-pin TSOP

32-pin TSOP (reverse)

A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
V

SS

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

(Top view)

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

V

CC

A15
A17
WE#
A13
A8
A9
A11
OE#
A10
CS#
I/O7
I/O6
I/O5
I/O4
I/O3

Pin Description

Pin name Function

A0 to A18 Address input
I/O0 to I/O7 Data input/output
CS# (CS) Chip select
OE# (OE) Output enable
WE# (WE) Write enable
VCC Power supply
VSS Ground

V

CC

A15
A17
WE#
A13
A8
A9
A11
OE#
A10
CS#
I/O7
I/O6
I/O5
I/O4
I/O3

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

(Top view)

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
V

SS

Rev.2.00, May.26.2004, page 3 of 12

R1LP0408C-I Series

Block Diagram

LSB

MSB

A11

A9

A8
A15
A18
A10
A13
A17
A16
A14
A12

I/O0

I/O7

Row
Decoder

Input
Data
Control

•

•

•

•

•

•

•

LSB

Memory Matrix
2,048 2,048

Column Decoder

A3 A2A1A0 A6A5

•

•

×

Column I/O

A4 A7

MSB

V

CC

V

SS

•

•

CS#

WE#

OE#

Rev.2.00, May.26.2004, page 4 of 12

Timing Pulse Generator

Read/Write Control

R1LP0408C-I Series

Operation Table

WE# CS# OE# Mode VCC current I/O0 to I/O7 Ref. cycle

, I

× H × Not selected I

High-Z 

SB

SB1

H L H Output disable ICC High-Z 
H L L Read ICC Dout Read cycle
L L H Write ICC Din Write cycle (1)
L L L Write ICC Din Write cycle (2)
Note: H: VIH, L: VIL, ×: VIH or VIL

Absolute Maximum Ratings

Parameter Symbol Value Unit

Power supply voltage relative to V

V

SS

Terminal voltage on any pin relative to VSS V
Power dissipation PT 0.7 W
Operating temperature Topr −40 to +85 °C
Storage temperature range Tstg −65 to +150 °C
Storage temperature range under bias Tbias −40 to +85 °C
Notes: 1. VT min: −3.0 V for pulse half-width ≤ 30 ns.

2. Maximum voltage is +7.0 V.

−0.5 to +7.0 V

CC

−0.5*1 to VCC + 0.3*2 V

T

DC Operating Conditions

(Ta = −40 to +85°C)

Parameter Symbol Min Typ Max Unit

Supply voltage VCC 4.5 5.0 5.5 V
V
Input high voltage VIH 2.2  V
Input low voltage VIL −0.3*1  0.8 V
Note: 1. VIL min: −3.0 V for pulse half-width ≤ 30 ns.

Rev.2.00, May.26.2004, page 5 of 12

0 0 0 V

SS

+ 0.3 V

CC

R1LP0408C-I Series

DC Characteristics

Parameter Symbol Min Typ Max Unit Test conditions

Input leakage current |I
Output leakage current |ILO|   1 µA CS# = VIH or OE# = VIH or

Operating current ICC  1.5*1 3 mA CS# = VIL,

Average operating current I

I

Standby current ISB  0.1*1 0.5 mA CS# = VIH
Standby current

−5SI

to +85°C I
to +70°C I
to +40°C I
to +25°C I

−7LI

to +85°C I
to +70°C I
to +40°C I

to +25°C I
Output low voltage VOL   0.4 V IOL = 2.1 mA
Output high voltage VOH 2.4   V IOH = −1.0 mA
V
Notes: 1. Typical values are at VCC = 5.0 V, Ta = +25°C and specified loading, and not guaranteed.

2. Typical values are at V

= 5.0 V, Ta = +40°C and specified loading, and not guaranteed.

CC

|   1 µA Vin = VSS to VCC

LI

WE# = VIL or V

Others = VIH/ VIL, I

 8*1 25 mA Min. cycle, duty = 100%,

CC1

= VSS to VCC

I/O

= 0 mA

I/O

CS# = VIL, Others = VIH/V
I

= 0 mA

I/O

 2*1 5 mA Cycle time = 1 µs,

CC2

duty = 100%,
I

= 0 mA, CS# ≤ 0.2 V,

I/O

VIH ≥ VCC − 0.2 V, VIL ≤ 0.2 V

  10 µA Vin ≥ 0 V, CS# ≥ VCC − 0.2 V

SB1

  8 µA

SB1

 1.0*2 3 µA

SB1

 0.8*1 3 µA

SB1

  20 µA

SB1

  16 µA

SB1

 1.0*2 10 µA

SB1

 0.8*1 10 µA

SB1

2.6   V IOH = −0.1 mA

OH2

IL

Capacitance

(Ta = +25°C, f = 1.0 MHz)

Parameter Symbol Min Typ Max Unit Test conditions Note
Input capacitance Cin   8 pF Vin = 0 V 1
Input/output capacitance C

Note: 1. This parameter is sampled and not 100% tested.

Rev.2.00, May.26.2004, page 6 of 12

  10 pF V

I/O

= 0 V 1

I/O

R1LP0408C-I Series

AC Characteristics

(Ta = −40 to +85°C, VCC = 5 V ± 10%, unless otherwise noted.)

Test Conditions

• Input pulse levels: V

= 0.4 V, VIH = 2.4 V

IL

• Input rise and fall time: 5 ns

• Input and output timing reference levels: 1.5 V

• Output load: 1 TTL Gate + C

1 TTL Gate + C

(50 pF) (R1LP0408C-5SI)

L

(100 pF) (R1LP0408C-7LI)

L

(Including scope and jig)

Read Cycle

R1LP0408C-I

-5SI -7LI
Parameter Symbol Min Max Min Max Unit Notes

Read cycle time tRC 55  70  ns
Address access time tAA  55  70 ns
Chip select access time tCO  55  70 ns
Output enable to output valid tOE  25  35 ns
Chip select to output in low-Z tLZ 10  10  ns 2
Output enable to output in low-Z t
Chip deselect to output in high-Z tHZ 0 20 0 25 ns 1, 2
Output disable to output in high-Z t
Output hold from address change tOH 10  10  ns

5  5  ns 2

OLZ

0 20 0 25 ns 1, 2

OHZ

Rev.2.00, May.26.2004, page 7 of 12

R1LP0408C-I Series

Write Cycle

R1LP0408C-I

-5SI -7LI
Parameter Symbol Min Max Min Max Unit Notes

Write cycle time tWC 55  70  ns
Chip selection to end of write tCW 50  60  ns 4
Address setup time tAS 0  0  ns 5
Address valid to end of write tAW 50  60  ns
Write pulse width tWP 40  50  ns 3, 12
Write recovery time tWR 0  0  ns 6
Write to output in high-Z t
Data to write time overlap tDW 25  30  ns
Data hold from write time tDH 0  0  ns
Output active from end of write tOW 5  5  ns 2
Output disable to output in high-Z t
Notes: 1. tHZ, t

OHZ

and t

are defined as the time at which the outputs achieve the open circuit conditions

WHZ

and are not referred to output voltage levels.

2. This parameter is sampled and not 100% tested.

3. A write occurs during the overlap (tWP) of a low CS# and a low WE#. A write begins at the later

transition of CS# going low or WE# going low. A write ends at the earlier transition of CS# going
high or WE# going high. tWP is measured from the beginning of write to the end of write.

4. tCW is measured from CS# going low to the end of write.

5. tAS is measured from the address valid to the beginning of write.

6. tWR is measured from the earlier of WE# or CS# going high to the end of write cycle.

7. During this period, I/O pins are in the output state so that the input signals of the opposite phase

to the outputs must not be applied.

8. If the CS# low transition occurs simultaneously with the WE# low transition or after the WE#

transition, the output remain in a high impedance state.

9. Dout is the same phase of the write data of this write cycle.

10. Dout is the read data of next address.

11. If CS# is low during this period, I/O pins are in the output state. Therefore, the input signals of

the opposite phase to the outputs must not be applied to them.

12. In the write cycle with OE# low fixed, t

data bus contention. tWP ≥ tDW min + t

0 20 0 25 ns 1, 2, 7

WHZ

0 20 0 25 ns 1, 2, 7

OHZ

must satisfy the following equation to avoid a problem of

WP

max

WHZ

Rev.2.00, May.26.2004, page 8 of 12

R1LP0408C-I Series

Timing Waveform

Read Timing Waveform (WE# = VIH)

t

RC

Address

CS#

OE#

Dout

High impedance

Valid address

t

AA

t

CO

t

LZ

t

OE

t

OLZ

t

HZ

t

OHZ

Valid data

t

OH

Rev.2.00, May.26.2004, page 9 of 12

R1LP0408C-I Series

Write Timing Waveform (1) (OE# Clock)

t

WC

Address

OE#

CS#

WE#

Dout

Din

Valid address

t

AW

t

CW

*8

t

AS

t

OHZ

t

WP

t

WR

High impedance

t

DW

t

DH

Valid data

Rev.2.00, May.26.2004, page 10 of 12

R1LP0408C-I Series

Write Timing Waveform (2) (OE# Low Fixed)

t

WC

Address

CS#

WE#

Dout

Din

Valid address

t

CW

*8

t

AW

t

WP

t

AS

t

WHZ

t

WR

t

OW

t

OH

*9

*10

High impedance

t

DW

t

DH

*11

Valid data

Rev.2.00, May.26.2004, page 11 of 12

R1LP0408C-I Series

Low VCC Data Retention Characteristics

(Ta = −40 to +85°C)

Parameter Symbol Min Typ Max Unit Test conditions*3

for data retention VDR 2   V CS# ≥ VCC − 0.2 V, Vin ≥ 0 V

V

CC

Data
retention
current

−5SI

to +85°C I
to +70°C I
to +40°C I
to +25°C I

−7LI

to +85°C I
to +70°C I
to +40°C I

to +25°C I
Chip deselect to data retention time t
Operation recovery time tR t
Notes: 1. Typical values are at VCC = 3.0 V, Ta = +25°C and specified loading, and not guaranteed.

2. Typical values are at VCC = 3.0 V, Ta = +40°C and specified loading, and not guaranteed.

3. CS# controls address buffer, WE# buffer, OE# buffer, and Din buffer. In data retention mode,

Vin levels (address, WE#, OE#, I/O) can be in the high impedance state.

4. tRC = read cycle time.

  10 µA VCC = 3.0 V, Vin ≥ 0 V

CCDR

  8 µA CS# ≥ VCC − 0.2 V

CCDR

 1.0*23 µA

CCDR

0.8*13 µA

CCDR

  20 µA

CCDR

  16 µA

CCDR

 1.0*210 µA

CCDR

 0.8*110 µA

CCDR

0   ns See retention waveform

CDR

*4  ns

RC

Low VCC Data Retention Timing Waveform (CS# Controlled)

V

CC

4.5 V

2.2 V
V

DR

CS#

0 V

t

CDR

Data retention mode

CS# ≥ VCC – 0.2 V

t

R

Rev.2.00, May.26.2004, page 12 of 12

Revision History R1LP0408C-I Series Data Sheet

Contents of Modification Rev. Date
Page Description

1.00 Aug.01.2003  Initial issue

2.00 May.26.2004 6

12

12

DC characteristics

−5SI and −7LI items’ description are divided.
Low V

Data Retention Characteristics

CC

−5SI and −7LI items’ description are divided.
Low V

Data Retention Timing Waveform

CC

2.4 V to 2.2 V

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