Datasheet PSMN070-200B, PSMN070-200P Datasheet (Philips)

DISCRETE SEMICONDUCTORS

DATA SH EET

PSMN070-200B; PSMN070-200P

N-channel TrenchMOS

(TM)

transistor

Product specification August 1999

Philips Semiconductors Product specification

N-channel TrenchMOS

(TM)

transistor

PSMN070-200B; PSMN070-200P

FEATURES SYMBOL QUICK REFERENCE DATA

• ’Trench’ technology

• Very low on-state resistance

• Fast switching

• Low thermal resistance

g

d

V

= 200 V

DSS

ID = 35 A

DS(ON)

≤ 70 mΩ

R

s

GENERAL DESCRIPTION

SiliconMAX products use the latest Philips Trench technology to achieve the lowest possible on-state resistance in

each package at each voltage rating.

Applications:-

• d.c. to d.c. converters

• switched mode power supplies
The PSMN070-200P is supplied in the SOT78 (TO220AB) conventional leaded package.

The PSMN070-200B is supplied in the SOT404 surface mounting package.

PINNING SOT78 (TO220AB) SOT404 (D2PAK)

PIN DESCRIPTION

1 gate
2 drain

1

3 source

tab drain

tab

123

tab

2

13

LIMITING VALUES

Limiting values in accordance with the Absolute Maximum System (IEC 134)

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

DSS

V

DGR

V

GS

I

D

I

DM

P

D

T

, T

j

Drain-source voltage Tj = 25 ˚C to 175˚C - 200 V
Drain-gate voltage Tj = 25 ˚C to 175˚C; RGS = 20 kΩ - 200 V
Gate-source voltage - ± 20 V
Continuous drain current Tmb = 25 ˚C - 35 A

T

= 100 ˚C - 25 A

mb

Pulsed drain current Tmb = 25 ˚C - 140 A
Total power dissipation Tmb = 25 ˚C - 250 W
Operating junction and - 55 175 ˚C

stg

storage temperature

1 It is not possible to make connection to pin:2 of the SOT404 package

August 1999 2 Rev 1.000

Philips Semiconductors Product specification

(TM)

transistor

PSMN070-200B; PSMN070-200PN-channel TrenchMOS

AVALANCHE ENERGY LIMITING VALUES

Limiting values in accordance with the Absolute Maximum System (IEC 134)

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

E

AS

Non-repetitive avalanche Unclamped inductive load, IAS = 35 A; - 462 mJ
energy t

= 100 µs; Tj prior to avalanche = 25˚C;

p

V

≤ 50 V; RGS = 50 Ω; VGS = 10 V; refer

DD

to fig:15

I

AS

Non-repetitive avalanche - 35 A
current

THERMAL RESISTANCES

SYMBOL PARAMETER CONDITIONS TYP. MAX. UNIT

R

th j-mb

Thermal resistance junction - 0.6 K/W
to mounting base

R

th j-a

Thermal resistance junction SOT78 package, in free air 60 - K/W
to ambient SOT404 package, pcb mounted, minimum 50 - K/W

footprint

ELECTRICAL CHARACTERISTICS

Tj= 25˚C unless otherwise specified

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

(BR)DSS

V

GS(TO)

R

DS(ON)

I

GSS

I

DSS

Q

g(tot)

Q

gs

Q

gd

t

d on

t

r

t

d off

t

f

L

d

L

d

Drain-source breakdown VGS = 0 V; ID = 0.25 mA; 200 - - V
voltage T

= -55˚C 178 - - V

j

Gate threshold voltage VDS = VGS; ID = 1 mA 2.0 3.0 4.0 V

T

= 175˚C 1.0 - - V

j

T

= -55˚C - - 6 V

j

Drain-source on-state VGS = 10 V; ID = 17 A - 60 70 mΩ
resistance T

= 175˚C - - 203 mΩ

j

Gate source leakage current VGS = ±10 V; VDS = 0 V - 2 100 nA
Zero gate voltage drain VDS = 200 V; VGS = 0 V; - 0.05 10 µA
current T

Total gate charge ID = 35 A; V

= 160 V; VGS = 10 V - 77 - nC

DD

= 175˚C - - 500 µA

j

Gate-source charge - 16 - nC
Gate-drain (Miller) charge - 28 - nC

Turn-on delay time VDD = 100 V; RD = 2.7 Ω; - 22 - ns
Turn-on rise time VGS = 10 V; RG = 5.6 Ω - 100 - ns
Turn-off delay time Resistive load - 80 - ns
Turn-off fall time - 90 - ns

Internal drain inductance Measured from tab to centre of die - 3.5 - nH
Internal drain inductance Measured from drain lead to centre of die - 4.5 - nH

(SOT78 package only)

L

s

Internal source inductance Measured from source lead to source - 7.5 - nH

bond pad

C

iss

C

oss

C

rss

Input capacitance VGS = 0 V; VDS = 25 V; f = 1 MHz - 4570 - pF
Output capacitance - 370 - pF
Feedback capacitance - 160 - pF

August 1999 3 Rev 1.000

Philips Semiconductors Product specification

(TM)

transistor

PSMN070-200B; PSMN070-200PN-channel TrenchMOS

REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS

Tj = 25˚C unless otherwise specified

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

I

S

I

SM

V

SD

t

rr

Q

rr

Continuous source current - - 35 A
(body diode)
Pulsed source current (body - - 140 A
diode)
Diode forward voltage IF = 25 A; VGS = 0 V - 0.85 1.2 V

Reverse recovery time IF = 20 A; -dIF/dt = 100 A/µs; - 160 - ns
Reverse recovery charge VGS = 0 V; VR = 30 V - 1.0 - µC

August 1999 4 Rev 1.000

Philips Semiconductors Product specification

(TM)

transistor

Normalised Power Derating, PD (%)

100

90
80
70
60
50
40
30
20
10

0

0 25 50 75 100 125 150 175

Mounting Base temperature, Tmb (C)

Fig.1. Normalised power dissipation.

PD% = 100

Normalised Current Derating, ID (%)

100

90
80
70
60
50
40
30
20
10

0

0 25 50 75 100 125 150 175

Mounting Base temperature, Tmb (C)

⋅

PD/P

D 25 ˚C

= f(Tmb)

Fig.2. Normalised continuous drain current.

ID% = 100

⋅

ID/I

= f(Tmb); VGS ≥ 10 V

D 25 ˚C

PSMN070-200B; PSMN070-200PN-channel TrenchMOS

Transient thermal impedance, Zth j-mb (K/W)

1

D = 0.5

0.2

0.1

0.1

0.05

0.02

0.01

single pulse

0.001
1E-06 1E-05 1E-04 1E-03 1E-02 1E-01 1E+00

Pulse width, tp (s)

Fig.4. Transient thermal impedance.

Z

= f(t); parameter D = tp/T

th j-mb

Drain Current, ID (A)

40

Tj = 25 C

35

30

25

20

15

10

5

0

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

Drain-Source Voltage, VDS (V)

Fig.5. Typical output characteristics, T

ID = f(VDS)

8 V

P

D

VGS = 10V

tp

D = tp/T

T

j

= 25 ˚C

6 V

5.2 V

5 V

4.8 V

4.6 V

4.4 V

4.2 V

.

D.C.

(A)

DM

tp = 10 us

100 us

1 ms
10 ms

100 ms

p

Drain-Source On Resistance, RDS(on) (Ohms)

0.2

0.18

0.16

0.14

0.12

0.1

0.08

0.06

0.04

0.02

4.4 V

4.6 V

4.2 V

4.8 V

5 V

0

0 5 10 15 20 25 30 35 40

Drain Current, ID (A)

8 V

5.2 V

VGS = 10V

Fig.6. Typical on-state resistance, T

R

= f(ID)

DS(ON)

Tj = 25 C

6V

= 25 ˚C

j

.

Peak Pulsed Drain Current, I

1000

RDS(on) = VDS/ ID

100

10

1

1 10 100 1000

Drain-Source Voltage, VDS (V)

Fig.3. Safe operating area

& IDM = f(VDS); IDM single pulse; parameter t

I

D

August 1999 5 Rev 1.000

Philips Semiconductors Product specification

(TM)

transistor

Drain current, ID (A)

40

VDS > ID X RDS(ON)

35
30
25
20
15
10

5
0

0123456

Gate-source voltage, VGS (V)

175 C

Tj = 25 C

Fig.7. Typical transfer characteristics.

I

= f(VGS)

D

Transconductance, gfs (S)

50

VDS > ID X RDS(ON)

45
40
35
30
25
20
15
10

5
0

0 5 10 15 20 25 30 35 40

Drain current, ID (A)

Fig.8. Typical transconductance, T

Tj = 25 C

175 C

= 25 ˚C

j

.

gfs = f(ID)

PSMN070-200B; PSMN070-200PN-channel TrenchMOS

Threshold Voltage, VGS(TO) (V)

4.5
4

3.5
3

2.5
2

1.5
1

0.5
0

-60 -40 -20 0 20 40 60 80 100 120 140 160 180
Junction Temperature, Tj (C)

Fig.10. Gate threshold voltage.

= f(Tj); conditions: ID = 1 mA; VDS = V

V

GS(TO)

Drain current, ID (A)

1.0E-01

1.0E-02

1.0E-03

1.0E-04

1.0E-05

1.0E-06
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

minimum

Gate-source voltage, VGS (V)

Fig.11. Sub-threshold drain current.

I

= f(V

D

; conditions: Tj = 25 ˚C

GS)

maximum

typical

minimum

typical

maximum

GS

Normalised On-state Resistance

2.9

2.7

2.5

2.3

2.1

1.9

1.7

1.5

1.3

1.1

0.9

0.7

0.5

-60 -40 -20 0 20 40 60 80 100 120 140 160 180
Junction temperature, Tj (C)

Fig.9. Normalised drain-source on-state resistance.

R

DS(ON)/RDS(ON)25 ˚C

= f(Tj)

Capacitances, Ciss, Coss, Crss (pF)

10000

1000

100

10

0.1 1 10 100

Fig.12. Typical capacitances, C

Drain-Source Voltage, VDS (V)

iss

, C

oss

C = f(VDS); conditions: VGS = 0 V; f = 1 MHz

Ciss

Coss

Crss

, C

rss

.

August 1999 6 Rev 1.000

Philips Semiconductors Product specification

(TM)

transistor

Gate-source voltage, VGS (V)

15

ID = 35 A

14
13

Tj = 25 C

12
11
10

9
8
7
6
5
4
3
2
1
0

0 102030405060708090100

Gate charge, QG (nC)

VDD = 40 V

VDD = 160 V

Fig.13. Typical turn-on gate-charge characteristics.

V

= f(QG)

GS

Source-Drain Diode Current, IF (A)

40

VGS = 0 V

35
30
25
20
15
10

5
0

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2

Source-Drain Voltage, VSDS (V)

175 C

Tj = 25 C

PSMN070-200B; PSMN070-200PN-channel TrenchMOS

Maximum Avalanche Current, I

100

10

Tj prior to avalanche = 150 C

1

0.001 0.01 0.1 1 10
Avalanche time, t

Fig.15. Maximum permissible non-repetitive

avalanche current (I

AS

unclamped inductive load

(A)

AS

25 C

(ms)

AV

) versus avalanche time (tAV);

Fig.14. Typical reverse diode current.

I

= f(V

F

August 1999 7 Rev 1.000

); conditions: V

SDS

= 0 V; parameter T

GS

j

Philips Semiconductors Product specification

MECHANICAL DATA

Plastic single-ended package; heatsink mounted; 1 mounting hole; 3-lead TO-220 SOT78

(TM)

D

L

D

L

2

1

(1)

b

1

transistor

P

PSMN070-200B; PSMN070-200PN-channel TrenchMOS

AE

A

1

q

L

1

Q

123

DIMENSIONS (mm are the original dimensions)

b

A

UNIT

mm

Note

1. Terminals in this zone are not tinned.

OUTLINE
VERSION

SOT78 TO-220

A

1

4.5

1.39

4.1

1.27

b

c

1

0.9

0.7

IEC JEDEC EIAJ

0.7

1.3

0.4

1.0

e

e

0 5 10 mm

D

D

1

15.8

6.4

15.2

5.9

REFERENCES

b

scale

e

10.3

9.7

E

2.54

15.0

13.5

L

L

1

3.30

2.79

(1)

L

2

max.

3.0

c

qQ

P

3.8

3.0

3.6

2.7

EUROPEAN

PROJECTION

2.6

2.2

ISSUE DATE

97-06-11

Fig.16. SOT78 (TO220AB); pin 2 connected to mounting base (Net mass:2g)

Notes

1. This product is supplied in anti-static packaging. The gate-source input must be protected against static
discharge during transport or handling.

2. Refer to mounting instructions for SOT78 (TO220AB) package.

3. Epoxy meets UL94 V0 at 1/8".

August 1999 8 Rev 1.000

Philips Semiconductors Product specification

MECHANICAL DATA

Plastic single-ended surface mounted package (Philips version of D2-PAK); 3 leads
(one lead cropped)

(TM)

transistor

PSMN070-200B; PSMN070-200PN-channel TrenchMOS

SOT404

A

mounting

base

A

1

L

p

c

Q

E

D

1

D

H

D

2

13

b

e e

0 2.5 5 mm

scale

DIMENSIONS (mm are the original dimensions)

A

UNIT

mm

A

4.50

4.10

OUTLINE

VERSION

SOT404

b

1

1.40

0.85

1.27

0.60

IEC JEDEC EIAJ

0.64

0.46

max.

D

11

D

1

1.60

10.30

1.20

REFERENCES

9.70

E

eLpHDQc

2.60

15.40

2.90

2.54

2.10

14.80

2.20

EUROPEAN

PROJECTION

ISSUE DATE

98-12-14
99-06-25

Fig.17. SOT404 surface mounting package. Centre pin connected to mounting base.

Notes

1. This product is supplied in anti-static packaging. The gate-source input must be protected against static
discharge during transport or handling.

2. Refer to SMD Footprint Design and Soldering Guidelines, Data Handbook SC18.

3. Epoxy meets UL94 V0 at 1/8".

August 1999 9 Rev 1.000

Philips Semiconductors Product specification

MOUNTING INSTRUCTIONS

Dimensions in mm

DEFINITIONS

(TM)

transistor

9.0

3.8

PSMN070-200B; PSMN070-200PN-channel TrenchMOS

11.5

17.5

2.0

5.08

Fig.18. SOT404 : soldering pattern for surface mounting

.

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and
operation of the device at these or at any other conditions above those given in the Characteristics sections of
this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

 Philips Electronics N.V. 1999

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the
copyright owner.

The information presented in this document does not form part of any quotation or contract, it is believed to be
accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under patent or other
industrial or intellectual property rights.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices or systems where malfunction of these
products can be reasonably expected to result in personal injury. Philips customers using or selling these products
for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting
from such improper use or sale.

August 1999 10 Rev 1.000

Philips Semiconductors Product specification

(TM)

transistor

PSMN070-200B; PSMN070-200PN-channel TrenchMOS

NOTES

August 1999 11 Rev 1.000

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© Philips Electronics N.V. SCA
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

2000

Internet: http://www.semiconductors.philips.com

69

Printed in The Netherlands 603502/300/03/pp12 Date of release: August 1999 Document order number: 9397 750 06972