Datasheet PSMN015-100B, PSMN015-100P Datasheet (Philips)

Philips Semiconductors Product specification

N-channel TrenchMOS transistor PSMN015-100B, PSMN015-100P

FEATURES SYMBOL QUICK REFERENCE DATA

• ’Trench’ technology

• Very low on-state resistance V

d

= 100 V

DSS

• Fast switching

• Low thermal resistance I

g

s

R

DS(ON)

= 75 A

D

≤ 15 mΩ

GENERAL DESCRIPTION

SiliconMAX products use the latest Philips Trench technology to achieve the lowest possible on-state resistance in

each package at each voltage rating.

Applications:-

• d.c. to d.c. converters

• switched mode power supplies
The PSMN015-100P is supplied in the SOT78 (TO220AB) conventional leadedpackage.

The PSMN015-100B is supplied in the SOT404 surface mounting package.

PINNING SOT78 (TO220AB) SOT404 (D2PAK)

PIN DESCRIPTION

1 gate
2 drain

1

tab

tab

3 source

tab drain

123

2

13

LIMITING VALUES

Limiting values in accordance with the Absolute Maximum System (IEC 134)

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

DSS

V

DGR

V

GS

I

D

I

DM

P

D

Tj, T

1 It is not possible to make connection to pin:2 of the SOT404 package
2 Maximum continuous current limited by package

Drain-source voltage Tj = 25 ˚C to 175˚C - 100 V
Drain-gate voltage Tj = 25 ˚C to 175˚C; RGS = 20 kΩ - 100 V
Gate-source voltage - ± 20 V
Continuous drain current Tmb = 25 ˚C - 75

Tmb = 100 ˚C - 53 A
Pulsed drain current Tmb = 25 ˚C - 240 A
Total power dissipation Tmb = 25 ˚C - 230 W
Operating junction and - 55 175 ˚C

stg

storage temperature

2

A

August 1999 1 Rev 1.100

Philips Semiconductors Product specification

N-channel TrenchMOS transistor PSMN015-100B, PSMN015-100P

AVALANCHE ENERGY LIMITING VALUES

Limiting values in accordance with the Absolute Maximum System (IEC 134)

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

E

AS

I

AS

THERMAL RESISTANCES

SYMBOL PARAMETER CONDITIONS TYP. MAX. UNIT

R

th j-mb

R

th j-a

Non-repetitive avalanche Unclamped inductive load, IAS = 74 A; - 481 mJ
energy tp = 100 µs; Tj prior to avalanche = 25˚C;

VDD ≤ 50 V; RGS = 50 Ω; VGS = 10 V; refer

to fig:15
Non-repetitive avalanche - 75 A
current

Thermal resistance junction - 0.65 K/W
to mounting base
Thermal resistance junction SOT78 package, in free air 60 - K/W
to ambient SOT404 package, pcb mounted, minimum 50 - K/W

footprint

ELECTRICAL CHARACTERISTICS

Tj= 25˚C unless otherwise specified

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

(BR)DSS

V

GS(TO)

R

DS(ON)

I

GSS

I

DSS

Q

g(tot)

Q

gs

Q

gd

t

d on

t

r

t

d off

t

f

L

d

L

d

L

s

C

iss

C

oss

C

rss

Drain-source breakdown VGS = 0 V; ID = 0.25 mA; 100 - - V
voltage Tj = -55˚C 89 - - V
Gate threshold voltage VDS = VGS; ID = 1 mA 2.0 3.0 4.0 V

Tj = 175˚C 1.0 - - V

Tj = -55˚C - - 6 V
Drain-source on-state VGS = 10 V; ID = 25 A - 12 15 mΩ
resistance Tj = 175˚C - - 41 mΩ
Gate source leakage current VGS = ±10 V; VDS = 0 V - 2 100 nA
Zero gate voltage drain VDS = 100 V; VGS = 0 V; - 0.05 10 µA
current Tj = 175˚C - - 500 µA

Total gate charge ID = 75 A; V

= 80 V; VGS = 10 V - 109 - nC

DD

Gate-source charge - 20 - nC
Gate-drain (Miller) charge - 50 - nC

Turn-on delay time VDD = 50 V; RD = 1.8 Ω; - 30 - ns
Turn-on rise time VGS = 10 V; RG = 5.6 Ω -80-ns
Turn-off delay time Resistive load - 150 - ns
Turn-off fall time - 95 - ns

Internal drain inductance Measured from tab to centre of die - 3.5 - nH
Internal drain inductance Measured from drain lead to centre of die - 4.5 - nH
Internal source inductance Measured from source lead to source - 7.5 - nH

bond pad

Input capacitance VGS = 0 V; VDS = 25 V; f = 1 MHz - 4720 - pF
Output capacitance - 650 - pF
Feedback capacitance - 380 - pF

August 1999 2 Rev 1.100

Philips Semiconductors Product specification

N-channel TrenchMOS transistor PSMN015-100B, PSMN015-100P

REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS

Tj = 25˚C unless otherwise specified

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

I

S

I

SM

V

SD

t

rr

Q

rr

Continuous source current - - 75 A
(body diode)
Pulsed source current (body - - 240 A
diode)
Diode forward voltage IF = 25 A; VGS = 0 V - 0.8 1.2 V

Reverse recovery time IF = 20 A; -dIF/dt = 100 A/µs; - 90 - ns
Reverse recovery charge VGS = 0 V; VR = 30 V - 0.3 - µC

August 1999 3 Rev 1.100

Philips Semiconductors Product specification

N-channel TrenchMOS transistor PSMN015-100B, PSMN015-100P

Normalised Power Derating, PD (%)

100

90
80
70
60
50
40
30
20
10

0

0 25 50 75 100 125 150 175

Mounting Base temperature, Tmb (C)

Fig.1. Normalised power dissipation.

PD% = 100⋅PD/P

Normalised Current Derating, ID (%)

100

90
80
70
60
50
40
30
20
10

0

0 25 50 75 100 125 150 175

Mounting Base temperature, Tmb (C)

D 25 ˚C

= f(Tmb)

Fig.2. Normalised continuous drain current.

ID% = 100⋅ID/I

D 25 ˚C

= f(Tmb)

Transient thermal impedance, Zth j-mb (K/W)

1

D = 0.5

0.2

0.1

0.1

0.05

0.02

0.01

single pulse

0.001
1E-06 1E-05 1E-04 1E-03 1E-02 1E-01 1E+00

Pulse width, tp (s)

P

D

D = tp/T

tp

T

Fig.4. Transient thermal impedance.

Z

= f(t); parameter D = tp/T

th j-mb

Drain Current, ID (A)

50

VGS = 15V

45
40
35
30
25
20
15
10

5
0

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

10 V

Drain-Source Voltage, VDS (V)

5 V

Tj = 25 C

3.6 V

4.6 V

4.4 V

4.2 V
4 V

3.8 V

Fig.5. Typical output characteristics, Tj = 25 ˚C

ID = f(VDS); parameter V

GS

.

Peak Pulsed Drain Current, IDM (A)

1000

RDS(on) = VDS/ ID

100

10

1

1 10 100 1000

D.C.

Drain-Source Voltage, VDS (V)

tp = 10 us

100 us

1 ms

10 ms
100 ms

Fig.3. Safe operating area. Tmb = 25 ˚C

ID & IDM = f(VDS); IDM single pulse; parameter t

p

Drain-Source On Resistance, RDS(on) (Ohms)

0.05

0.045

0.04

0.035

0.03

0.025

0.02

0.015

0.01

0.005
0

4 V

4.2 V

0 5 10 15 20 25 30 35 40 45 50

4.4 V

Drain Current, ID (A)

4.6 V

Tj = 25 C

VGS = 15V

Fig.6. Typical on-state resistance, Tj = 25 ˚C

R

= f(VGS)

DS(ON)

5V

10 V

.

August 1999 4 Rev 1.100

Philips Semiconductors Product specification

N-channel TrenchMOS transistor PSMN015-100B, PSMN015-100P

Drain current, ID (A)

80

VDS > ID X RDS(ON)

70
60
50
40
30
20
10

0

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6

Gate-source voltage, VGS (V)

175 C

Tj = 25 C

Fig.7. Typical transfer characteristics.

ID = f(VGS); parameter T

Transconductance, gfs (S)

80
70
60
50
40
30
20
10

0

0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80

Tj = 25 C

Drain current, ID (A)

j

VDS > ID X RDS(ON)

175 C

Fig.8. Typical transconductance, Tj = 25 ˚C

gfs = f(ID)

Threshold Voltage, VGS(TO) (V)

4.5

4

3.5

3

2.5

2

1.5

1

0.5

0

-60 -40 -20 0 20 40 60 80 100 120 140 160 180
Junction Temperature, Tj (C)

maximum

typical

minimum

Fig.10. Gate threshold voltage.

V

= f(Tj); conditions: ID = 1 mA; VDS = V

GS(TO)

Drain current, ID (A)

1.0E-01

1.0E-02

1.0E-03

1.0E-04

1.0E-05

1.0E-06
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

.

Fig.11. Sub-threshold drain current.

minimum

typical

Gate-source voltage, VGS (V)

ID = f(V

; Tj = 25 ˚C

GS)

maximum

GS

Normalised On-state Resistance

2.9

2.7

2.5

2.3

2.1

1.9

1.7

1.5

1.3

1.1

0.9

0.7

0.5

-60 -40 -20 0 20 40 60 80 100 120 140 160 180
Junction temperature, Tj (C)

Fig.9. Normalised drain-source on-state resistance.

R

DS(ON)/RDS(ON)25 ˚C

= f(Tj)

Capacitances, Ciss, Coss, Crss (pF)

10000

1000

100

0.1 1 10 100

Fig.12. Typical capacitances, C

Drain-Source Voltage, VDS (V)

iss

, C

C = f(VDS); conditions: VGS = 0 V; f = 1 MHz

oss

Ciss

Coss
Crss

, C

rss

.

August 1999 5 Rev 1.100

Philips Semiconductors Product specification

N-channel TrenchMOS transistor PSMN015-100B, PSMN015-100P

Gate-source voltage, V

15

ID = 75A

14
13

Tj = 25 C

12
11
10

9
8
7
6
5
4
3
2
1
0

0 102030405060708090100110120

(V)

GS

VDD = 20 V

Gate charge, Q

G

VDD = 80 V

(nC)

Fig.13. Typical turn-on gate-charge characteristics

V

= f(QG)

GS

Source-Drain Diode Current, IF (A)

100

VGS = 0 V

90
80
70
60
50
40
30
20
10

0

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5

175 C

Tj = 25 C

Source-Drain Voltage, VSDS (V)

Maximum Avalanche Current, I

100

Tj prior to avalanche = 150 C

10

1

0.001 0.01 0.1 1 10
Avalanche time, t

(A)

AS

25 C

(ms)

AV

Fig.15. Maximum permissible non-repetitive

avalanche current (IAS) versus avalanche time (tAV);

unclamped inductive load

Fig.14. Typical reverse diode current.

IF = f(V

); conditions: V

SDS

= 0 V; parameter T

GS

j

August 1999 6 Rev 1.100

Philips Semiconductors Product specification

N-channel TrenchMOS transistor PSMN015-100B, PSMN015-100P

MECHANICAL DATA

Plastic single-ended package; heatsink mounted; 1 mounting hole; 3-lead TO-220 SOT78

AE

P

A

1

D

1

D

(1)

L

2

b

1

L

DIMENSIONS (mm are the original dimensions)

b

A

UNIT

mm

Note

1. Terminals in this zone are not tinned.

OUTLINE
VERSION

SOT78 TO-220

A

1

4.5

1.39

4.1

1.27

b

c

1

0.9

0.7

IEC JEDEC EIAJ

0.7

1.3

0.4

1.0

123

e

e

0 5 10 mm

D

D

1

15.8

6.4

15.2

5.9

REFERENCES

q

L

1

Q

L

2

max.

3.0

(1)

c

qQ

P

3.8

3.0

3.6

2.7

EUROPEAN

PROJECTION

2.6

2.2

ISSUE DATE

97-06-11

b

scale

e

10.3

9.7

E

2.54

15.0

13.5

L

L

1

3.30

2.79

Fig.16. SOT78 (TO220AB); pin 2 connected to mounting base (Net mass:2g)

Notes

1. This product is supplied in anti-static packaging. The gate-source input must be protected against static
discharge during transport or handling.

2. Refer to mounting instructions for SOT78 (TO220AB) package.

3. Epoxy meets UL94 V0 at 1/8".

August 1999 7 Rev 1.100

Philips Semiconductors Product specification

N-channel TrenchMOS transistor PSMN015-100B, PSMN015-100P

MECHANICAL DATA

Plastic single-ended surface mounted package (Philips version of D2-PAK); 3 leads
(one lead cropped)

base

A

1

L

p

c

Q

E

D

1

D

H

D

2

13

b

e e

0 2.5 5 mm

scale

mounting

SOT404

A

DIMENSIONS (mm are the original dimensions)

A

UNIT

mm

A

4.50

4.10

OUTLINE
VERSION

SOT404

b

1

1.40

0.85

1.27

0.60

IEC JEDEC EIAJ

0.64

0.46

max.

11

D

D

1

1.60

1.20

REFERENCES

E

10.30

9.70

2.54

eLpHDQc

2.60

15.40

2.90

2.10

14.80

2.20

EUROPEAN

PROJECTION

ISSUE DATE

98-12-14
99-06-25

Fig.17. SOT404 surface mounting package. Centre pin connected to mounting base.

Notes

1. This product is supplied in anti-static packaging. The gate-source input must be protected against static
discharge during transport or handling.

2. Refer to SMD Footprint Design and Soldering Guidelines, Data Handbook SC18.

3. Epoxy meets UL94 V0 at 1/8".

August 1999 8 Rev 1.100

Philips Semiconductors Product specification

N-channel TrenchMOS transistor PSMN015-100B, PSMN015-100P

MOUNTING INSTRUCTIONS

Dimensions in mm

9.0

3.8

Fig.18. SOT404 : soldering pattern for surface mounting

11.5

17.5

2.0

5.08

.

DEFINITIONS

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and
operation of the device at these or at any other conditions above those given in the Characteristics sections of
this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

 Philips Electronics N.V. 1999

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the
copyright owner.

The information presented in this document does not form part of any quotation or contract, it is believed to be
accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under patent or other
industrial or intellectual property rights.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices or systems where malfunction of these
products can be reasonably expected to result in personal injury. Philips customers using or selling these products
for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting
from such improper use or sale.

August 1999 9 Rev 1.100