Datasheet PSMN005-25D Datasheet (Philips)

DISCRETE SEMICONDUCTORS

DATA SH EET

PSMN005-25D

N-channel logic level
TrenchMOS

Product specification October 1999

(TM)

transistor

Philips Semiconductors Product specification

N-channel logic level TrenchMOS

(TM)

transistor

PSMN005-25D

FEATURES SYMBOL QUICK REFERENCE DATA

• ’Trench’ technology V

• Very low on-state resistance

• Fast switching

• Logic level compatible

g

d

= 25 V

DSS

ID = 75 A

R

s

≤ 5.8 mΩ (VGS = 10 V)

DS(ON)

R

≤ 7.5 mΩ (VGS = 5 V)

DS(ON)

GENERAL DESCRIPTION PINNING SOT428 (DPAK)

SiliconMAXproductsusethelatest PIN DESCRIPTION

Philips Trench technology to
achieve the lowest possible 1 gate
on-state resistance in each
package at each voltage rating. 2 drain

1

Applications:- 3 source

• d.c. to d.c. converters

• switched mode power supplies tab drain

tab

2

1

3

The PSMN005-25D is supplied in
the SOT428 (Dpak) surface
mounting package.

LIMITING VALUES

Limiting values in accordance with the Absolute Maximum System (IEC 134)

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

DSS

V

DGR

V

GS

V

GSM

I

D

I

DM

P

D

T

, T

j

Drain-source voltage Tj = 25 ˚C to 175˚C - 25 V
Drain-gate voltage Tj = 25 ˚C to 175˚C; RGS = 20 kΩ -25V
Continuous gate-source - ± 15 V
voltage
Peak pulsed gate-source Tj ≤ 150 ˚C - ± 20 V
voltage
Continuous drain current Tmb = 25 ˚C; VGS = 5 V - 75

T

= 100 ˚C; VGS = 5 V - 70 A

mb

2

Pulsed drain current Tmb = 25 ˚C - 240 A
Total power dissipation Tmb = 25 ˚C - 125 W
Operating junction and - 55 175 ˚C

stg

storage temperature

A

1 It is not possible to make connection to pin 2 of the SOT428 package.
2 Continuous current rating limited by package.

October 1999 2 Rev 1.100

Philips Semiconductors Product specification

(TM)

transistor

PSMN005-25DN-channel logic level TrenchMOS

AVALANCHE ENERGY LIMITING VALUES

Limiting values in accordance with the Absolute Maximum System (IEC 134)

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

E

AS

I

AS

Non-repetitive avalanche Unclamped inductive load, IAS = 75 A; - 120 mJ
energy t

= 100 µs; Tj prior to avalanche = 25˚C;

p

V

≤ 15 V; RGS = 50 Ω; VGS = 5 V

DD

Non-repetitive avalanche - 75 A
current

THERMAL RESISTANCES

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

R

th j-mb

Thermal resistance junction - - 1.2 K/W
to mounting base

R

th j-a

Thermal resistance junction SOT428 package, pcb mounted, minimum - 50 - K/W
to ambient footprint

ELECTRICAL CHARACTERISTICS

Tj= 25˚C unless otherwise specified

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

(BR)DSS

V

GS(TO)

R

DS(ON)

I

GSS

I

DSS

Q

g(tot)

Q

gs

Q

gd

t

d on

t

r

t

d off

t

f

L

d

L

s

C

iss

C

oss

C

rss

Drain-source breakdown VGS = 0 V; ID = 0.25 mA; 25 - - V
voltage T

= -55˚C 23 - - V

j

Gate threshold voltage VDS = VGS; ID = 1 mA 1 1.5 2 V

T

= 175˚C 0.5 - - V

j

= -55˚C - - 2.3 V

T

j

Drain-source on-state VGS = 10 V; ID = 25 A - 5 5.8 mΩ
resistance V

= 5 V; ID = 25 A - 6.2 7.5 mΩ

GS

V

= 5 V; ID = 25 A; Tj = 175˚C - - 14 mΩ

GS

Gate source leakage current VGS = ±10 V; VDS = 0 V - 0.02 100 nA
Zero gate voltage drain VDS = 25 V; VGS = 0 V; - 0.05 10 µA
current T

Total gate charge ID = 75 A; V

= 15 V; VGS = 5 V - 60 - nC

DD

= 175˚C - - 500 µA

j

Gate-source charge - 8 - nC
Gate-drain (Miller) charge - 32 - nC

Turn-on delay time VDD = 15 V; RD = 0.6 Ω; - 21 - ns
Turn-on rise time VGS = 10 V; RG = 10 Ω - 170 - ns
Turn-off delay time Resistive load - 270 - ns
Turn-off fall time - 216 - ns

Internal drain inductance Measured tab to centre of die - 3.5 - nH
Internal source inductance Measured from source lead to source - 7.5 - nH

bond pad

Input capacitance VGS = 0 V; VDS = 20 V; f = 1 MHz - 3500 - pF
Output capacitance - 970 - pF
Feedback capacitance - 640 - pF

October 1999 3 Rev 1.100

Philips Semiconductors Product specification

(TM)

transistor

PSMN005-25DN-channel logic level TrenchMOS

REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS

Tj = 25˚C unless otherwise specified

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

I

S

I

SM

V

SD

t

rr

Q

rr

Continuous source current - - 75 A
(body diode)
Pulsed source current (body - - 240 A
diode)
Diode forward voltage IF = 25 A; VGS = 0 V - 0.95 1.2 V

Reverse recovery time IF = 25 A; -dIF/dt = 100 A/µs; - 140 - ns
Reverse recovery charge VGS = 0 V; VR = 25 V - 0.27 - µC

October 1999 4 Rev 1.100

Philips Semiconductors Product specification

Normalised Power Derating, PD (%)

100

90
80
70
60
50
40
30
20
10

0

0 25 50 75 100 125 150 175

Mounting Base temperature, Tmb (C)

Fig.1. Normalised power dissipation.

PD% = 100

Normalised Current Derating, ID (%)

100

90
80
70
60
50
40
30
20
10

0

0 25 50 75 100 125 150 175

Mounting Base temperature, Tmb (C)

⋅

PD/P

D 25 ˚C

= f(Tmb)

Fig.2. Normalised continuous drain current.

ID% = 100

⋅

ID/I

= f(Tmb); conditions: VGS ≥ 5 V

D 25 ˚C

(TM)

transistor

PSMN005-25DN-channel logic level TrenchMOS

Transient thermal impedance, Zth j-mb (K/W)

10

1

D = 0.5

0.2

0.1

0.1

0.05

0.02

0.01
single pulse

0.001
1E-06 1E-05 1E-04 1E-03 1E-02 1E-01 1E+00

Pulse width, tp (s)

Fig.4. Transient thermal impedance.

Z

= f(t); parameter D = tp/T

th j-mb

Drain Current, ID (A)

50
45
40
35
30
25
20
15
10

5
0

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

5 V

10V

3 V

VGS = 2.8 V

Drain-Source Voltage, VDS (V)

Fig.5. Typical output characteristics, T

ID = f(VDS)

P

D

tp

D = tp/T

T

Tj = 25 C

= 25 ˚C

j

2.6 V

2.4 V

2.2 V

2 V

.

Peak Pulsed Drain Current, IDM (A)

1000

RDS(on) = VDS/ ID

tp = 10 us

100

10

1

1 10 100

D.C.

Drain-Source Voltage, VDS (V)

Fig.3. Safe operating area. T

I

& IDM = f(VDS); IDM single pulse; parameter t

D

100 us

1 ms

10 ms
100 ms

= 25 ˚C

mb

p

Drain-Source On Resistance, RDS(on) (Ohms)

0.03

0.025

0.02

0.015

0.01

0.005

2.2 V

0

0 5 10 15 20 25 30 35 40 45 50

2.4 V 2.6 V

Drain Current, ID (A)

Fig.6. Typical on-state resistance, T

R

= f(ID)

DS(ON)

Tj = 25 C

2.8 V
3 V

5 V

VGS = 10V

= 25 ˚C

j

.

October 1999 5 Rev 1.100

Philips Semiconductors Product specification

Drain current, ID (A)

50

VDS > ID X RDS(ON)

45
40
35
30
25
20
15
10

5
0

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3

Gate-source voltage, VGS (V)

175 C

Tj = 25 C

Fig.7. Typical transfer characteristics.

I

= f(VGS)

D

Transconductance, gfs (S)

80

VDS > ID X RDS(ON)

75
70
65
60
55
50
45
40
35
30
25
20
15
10

5
0

0 5 10 15 20 25 30 35 40 45 50

Drain current, ID (A)

Fig.8. Typical transconductance, T

Tj = 25 C

175 C

= 25 ˚C

j

gfs = f(ID)

(TM)

.

transistor

Threshold Voltage, VGS(TO) (V)

2.25

2

1.75

1.5

1.25

1

0.75

0.5

0.25

0

-60 -40 -20 0 20 40 60 80 100 120 140 160 180

V

GS(TO)

1.0E-01

1.0E-02

1.0E-03

1.0E-04

1.0E-05

1.0E-06
0 0.5 1 1.5 2 2.5 3

I

= f(V

D

PSMN005-25DN-channel logic level TrenchMOS

maximum

typical

minimum

Junction Temperature, Tj (C)

Fig.10. Gate threshold voltage.

= f(Tj); conditions: ID = 1 mA; VDS = V

Drain current, ID (A)

VDS = 5 V

minimum typical maximum

Gate-source voltage, VGS (V)

Fig.11. Sub-threshold drain current.

; conditions: Tj = 25 ˚C; VDS = V

GS)

GS

GS

Normalised On-state Resistance

2

1.9

1.8

1.7

1.6

1.5

1.4

1.3

1.2

1.1
1

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1
0

-60 -40 -20 0 20 40 60 80 100 120 140 160 180
Junction temperature, Tj (C)

Fig.9. Normalised drain-source on-state resistance.

R

DS(ON)/RDS(ON)25 ˚C

= f(Tj)

Capacitances, Ciss, Coss, Crss (pF)

10000

Ciss

1000

100

0.1 1 10 100
Drain-Source Voltage, VDS (V)

Fig.12. Typical capacitances, C

Coss
Crss

, C

iss

oss

C = f(VDS); conditions: VGS = 0 V; f = 1 MHz

, C

rss

.

October 1999 6 Rev 1.100

Philips Semiconductors Product specification

(TM)

Gate-source voltage, VGS (V)

15

ID = 75 A

14
13

VDD = 15 V

12

Tj = 25 C

11
10

9
8
7
6
5
4
3
2
1
0

0 102030405060708090100110

Gate charge, QG (nC)

Fig.13. Typical turn-on gate-charge characteristics.

V

= f(QG)

GS

Source-Drain Diode Current, IF (A)

50

VGS = 0 V

45
40
35
30
25
20
15
10

5
0

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2

175 C

Tj = 25 C

Source-Drain Voltage, VSDS (V)

transistor

Maximum Avalanche Current, I

100

10

1

0.001 0.01 0.1 1 10

Fig.15. Maximum permissible non-repetitive

avalanche current (I

PSMN005-25DN-channel logic level TrenchMOS

(A)

AS

Tj prior to avalanche = 150 C

Avalanche time, t

) versus avalanche time (tAV);

AS

unclamped inductive load

AV

(ms)

25 C

Fig.14. Typical reverse diode current.

I

= f(V

F

October 1999 7 Rev 1.100

); conditions: V

SDS

= 0 V; parameter T

GS

j

Philips Semiconductors Product specification

MECHANICAL DATA

Plastic single-ended surface mounted package (Philips version of D-PAK); 3 leads
(one lead cropped)

L

2

E

b

2

2

A

D

L

13

b

1

e

e

1

wA

M

bc

(TM)

transistor

seating plane

A

1

mounting

base

H

E

L

1

PSMN005-25DN-channel logic level TrenchMOS

SOT428

y

A

A

2

E

1

D

1

0 10 20 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

A

UNIT

Note

1. Measured from heatsink back to lead.

A

1

max.

0.65

0.45

0.89

0.71

2.38

mm

2.22

OUTLINE
VERSION

SOT428 98-04-07

b

1

b

b

2

max.

0.89

1.1

0.71

IEC JEDEC EIAJ

5.36

0.9

5.26

2

D

c

max.

0.4

6.22

0.2

5.98

REFERENCES

max.

4.81

4.45

E

D

E

max.

6.73

6.47

min.

4.0

1

2.285

1

ee

1

4.57

H

max.

10.4

9.6

E

2.95

2.55

L

1

L

min.

0.5

EUROPEAN

PROJECTION

L

0.7

0.5

2

w

max.

0.2 0.2

ISSUE DATE

y

Fig.16. SOT428 surface mounting package. Centre pin connected to mounting base.

Notes

1. This product is supplied in anti-static packaging. The gate-source input must be protected against static
discharge during transport or handling.

2. Refer to SMD Footprint Design and Soldering Guidelines, Data Handbook SC18.

3. Epoxy meets UL94 V0 at 1/8".

October 1999 8 Rev 1.100

Philips Semiconductors Product specification

MOUNTING INSTRUCTIONS

Dimensions in mm

(TM)

transistor

7.0

7.0

2.15

2.5

4.57

1.5

Fig.17. SOT428 : soldering pattern for surface mounting

PSMN005-25DN-channel logic level TrenchMOS

.

October 1999 9 Rev 1.100

Philips Semiconductors Product specification

(TM)

transistor

PSMN005-25DN-channel logic level TrenchMOS

DEFINITIONS

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and
operation of the device at these or at any other conditions above those given in the Characteristics sections of
this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

 Philips Electronics N.V. 1999

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the
copyright owner.

The information presented in this document does not form part of any quotation or contract, it is believed to be
accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under patent or other
industrial or intellectual property rights.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices or systems where malfunction of these
products can be reasonably expected to result in personal injury. Philips customers using or selling these products
for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting
from such improper use or sale.

October 1999 10 Rev 1.100

Philips Semiconductors Product specification

(TM)

transistor

NOTES

PSMN005-25DN-channel logic level TrenchMOS

October 1999 11 Rev 1.100

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© Philips Electronics N.V. SCA
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in thisdocument does not form part of anyquotation or contract, is believedto be accurate and reliable and maybe changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

2000

Internet: http://www.semiconductors.philips.com

69

Printed in The Netherlands 603502/300/05/pp12 Date of release: October 1999 Document order number: 9397 750 06977