Datasheet PSMN004-25B, PSMN004-25P Datasheet (Philips)

Philips Semiconductors Product specification

N-channel logic level TrenchMOS transistor PSMN004-25B, PSMN004-25P

FEATURES SYMBOL QUICK REFERENCE DATA

• ’Trench’ technology V

d

= 25 V

DSS

• Very low on-state resistance

• Fast switching

ID = 75 A

• Low thermal resistance

g

R

R

s

≤ 4 mΩ (VGS = 10 V)

DS(ON)

≤ 5 mΩ (VGS = 5 V)

DS(ON)

GENERAL DESCRIPTION

SiliconMAX products use the latest Philips Trench technology to achieve the lowest possible on-state resistance in

each package at each voltage rating.

Applications:-

• d.c. to d.c. converters

• switched mode power supplies
The PSMN004-25P is supplied in the SOT78 (TO220AB) conventional leaded package.
The PSMN004-25B is supplied in the SOT404 surface mounting package.

PINNING SOT78 (TO220AB) SOT404 (D2PAK)

PIN DESCRIPTION

1 gate
2 drain

1

tab

tab

3 source

tab drain

123

2

13

LIMITING VALUES

Limiting values in accordance with the Absolute Maximum System (IEC 134)

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

DSS

V

DGR

V

GS

V

GSM

I

D

I

DM

P

D

Tj, T

1 It is not possible to make connection to pin:2 of the SOT404 package
2 maximum continuous current limited by package

Drain-source voltage Tj = 25 ˚C to 175˚C - 25 V
Drain-gate voltage Tj = 25 ˚C to 175˚C; RGS = 20 kΩ -25V
Continuous gate-source - ± 16 V
voltage
Peak pulsed gate-source Tj ≤ 150 ˚C - ± 20 V
voltage
Continuous drain current Tmb = 25 ˚C; VGS = 5 V - 75

Tmb = 100 ˚C; VGS = 5 V - 75

2
2

Pulsed drain current Tmb = 25 ˚C - 240 A
Total power dissipation Tmb = 25 ˚C - 230 W
Operating junction and - 55 175 ˚C

stg

storage temperature

A
A

January 2000 1 Rev 1.200

Philips Semiconductors Product specification

N-channel logic level TrenchMOS transistor PSMN004-25B, PSMN004-25P

THERMAL RESISTANCES

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

R

th j-mb

R

th j-a

AVALANCHE ENERGY LIMITING VALUES

Limiting values in accordance with the Absolute Maximum System (IEC 134)

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

E

AS

I

AS

Thermal resistance junction - - 0.65 K/W
to mounting base
Thermal resistance junction SOT78 package, vertical in still air - 60 - K/W
to ambient SOT404 package, pcb mounted, minimum - 50 - K/W

footprint

Non-repetitive avalanche Unclamped inductive load, IAS = 75 A; - 120 mJ
energy tp = 100 µs; Tj prior to avalanche = 25˚C;

VDD ≤ 15 V; RGS = 50 Ω; VGS = 5 V
Non-repetitive avalanche - 75 A
current

ELECTRICAL CHARACTERISTICS

Tj= 25˚C unless otherwise specified

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

(BR)DSS

V

GS(TO)

R

DS(ON)

I

GSS

I

DSS

Q

g(tot)

Q

gs

Q

gd

t

d on

t

r

t

d off

t

f

L

d

L

d

L

s

C

iss

C

oss

C

rss

Drain-source breakdown VGS = 0 V; ID = 0.25 mA; 25 - - V
voltage Tj = -55˚C 22 - - V
Gate threshold voltage VDS = VGS; ID = 1 mA 1 1.5 2 V

Tj = 175˚C 0.5 - - V

Tj = -55˚C - - 2.3 V
Drain-source on-state VGS = 10 V; ID = 25 A - 3.5 4 mΩ
resistance VGS = 5 V; ID = 25 A - 4 5 mΩ

VGS = 4.5 V; ID = 25 A - - 5.4 mΩ

VGS = 5 V; ID = 25 A; Tj = 175˚C - - 9.25 mΩ
Gate-source leakage current VGS = ± 10 V; VDS = 0 V; - 0.02 100 nA
Zero gate voltage drain VDS = 25 V; VGS = 0 V; - 0.05 10 µA
current Tj = 175˚C - - 500 µA

Total gate charge ID = 75 A; V

= 15 V; VGS = 5 V - 97 - nC

DD

Gate-source charge - 20 - nC
Gate-drain (Miller) charge - 39 - nC

Turn-on delay time VDD = 15 V; RD = 1.2 Ω -45-ns
Turn-on rise time VGS = 5 V; RG = 5.6 Ω - 220 - ns
Turn-off delay time Resistive load - 435 - ns
Turn-off fall time - 320 - ns

Internal drain inductance Measured tab to centre of die - 3.5 - nH
Internal drain inductance Measured from drain lead to centre of die - 4.5 - nH

(SOT78 package only)
Internal source inductance Measured from source lead to source - 7.5 - nH

bond pad
Input capacitance VGS = 0 V; VDS = 20 V; f = 1 MHz - 6000 - pF

Output capacitance - 1700 - pF
Feedback capacitance - 1400 - pF

January 2000 2 Rev 1.200

Philips Semiconductors Product specification

N-channel logic level TrenchMOS transistor PSMN004-25B, PSMN004-25P

REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS

Tj = 25˚C unless otherwise specified

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

I

S

I

SM

V

SD

t

rr

Q

rr

Continuous source current - - 75 A
(body diode)
Pulsed source current (body - - 240 A
diode)
Diode forward voltage IF = 25 A; VGS = 0 V - 0.85 1.2 V

I

= 75 A; VGS = 0 V - 1.1 -

F

Reverse recovery time IF = 20 A; -dIF/dt = 100 A/µs; - 400 - ns
Reverse recovery charge VGS = 0 V; VR = 25 V - 1 - µC

January 2000 3 Rev 1.200

Philips Semiconductors Product specification

D

N-channel logic level TrenchMOS transistor PSMN004-25B, PSMN004-25P

Normalised Power Derating, PD (%)

100

90
80
70
60
50
40
30
20
10

0

0 25 50 75 100 125 150 175

Mounting Base temperature, Tmb (C)

Fig.1. Normalised power dissipation.

PD% = 100⋅PD/P

Normalised Current Derating, ID (%)

100

90
80
70
60
50
40
30
20
10

0

0 25 50 75 100 125 150 175

Mounting Base temperature, Tmb (C)

D 25 ˚C

= f(Tmb)

Fig.2. Normalised continuous drain current.

ID% = 100⋅ID/I

D 25 ˚C

= f(Tmb)

Transient thermal impedance, Zth j-mb (K/W)

1

D = 0.5

0.2

0.1

0.1

0.05

0.02

0.01

single pulse

0.001
1E-06 1E-05 1E-04 1E-03 1E-02 1E-01 1E+00

Pulse width, tp (s)

P

D

tp

D = tp/T

T

Fig.4. Transient thermal impedance.

Z

= f(t); parameter D = tp/T

th j-mb

Drain Current, ID (A)

100

10 V

90
80
70
60
50
40
30
20
10

0

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

5 V

4.5 V

Drain-Source Voltage, VDS (V)

2.8 V

Tj = 25 C

VGS = 2.6 V

2.4 V

2.2 V

2 V

1.8 V

Fig.5. Typical output characteristics, Tj = 25 ˚C.

ID = f(VDS)

Peak Pulsed Drain Current, IDM (A)

1000

RDS(on) = VDS/ ID

tp = 10 us

100

D.C.

10

1

1 10 100

Drain-Source Voltage, VDS (V)

100 us

1 ms

10 ms
100 ms

Fig.3. Safe operating area. Tmb = 25 ˚C

ID & IDM = f(VDS); IDM single pulse; parameter t

p

rain-Source On Resistance, RDS(on) (Ohms)

0.02

0.018

0.016

0.014

0.012

0.008

0.006

0.004

0.002

2 V 2.2 V

0.01

Tj = 25 C

0

0 102030405060708090100

2.4 V

Drain Current, ID (A)

2.6 V

5 V

VGS = 10V

2.8 V

4.5 V

Fig.6. Typical on-state resistance, Tj = 25 ˚C.

R

= f(ID)

DS(ON)

January 2000 4 Rev 1.200

Philips Semiconductors Product specification

N-channel logic level TrenchMOS transistor PSMN004-25B, PSMN004-25P

Drain current, ID (A)

100

VDS > ID X RDS(ON)

90
80
70
60
50
40
30
20
10

0

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3

Gate-source voltage, VGS (V)

175 C

Tj = 25 C

Fig.7. Typical transfer characteristics.

ID = f(VGS)

Transconductance, gfs (S)

140

VDS > ID X RDS(ON)

120

100

80

60

40

20

Tj = 25 C

175 C

Threshold Voltage, VGS(TO) (V)

2.25

2

1.75

1.5

1.25

1

0.75

0.5

0.25

0

-60 -40 -20 0 20 40 60 80 100 120 140 160 180
Junction Temperature, Tj (C)

maximum

typical

minimum

Fig.10. Gate threshold voltage.

V

= f(Tj); conditions: ID = 1 mA; VDS = V

GS(TO)

Drain current, ID (A)

1.0E-01
VDS = 5 V

1.0E-02

1.0E-03

1.0E-04

1.0E-05

minimum typical maximum

GS

0

0 102030405060708090100

Drain current, ID (A)

Fig.8. Typical transconductance, Tj = 25 ˚C.

gfs = f(ID)

Normalised On-state Resistance

2

1.9

1.8

1.7

1.6

1.5

1.4

1.3

1.2

1.1
1

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1
0

-60 -40 -20 0 20 40 60 80 100 120 140 160 180
Junction temperature, Tj (C)

Fig.9. Normalised drain-source on-state resistance.

R

DS(ON)/RDS(ON)25 ˚C

= f(Tj)

1.0E-06
0 0.5 1 1.5 2 2.5 3

Gate-source voltage, VGS (V)

Fig.11. Sub-threshold drain current.

ID = f(V

100000

10000

1000

0.1 1 10 100

Fig.12. Typical capacitances, C

; conditions: Tj = 25 ˚C; VDS = V

GS)

Capacitances, Ciss, Coss, Crss (pF)

Drain-Source Voltage, VDS (V)

, C

iss

C = f(VDS); conditions: VGS = 0 V; f = 1 MHz

Ciss

Coss

Crss

oss

, C

GS

.

rss

January 2000 5 Rev 1.200

Philips Semiconductors Product specification

N-channel logic level TrenchMOS transistor PSMN004-25B, PSMN004-25P

Gate-source voltage, VGS (V)

15

ID = 75 A

14
13

VDD = 15 V

12

Tj = 25 C

11
10

9
8
7
6
5
4
3
2
1
0

0 25 50 75 100 125 150 175 200 225 250

Gate charge, QG (nC)

Fig.13. Typical turn-on gate-charge characteristics.

V

= f(QG)

GS

Source-Drain Diode Current, IF (A)

100

VGS = 0 V

90
80
70
60
50
40
30
20
10

0

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2

175 C

Tj = 25 C

Source-Drain Voltage, VSDS (V)

Maximum Avalanche Current, I

100

10

1

0.001 0.01 0.1 1 10

Tj prior to avalanche = 150 C

Avalanche time, t

(A)

AS

25 C

(ms)

AV

Fig.15. Maximum permissible non-repetitive

avalanche current (IAS) versus avalanche time (tAV);

unclamped inductive load

Fig.14. Typical reverse diode current.

IF = f(V

); conditions: V

SDS

= 0 V; parameter T

GS

j

January 2000 6 Rev 1.200

Philips Semiconductors Product specification

N-channel logic level TrenchMOS transistor PSMN004-25B, PSMN004-25P

MECHANICAL DATA

Plastic single-ended package; heatsink mounted; 1 mounting hole; 3-lead TO-220 SOT78

AE

P

A

1

D

1

D

(1)

L

2

b

1

L

DIMENSIONS (mm are the original dimensions)

b

A

UNIT

mm

Note

1. Terminals in this zone are not tinned.

OUTLINE
VERSION

SOT78 TO-220

A

1

4.5

1.39

4.1

1.27

b

c

1

0.9

0.7

IEC JEDEC EIAJ

0.7

1.3

0.4

1.0

123

e

e

0 5 10 mm

D

D

1

15.8

6.4

15.2

5.9

REFERENCES

q

L

1

Q

L

2

max.

3.0

(1)

c

P

qQ

3.8

3.0

3.6

2.7

EUROPEAN

PROJECTION

2.6

2.2

ISSUE DATE

97-06-11

b

scale

e

10.3

9.7

E

2.54

15.0

13.5

L

L

1

3.30

2.79

Fig.16. SOT78 (TO220AB); pin 2 connected to mounting base (Net mass:2g)

Notes

1. This product is supplied in anti-static packaging. The gate-source input must be protected against static
discharge during transport or handling.

2. Refer to mounting instructions for SOT78 (TO220AB) package.

3. Epoxy meets UL94 V0 at 1/8".

January 2000 7 Rev 1.200

Philips Semiconductors Product specification

N-channel logic level TrenchMOS transistor PSMN004-25B, PSMN004-25P

MECHANICAL DATA

Plastic single-ended surface mounted package (Philips version of D2-PAK); 3 leads
(one lead cropped)

base

A

1

L

p

c

Q

E

D

1

D

H

D

2

13

b

e e

0 2.5 5 mm

scale

mounting

SOT404

A

DIMENSIONS (mm are the original dimensions)

A

UNIT

mm

A

4.50

4.10

OUTLINE

VERSION

SOT404

b

1

1.40

0.85

1.27

0.60

IEC JEDEC EIAJ

0.64

0.46

max.

11

D

D

1

1.60

1.20

REFERENCES

E

10.30

9.70

2.54

eLpHDQc

2.60

15.40

2.90

2.10

14.80

2.20

EUROPEAN

PROJECTION

ISSUE DATE

98-12-14
99-06-25

Fig.17. SOT404 surface mounting package. Centre pin connected to mounting base.

Notes

1. This product is supplied in anti-static packaging. The gate-source input must be protected against static
discharge during transport or handling.

2. Refer to SMD Footprint Design and Soldering Guidelines, Data Handbook SC18.

3. Epoxy meets UL94 V0 at 1/8".

January 2000 8 Rev 1.200

Philips Semiconductors Product specification

N-channel logic level TrenchMOS transistor PSMN004-25B, PSMN004-25P

MOUNTING INSTRUCTIONS

Dimensions in mm

9.0

3.8

11.5

17.5

2.0

5.08

Fig.18. SOT404 : soldering pattern for surface mounting.

DEFINITIONS

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and
operation of the device at these or at any other conditions above those given in the Characteristics sections of
this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

 Philips Electronics N.V. 2000

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the
copyright owner.

The information presented in this document does not form part of any quotation or contract, it is believed to be
accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under patent or other
industrial or intellectual property rights.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices or systems where malfunction of these
products can be reasonably expected to result in personal injury. Philips customers using or selling these products
for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting
from such improper use or sale.

January 2000 9 Rev 1.200