Datasheet PSD813F2, PSD813F2V, PSD813F3, PSD813F3V, PSD813F4 Datasheet (SGS Thomson Microelectronics)

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PRELIMINARY DATA

June 2003

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Rev. 3.0

PSD813F2/3/4/5, PSD833F2

PSD834F2, PSD853F2, PSD854F2

Flash In-System Pro gramma bl e

(ISP) Peripherals For 8-bit MCUs

FEATURES SUMMARY

■ 5V±10% Single Supply Voltage

■ Up to 2Mbit of Primary Flash Memory (8 uniform

sectors, 32K x 8)

■ Up to 256Kbit Secondary Flash Memory (4

uniform sectors)

■ Up to 2 56Kbi t SRAM

■ Over 3,000 Gates of PLD: DPLD and CPLD

■ 27 Reconfigurable I/O ports

■ Enhanced JTAG Serial Port

■ Programmable power managem ent

■ High Endurance:

– 100,000 Erase/WRITE Cycles of Flash

Memory

– 1,000 Erase/W RITE Cycles of PLD

Figure 1. 52-pin, Plastic, Quad, Flat Package

Figure 2. 52-lead, Plastic-Lead Chip Carrier

PQFP52 (T)

PLCC52 (K)

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TABLE OF CONTENTS

SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Table 1. Product Range (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

KEY FEATURES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 3. PSD8XXFX Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

PSD8XXFX ARCHITECTURAL OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Page Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

PLDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 2. PLD I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

MCU Bus Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

JTAG Port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

In-System Programming (ISP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Power Management Unit (PMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 3. JTAG SIgnals on Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 4. Methods of Programming Different Functional Blocks of the PSD8XXFX. . . . . . . . . . . . . 12

DEVELOPMENT SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 4. PSDsoft Express Development Tool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 5. Pin Description (for the PLCC52 package - Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

PSD8XXFX Register Description and Address Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 6. I/O Port Latched Address Output Assignments (Note1) . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 7. Register Address Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

DETAILED OPERATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

MEMORY BLOCKS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Primary Flash Memo ry and Seco nd ary Flash memo ry Descr iption . . . . . . . . . . . . . . . . . . . . . 18

Memory Block Select Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 8. Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Power-down Instruction and Power-up Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

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READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 9. Status Bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Programming Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

Figure 5. Data Polling Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 6. Data Toggle Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Erasing Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Specific Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 10. Sector Protection/Security Bit Definition – Flash Protection Register . . . . . . . . . . . . . . . 25

Table 11. Sector Protection/Security Bit Definition – PSD/EE Protection Register. . . . . . . . . . . . . 25

SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Sector Select and SRAM Select. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

Figure 7. Priority Level of Memory and I/O Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 12. VM Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 8. 8031 Memory Modules – Separate Space. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 9. 8031 Memory Modules – Combined Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Page Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 10. Page Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

PLDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 13. DPLD and CPLD Inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

The Turbo Bit in PSD8XXFX. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 11. PLD Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Decode PLD (DPLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 12. DPLD Logic Array. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Complex PLD (CPLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 13. Macrocell and I/O Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Output Macrocell (OMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 14. Output Macrocell Port and Data Bit Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Product Term Allocator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 14. CPLD Output Macrocell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Input Macrocells (IMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 15. Input Macrocell. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Figure 16. Handshaking Communication Using Input Macrocells. . . . . . . . . . . . . . . . . . . . . . . . . . 39

MCU BUS INTERFACE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 15. MCUs and their Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Figure 17. An Example of a Typical 8-bit Multiplexed Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . 41

Figure 18. An Example of a Typical 8-bit Non-Multiplexed Bus Interface . . . . . . . . . . . . . . . . . . . . 42

Table 16. Eight-Bit Data Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

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MCU Bus Interface Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Figure 19. Interfacing the PSD8XXFX with an 80C31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 17. 80C251 Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3

Table 18. Interfacing the PSD8XXFX with the 80C251, with One READ Input. . . . . . . . . . . . . . . . 44

Figure 20. Interfacing the PSD8XXFX with the 80C251, with RD and PSEN Inputs. . . . . . . . . . . . 45

Figure 21. Interfacing the PSD8XXFX with the 80C51X, 8-bit Data Bus. . . . . . . . . . . . . . . . . . . . . 46

Figure 22. Interfacing the PSD8XXFX with a 68HC11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

I/O PORTS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 8

General Port Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Figure 23. General I/O Port Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48

Port Operating Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

MCU I/O Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

PLD I/O Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Address Ou t Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 19. Port Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Table 20. Port Operating Mode Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Table 21. I/O Port Latched Address Output Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Address In Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Data Port Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Peripheral I/O Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1

JTAG In-System Programming (ISP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Figure 24. Peripheral I/O Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Port Configuration Registers (PCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Table 22. Port Configuration Registers (PCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Table 23. Port Pin Direction Control, Output Enable P.T. Not Defined . . . . . . . . . . . . . . . . . . . . . . 52

Table 24. Port Pin Direction Control, Output Enable P.T. Defined . . . . . . . . . . . . . . . . . . . . . . . . . 52

Table 25. Port Direction Assignment Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Table 26. Drive Register Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Port Data Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Table 27. Port Data Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Ports A and B – Functionality and Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Figure 25. Port A and Port B Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Port C – Functionality and Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Figure 26. Port C Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Port D – Functionality and Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Figure 27. Port D Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

External Chip Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 7

Figure 28. Port D External Chip Select Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

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POWER MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 8

Table 28. Power-down Mode’s Effect on Ports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Figure 29. APD Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Table 29. PSD8XXFX Timing and Stand-by Current during Power-down Mode. . . . . . . . . . . . . . . 59

Figure 30. Enable Power-down Flow Chart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

PLD Power Management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Table 30. Power Management Mode Registers PMMR0 (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . 61

Table 31. Power Management Mode Registers PMMR2 (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . 61

PSD Chip Select Input (CSI, PD2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62

Input Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Input Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Table 32. APD Counter Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

RESET TIMING AND DEVICE STATUS AT RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Warm Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

I/O Pin, Register and PLD Status at Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Reset of Flash Memory Erase and Program Cycles (on the PSD834Fx) . . . . . . . . . . . . . . . . . 63

Figure 31. Reset (RESET) Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Table 33. Status During Power-On Reset, Warm Reset and Power-down Mode. . . . . . . . . . . . . . 64

PROGRAMMING IN-CIRCUIT USING THE JTAG SERIAL INTERFACE . . . . . . . . . . . . . . . . . . . . . . 65

Standard JTAG Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Table 34. JTAG Port Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

JTAG Extensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 6

Security and Flash memory Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

INITIAL DELIVERY STATE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Table 35. JTAG Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 6

AC/DC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Figure 32. PLD ICC /Frequency Consumption (5 V range). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Figure 33. PLD ICC /Frequency Consumption (3 V range). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Table 36. Example of PSD8XXFX Typical Power Calculation at V

CC

= 5.0 V (Turbo Mode On) . . 69

Table 37. Example of PSD8XXFX Typical Power Calculation at V

CC

= 5.0 V (Turbo Mode Off) . . 70

MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Table 38. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

PSD8XXF2/3/4/5

6/103

DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2

Table 39. Operating Conditions (5V devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Table 40. Operating Conditions (3V devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Table 41. AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Figure 34. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Figure 35. AC Measurement Load Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Table 42. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Table 43. AC Symbols for PLD Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73

Figure 36. Switching Waveforms – Key. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73

Table 44. DC Characteristics (5V devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Table 45. DC Characteristics (3V devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Figure 37. Input to Output Disable / Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Table 46. CPLD Combinatorial Timing (5V devices). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76

Table 47. CPLD Combinatorial Timing (3V devices). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76

Figure 38. Synchronous Clock Mode Timing – PLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Table 48. CPLD Macrocell Synchronous Clock Mode Timing (5V devices) . . . . . . . . . . . . . . . . . . 77

Table 49. CPLD Macrocell Synchronous Clock Mode Timing (3V devices) . . . . . . . . . . . . . . . . . . 78

Figure 39. Asynchronous Reset / Preset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Figure 40. Asynchronous Clock Mode Timing (product term clock) . . . . . . . . . . . . . . . . . . . . . . . . 79

Table 50. CPLD Macrocell Asynchronous Clock Mode Timing (5V devices) . . . . . . . . . . . . . . . . . 80

Table 51. CPLD Macrocell Asynchronous Clock Mode Timing (3V devices) . . . . . . . . . . . . . . . . . 81

Figure 41. Input Macrocell Timing (product term clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Table 52. Input Macrocell Timing (5V devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Table 53. Input Macrocell Timing (3V devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Figure 42. READ Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Table 54. READ Timing (5V devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84

Table 55. READ Timing (3V devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85

Figure 43. WRITE Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 6

Table 56. WRITE Timing (5V devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87

Table 57. WRITE Timing (3V devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88

Table 58. Program, WRITE and Erase Times (5V devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Table 59. Program, WRITE and Erase Times (3V devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Figure 44. Peripheral I/O READ Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Table 60. Port A Peripheral Data Mode READ Timing (5V devices). . . . . . . . . . . . . . . . . . . . . . . . 90

Table 61. Port A Peripheral Data Mode READ Timing (3V devices). . . . . . . . . . . . . . . . . . . . . . . . 91

Figure 45. Peripheral I/O WRITE Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Table 62. Port A Peripheral Data Mode WRITE Timing (5V devices) . . . . . . . . . . . . . . . . . . . . . . . 92

Table 63. Port A Peripheral Data Mode WRITE Timing (3V devices) . . . . . . . . . . . . . . . . . . . . . . . 92

Figure 46. Reset (RESET) Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Table 64. Reset (RESET) Timing (5V devices). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Table 65. Reset (RESET) Timing (3V devices). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Table 66. V

STBYON

Timing (5V devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Table 67. V

STBYON

Timing (3V devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

7/103

PSD8XXF2/3/4/5

Figure 47. ISC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Table 68. ISC Timing (5V devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Table 69. ISC Timing (3V devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Table 70. Power-down Timing (5V devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Table 71. Power-down Timing (3V devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Figure 48. PQFP52 Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 6

Figure 49. PLCC52 Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Figure 50. PQFP52 - 52-pin Plastic, Quad, Flat Package Mechanical Drawing . . . . . . . . . . . . . . . 96

Table 72. PQFP52 - 52-pin Plastic, Quad, Flat Package Mechanica l Dimensions . . . . . . . . . . . . . 97

Figure 51. PLCC52 - 52-lead Plastic Lead, Chip Carrier Package Mechanical Drawing . . . . . . . . 98

Table 73. PLCC52 - 52-lead Plastic Lead, Chip Carrier Package Mechanical Dimensions . . . . . . 98

PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Table 74. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

APPENDIX A. PQFP52 PIN ASSIGNMENTS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

APPENDIX B. PLCC52 PIN ASSIGNMENTS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

PSD8XXF2/3/4/5

8/103

SUMMARY DESCRIPTION

The PSD8XXFX family of memory systems for mi­crocontrollers (MCUs) brings In-System-Program­mability (ISP) to Flash memory and programmable
logic. The result is a simple and flexible solution for
embedded designs. PSD8X X FX dev ices co mbine
many of the peripheral functions found in MCU
based applications.

Table 1 summarizes all the devices in the
PSD834F2, PSD853F2, PSD854F2.

The CPLD in the P SD 8XX FX devices features an
optimized macrocell logic architecture. The PSD
macrocell was created to address the unique re­quirements of embedded system designs. It al­lows direct connection between the system
address/data bus, and the internal PSD8XXFX
registers, to simplify communi cation between the
MCU and other supporting devices.

The PSD8XXFX device includes a JTAG Serial
Programming interface, to allow In-System Pro­gramming (ISP) of the

entire device

. This feature
reduces development time, simplifies the manu­facturing flow, and dramatically lowers the cost of
field upgrades. Using ST’s special Fast-JTAG pro­gramming, a design can be rapidly programmed
into the PSD8XXFX in as little as seven seconds.

The innovative PSD8XXFX family solves key
problems faced by designers when managing dis­crete Flash memory devices, such as:

– First-time In-System Programming (ISP)
– Complex address dec oding
– Simultaneous read and write to the device.
The JTAG Serial Interface block allows In-System

Programming (ISP), and eliminates the need for
an external Boot EPROM, or an external program­mer. To simplify Flash memory updates, program
execution is performed from a secondary Flash
memory while the primary Flash memory is being
updated. This solution avoids the complicated
hardware and software overhead necessary to im­plement IAP.

ST makes available a software devel opment tool,
PSDsoft Express, that generates ANSI-C com pli­ant code for us e w ith y our t arget M CU. T his code
allows you to manipulate the non-volatile memory
(NVM) within the PSD8XXFX. Code examples are
also provided for:

– Flash memory IAP via the UART of the host

MCU

– Memory paging to execute code across several

PSD8XXFX memory pages

– Loading, reading, and manipulation of

PSD8XXFX macrocells by the MCU.

Table 1. Product Range (Note 1)

Note: 1. All product s suppor t: JTAG se rial ISP, MCU para llel ISP, I SP Flash me mory, I SP CPLD, Security features, Power M anagem ent

Unit (PMU), Autom a t ic Power-down (APD )

2. SRAM ma y be backed up usi ng an external battery.

Part Number

Primary Flash

Memory

(8 Sectors)

Secondary

Flash Memory

(4 Sectors)

SRAM

2

I/O Ports

Number of

Macrocells

Serial

ISP

JTAG/

ISC Port

Turbo

Mode

Input Output

PSD813F2 1 Mbit 256 Kbit 16 Kbit 27 24 16 yes yes
PSD813F3 1 Mbit none 16 Kbit 27 24 16 yes yes
PSD813F4 1 Mbit 256 Kbit none 27 24 16 yes yes
PSD813F5 1 Mbit none none 27 24 16 yes yes
PSD833F2 1 Mbit 256 Kbit 64 Kbit 27 24 16 yes yes
PSD834F2 2 Mbit 256 Kbit 64 Kbit 27 24 16 yes yes
PSD853F2 1 Mbit 256 Kbit 256 Kbit 27 24 16 yes yes
PSD854F2 2 Mbit 256 Kbit 256 Kbit 27 24 16 yes yes

9/103

PSD8XXF2/3/4/5

KEY FEATURES

■ A simple interface to 8-bit microcontrollers that

use either multiplexed or non-multiplexed
busses. The bus interface logic uses the control
signals generated by the microcontroller
automatically when the address is decoded and
a READ or WRITE is performed. A partial list of
the MCU families supported include:

– Intel 8031, 80196, 80186, 80C251, and

80386EX

– Motorola 68HC11 , 68HC16, 68HC12, and

683XX
– Philips 8031 and 8051XA
– Zilog Z80 and Z8

■ Internal 1 or 2 Mbit Flash memory. This is the

main Flash memory. It is divided into eight
equal-sized blocks that can be accessed with
user-specified addresses.

■ Internal secondary 256 Kbit Flash boot memory.

It is di vided into f our equal-si zed blo cks that can
be accessed with user-specified addresses.
This seconda ry me mo ry brings th e abilit y to
execute code and update the main Flash

concurrently

.

■ Optional 16, 64 or 256 Kbit SRAM. The SRAM’s

contents can be protected from a power failure
by connecting an external battery.

■ CPLD with 16 Output Micro Cells (OMCs) and

24 Input Micro Cells (IMCs). The CPLD may be
used to efficiently implement a variety of logic
functions for internal and external control.
Examples include state machines, loadable
shift registers, and loadable counters.

■ Decode PLD (DPLD) that decodes address for

selection of internal memory blocks.

■ 27 individually configurable I/O port pins that

can be used for the following functions:
– MCU I/Os
–PLD I/Os
– Latched MCU address output
– Specia l function I/Os.
– 16 of the I/O ports may be configured as

open-drain outputs.

■ Standby current as low as 50 µA for 5 V devices.

■ Built-in JTAG compliant serial port allows full-

chip In-System Programmability (ISP). With it,
you can program a blank device or reprogram a
device in the factory or the field.

■ Internal page register that can be used to

expand the microcontroller address space by a
factor of 256.

■ Internal programmable Power Management

Unit (PMU) that supports a low power mode
called Power Down Mode. The PMU can
automatically detect a lack of microcontroller
activity and put the PSD8XXF into Power-down
mode.

■ Erase/WRITE cycles:

– Flash memory – 100,000 minimum
– PLD – 1,000 minimum
– Data Retention: 15 year minimum (for Main

Flash memory, Boot, PLD and Configuration
bits)

PSD8XXF2/3/4/5

10/103

Figure 3. PSD8XXFX Block Diagram

PROG.

MCU BUS

INTRF.

ADIO

PORT

CNTL0,

CNTL1,

CNTL2

AD0 – AD15

CLKIN

(PD1)

CLKIN

CLKIN

PLD

INPUT

BUS

PROG.

PORT

PORT

A

PROG.

PORT

PORT

B

POWER

MANGMT

UNIT

1 OR 2 MBIT PRIMARY

FLASH MEMORY

8 SECTORS

VSTDBY

PA0 – PA7

PB0 – PB7

PROG.

PORT

PORT

C

PROG.

PORT

PORT

D

PC0 – PC7

PD0 – PD2

ADDRESS/DATA/CONTROL BUS

PORT A ,B & C

3 EXT CS TO PORT D

24 INPUT MACROCELLS

PORT A ,B & C

73

73

256 KBIT SECONDARY

NON-VOLATILE MEMORY

(BOOT OR DATA)

4 SECTORS

256 KBIT BATTERY

BACKUP SRAM

RUNTIME CONTROL

AND I/O REGISTERS

SRAM SELECT

PERIP I/O MODE SELECTS

MACROCELL FEEDBACK OR PORT INPUT

CSIOP

FLASH ISP CPLD

(CPLD)

16 OUTPUT MACROCELLS

FLASH DECODE

PLD

(

DPLD

)

PLD, CONFIGURATION

& FLASH MEMORY

LOADER

JTAG

SERIAL

CHANNEL

(

PC2

)

PAGE

REGISTER

EMBEDDED

ALGORITHM

SECTOR

SELECTS

SECTOR

SELECTS

GLOBAL

CONFIG. &

SECURITY

AI02861E

8

11/103

PSD8XXF2/3/4/5

PSD8XXFX ARCHITECTURAL OVERVIEW

PSD8XXFX devices contain several major func­tional blocks. Figure 3 shows the architecture of
the PSD8XXFX device family. The functions of
each block are d escribed briefly in the following
sections. Many of the blocks perform multiple
functions and are user configurable.

Memory

Each of the memory blocks is briefly discussed in
the following paragraphs. A more detail ed di scus­sion can be fo und in the section ent itled “MEM O­RY BLOCKS“ on page 18.

The 1 Mbit or 2 Mbit (128K x 8, or 256K x 8) Flash
memory is the primary memory of the PSD8XXFX.
It is divided into 8 equally-sized sectors that are in­dividually selectable.

The optional 256 Kbit (32K x 8) secondary Flash
memory is divided into 4 equally-sized sectors.
Each sector is individually selectable.

The optional SRAM is intended for use as a
scratch-pad memory or as an extension to the
MCU SRAM. If an external battery is connected to
Voltage Stand-by (V

STBY

, PC2), data is retained in

the event of power failure.
Each sector of mem ory can be located in a differ-

ent address space as defined by the user. The ac­cess times for all memory types includes the
address latching and DPLD decoding time.

Page R egi s te r

The 8-bit Page Register expands the address
range of the MCU by up to 256 times. The paged
address can be used as part of the address space
to access external memory and peripherals, or in­ternal memory and I/O. The Page Register can
also be used to change the address mapping of
sectors of the Flash memories into different mem­ory spaces for IAP.

PLDs

The device contains t wo PLDs, the Decode PLD
(DPLD) and the Complex PLD (CPLD), as shown
in Table 2, each op timized for a different function.
The functional partitioning of the PLDs reduces
power consumption, optim izes cost/performance,
and eases design entry.

Table 2. PLD I/O

The DPLD is used to decode addresses and to
generate Sector Select signals for the PSD8XXFX
internal memory and registers. The DPLD has
combinatorial outputs. T he CPLD has 16 Output
Macrocells (OMC) and 3 combinatorial outputs.
The PSD8XXFX also has 24 Input Macrocells
(IMC) that can be configured as inputs to the
PLDs. The PLDs receive their inputs from the PLD
Input Bus and are differentiated by their output
destinations, number of product terms, an d mac­rocells.

The PLDs consume minimal power. The speed
and power consumption of the PLD i s controlled
by the Turbo bit in PMMR0 and othe r bits in the
PMMR2. These registers are set by the MCU at
run-time. There is a slight penalty to PLD propaga­tion time when invoking the power management
features.

I/O P or t s

The PSD8XXFX has 27 individually configurable I/
O pins distributed over the four ports (Port A , B, C,
and D). Each I/O pin can be individually configured
for different functions. Ports can be configured as
standard MCU I/O ports, PLD I/O, or latched ad­dress outputs for MCUs using multiplexed ad­dress/data buses.

The JTAG pins can be enabled o n Port C for In­System Programming (ISP).

Ports A and B can a lso be configured as a data
port for a non-multiplexed bus.

MCU Bus Interface

PSD8XXFX interfaces easily with most 8-bit
MCUs that have either multiplexed or non-multi­plexed address/data b uses. The de vice is config­ured to respond to the MCU’s control signals,
which are also used as inputs to the PLDs. For ex­amples, please see the section entitled “MCU Bus
Interface Examples“ on page 43.

Name Inputs Outputs

Product

Terms

Decode PLD (DPLD) 73 17 42
Complex PLD (CPLD) 73 19 140

PSD8XXF2/3/4/5

12/103

JTAG Port

In-System Programming (ISP) can be pe rformed
through the JTAG signals on Port C. This serial in­terface allows complete programming of the entire
PSD8XXFX device. A bla nk device can be com­pletely programmed. The JTAG signals (TMS,
TCK, TSTAT

, TERR, TDI, TDO) can be multi­plexed with other functions on P ort C. Table 3 in­dicates the JTAG pin assignments.

In-System Programming (ISP)

Using the JTAG signals on Port C, the entire
PSD8XXFX device can be programmed or erased
without the use of the MCU. The primary Flash
memory can also be programmed in-system by
the MCU executing the programming algorithms
out of the secondary memory, or SRAM. The sec­ondary memory can be programmed the same
way by executing out of the pri mary F lash m emo­ry. The PLD or other PSD8XXFX Configuration
blocks can be pr ogrammed thro ugh the JTAG port
or a device programmer. Table 4 in dicates which
programming methods can program different func­tional blocks of the PSD8XXFX.

Power Management Unit (PMU)

The Power Management Unit (PMU) gives the
user control of the power consumption on selected
functional blocks based on system requirements.
The PMU includes an Automatic Power-down
(APD) Unit that turns off device functions during

MCU inactivity. The APD Unit has a Power-down
mode that helps reduce power consump t ion.

The PSD8XXFX al so has some bi ts that are con­figured at run-time by the MCU to reduce power
consumption of the CPLD. The Turbo bit in
PMMR0 can be reset to 0 and the CPLD latches its
outputs and goes to sleep until the next transit ion
on its inputs.

Additionally, bits in PMMR2 can be set by the
MCU to block signals from entering the CP LD to
reduce power consumption. P lease see the sec­tion entitled “POWER MANAGEMENT” on page
58 for more details.

Table 3. JTAG SIgnals on Port C

Table 4. Methods of Programming Different Functional Blocks of the PSD8XXFX

Port C Pins JTAG Signal

PC0 TMS
PC1 TCK
PC3 TSTAT
PC4 TERR
PC5 TDI
PC6 TDO

Functional Block JTAG Programming Device Programmer IAP

Primary Flash Memory Yes Yes Yes
Secondary Flash Memory Yes Yes Yes
PLD Array (DPLD and CPLD) Yes Yes No
PSD8XXFX Config urati on Yes Yes No

13/103

PSD8XXF2/3/4/5

DEVELOPMEN T SYST EM

The PSD8XXFX family is supported by PSDsoft
Express, a Windows-based software development
tool. A PSD8XXFX design is quickly and easily
produced in a point and click environment. The de­signer does not need to enter Hardware Descrip­tion Language (HDL) equations, unless desired, to
define PSD8XXFX pin functions and memory map
information. The general desig n flow is shown in
Figure 4. PSDsoft Express is available from our

web site (the address is given on the back page of
this data sheet) or other distribution channels.

PSDsoft Express directly supports two low cost
device programmers form ST: PSDpro and
FlashLINK (JTAG). Both of these programmers
may be purchased through your local distributor/
representative, or directly from our web site using
a credit card. The PSD8XXFX is also supported by
third party device programm ers. See our web site
for the current list.

Figure 4. PSDsoft Express Development Tool

PSD Configuration

PSD Fitter

PSD Simulator

PSD Programmer

*.OBJ FILE

PLD DESCRIPTION

CONFIGURE MCU BUS

INTERFACE AND OTHER

PSD ATTRIBUTES

LOGIC SYNTHESIS

AND FITTING

PSDsilos III

DEVICE SIMULATION

(OPTIONAL)

PSDPro, or

FlashLINK (JTAG)

ADDRESS TRANSLATION

AND MEMORY MAPPING

PSDabel

MODIFY ABEL TEMPLATE FILE

OR GENERATE NEW FILE

PSD TOOLS

GENERATE C CODE

SPECIFIC TO PSD

FUNCTIONS

USER'S CHOICE OF

MICROCONTROLLER

COMPILER/LINKER

*.OBJ AND *.SVF

FILES AVAILABLE

FOR 3rd PARTY

PROGRAMMERS

(CONVENTIONAL or

JTAG-ISC)

FIRMWARE

HEX OR S-RECORD

FORMAT

AI04918

PSD8XXF2/3/4/5

14/103

PIN DESCRIPTION

Table 5 describes the signal names and signal
functions of the PSD8XXFX.

Table 5. Pin Description (for the PLCC52 package - Note 1)

Pin Name Pin Type Description

ADIO0-7 30-37 I/O

This is the lower Address/Data port. Connect your MCU address or address/data bus
according to the following rules:

1. If your MCU has a multiplexed address/data bus where the data is multiplexed with the
lower address bits, connect AD0-AD7 to this port.

2. If your MCU does not have a multiplexed address/data bus, or you are using an
80C251 in page mode, connect A0-A7 to this port.

3. If you are using an 80C51XA in burst mode, connect A4/D0 through A11/D7 to this
port.
ALE or AS latches the address. The PSD8XXFX drives data out only if the READ signal is
active and one of the PSD8XXFX functional blocks was selected. The addresses on this
port are passed to the PLDs.

ADIO8-15 39-46 I/O

This is the upper Address/Data port. Connect your MCU address or address/data bus
according to the following rules:

1. If your MCU has a multiplexed address/data bus where the data is multiplexed with the
lower address bits, connect A8-A15 to this port.

2. If your MCU does not have a multiplexed address/data bus, connect A8-A15 to this
port.

3. If you are using an 80C251 in page mode, connect AD8-AD15 to this port.

4. If you are using an 80C51XA in burst mode, connect A12/D8 through A19/D15 to this
port.
ALE or AS latches the address. The PSD8XXFX drives data out only if the READ signal is
active and one of the PSD8XXFX functional blocks was selected. The addresses on this
port are passed to the PLDs.

CNTL0 47 I

The following control signals can be connected to this port, based on your MCU:

1. WR

– active Low Write Strobe input.

2. R_W

– active High READ/active Low write input.
This port is connected to the PLDs. Therefore, these signals can be used in decode and
other logic equations.

CNTL1 50 I

The following control signals can be connected to this port, based on your MCU:

1. RD

– active Low Read Strobe input.

2. E – E clock input.

3. DS

– active Low Data Strobe input.

4. PSEN

– connect PSEN to this port when it is being used as an active Low READ

signal. For example, when the 80C251 outputs more than 16 address bits, PSEN

is
actually the READ signal.
This port is connected to the PLDs. Therefore, these signals can be used in decode and
other logic equations.

CNTL2 49 I

This port can be used to input the PSEN

(Program Select Enable) signal from any MCU
that uses this signal for code exclusively. If your MCU does not output a Program Select
Enable signal, this port can be used as a generic input. This port is connected to the
PLDs.

Reset

48 I

Resets I/O Ports, PLD macrocells and some of the Configuration Registers. Must be Low
at Power-up.

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PSD8XXF2/3/4/5

PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7

29
28
27
25
24
23
22
21

I/O

These pins make up Port A. These port pins are configurable and can have the following
functions:

1. MCU I/O – write to or read from a standard output or input port.

2. CPLD macrocell (McellAB0-7) outputs.

3. Inputs to the PLDs.

4. Latched address outputs (see Table 6).

5. Address inputs. For example, PA0-3 could be used for A0-A3 when using an 80C51XA
in burst mode.

6. As the data bus inputs D0-D7 for non-multiplexed address/data bus MCUs.

7. D0/A16-D3/A19 in M37702M2 mode.

8. Peripheral I/O mode.
Note: PA0-P A3 can only output CMOS signals with an option for high slew rate. However,
PA4-PA7 can be configured as CMOS or Open Drain Outputs.

PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7

7
6
5
4
3
2
52
51

I/O

These pins make up Port B. These port pins are configurable and can have the following
functions:

1. MCU I/O – write to or read from a standard output or input port.

2. CPLD macrocell (McellAB0-7 or McellBC0-7) outputs.

3. Inputs to the PLDs.

4. Latched address outputs (see Table 6).
Note: PB0-PB3 can only output CMOS signals with an option for high slew rate. However,
PB4-PB7 can be configured as CMOS or Open Drain Outputs.

PC0 20 I/O

PC0 pin of Port C. This port pin can be configured to have the following functions:

1. MCU I/O – write to or read from a standard output or input port.

2. CPLD macrocell (McellBC0) output.

3. Input to the PLDs.

4. TMS Input

2

for the JTAG Serial Interface.

This pin can be configured as a CMOS or Open Drain output.

PC1 19 I/O

PC1 pin of Port C. This port pin can be configured to have the following functions:

1. MCU I/O – write to or read from a standard output or input port.

2. CPLD macrocell (McellBC1) output.

3. Input to the PLDs.

4. TCK Input

2

for the JTAG Serial Interface.

This pin can be configured as a CMOS or Open Drain output.

PC2 18 I/O

PC2 pin of Port C. This port pin can be configured to have the following functions:

1. MCU I/O – write to or read from a standard output or input port.

2. CPLD macrocell (McellBC2) output.

3. Input to the PLDs.

4. V

STBY

– SRAM stand-by voltage input for SRAM battery backup.

This pin can be configured as a CMOS or Open Drain output.

PC3 17 I/O

PC3 pin of Port C. This port pin can be configured to have the following functions:

1. MCU I/O – write to or read from a standard output or input port.

2. CPLD macrocell (McellBC3) output.

3. Input to the PLDs.

4. TSTAT

output2 for the JTAG Serial Interface.

5. Ready/Busy

output for parallel In-System Programming (ISP).

This pin can be configured as a CMOS or Open Drain output.

PC4 14 I/O

PC4 pin of Port C. This port pin can be configured to have the following functions:

1. MCU I/O – write to or read from a standard output or input port.

2. CPLD macrocell (McellBC4) output.

3. Input to the PLDs.

4. TERR

output2 for the JTAG Serial Interface.

5. Battery-on Indicator (VBATON). Goes High when power is being drawn from the
external battery.
This pin can be configured as a CMOS or Open Drain output.

Pin Name Pin Type Description

PSD8XXF2/3/4/5

16/103

Note: 1. The pin numbers in this t abl e are for the PLCC package only. See the package inf ormation, on page 98 onwards, for pin nu mb ers

on other pa ck age types.

2. These functions ca n be m ultiplexe d wi th other functions.

PSD8XXFX REGISTER DESCRIPTION AND ADDRESS OFFSET

Table 7 shows the offset addresses to the
PSD8 XXFX regis ters re lati ve to th e CS IOP ba se
address. The CSIOP space is the 256 bytes of ad­dress that is allocated by the user to the internal

PSD8XXFX registers. Table 7 provides brief de­scriptions of the registers in CSIOP space. The fol­lowing section gives a more detailed description.

PC5 13 I/O

PC5 pin of Port C. This port pin can be configured to have the following functions:

1. MCU I/O – write to or read from a standard output or input port.

2. CPLD macrocell (McellBC5) output.

3. Input to the PLDs.

4. TDI input

2

for the JTAG Serial Interface.

This pin can be configured as a CMOS or Open Drain output.

PC6 12 I/O

PC6 pin of Port C. This port pin can be configured to have the following functions:

1. MCU I/O – write to or read from a standard output or input port.

2. CPLD macrocell (McellBC6) output.

3. Input to the PLDs.

4. TDO output

2

for the JTAG Serial Interface.

This pin can be configured as a CMOS or Open Drain output.

PC7 11 I/O

PC7 pin of Port C. This port pin can be configured to have the following functions:

1. MCU I/O – write to or read from a standard output or input port.

2. CPLD macrocell (McellBC7) output.

3. Input to the PLDs.

4. DBE – active Low Data Byte Enable input from 68HC912 type MCUs.
This pin can be configured as a CMOS or Open Drain output.

PD0 10 I/O

PD0 pin of Port D. This port pin can be configured to have the following functions:

1. ALE/AS input latches address output from the MCU.

2. MCU I/O – write or read from a standard output or input port.

3. Input to the PLDs.

4. CPLD output (External Chip Select).

PD1 9 I/O

PD1 pin of Port D. This port pin can be configured to have the following functions:

1. MCU I/O – write to or read from a standard output or input port.

2. Input to the PLDs.

3. CPLD output (External Chip Select).

4. CLKIN – clock input to the CPLD macrocells, the APD Unit’s Power-down counter, and
the CPLD AND Array.

PD2 8 I/O

PD2 pin of Port D. This port pin can be configured to have the following functions:

1. MCU I/O – write to or read from a standard output or input port.

2. Input to the PLDs.

3. CPLD output (External Chip Select).

4. PSD Chip Select Input (CSI

). When Low, the MCU can access the PSD8XXFX
memory and I/O. When High, the PSD8XXFX memory blocks are disabled to conserve
power.

V

CC

15, 38 Supply Voltage

GND

1, 16,
26

Ground pins

Pin Name Pin Type Description

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PSD8XXF2/3/4/5

Table 6. I/O Port Latched Address Output Assignments (Note1)

Note: 1. See the sect i on entitle d “I/O PORTS”, on page 48, on how to enabl e the Latch ed A ddress Output funct i on.

2. N/A = Not Applicable

Table 7. Register Address Offset

Note: 1. Other registers that are not part of the I/O ports.

MCU

Port A Port B

Port A (3:0) Port A (7:4) Port B (3:0) Port B (7:4)

8051XA (8-bit) N/A Address a7-a4 Address a11-a8 N/A
80C251 (page mode) N/A N/A Address a11-a8 Address a15-a12
All other 8-bit multiplexed Address a3-a0 Address a7-a4 Address a3-a0 Address a7-a4
8-bit non-multiplexed bus N/A N/A Address a3-a0 Address a7-a4

Register Name Port A Port B Port C Port D

Other

1

Description

Data In 00 01 10 11 Reads Port pin as input, MCU I/O input mode
Control 02 03 Selects mode between MCU I/O or Address Out

Data Out 04 05 12 13

Stores data for output to Port pins, MCU I/O output
mode

Direction 06 07 14 15 Configures Port pin as input or output

Drive Select 08 09 16 17

Configures Port pins as either CMOS or Open
Drain on some pins, while selecting high slew rate
on other pins.

Input Macrocell 0A 0B 18 Reads Input Macrocells

Enable Out 0C 0D 1A 1B

Reads the status of the output enable to the I/O
Port driver

Output Macrocells
AB

20 20

READ – reads output of macrocells AB
WRITE – loads macrocell flip-flops

Output Macrocells
BC

21 21

READ – reads output of macrocells BC

WRITE – loads macrocell flip-flops
Mask Macrocells AB 22 22 Blocks writing to the Output Macrocells AB
Mask Macrocells BC 23 23 Blocks writing to the Output Macrocells BC
Primary Flash

Protection

C0 Read only – Primary Flash Sector Protection

Secondary Flash
memory Protection

C2

Read only – PSD8XXFX Security and Secondary

Flash memory Sector Protection
JTAG Enable C7 Enables JTAG Port
PMMR0 B0 Power Management Register 0
PMMR2 B4 Power Management Register 2
Page E0 Page Register

VM E2

Places PSD8XXFX memory areas in Program

and/or Data space on an individual basis.

PSD8XXF2/3/4/5

18/103

DETAILED OPERATION

As shown in Figure 3, the PSD8XXFX cons i sts of
six major types of functional blocks:

■ Memory Blocks

■ PLD Blocks

■ MCU Bus Interface

■ I/O Ports

■ Power Management Unit (PMU)

■ JTAG Interface

The functions of ea ch block are described i n the
following sections. Many of the blocks perform
multiple functions, and are user configurable.

MEMORY BLOCKS

The PSD8XXFX has the following memory blocks:
– Primary Flash memory
– Optional Secondary Flash memory
– Optio nal SRAM
The Memory Select signals for these blocks origi-

nate from the Decode PLD (DP LD) and are user­defined in PSDsoft Express.

Primary Flash Memory and Secon dary F lash
memory Description

The primary Flash memory is divided evenly into
eight equal sectors. The secondary Flash memory
is divided into four e qual sectors. Each sect or of
either memory block can be s eparately protected
from Program and Erase cycles.

Flash memory may be erased on a sector-by-sec­tor basis. Flash sector erasure may be suspended
while data is read from other sectors of the block
and then resumed after reading.

During a Program or Erase cycle in Flash memory,
the status can be output on Ready/Busy

(PC3).
This pin is set up using PSDsoft Express Configu­ration.

Memory Block Select Signals

The DPLD generates the Select signals fo r all the
internal memory blocks (see the section entitled
“PLDS”, on p age 30 ). Eac h o f the eight sectors of
the primary Flash memory has a Select signal

(FS0-FS7) which can contain up to three prod uct
terms. Each of the four sectors of the secondary
Flash memory has a Select signal (CSBOOT0­CSBOOT3) which can contain up to three product
terms. Having three product terms for each Select
signal allows a given sector to be mapped in differ­ent areas of system memory. When using a MCU
with separate Program and Data space, these
flexible Select signals allow dynamic re-mapping
of sectors from one memory space to the other.

Ready/Busy

(PC3). This signal can be used to

output the Ready/Busy

status of the PSD8XXF X.

The output on Ready/Busy

(PC3) is a 0 (Busy)

when Flash memory is being written to,

or

when
Flash memory is being erased. The output is a 1
(Ready) when no WRITE or Erase cycle is in
progress.

Memory Operation . The primary Flash memory
and secondary Flash memory are addressed
through the MCU Bus Interface. The MCU can ac­cess these memories in one of two ways:

■ The MCU can execute a typical bus WRITE or

READ

operation

just as it would if accessing a

RAM or ROM device using standard bus cycles.

■ The MCU can execute a specific instruction that

consists of several WRITE and READ
operations. This involves writing specific data
patterns to special addresses within the Flash
memory to invoke an embedded algorithm.
These instructions are summarized in Table 8.

Typically, the MCU can read Flash memory using
READ operations, just as it would read a ROM de­vice. However, Flash memory can only be altered
using specific Erase and Program instructions. For
example, the MCU cannot write a single by te di­rectly to Flash memory as it would write a byte to
RAM. To program a byte into Flash memory, t he
MCU must execute a Program instruction, then
test the status of the Program cycle. This status
test is achieved by a READ operation or polling
Ready/Busy

(PC3).

Flash memory can also be read by using special
instructions to retrieve particular Flash devi ce in­formation (sector protect status and ID).

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PSD8XXF2/3/4/5

Table 8. Instructions

Note: 1. All bus cyc l es are WRITE bus cycles, except the ones with the “READ” label

2. All values are in hexadecimal:
X = Don’t Care. Addresses of the form X XXXh, in this table, must be even addres ses
RA = Address of the memory l ocation to be read
RD = Data re ad from loca ti on RA during t he READ cyc le
PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of Write Strobe (WR

, CNTL0).
PA is an even address fo r P SD in word programmin g mode.
PD = Data word to be progr am m ed at location PA. Data is la tc hed on the rising edge of Write Strobe (WR

, CNTL0)
SA = Addr ess of the se ctor to be erased or ve rified. T he Sec tor Sel ect (FS 0-FS7 o r CSB OOT0-CSBO OT3) of the se ctor t o be
erased, or verified, must be Active (High).

3. Sector Se l ect (FS0 to FS7 or CSBOOT0 to C SBOOT3) signals are act i ve High, and ar e defined in PSD soft Expre ss .

4. Only address bits A11-A0 are used in instruction decoding.

5. No Unloc k or instruction cycles are required when the devic e i s in the READ Mode

6. The Reset instruction is required to return to the READ Mode after reading the Flash ID, or after reading the Sector Protection Sta­tus, or if the Er ror Flag (DQ5/DQ13) bit goes High.

7. Additi onal sectors to be erased must be written at the end of t he Sector Erase i nstructi on within 80µs.

8. The dat a is 00h for an unp rotected sector, and 01h for a protec ted sector. In the fourth c ycle, the Sec tor Select i s active, and
(A1,A0)= (1,0)

9. The Unlock Bypass instruction is required prior to the Unlock Bypass Program instruction.

10. The Unlock Bypas s Reset Flas h i nstructi on is requi red to return to readi ng memory data when t he device is i n the Unloc k Bypass
mode.

11. The system may perform READ and Program cycles in non-erasing sectors, read the Flash ID or read the Sector Protection Status
when in the S uspend Sector Erase mo de. T he Suspend Sector Erase instruction is valid only during a Secto r E rase cycle.

12. The Resume Sector Erase instruction is valid only during the Suspend Sector Erase mode.

13. The MCU can not i nvok e these inst ruct ion s whi le exe cutin g cod e from th e sa me Flash mem ory as t hat fo r which th e ins truc tio n is
intended. The MCU must fetch, for example, the code from the secondary Flash memory when reading the Sector Protection Status
of th e prima ry Flas h m em o ry.

Instruction

FS0-FS7 or
CSBOOT0-

CSBOOT3

Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7

READ

5

1

“READ”
RD @ RA

Read Main
Flash ID

6

1

AAh@
X555h

55h@
XAAAh

90h@
X555h

Read identifier
(A6,A1,A0 = 0,0,1)

Read Sector
Protection

6,8,13

1

AAh@
X555h

55h@
XAAAh

90h@
X555h

Read identifier
(A6,A1,A0 = 0,1,0)

Program a
Flash Byte

13

1

AAh@
X555h

55h@
XAAAh

A0h@
X555h

PD@ PA

Flash Sector
Erase

7,13

1

AAh@
X555h

55h@
XAAAh

80h@
X555h

AAh@ XAAAh

55h@
XAAAh

30h@
SA

30h

7

@

next SA

Flash Bulk
Erase

13

1

AAh@
X555h

55h@
XAAAh

80h@
X555h

AAh@ XAAAh

55h@
XAAAh

10h@
X555h

Suspend
Sector Erase

11

1

B0h@
XXXXh

Resume
Sector Erase

12

1

30h@
XXXXh

Reset

6

1

F0h@
XXXXh

Unlock Bypass 1

AAh@
X555h

55h@
XAAAh

20h@
X555h

Unlock Bypass
Program

9

1

A0h@
XXXXh

PD@ PA

Unlock Bypass
Reset

10

1

90h@
XXXXh

00h@
XXXXh

PSD8XXF2/3/4/5

20/103

INSTRUCTIONS

An instruction consists of a sequenc e of specific
operations. Each received byte is sequentially de­coded by the PSD8XXFX and not executed as a
standard WRITE operation. The instruction is exe­cuted when the correct number of bytes are prop­erly received and the time between two
consecutive bytes is shorter t han the tim e-out pe­riod. Some instructions are structured to include
READ operations after the initial WRITE opera­tions.

The instruction must be followed exactly. A ny in­valid combination of instruction bytes or time-out
between two consecutive by tes while addressing
Flash memory reset s the device logic into REA D
Mode (Flash memory is read like a ROM device).

The PSD8XXFX supports the instructions summa­rized in Table 8:

Flash memory:

■ Erase memory by chip or sector

■ Suspend or resume sector erase

■ Program a Byte

■ Reset to READ Mode

■ Read primary Flash Identifier value

■ Read Sector Protection Status

■ Bypass (on the PSD833F2, PSD834F 2,

PSD853F2 and PSD854F2)

These instructions are detailed in Table 8. F or ef­ficient decoding of the instructions, the first two
bytes of an instruct ion are the coded cycles and
are followed by an instruction byte or confirmation
byte. The coded cycles consist of writing the data
AAh to address X555h during the first cycle and
data 55h to address XAAAh during the second cy­cle. Address signals A15-A12 are Do n’t Care dur­ing the instruction WRITE cycles. However, the
appropriate Sector Select (FS0-FS7 or
CSBOOT0-CSBOOT3 ) m ust be selected.

The primary and secondary Flash memories have
the same instruction set (except for Read Primary
Flash Identifier). The Sector Select signals deter­mine which Flash memory is to receive and exe­cute the instruction. The primary Flash memory is
selected if any one of Sector Select (FS0-FS7) is
High, and the secondary Flash memory is selected
if any one of Sector Select (CSBOOT0­CSBOOT3) is High.

Power-down Instruction and Power-up Mode
Power-up Mode. The PSD8XXFX internal logic

is reset upon Power-up to the READ Mode. Sector
Select (FS0-FS7 and CSBOOT0-CSBOOT3)

must be held Low, and Write Strobe (WR

, CNTL0)
High, during Power-up for maximum security of
the data contents and to remove the poss ibility of
a byte being written on the first edge of Write
Strobe (WR

, CNTL0). Any WRITE cycle initiation

is locked when V

CC

is below V

LKO

.

READ

Under typical conditions, the MCU may read t he
primary Flash memory or the secondary Flash
memory using READ operations just as it would a
ROM or RAM device. Alternately, the MCU may
use READ operations to ob tain status inform at ion
about a Program or Erase cycle that is currently in
progress. Lastly, the MCU may use instructions to
read special data from these memory blocks. The
following sections describe these READ functions.

Read Memory Contents. Primary Flash memor y
and secondary Flash memory are placed in the
READ Mode after Power-up, chip reset, or a Reset
Flash instruction (see Table 8). The MCU can read
the memory contents of the primary Flash memory
or the secondary Flash memory by using RE AD
operations any time the READ operation is not
part of an instruction.

Read Primary Flash Identifier. The primary
Flash memory identifier is read with an instruction
composed of 4 operations: 3 specific WRITE oper­ations and a RE AD operation (see Table 8). Dur­ing the READ operation, address bits A6, A1, and
A0 must be 0,0,1, respectivel y, and the appropri­ate Sector Select (FS0-FS7) must be High. The
identifier for the PSD813F2/3/4/5 is E4h, and for
the PSD83xF2 or PSD85xF2 it is E7h.

Read Memory Sector Protection Status. The
primary Flash memory Sector Protection Status is
read with an instruction composed of 4 operations:
3 specific WRITE operations and a READ opera­tion (see Table 8). During the READ operation, ad­dress bits A6, A1, and A0 must be 0,1,0,
respectively, while Sector Select (FS0-FS7 or
CSBOOT0-CSBOOT3) designates the Flash
memory sector whose protection has to be veri­fied. The READ operation produces 01h if the
Flash memory sector is protected, or 00h if the
sector is not protected.

The sector protection status for all NVM blocks
(primary Flash memory or secondary Flash mem­ory) can also b e read by the M CU accessing the
Flash Protection registers in PSD I/O space. See
the section entitled “Flash Memory Sector Pro­tect”, on page 25, for register definitions.

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PSD8XXF2/3/4/5

Reading the Erase/Program Status Bits. The

PSD8XXFX provides several status bits to be
used by the MCU to confirm th e completion of an
Erase or Program cycle of Flash memory. These
status bits minimize the time that the M CU spends
performing these tasks and are defined in Table 9.
The status bits can be read as many times as
needed.

For Flash memory, the MCU can perform a READ
operation to obtain these status bits while an
Erase or Program instruction is being executed by
the embedded algo rithm. See the section ent itled
“Programming Flash Memory”, on page 22, for de­tails.

Data Polling Flag (DQ7). When erasing or pro­gramming in Flash memory, the Data Polling Flag
(DQ7) bit outputs the compl em ent of the bit bei ng
entered for programming/writing on the DQ7 bit.
Once the Program instruction or the WRITE oper­ation is completed, the true logic value i s read on
the Data Polling Flag (DQ7) bit (in a READ opera­tion).

■ Data Polling is effective after the fourth WRITE

pulse (for a Program instruction) or after the
sixth WRITE pulse (for an Erase instruction). It
must be performed at the address being
programmed or at an address within the Flash
memory sector being erased.

■ During an Erase cycle, the Data Pollin g Flag

(DQ7) bit outputs a 0. After completion of the
cycle, the Data Polling Flag (DQ7) bit outputs
the last bit programmed (it is a 1 after erasing).

■ If the byte to be programmed is in a protected

Flash memory sector, the instruction is ignored.

■ If all the Flash memory sectors to be erased are

protected, the Data Po lling Flag (DQ7) b it is
reset to 0 for about 100µs, and then returns to
the previous addressed byte. No erasure is
performed.

Toggle Fla g (D Q6) . The PSD8XXFX offers an­ot her wa y f or de t er m in in g wh en t h e F lash memory
Program cycle is completed. During the internal
WRITE operation and when either the FS0-FS7 or
CSBOOT0-CSBOOT3 is true, the Toggle Flag
(DQ6) bit toggles from 0 to 1 and 1 to 0 on subse­quent attempts to read any byte of the memory.

When the internal cycle is complete, the toggling
stops and the data read on the Data Bus D0-D7 is
the addressed memory byte. The device is now
accessible for a new READ or WRITE operation.
The cycle is finished when two successive READs
yield the same output data.

■ The Toggle Flag (DQ6) bit is effective after the

fourth WRITE pulse (for a Program instruction)
or after the sixth WRITE pulse (for an Erase
instruction).

■ If the byte to be programmed belongs to a

protected Flash memory sector, the instruction
is ignored.

■ If all the Flash memory sectors selected for

erasure are protected, the Toggle Flag (DQ6) bit
toggles to 0 for about 100µs and then returns to
the previous addressed byte.

Error Flag (DQ5). During a normal Program or
Erase cycle, the Error Flag (DQ5) bit is to 0. This
bit is set to 1 when there is a failure during Flash
memory Byte Program, Sector Erase, or Bulk
Erase cycle.

In the case of Flash memory programming, the Er­ror Flag (DQ5) bit indicates the attempt to program
a Flash memory bit from the programmed state, 0,
to the erased state, 1, which is not valid. The Error
Flag (DQ5) bit may also indicate a Time-out condi­tion while attempting to program a byte.

In case of an error in a Flash memory Sector Erase
or Byte Prog ram cycle, th e Flash memory sector i n
which the error occurred or to which the pro­grammed byte bel ongs must no longer be used.
Other Flash memory sectors may still be used.
The Error Flag (DQ5) bit is reset after a Reset
Flash instruction.

Erase Time-out Flag (DQ3). The Erase Time­out Flag (DQ3) bit reflects the time-out period al­lowed between two consecutive S ector Erase in­structions. The Erase Time-out Flag (DQ3) bit is
reset to 0 after a Sector Erase cycle for a time pe­riod of 100µs + 20% unless an additional Sector
Erase instruction is decoded. After this time peri­od, or when the additional Sector Erase instruction
is decoded, the Eras e Time-out Flag (DQ3) bit is
set to 1.

Table 9. Status Bit

Note: 1. X = Not guaranteed value , c an be read either 1 or 0.

2. DQ7-DQ0 represent the Data Bus bits, D7-D0.

3. FS0-FS 7 and CSBOO T 0-CSBOOT 3 are active High.

Functional Block

FS0-FS7/CSBO OT0-

CSBOOT3

DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0

Flash Memory

V

IH

Data
Polling

Toggle
Flag

Error
Flag

X

Erase
Time­out

XXX

PSD8XXF2/3/4/5

22/103

Programming Flash Memory

Flash memory must be erased prior to being pro­grammed. A byte of Flash memory is erased to all
1s (FFh), and is programmed by setting selected
bits to 0. The MCU may erase Fl ash memory all at
once or by-sector, but not byte-by-byte. Howe ve r,
the MCU may program Flash memory byte-by­byte.

The primary and secondary Flash memories re­quire the MCU to send an instruction to program a
byte or to erase sectors (see Table 8).

Once the MCU issues a Flash memory Program or
Erase instruction, it must check for the status bits
for completion. The embedded algorithms that are
invoked inside the PSD8XXFX support several
means to provide status to the MCU. Status may
be checked using any of three methods: Data Poll­ing, Data Toggle, or Ready/Busy

(PC3).

Data Polling. Polling on the Data Polling Flag
(DQ7) bit is a method of checking whether a P ro­gram or Erase cycle is in progress or has complet­ed. Figure 5 shows the Data Polling algorithm.

When the MCU i ssues a Program i nstruction, the
embedded algorithm within the PSD8XXFX be­gins. The MCU then reads the location of the byte
to be programmed in Flash memory to check sta­tus. The Data Polling Flag (DQ7) bit of this location
becomes the complement of b7 of the original data
byte to be programmed. The MCU continues to
poll this location, comparing the Dat a P olling Fl ag
(DQ7) bit and monitoring the Error Flag (DQ5) bit.
When the Data Polling Flag (DQ7) bit matches b7
of the original data, and the E rror Flag (DQ5) bit
remains 0, the embedded algorithm is complete. If
the Error Flag (DQ5) bit is 1, the MCU should test
the Data Polling Flag (DQ7) bit again since the
Data Polling Flag (DQ7) bit may have changed si­multaneously with the Error Flag (DQ5) bit (see
Figure 5).

The Error Flag (DQ5) bit is set if either an internal
time-out occurred while the embedded algorithm
attempted to program the byte or if the MCU at­tempted to program a 1 to a bit that was not erased
(not erased is logic 0).

It is suggested (as with all Flash memories) to read
the location again after the embedded program-

ming algorithm has completed, to compare the
byte that was written to the Flash memory with the
byte that was intended to be written.

When using the Data Polling method during an
Erase cycle, Figure 5 still applies. However, the
Data Polling Flag (DQ7) bit is 0 until the Erase cy­cle is complete. A 1 on the Error Flag (DQ5) bit in­dicates a time-out condition on the Erase cycle; a
0 indicates no error. The MCU can read any loca­tion within the sector being erased to get the Data
Polling Flag (DQ7) bit and the Error Flag (DQ5) bit.

PSDsoft Express generates ANSI C code func­tions which implement these Data Polling algo­rithms.

Figure 5. Dat a Polling Flo wchart

READ DQ5 & DQ7

at VALID ADDRESS

START

READ DQ7

FAIL PASS

AI01369B

DQ7

=

DATA

YES

NO

YES

NO

DQ5

= 1

DQ7

=

DATA

YES

NO

23/103

PSD8XXF2/3/4/5

Data Toggle . Checking the Toggle Flag (DQ6) bit

is a method of determining wh ether a Program or
Erase cycle is in progress or has completed. Fig­ure 6 shows the Data Toggle algorithm.

When the MCU i ssues a Program instruction, the
embedded algorithm within the PSD8XXFX be­gins. The MCU then reads the location of the byte
to be programmed in Flash memory to check sta­tus. The Toggle Flag (DQ6) bit of this location tog­gles each time the MCU reads this locat ion until
the embedded algorithm is complete. The MCU
continues to read this location, chec king the Tog­gle Flag (DQ6) bit and monitoring the Error Flag
(DQ5) bit. When the Toggle Flag (DQ6) bi t stops
toggling (two consecutive reads yield the same
value), and the Error Flag (DQ5) bit remains 0, the
embedded algorithm is complete. If the Error Flag
(DQ5) bit is 1, the MCU should test the Toggle
Flag (DQ6) bit again, since the Toggle Flag (DQ6)
bit may have changed simultaneously with the Er­ror Flag (DQ5) bit (see Figure 6).

Figure 6. Dat a Toggle Flowchart

The Error Flag (DQ5) bit is set if either an internal
time-out occurred while the embedded algorithm
attempted to program the byte, or if the MCU at­tempted to program a 1 to a bit that was not erased
(not erased is logic 0).

It is suggested (as with all Flash memories) to read
the location again after the embedded program­ming algorithm has completed, to compare the
byte that was written to Flash memory with the
byte that was intended to be written.

When using the Data Toggle method after an
Erase cycle, Figure 6 still applies. the Toggle Flag
(DQ6) bit toggles until the Erase cycle is complete.
A 1 on the Error Flag (DQ5) bit indicates a time-out
condition on the Erase cycle; a 0 indicates no er­ror. The MCU can read any location within the sec­tor being erased to get the Toggle Fla g (DQ6) bit
and the Error Flag (DQ5) bit.

PSDsoft Express generates ANSI C code func­tions which implement these Data T oggling algo­rithms.

Unlock Bypass (PSD833F2x, PSD834F2x,
PSD853F2x, PSD854F2x). The Unlock Bypass

instructions allow the system to program bytes to
the Flash memories faster than using the standard
Program instruction. The Unlock Bypass mode is
entered by fi rst ini tiati ng two Unl ock cycle s. This is
followed by a third WRITE cycle containing the Un­lock Bypass code, 20h (as shown in Table 8).

The Flash memory then enters the Unlock Bypass
mode. A two-cycle Unlock Bypass Program in­struction is all that is required t o program in this
mode. The first cycle in this instruction contains
the Unlock Bypass Program code, A0h. The sec­ond cycle contains the program address and data.
Additional data is programm ed in the same man­ner. These instructions dispense with the initial
two Unlock cycles required in the standard Pro­gram instruction, resulting in faster total Flash
memory programming.

During the Unlock Bypass mode, only the Unlock
Bypass Program and Unlock Bypass Reset Flash
instructions are valid.

To exit the Un l o ck Bypass mode, the system mus t
issue the two -cycle Un lock Bypass Reset F lash in­struction. The first cycle must contain the data
90h; the second cycle the data 00h. Addresses are
Don’t Care for both cycles. The Flash memory
then returns to READ Mode.

READ

DQ5 & DQ6

START

READ DQ6

FAIL PASS

AI01370B

DQ6

=

TOGGLE

NO

NO

YES

YES

DQ5

= 1

NO

YES

DQ6

=

TOGGLE

PSD8XXF2/3/4/5

24/103

Erasing Flash Memory
Flash Bulk Erase. The Flash Bulk E rase instruc-

tion uses six WRITE operations followed by a
READ operation of the status register, as de­scribed in Table 8. If any byte of the Bulk Er ase in­struction is wrong, the Bulk Erase instruction
aborts and the device is reset t o the Read Flash
memory status.

During a Bulk Erase, the memory status may be
checked by reading the Error Flag (DQ5) bit, the
Toggle Flag (DQ 6) bit, and the Data Polling Flag
(DQ7) bit, as detailed in the section entitled “Pro­gramming Flash Memory”, on page 22. The Error
Flag (DQ5) bit returns a 1 if there has been an
Erase Failure (maximum number of Erase cycles
have been executed).

It is not necessary to program the memory with
00h because the PSD8X XFX automatically does
this before erasing to 0FFh.

During execution of the Bulk Erase instruction, the
Flash memory does not accept any instructions.

Flash Sector Erase. The Sector Erase instruc­tion uses six WRITE operations, as descr ibed in
Table 8. Additional Flash Sector Erase codes and
Flash memory sector addresses can be written
subsequently to erase other Flash memory sec­tors in parallel, without further coded cycles, if the
additional bytes are transmitted in a shorter time
than the time-out period of about 100µs. The input
of a new Sector Erase code restarts the time-out
period.

The status of the internal timer can be m onitored
through the level of the Erase Time-out Flag (DQ3)
bit. If the Erase Time-out Flag (DQ3) bit is 0, the
Sector Erase instruction has been received and
the time-out period is counting. If the E rase Time­out Flag (DQ3) bit is 1, the time-out period has ex­pired and the PSD8XXFX is busy erasing the
Flash memory sector(s). Before and during Erase
time-out, any instruction other than Suspend Sec­tor Erase and Resume Sector Erase instructions
abort the cycle that is currently in progress, and re­set the device to READ Mode. It is not necessary
to program the Flash m emory sector with 00 h as
the PSD8XXFX does this automatically before
erasing (byte = FFh).

During a Sector Erase, the memory status may be
checked by reading the Error Flag (DQ5) bit, the
Toggle Flag (DQ 6) bit, and the Data Polling Flag

(DQ7) bit, as detailed in the section entitled “Pro­gramming Flash Memory”, on page 22.

During execution of the Erase cycle, the Flash
memory accepts only Reset and Suspend Sector
Erase instructions. Erasure of one Flash memory
sector may be suspended, in order to read data
from another Flash memory se ctor, and then re­sume d.

Suspend Sector Erase. When a Sector Erase
cycle is in progress, the Suspend Sector Erase in­struction can be used to suspend the cycle by writ­ing 0B0h to any address when an appropriate
Sector Se lect (F S0-FS7 o r CSBOOT0- CSBOOT3)
is High. (See Table 8). This allows reading of data
from another Flash memory sector after the Erase
cycle has been suspended. Suspend Sector
Erase is accepted only during an Er ase cycle and
defaults to READ Mode. A Suspend Sector Erase
instruction executed during an Erase time-out pe­riod, in addition to suspending the Erase cycle, ter­minates the time out period.

The Toggle Flag (DQ6) bit stops toggling when the
PSD8XXFX internal logic is suspended . The sta­tus of this bit must be monitored at an address
within the Flash memory sector being erased. The
Toggle Flag (DQ6) bit stops toggling between

0.1 µ s a nd 15 µs a fter the Suspend S ector Erase
instruction has been executed. The PSD8XXFX is
then automatically set to READ Mode.

If an Suspend Sector Erase instruction was exe­cuted, the following rules apply:

– Attempting to read from a Flash memory sector

that was being erased outputs invalid data.

– Reading from a Flash sector that was

not

being

erased is valid.

– The Flash memory

cannot

be programmed, and
only responds to Resume Sector Erase and
Reset Flash instructions (READ is an operation
and is allowed).

– If a Reset Flash instruction is received, data in

the Flash memory sector that was being erased
is invalid .

Resume Sector Erase. If a Suspend Sector
Erase instruction was previously executed, the
erase cycle may be resumed with this instruction.
The Resume Sector E rase instruction consists of
writing 030h to any address while an appropriate
Sector Se lect (F S0-FS7 o r CSBOOT0- CSBOOT3)
is High. (See Table 8.)

25/103

PSD8XXF2/3/4/5

Specific Features
Flash Memory Sector Protect. Each primary

and secondary Flash memory sector can be sepa­rately protected against Program and Erase cy­cles. Sector Protection provides additional data
security because it disables all Program or Erase
cycles. This mode can be activated through the
JTAG Port or a Device Programmer.

Sector protection can be selec ted for each sector
using the PSDsoft Express Configuration pro­gram. This automatically protects selected sectors
when the device is programmed through the JTAG
Port or a Device Programmer. Flash memory sec­tors can be unprotecte d to allow updating of t heir

contents using the JTAG Port or a Device Pro­grammer. The MCU can read (but cannot change)
the sector protection bits.

Any attempt to program or erase a protected Flash
memory sector is ignored by the device. The Verify
operation results in a READ of the protected data.
This allows a guarantee of the retention of the Pro­tection status.

The sector protection status can be read by the
MCU through the Flash memory protection and
PSD/EE protection registers (in the CSIOP block).
See Table 10 and Table 11.

Table 10. Sector Protection/Security Bit Definition – Flash Protection Register

Note: 1. Bit De fi nitions:

Sec<i>_Prot 1 = Primary Flash memory or secondary Flash memory Sector <i> is write protected.
Sec<i>_Pr ot 0 = Primary Flash mem ory or secondary Flash mem ory Sector <i> is not write protected.

Table 11. Sector Protection/Security Bit Definition – PSD/EE Protection Register

Note: 1. Bit De fi nitions:

Sec<i>_Prot 1 = Secondary Flash memory Sector <i> is write protected.
Sec<i>_Pr ot 0 = Secondary Flash memory Sector <i> is not write protected.
Security_Bit 0 = Security Bit in device has not been set.

1 = Security B i t in device has been set.

Reset Flash. The Reset Flash instruction con­sists of one WRITE cycle (see Table 8). It can also
be optionally preceded by the standard two
WRITE decoding cycles (writing AAh to 555h and
55h to AAAh). It must be executed after:

– Reading the Flash Protection Status or Flash ID
– An Error condition has occurred (and the device

has set the Error Flag (DQ5) bit to 1) during a
Flash memory Program or Erase cycle.

On the PSD813F2 /3/4/5, the Reset Fla sh instruc­tion puts the Flash memory back into normal
READ Mode. It ma y take the Flash memory up t o
a few milliseconds to complete the Reset cycle.
The Reset Flash instruction is ignored when it is is­sued during a Pr ogram o r Bulk E ras e cycle of t he
Flash memory. The Reset Flash instruction aborts
any on-going Sector Erase cycle, and returns the
Flash memory to the normal READ Mode within a
few millis e co n ds .

On the PSD83xF2 or PSD85xF2, t he Reset Flash
instruction puts the Flash m emory back into nor­mal READ Mode. If an Error condition has oc-

curred (and the device has set the Error Flag
(DQ5) bit to 1) the Flash m emory is p ut back into
normal READ Mode within 25 µs of the Reset
Flash instruction having been issued. The Reset
Flash instruction is ignored when it is issued dur­ing a Program or Bulk Erase cycle of the Flash
memory. The Reset F lash instruction aborts any
on-going Sector Erase cycle, and returns the
Flash memory to the normal READ Mode within
25 µs.

Reset (RESET

) Signal (on the PSD83xF2 and

PSD85 xF2). A pulse on Reset (RESET

) aborts
any cycle that is in progress, and resets the Flash
memory to the READ Mode. When the reset oc­curs during a Program or Erase cycle, the Flash
memory takes up to 25 µs to return to the READ
Mode. It is recommended that the Reset (RESET

)
pulse (except for Power On Reset, as described
on page 63) be at least 25µs so that the Flash
memory is always ready for the MCU to fetch the
bootstrap instructions after the Reset cycle is com­plete.

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Sec7_Prot Sec6_Prot Sec5_Prot Sec4_Prot Sec3_Prot Sec2_Prot Sec1_Prot Sec0_Prot

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Security_Bit not used not used not used Sec3_Prot Sec2_Prot Sec1_Prot Sec0_Prot

PSD8XXF2/3/4/5

26/103

SRAM

The SRAM is enab led when SRAM Select (RS0)
from the DPLD is High. SRAM Select (RS0) can
contain up to two prod uct terms, allow ing flexible
memory ma pping.

The SRAM can be backed up using an external
battery. The external battery should be connected
to Voltage Stand-by (V

STBY

, PC2). If you have an
external battery connected to the PSD8XXFX, the
contents of the SRAM are retained i n the event of
a power loss. The contents of the SRAM are re­tained so long as the battery voltage remains at
2 V or greater. If the supply voltage falls below the
battery voltage, an internal power switch-over to
the battery occurs.

PC4 can be configured as an output that indicates
when power is being drawn from the ext ernal ba t­tery. Battery-on Indicator (VBATON, PC 4) is Hi gh
with the supply voltage falls below the battery volt­age and the battery on Voltage Stand-by (V

STBY

,

PC2) is supplying power to the internal SRAM.
SRAM Select (RS0), Voltage Stand-by (V

STBY

,
PC2) and Battery-on Indicator (VBATON, PC4)
are all configured using PSDsoft Express Configu­ration.

Sector Select and SRAM Select

Sector Select (FS0-FS7, CSBOOT0-CSBOOT3)
and SRAM Select (RS0) are all outputs of the
DPLD. They are setup by writing equations for
them in PSDabel . The foll owing rules apply to the
equations for these signals:

1. Primary Flash memory and secondary Flash

memory Sector Select signals must

not

be

larger than the physical sector size.

2. Any primary Flash memory sector must

not

be
mapped in the same memory space as another
Flash memory sector.

3. A secondary Flash memory sector must

not

be
mapped in the same memory space as another
secondary Flash memory sector.

4. SRAM, I/O, and Peripheral I/O spaces must

not

overlap.

5. A secondary Flash memory sector

may

overlap

a primary Flash memory sector. In case of

overlap, priority is given to the secondary Flash
memory sector.

6. SRAM, I/O, and Peripheral I/O spaces

may

overlap any other memory sector. Priority is
given to the SRAM, I/O, or Peripheral I/O.

Example. FS0 is valid when the address is in the
range of 8000h to BFFFh, CSBOOT0 is valid from
8000h to 9FFF h, and RS0 i s valid from 8000 h to
87FFh. Any addres s in the range of RS0 always
accesses the SRAM. Any address in the range of
CSBOOT0 greater than 87FFh (and less than
9FFFh) automatically addresses secondary Flash
memory segment 0. Any address greater than
9FFFh accesses the prima ry Flash memory seg­ment 0. You can see that half of the primary Flash
memory segment 0 and o ne-fourth of secondary
Flash memory segment 0 cannot be accessed in
this example. Also no te that an equ ation that de­fined FS1 to anywhere in the range of 8000h to
BFFFh would

not

be valid.

Figure 7 shows the priority levels for all memory
components. Any component on a higher level can
overlap and has priority over any component on a
lower level. Components on the same level must

not

overlap. Level one has the highest priority and

level 3 has the lowest.

Figure 7. Priority Level of Memory and I/O
Components

Level 1

SRAM, I/O, or
Peripheral I/O

Level 2

Secondary

Non-Volatile Memory

Highest Priority

Lowest Priority

Level 3

Primary Flash Memory

AI02867D

27/103

PSD8XXF2/3/4/5

Memory Select Configuration for MCUs with
Separate Program and Data Spaces. The 8031

and compatible family of MCUs, which includes
the 80C51, 80C151, 80C251, and 80C51XA, have
separate address spaces for Program memory
(selected using Program Select Enable (PSEN

,
CNTL2)) and Data memory (selected using Read
Strobe (RD

, CNTL1)). Any of the memories within
the PSD8XXFX can reside in either space or both
spaces. This is controlled through manipulation of
the VM register that resides in the CSIOP space.

The VM register is set using PSDsoft Express to
have an initial value. It can subsequently be

changed by the MCU so that memory mapping
can be changed on-the-fly.

For example, you may wish to have SRAM and pri­mary Flash memory in the Data space at Boot-up,
and secondary Flash memory in the Program
space at Boot-up, and later swap the prima ry and
secondary Flash memories. This is easily done
with the VM register by using PSDsoft Express
Configuration to configure it for Boot-up and hav­ing the MCU change it when desired. Table 12 de­scribes the VM Register.

Table 12. VM Register

Configuration Modes for MCUs with Separate
Program and Data Spaces. Separate Space
Modes. Program space is separated from Data

space. For example, Program Select Enable
(PSEN

, CNTL2) is used to access the program

code from the p rimary Flash m emory, whi le Read
Strobe (RD

, CNTL1) is used to access data from
the secondary Flash memory, SRAM and I/O Port
blocks. This configuration requires the VM register
to be set to 0Ch (see Figure 8).

Figure 8. 8031 Memory Modules – Separate S pac e

Bit 7

PIO_EN

Bit 6 Bit 5

Bit 4

Primary

FL_Data

Bit 3

Secondary

EE_Data

Bit 2

Primary

FL_Code

Bit 1

Secondary

EE_Code

Bit 0

SRAM_Code

0 = disable
PIO mode

not used not used

0 = RD
can’t
access
Flash
memory

0 = R

D can’t
access Secondary
Flash memory

0 = PSEN
can’t
access
Flash
memory

0 = PSE

N can’t
access Secondary
Flash memory

0 = PSEN
can’t
access
SRAM

1= enable
PIO mode

not used not used

1 = RD
access
Flash
memory

1 = R

D access
Secondary Flash
memory

1 = PSEN
access
Flash
memory

1 = PSE

N access
Secondary Flash
memory

1 = PSEN
access
SRAM

Primary

Flash

Memory

DPLD

Secondary

Flash

Memory

SRAM

RS0

CSBOOT0-3

FS0-FS7

CS CSCS

OE OE

RD

PSEN

OE

AI02869C

PSD8XXF2/3/4/5

28/103

Combined Space Modes. The Program and
Data spaces are combined into one memory
space that allows the primary Flash memory, sec­ondary Flash memory, and SRAM to be accessed
by either Program Select Enable (PSEN

, CNTL2)

or Read Strobe (RD

, CNTL1). For example, to
configure the primary Flash mem ory in Combi ned
space, bits b2 and b4 of the VM register are set to
1 (see Figure 9).

Figure 9. 8031 Memory Modules – Combine d Space

Primary

Flash

Memory

DPLD

Secondary

Flash

Memory

SRAM

RS0

CSBOOT0-3

FS0-FS7

RD

CS CSCS

RD

OE OE

VM REG BIT 2

PSEN

VM REG BIT 0

VM REG BIT 1

VM REG BIT 3

VM REG BIT 4

OE

AI02870C

29/103

PSD8XXF2/3/4/5

Page Regi st er

The 8-bit Page Register increases the addressing
capability of the MCU by a factor of up to 256. The
contents of the register can also be read by the
MCU. The outputs of the Page R egister (PGR0­PGR7) are inputs to the DPLD decoder and can be
included in the Sector Select (FS0-FS7,
CSBOOT0-CSBOOT3 ), and SRAM Select (RS0)
equations.

If memory paging is not needed, or if not all 8 page
register bits are needed for memory paging, then
these bits may be used in the CPLD f or general
logic. See Application Note

AN1154

.

Figure 10 shows the Page Register. The eight flip­flops in the register are connected to the internal
data bus D0-D7. The MCU can write to or read
from the Page Register. The Page Register can be
accessed at address location CSIOP + E0h.

Figure 10. Page Register

RESET

D0-D7

R/W

D0 Q0

Q1
Q2
Q3
Q4
Q5
Q6
Q7

D1
D2
D3
D4
D5
D6
D7

PAGE

REGISTER

PGR0
PGR1

PGR2
PGR3

DPLD

AND

CPLD

INTERNAL
SELECTS
AND LOGIC

PLD

PGR4
PGR5
PGR6
PGR7

AI02871B

PSD8XXF2/3/4/5

30/103

PLDS

The PLDs bring programmable l ogic functionality
to the PSD8XXFX. After specifying the logic for the
PLDs using the PSDabel tool in PSDsoft Express,
the logic is programmed into the device and avail­able upon Power-up.

The PSD8XXFX con tains two PLDs: the Decode
PLD (DPLD), and the Co mplex P LD (CP LD). T he
PLDs are briefly discussed in the next few para­graphs, and in mo re detail in the section entitled
“Decode PLD (DPLD)”, on page 32, and the sec­tion entitled “Complex PLD (CPLD)”, also on page

33. Figure 11 shows the configuration of the PLDs.
The DPLD performs add ress decoding for S elect

signals for internal components, such as memory,
registers, and I/O ports.

The CPLD can be used for logic functions, such as
loadable counters and shift registers, state ma­chines, and encoding and decoding logic. These
logic functions can be constructed using the 16
Output Macrocells (OMC), 24 Input Macrocells
(IMC), and the AND Array. The CPLD can also be
used to generate External Chip Select (ECS0­ECS2) signals.

The AND Array is used to form product terms.
These product terms are specified using PSDabel.
An Input Bus consisting of 73 signals is connected
to the PLDs. The signals are shown in Table 13.

The Turbo Bit in PS D8 X X FX

The PLDs in the PSD8XXFX can minimize power
consumption by switc hing off when i nputs rema in
unchanged for an extended time of about 70ns.
Resetting the Turbo bit to 0 (Bit 3 of PMMR0) au­tomatically places the PLDs into standby if no in­puts are changing. Turning the Turbo mode off
increases propagation delays while reducing pow­er consumption. See the section entitled “POWER
MANAGEMENT”, on page 58, on how to set the
Turbo bit.

Additionally, five bits are available in PMMR2 to
block MCU control signals from entering the PLDs.
This reduces power consumption and can be used
only when these MCU control signals are not used
in PLD logic equations.

Each of the two PLDs has unique characteristics
suited for its applications. They are described in
the following sections.

Table 13. D PL D and C P LD I npu t s

Note: 1. The addres s i nputs are A19-A4 in 80C51XA mode.

Input Source Input Name

Number

of

Signals

MCU Address Bus

1

A15-A0 16

MCU Control Signals CNTL2-CNTL0 3
Reset RST

1
Power-down PDN 1
Port A Input

Macrocells

PA7-PA0 8

Port B Input
Macrocells

PB7-PB0 8

Port C Input
Macrocells

PC7-PC0 8

Port D Inputs PD2-PD0 3
Page Register PGR7-PGR0 8
Macrocell AB

Feedback

MCELLAB.FB7­FB0

8

Macrocell BC
Feedback

MCELLBC.FB7­FB0

8

Secondary Flash
memory Program
Status Bit

Ready/Busy

1

31/103

PSD8XXF2/3/4/5

Figure 11. PLD Diagram

PLD INPUT BUS

8

INPUT MACROCELL & INPUT PORTS

DIRECT MACROCELL INPUT TO MCU DATA BUS

CSIOP SELECT

SRAM SELECT

SECONDARY NON-VOLATILE MEMORY SELECTS

DECODE PLD

PAGE

REGISTER

PERIPHERAL SELECTS

JTAG SELECT

CPLD

PT

ALLOC.

MACROCELL

ALLOC.

MCELLAB

MCELLBC

DIRECT MACROCELL ACCESS FROM MCU DATA BUS

24 INPUT MACROCELL

(PORT A,B,C)

16 OUTPUT

MACROCELL

I/O PORTS

PRIMARY FLASH MEMORY SELECTS

3

PORT D INPUTS

TO PORT A OR B

TO PORT B OR C

DATA

BUS

8

8

8

4

1

1

2

1

EXTERNAL CHIP SELECTS

TO PORT D

3

73

16

73

24

OUTPUT MACROCELL FEEDBACK

AI02872C

PSD8XXF2/3/4/5

32/103

Decode PLD (DPLD)

The DPLD, shown in Figure 12, is used for decod­ing the address for internal and ext ernal compo­nents. The DPLD can be used to generate the
following decode signals:

■ 8 Sector Select (FS0-FS7) signals for the

primary Flash memory (three product terms
each)

■ 4 Sector Select (CSBOOT0-CSBOOT3) signals

for the secondary Flash memory (three product
terms each)

■ 1 internal SRAM Select (RS0) signal (two

product terms)

■ 1 internal CSIOP Select (PSD Configuration

Register) signal

■ 1 JTAG Select signal (enables JTAG on Port C)

■ 2 internal Peripheral Select signals

(Peripheral I/O mode).

Figure 12. DPLD Logic Array

(INPUTS)

(24)

(8)

(16)

(1)

PDN (APD OUTPUT)

I/O PORTS (PORT A,B,C)

(8)

PGR0 -PGR7

(8)

MCELLAB.FB [7:0] (FEEDBACKS)

MCELLBC.FB [7:0] (FEEDBACKS)

A[15:0

]

*

(3)

(3)

PD[2:0] (ALE,CLKIN,CSI)

CNTRL[2:0

] (

READ/WRITE CONTROL SIGNALS)

(1)

(1)

RESET

RD_BSY

RS0

CSIOP

PSEL0

PSEL1

8 PRIMARY FLASH
MEMORY SECTOR SELECTS

SRAM SELECT
I/O DECODER

SELECT

PERIPHERAL I/O MODE
SELECT

CSBOOT 0

CSBOOT 1

CSBOOT 2

CSBOOT 3

FS0

FS7

3

3

3

3

3

3

3

3

3

3

3

3

2

JTAGSEL

AI02873D

FS1

FS2

FS3

FS6

FS5

FS4

1

1

1

1

33/103

PSD8XXF2/3/4/5

Complex PLD (CPLD)

The CPLD can be used to implement system logic
functions, such as loadable counters and shift reg­isters, system mailboxes, ha ndshaking protocols,
state machines, and random logic. The CPLD can
also be used to gene rate three External C hip Se­lect (ECS0-ECS2), routed to Port D.

Although External Chip Select (ECS0-ECS2) can
be produced by any Output Macrocell (OMC),
these th ree Exte rnal Ch ip Se lect ( EC S0-ECS2) on
Port D do not consume any Output Macrocells
(OMC).

As shown in Figure 11, the CPLD has the following
blocks:

■ 24 Input Macrocells (IMC)

■ 16 Output Macrocells (OMC)

■ Macro ce ll Al lo c at o r

■ Product Term Allocator

■ AND Array capable of generating up to 137

product terms

■ Four I/O Ports.

Each of the blocks are described in the sections
that fo llow.

The Input Macrocells (IMC) and Output Macrocells
(OMC) are connected to the PSD8XXFX internal
data bus and can be directly accessed by the
MCU. This enables the MCU software to load data
into the Output Macrocells (OMC) or read data
from both the Input and Output Macrocells (IMC
and OMC).

This feature allows efficient implementation of sys­tem logic and elimi nates the need to c onnect the
data bus to the AND Array as required in most
standard PLD macrocell architectures.

Figure 13. Macrocell and I/O Port

I/O PORTS

CPLD MACROCELLS

INPUT MACROCELLS

LATCHED

ADDRESS OUT

MUX

MUX

MUX

MUX MUX

D

D

Q

Q

Q

G

D

QD

WR

WR

PDR

DATA

PRODUCT TERM

ALLOCATOR

DIR

REG.

SELECT

INPUT

PRODUCT TERMS

FROM OTHER
MACROCELLS

POLARITY
SELECT

UP TO 10

PRODUCT TERMS

CLOCK
SELECT

PR DI LD

D/T

CK

CL

Q

D/T/JK FF

SELECT

PT CLEAR

PT
CLOCK

GLOBAL
CLOCK

PT OUTPUT ENABLE (OE

)

MACROCELL FEEDBACK

I/O PORT INPUT

ALE/AS

PT INPUT LATCH GATE/CLOCK

MCU LOAD

PT PRESET

MCU DATA IN

COMB.

/REG

SELECT

MACROCELL

TO

I/O PORT

ALLOC.

CPLD

OUTPUT

TO OTHER I/O PORTS

PLD INPUT BUSPLD INPUT BUS

MCU ADDRESS / DATA BUS

MACROCELL

OUT TO

MCU

DATA
LOAD

CONTROL

AND ARRAY

CPLD OUTPUT

I/O PIN

AI02874

PSD8XXF2/3/4/5

34/103

Output Macrocell (O MC )

Eight of the Output Macrocells (OMC) are con­nected to Po rts A and B pins and are named as
McellAB0-McellAB7. The other eight macrocells
are connected to Ports B and C pins and are
named as McellBC0-McellBC7. If an McellAB out­put is not assigned to a specific pin in PSDabel,
the Macrocell Allocator block assigns it to either
Port A or B. The same is true for a McellBC output
on Port B or C. Table 14 shows the macrocells and
port assignment.

The Output Macrocell (OMC) architecture is
shown in Figure 14. As shown in the figure, there
are native product terms a vailable from the AND
Array, and borrowed product terms available (if
unused) from other Output Macrocells (OMC). The
polarity of the product term is controlled by the

XOR gate. The O utput Macrocell (OMC) can im­plement either sequential log ic, using the flip-flop
element, or combinatorial logic. The multiplexer
selects between the sequential or combinatorial
logic outputs. The multiplexer out put can drive a
port pin and has a feedback path to the AND Array
inputs.

The flip-flop in the Output M acrocell (OM C) block
can be configured as a D, T, JK, or SR type in the
PSDabel program. The flip-flop’s clock, preset,
and clear inputs may be driven from a product
term of the AND Array. Alternatively, CLKIN (PD1)
can be used for the clock input to the flip-flop. The
flip-flop is clocked on the rising edge of CLKIN
(PD1). The preset and clear are active High inputs.
Each clear input can use up to two product terms.

Table 14. Output Macrocell Port and Data Bit Assignments

Output

Macrocell

Port

Assignment

Native Product Terms

Maximum Borrowed

Product Terms

Data Bit for Loading or

Reading

McellAB0 Port A0, B0 3 6 D0
McellAB1 Port A1, B1 3 6 D1
McellAB2 Port A2, B2 3 6 D2
McellAB3 Port A3, B3 3 6 D3
McellAB4 Port A4, B4 3 6 D4
McellAB5 Port A5, B5 3 6 D5
McellAB6 Port A6, B6 3 6 D6

McellAB7 Port A7, B7 3 6 D7
McellBC0 Port B0, C0 4 5 D0
McellBC1 Port B1, C1 4 5 D1
McellBC2 Port B2, C2 4 5 D2
McellBC3 Port B3, C3 4 5 D3
McellBC4 Port B4, C4 4 6 D4
McellBC5 Port B5, C5 4 6 D5
McellBC6 Port B6, C6 4 6 D6
McellBC7 Port B7, C7 4 6 D7

35/103

PSD8XXF2/3/4/5

Product Te rm A l lo cat or

The CPLD has a Product Term Allocator. The PS­Dabel compiler uses the Product Term Allocator to
borrow and place produ ct terms from one m acro­cell to another. The following list summarizes how
product terms are allocated:

■ McellAB0-McellAB7 all have three native

product terms and may borrow up to six more

■ McellBC0-McellBC3 all have four native product

terms and may borrow up to five more

■ McellBC4-McellBC7 all have four native product

terms and may borrow up to six more.

Each macrocell may only borrow product terms
from certain other macrocells. Product terms al­ready in use by one macrocell are not available for
another macrocell.

If an equation requires more product terms than
are available to it, then “external” product terms
are required, which consume other Output Macro­cells (OMC). If external product terms are used,
extra delay is added for the equation that required
the extra product terms.

This is called product term expansion. PSDsoft
Express performs this expansion as needed.

Loading and Reading the Output Macrocells
(OMC). The Outpu t Macrocells (OM C) block oc-

cupies a memory location in the MCU address
space, as defined by the CSIOP block (see the
section entitled “I/O PORTS”, on page 48). The
flip-flops in each of the 16 Output Macrocells
(OMC) can be loaded from the data bus by a MCU.
Loading the Output Macrocells (OMC) with data
from the MCU takes priority over internal func­tions. As such, the preset, clear, and c lock inputs
to the flip-flop can be overridden by the MCU. The
ability to load the flip-flops and read t hem back is
useful in such applications as loadable counters
and shift registers, mailboxes, and handshaking
protocols.

Data can be loaded to the Output Macrocells
(OMC) on the trailing ed ge of Write Strobe (WR

,
CNTL0) (edge loading) or during the time that
Write Strobe (WR

, CNTL0) is active (level load­ing). The method of loading is specified in PSDsoft
Express Configuration.

PSD8XXF2/3/4/5

36/103

Figure 14. CP LD Ou t put Macrocell

PT

ALLOCATOR

MASK

REG.

PT CLK

PT

PT

PT

CLKIN

FEEDBACK

(

.FB

)

PORT INPUT

AND ARRAY

PLD INPUT BUS

MUX

MUX

POLARITY

SELECT

LD

IN

CLR

Q

PRDIN

COMB/REG

SELECT

PORT

DRIVER

INPUT

MACROCELL

I/O PIN

MACROCELL

ALLOCATOR

INTERNAL DATA BUS

D

[

7:0

]

DIRECTION

REGISTER

CLEAR

(

.RE

)

PROGRAMMABLE

FF

(

D/T/JK/SR

)

WR

ENABLE

(

.OE

)

PRESET

(

.PR

)

RD

MACROCELL CS

AI02875B

37/103

PSD8XXF2/3/4/5

The OMC Mask Register. There is one Mask

Register for each of the two groups of eight Output
Macrocells (OMC). The Mask Registers can be
used to block the loading of data to individual Out­put Macrocells (OMC). The default value for the
Mask Registers is 00h, which allows loading of the
Output Macrocells (OMC). When a given bit in a
Mask Register is set to a 1, the MCU is blocked
from writing to the associated Ou tput Macrocells
(OMC). For example, suppose McellAB0­McellAB3 are being used for a state machine. You
would not want a MCU write to McellAB to over­write the state machine registers. Therefore, you
would want to load the Mask Register for McellAB
(Mask Macrocell AB) with the value 0Fh.

The Output Enable of the OMC. The Output
Macrocells (OMC) block can be connected to an I/
O port pin as a P LD output. The output enab le of
each port pin driver is con trolled by a single prod­uct term from the AND Array, ORed with the Direc­tion Register output. The pin is enabled upon
Power-up if no output enable equation is defined
and if the pin is declared as a PLD output in PSD­soft Express.

If the Output Mac rocell (OMC) output is de clared
as an internal node and not as a port pin output in
the PSDabel file, the port pin can be used for other
I/O functions. The internal node feedback can be
routed as an input to the AND Array.

Input Macrocells (IMC)

The CPLD has 24 Input Macrocells (IMC), one for
each pin on Ports A, B, and C. The architecture of
the Input Macrocells (IMC) is shown in Figure 15.
The Input Macrocells (IMC) are individually config­urable, and can be used as a latch, register, or to
pass incoming Port signals prior to driving them

onto the PLD input bus. The outputs of the Input
Macrocells (IMC) can be read by the MCU through
the internal data bus.

The enable fo r t he latch and c lock f or the register
are driven by a multiplexer whose inputs are a
product term from the CPLD AND Array or the
MCU Address Strobe (ALE/AS). Each product
term output is used to latch or clock four Input
Macrocells (IMC). Port inputs 3-0 can be con­trolled by one product term and 7-4 by another.

Configurations for the Input Macrocel ls (IMC) are
specified by equations written in PSDabel (see Ap­plication Note

AN1171

). Outputs of the Input Mac­rocells (IMC) can be read by the MCU via the IMC
buffer. See the section ent itled “I/O PORTS”, on
page 48.

Input Macrocells (IMC) can use Address Strobe
(ALE/AS, PD0) to latch address bits higher than
A15. Any latched addresses are routed to the
PLDs as inputs.

Input Macrocells (IMC) are pa rticularly useful with
handshaking communication applications where
two processors pass data back and forth through
a common mailbox. Figure 16 shows a typical con­figuration where the Master MCU writes to the Port
A Data Out Register. This, in turn, can be read by
the Slave MCU via the activation of the “Slave­Read” output enable product term.

The Slave can also write to the Port A Input Mac­rocells (IMC) and the Master can then read the In­put Macrocells (IMC) directly.

Note that the “Slave-Read” and “Slave-Wr” signals
are product terms that are derived from the Slave
MCU inputs Read Strobe (RD

, CNTL1), Write

Strobe (WR

, CNTL0), and Slave_CS.

PSD8XXF2/3/4/5

38/103

Figure 15. Input Macrocell

OUTPUT

MACROCELLS BC

AND

MACROCELL AB

PT

PT

FEEDBACK

AND ARRAY

PLD INPUT BUS

PORT

DRIVER

I/O PIN

INTERNAL DATA BUS

D

[

7:0

]

DIRECTION

REGISTER

MUX

MUX

ALE/AS

PT

Q

Q

D

D

G

LATCH

INPUT MACROCELL

ENABLE

(

.OE

)

D FF

INPUT MACROCELL

_

RD

AI02876B

39/103

PSD8XXF2/3/4/5

Figure 16. Handshaking Communication Using Input Macrocells

MASTER

MCU

MCU-RD

MCU-RD

MCU-WR

SLAVE–WR

SLAVE–CS

MCU-WR

D

[

7:0

]

D

[

7:0

]

CPLD

DQ

QD

PORT A

DATA OUT

REGISTER

PORT A

INPUT

MACROCELL

PORT A

SLAVE–READ

SLAVE

MCU

RD

WR

AI02877C

PSD

PSD8XXF2/3/4/5

40/103

MCU BUS INTERFACE

The “no-glue logic” MCU Bus Interface block can
be directly connected to most popular MCUs and
their control signals. Key 8-bit MCUs, with their
bus types and control signals, are shown in Tab le

15. The interface type is specified using the PSD­soft Express Configuration.

PSD8XXFX Interface to a Multiplexed 8-Bit
Bus. Figure 17 shows an example of a system us-

ing a MCU with an 8-bit multiplexed bus and a
PSD8XXFX. The ADIO port on the PSD8XXFX is

connected directly to the MCU address /data bus.
Address Strobe (ALE/AS, PD0) latches the ad­dress signals internally. Latched addresses can
be brought out to Port A or B. The PSD8XXFX
drives the ADIO data bus only when one of its in­ternal resources is accessed and Read Strobe
(RD

, CNTL1) is active. Should the system address
bus exceed sixteen bits, Port s A, B, C, or D may
be used as additional address inputs.

Table 15. MCUs and their Control Signals

Note: 1. Unused CN T L2 pin can be co nf i g ured as CPL D i nput. Other unused pins (PC7, PD0, PA3-0) can be c onfigured for other I/O func-

tions.

2. ALE/AS i nput is optional for MCU s wi t h a non-mult i pl exed bus

MCU

Data Bus

Width

CNTL0 CNTL1 CNTL2 PC7

PD0

2

ADIO0 PA3-P A0 PA7-P A3

8031 8 WR

RD PSEN

(Note 1)

ALE A0

(Note 1) (Note 1)

80C51XA 8 WR

RD PSEN

(Note 1)

ALE A4 A3-A0

(Note 1)

80C251 8 WR

PSEN

(Note 1) (Note 1)

ALE A0

(Note 1) (Note 1)

80C251 8 WR

RD PSEN

(Note 1)

ALE A0

(Note 1) (Note 1)

80198 8 WR

RD

(Note 1) (Note 1)

ALE A0

(Note 1) (Note 1)

68HC11 8 R/W

E

(Note

1

) (Note 1)

AS A0

(Note 1) (Note 1)

68HC912 8 R/W

E

(Note

1

)

DBE

AS A0

(Note

1

) (Note 1)

Z80 8 WR

RD

(Note 1) (Note 1) (Note 1)

A0 D3-D0 D7-D4

Z8 8 R/W

DS

(Note 1) (Note 1)

AS

A0

(Note

1

) (Note 1)

68330 8 R/W

DS

(Note 1) (Note 1)

AS A0

(Note 1) (Note 1)

M37702M2 8 R/W

E

(Note 1) (Note 1)

ALE A0 D3-D0 D7-D4

41/103

PSD8XXF2/3/4/5

Figure 17. An Example of a Typical 8-bit Multiplexed Bus Interface

MCU

WR

RD

BHE

ALE

RESET

AD[7:0

]

A[15:8

]

A[15:8

]

A[7:0

]

ADIO

PORT

PORT

A

PORT

B

PORT

C

WR (CNTRL0

)

RD (CNTRL1

)

BHE (CNTRL2

)

RST

ALE (PD0

)

PORT D

(

OPTIONAL

)

(

OPTIONAL

)

PSD

AI02878C

PSD8XXF2/3/4/5

42/103

PSD8XXFX Interface to a Non-Multiplexed 8-Bit
Bus. Figure 18 shows an example of a system us-

ing a MCU with an 8-bit non-multiplexed bus and
a PSD8XXFX. The address bus is connected to
the ADIO Port, and the data bus is connected to
Port A. Port A is in tri-state mode when the
PSD8XXFX is not accessed by the MCU. Should
the system address bus exceed sixteen bits, Ports
B, C, or D may be used for ad ditional address in­puts.

Data Byte Enable Reference. MCUs have differ­ent data byte orientations. Table 16 shows how
the PSD8XXFX interprets byte/word operations in
different bus WRITE configurations. Even-byte re­fers to locations with address A0 equal to 0 and
odd byte as locations with A0 equal to 1.

Table 16. Eight-Bit Data Bus

Figure 18. An Example of a Typical 8-bit Non-Multiplexed Bus Interface

BHE A0 D7-D0

X 0 Even Byte
X 1 Odd Byte

MCU

WR

RD

BHE

ALE

RESET

D[7:0

]

A[15:0

]

A[23:16

]

D[7:0

]

ADIO

PORT

PORT

A

PORT

B

PORT

C

WR (CNTRL0

)

RD (CNTRL1

)

BHE (CNTRL2

)

RST

ALE (PD0

)

PORT D

(OPTIONAL)

PSD

AI02879C

43/103

PSD8XXF2/3/4/5

MCU Bus Interface Examples

Figure 19 to Figure 22 show examples of the basic
connections between the PSD8XXFX and some
popular MCUs. The PSD8XXFX Control input pins
are labeled as to the MC U func tion for which t hey
are configured. The MCU bus interface is specified
using the PSDsoft Express Configuration.

80C31. Figure 19 shows t he bus interface for the
80C31, which has an 8-bit multiplexed address/
data bus. The lower address byte is mul tiplexed

with the data bus. T he MCU control signals Pr o­gram Select Enable (PSEN

, CNTL2), Read Strobe

(RD

, CNTL1), and Write Strobe (WR, CNTL0) may
be used for accessing the internal m emory and I/
O Ports blocks. Address Strobe (ALE/AS, PD0)
latches the address.

80C251. The Intel 80C251 M CU features a user­configurable bus interface with four possible bus
configurations, as shown in Table 17.

Figure 19. Interfacing the PSD8XXFX with an 80C31

Table 17. 80C251 Configurations

Configuration

80C251 READ/WRI TE

Pins

Connecting to PSD8XXFX Pins Page Mode

1

WR

RD

PSEN

CNTL0
CNTL1
CNTL2

Non-Page Mode, 80C31
compatible A7-A0 multiplex with
D7-D0

2

WR

PSEN only

CNTL0
CNTL1

Non-Page Mode
A7-A0 multiplex with D7-D0

3

WR

PSEN only

CNTL0
CNTL1

Page Mode
A15-A8 multiplex with D7-D0

4

WR

RD

PSEN

CNTL0
CNTL1
CNTL2

Page Mode
A15-A8 multiplex with D7-D0

EA/VP
X1

X2

RESET

RESET

INT0
INT1
T0
T1

P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7

P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7

PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7

PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7

PC0

PC2

PC1

PC3
PC4
PC5
PC6
PC7

P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7

ADIO0
ADIO1
ADIO2
ADIO3
ADIO4
ADIO5
ADIO6
ADIO7

ADIO8
ADIO9
ADIO10
ADIO11
ADIO12
ADIO13
ADIO14
ADIO15

CNTL0(WR)
CNTL1(RD)

CNTL2(PSEN)

PD0-ALE
PD1
PD2

RESET

RD

WR

PSEN

ALE/P

TXD
RXD

RESET

29
28
27
25
24
23
22
21

30

39

31
19

18

9

12
13
14
15

1
2
3
4
5
6
7
8

38
37
36
35
34
33
32

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7

31
32
33

34
35
36
37

39
40
41
42
43
44
45
46

47

48

50

49

10

9
8

7
6
5

4
3
2

52

51

PSD

80C31

AD7-AD0

AD[7:0

]

21
22
23
24
25
26
27

28

17
16

29
30

A8
A9
A10
A11
A12
A13
A14
A15

RD

WR

PSEN

ALE
11
10

RESET

20
19
18
17
14
13
12
11

AI02880C

PSD8XXF2/3/4/5

44/103

The first configuration is 80C31-compatible, and
the bus interface to the PSD8XXFX is identical to
that shown in Figure 19. The second and third con­figurations have the same bus connection as
shown in Figure 18. There is only one Read Strobe
(PSEN

) connected to CNTL1 on the PSD8XXF X.
The A16 connection to PA0 allows for a larger ad­dress input to the PSD8XXFX. The fourth configu­ration is shown in Figure 20. Read Strobe (RD

) is
connected to CNTL1 and Program Select Enable
(PSEN

) is connected to CNTL2.

The 80C251 has two major operating modes:
Page mode and Non-page mode. In Non-page

mode, the data is multiplexed with the lower ad­dress byte, and Address Strobe (ALE/AS, PD0) is
active in eve ry bus cycle. I n Pag e mode, da ta (D7­D0) is multiplexed with address (A15-A8). In a bus
cycle where there is a Page hit, Address Strobe
(ALE/AS, PD0) is not ac tive and only addresses
(A7-A0) are changing. T he PSD8XXFX supports
both modes. In Page Mode, the PSD bus timing is
identical to Non-Page Mode except the address
hold time and setup time with respect to Address
Strobe (ALE/AS, PD0) is not required. The PSD
access time is measured from address (A7-A0)
valid to data in v a lid.

Table 18. Interfacing the PSD8XXFX with the 80C251, with One READ Input

Note: 1. The A16 and A 17 connect i ons are optional.

2. In non-P age-Mode, AD 7-AD0 connects to ADIO7-ADIO0.

ADIO0
ADIO1
ADIO2
ADIO3
ADIO4
ADIO5
ADIO6
ADIO7

ADIO8
ADIO9
ADIO10

ADIO11
ADIO12
ADIO13
ADIO14
ADIO15

CNTL0(WR

)

CNTL1(RD

)

CNTL2(PSEN)

PD0- ALE
PD1
PD2

RESET

32

26

43
42
41
40
39
38
37
36

24
25

27
28
29
30

31

33

A0
A1
A2
A3
A4
A5
A6
A7

AD8
AD9
AD10

AD14
AD15

AD13

AD11

AD12

A0
A1
A2
A3

A4

A5
A6
A7

AD8
AD9

AD10

AD11

AD15

ALE

WR
A16

RD

AD14

AD12

AD13

14

9

2
3

4

5
6
7
8

21

20

11

13

P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7

P3.0/RXD
P3.1/TXD
P3.2/INT0

X2

X1

P3.3/INT1

RST

EA

A16

1

P0.1

P0.0
P0.2

P0.3
P0.4
P0.5
P0.6
P0.7

P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6

P2.7

ALE

PSEN

WR

RD/A16

PC0
PC1

PC3
PC4
PC5
PC6
PC7

19

18

30
31
32
33
34
35
36
37

39
40
41
42
43
44

45

46

48

8

9

10

49

50

47

29
28
27
25
24
23
22

21

20
19
18
17
14
13
12
11

PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7

PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7

7
6
5
4
3
2
52

51

80C251SB

PSD

RESET

RESET

35

P3.4/T0
P3.5/T1

16

15

17
10

RESET

PC2

AI02881C

A17

1

45/103

PSD8XXF2/3/4/5

Figure 20. Interfacing the PSD8XXFX with the 80C251, wi th RD and PSEN Inp uts

ADIO0
ADIO1
ADIO2
ADIO3
ADIO4
ADIO5
ADIO6
ADIO7

ADIO8
ADIO9
ADIO10

ADIO11
ADIO12
ADIO13
ADIO14
ADIO15

CNTL0(WR

)

CNTL1(RD

)

CNTL2(PSEN)

PD0- ALE
PD1
PD2

RESET

32

26

43
42
41
40
39
38
37
36

24
25

27
28
29
30

31

33

A0
A1
A2
A3
A4
A5
A6
A7

AD8
AD9
AD10

AD14
AD15

AD13

AD11
AD12

A0
A1
A2
A3
A4
A5
A6
A7

AD8
AD9
AD10
AD11

AD15

ALE

WR
PSEN

RD

AD14

AD12
AD13

14

9

2
3

4

5
6
7
8

21

20

11

13

P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7

P3.0/RXD
P3.1/TXD
P3.2/INT0

X2

X1

P3.3/INT1

RST

EA

P0.1

P0.0
P0.2

P0.3
P0.4
P0.5
P0.6
P0.7

P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6

P2.7

ALE

PSEN

WR

RD/A16

PC0
PC1

PC3
PC4
PC5
PC6
PC7

19

18

30
31
32
33
34
35
36
37

39
40
41
42
43
44
45
46

48

8

9

10

49

50

47

29
28
27
25
24
23
22
21

20
19
18
17
14
13
12
11

PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7

PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7

7
6
5
4
3
2
52
51

80C251SB

PSD

RESET

RESET

35

P3.4/T0
P3.5/T1

16

15

17
10

RESET

PC2

AI02882C

PSD8XXF2/3/4/5

46/103

80C51XA. The Philips 80C51XA MCU family sup­ports an 8- or 16-bit multiplexed bus that can have
burst cycles. Address b its (A3-A0) are not m ulti­plexed, while (A19-A4) are multiplexed with data
bits (D15-D0) in 16-bit mode. In 8-bit mode, (A11­A4) are multiplexed with data bits (D7-D0).

The 80C51XA can be configured to operate in
eight-bit data mode (as shown in Figure 21).

The 80C51XA improves bus throughput and per­formance by executing burst cycles for code fetch-

es. In Burst Mode, address A19-A4 are latched
internally by the PSD8X XFX, while the 80C51XA
changes the A3-A0 signals to fetch up to 16 bytes
of code. The PSD access time is then measured
from address A3-A0 valid to data in valid. The PSD
bus timing requirement in Bu rst Mode is identical
to the normal bus cycle, except the address setup
and hold time with respect to Address Strobe
(ALE/AS, PD0) does not apply.

Figure 21. Interfacing the PSD8XXFX with the 80C51X, 8-bit Data Bus

ADIO0
ADIO1

ADIO2
ADIO3
AD104
AD105
ADIO6
ADIO7

ADIO8
ADIO9
ADIO10
ADIO11
AD1012
AD1013
ADIO14
ADIO15

CNTL0(WR

)

CNTL1(RD

)

CNTL2(PSEN)
PD0-ALE

PD1
PD2

RESET

31

33

36

2
3
4
5
43
42
41
40
39
38
37

24
25
26

27

28
29
30

A4D0
A5D1
A6D2
A7D3
A8D4
A9D5

A10D6
A11D7

A12
A13
A14

A18
A19

A17

A15

A16

A0
A1
A2
A3

A4D0
A5D1
A6D2
A7D3
A8D4
A9D5
A10D6
A11D7
A12

A16
A17
A18
A19

A15

A13
A14

TXD1

T2EX
T2
T0

RST

EA/WAIT
BUSW

A1

A0/WRH

A2
A3

A4D0
A5D1
A6D2

A7D3
A8D4

A9D5
A10D6
A11D7
A12D8
A13D9

A14D10
A15D11
A16D12
A17D13
A18D14
A19D15

PSEN

RD

WRL

PC0
PC1

PC3
PC4

PC5
PC6
PC7

ALE

PSEN

RD

WR

ALE

32
19
18

30
31
32
33
34
35
36
37

39
40
41
42
43
44
45
46

48

8
9

10

49

50

47

7

9
8

16

XTAL1
XTAL2

RXD0
TXD0
RXD1

21
20

11
13

6

29
28
27
25

24
23
22
21

20
19
18
17
14
13
12
11

PB0
PB1
PB2
PB3

PB4
PB5
PB6
PB7

PA0
PA1

PA2
PA3

PA4
PA5
PA6
PA7

7
6
5
4
3

2
52
51

A0
A1
A2
A3

80C51XA

PSD

RESET

RESET

35

17

INT0
INT1

14

10

15

PC2

AI02883C

47/103

PSD8XXF2/3/4/5

68HC11. Figure 22 shows a bus interface to a

68HC11 where the PSD8XXFX is configured in 8­bit multiplexed mode with E and R/W settings. The

DPLD can be used to generate the READ and WR
signals for external devices.

Figure 22. Interfac ing the PSD8XXFX with a 68HC11

9
10
11
12
13
14
15
16

ADIO0
ADIO1
ADIO2
ADIO3
AD104
AD105
ADIO6
ADIO7

ADIO8
ADIO9
ADIO10
ADIO11
AD1012
AD1013
ADIO14
ADIO15

CNTL0(R_W)
CNTL1(E)

CNTL2

PD0–AS
PD1

PD2

RESET

20
21
22
23
24
25

3

5
4
6

42
41

40
39
38
37
36
35

AD0

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7

A8
A9

A10

A14
A15

A13

A11
A12

AD1
AD2
AD3

AD4
AD5
AD6
AD7

E
AS
R/W

XT
EX

RESET
IRQ
XIRQ

PA0
PA1
PA2

PE0
PE1
PE2
PE3

PE4
PE5
PE6
PE7

VRH
VRL

PA3
PA4
PA5
PA6
PA7

PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7

PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7

PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7

PC0
PC1

PC3
PC4

PC5
PC6
PC7

PD0
PD1
PD2
PD3
PD4
PD5

MODA

E

AS

R/W

31

30
31
32

33
34
35
36
37

39
40

41
42
43
44
45
46

48

8

9

10

49

50

47

8
7

17
19
18

34
33
32

43
44
45
46
47
48
49
50

52
51

30
29
28
27

29
28
27
25
24
23
22
21

20
19
18
17
14
13
12
11

PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7

7
6
5
4

3
2
52
51

MODB

2

68HC11

PSD

RESET

RESET

AD7-AD0

AD7-AD0

PC2

AI02884C

PSD8XXF2/3/4/5

48/103

I/O P O R TS

There are four programmable I/O ports: Ports A, B,
C, and D. Each of the ports is eight bits except Port
D, which is 3 bits. Each port pin is individually user
configurable, thus allowing multiple functions per
port. The ports are configured using P SDsoft Ex­press Configuration or by the MCU writing to on­chip registers in the CSIOP space.

The topics discussed in this section are:

■ Genera l Po rt a rch itecture

■ Port operating modes

■ Port Configuration Registers (PCR)

■ Port Data Registers

■ Individual Port functionality.

General Port Architecture

The general architecture of the I/O Port block is
shown in Figure 23. Individual Port architectures
are shown in Figure 25 to Figure 28. In general,
once the purpose fo r a port pin has been defined,

that pin is no longer available for other purposes.
Exceptions are noted.

As shown in Figure 23, the ports contain an output
multiplexer whose select signals are driven by the
configuration bits in the Control Registers (Ports A
and B only) and PSDsoft Express Conf iguration.
Inputs to the multiplexer include the following:

■ Output data from the Data Out register

■ Latched address outputs

■ CPLD macrocell output

■ External Chip Select (ECS0-ECS2) from the

CPLD.

The Port Data Buffer (PDB) is a tr i-state buffer that
allows only one source at a time to be read. The
Port Data Buffer (PDB) is connected to the Internal
Data Bus for feedback and can be read by the
MCU. The Data Out and macrocell outputs, Direc­tion and Control Registers, and port pin input are
all connected to the Port Data Buffer (PDB).

Figure 23. Ge neral I/O P ort Arc hit ect u re

INTERNAL DATA BUS

DATA OUT

REG.

DQ

D
G

Q

DQ

DQ

WR

WR

WR

ADDRESS

MACROCELL OUTPUTS

ENABLE PRODUCT TERM (.OE

)

EXT CS

ALE

READ MUX

P
D
B

CPLD-INPUT

CONTROL REG.

DIR REG.

INPUT

MACROCELL

ENABLE OUT

DATA IN

OUTPUT

SELECT

OUTPUT

MUX

PORT PIN

DATA OUT

ADDRESS

AI02885

49/103

PSD8XXF2/3/4/5

The Port pin’s tri-state output driver enable is con­trolled by a two input OR gate whose inputs come
from the CPLD AND Array enable product term
and the Direction Register. If the enable produ ct
term of any of the A rray outputs are not defined
and that port pin is not defined as a CP LD output
in the PSDabel file, then the Direction Register has
sole control of the buffer that drives the port pin.

The contents of these regist ers can be altered by
the MCU. The Port Data Buffer (PDB) feedback
path allows the M CU to check the contents of the
registers.

Ports A, B, and C have embedded Input Macro­cells (IMC). The Input Macrocells (IMC) can be
configured as latches, registers, or direct inputs to
the PLDs. The latches and registers are clocked
by Address Strobe (ALE/AS, PD0) or a product
term from the PLD AND Array. The outputs from
the Input Macrocells (IMC) drive the PLD input bus
and can be read by the MCU. See the section en­titled “Input Macrocell”, on page 38.

Port Opera tin g Modes

The I/O Ports have several modes of operation.
Some modes can be defined using PSDabel,
some by the MCU writing to the Control Registers
in CSIOP space, and some by both. The modes
that can only be defined using PSDsoft Express
must be programmed into the device and cannot
be changed unless the device i s reprogrammed.
The modes that can be changed by the MCU can
be done so dynamically at run-time . T he PLD I/O,
Data Port, Address Input, and Peripheral I/O
modes are the only modes t hat must be defined
before programming the device. All other modes
can be changed by the MCU at run-tim e. See Ap­plication Note

AN1171

for more detail.

Table 19 summarizes which mode s are available
on each port. Table 22 s hows how and where the
different modes are conf igured. Each of the port
operating modes are described in the following
sections.

MCU I/O Mode

In the MCU I/O mode, the MCU uses the I/O Ports
block to expand its own I/O ports. By setting up the
CSIOP space, the ports on the PSD8XXFX are
mapped into the MCU address space. The ad­dresses of the ports are listed in Table 7.

A port pin can be put into MCU I/O mode by writing
a 0 to the corresponding bit in the Control Regis­ter. The MCU I/O direction may be changed by
writing to the corresponding bit in the Direction
Register, or by the output enable product term.
See the section entitled “Peripheral I/O Mode”, on
page 51. When the pin is configured as an output,
the content of the Data Out Register drives the pin.
When configured as an input, the MCU can read
the port input through the Data In buf fer. See F ig­ure 23.

Ports C and D do not have Control Registers, and
are in MCU I/O mode by default. They can be used
for PLD I/O if equations are written for them in PS­Dabel.

PLD I/ O Mode

The PLD I/O Mode uses a po rt as an i nput to the
CPLD’s Input Macrocells (IMC), and/ or as an out­put from the CPLD’s Output Macrocells (OMC).
The output can be tri-stated with a control signal.
This output enable control sign al can be defined
by a product term from the PLD, or by resetting the
corresponding bit in the Direction Register to 0.
The corresponding bit in the Direction Register
must not be set to 1 if the pin is defined for a PLD
input signal in PSDabel. The PLD I/O mode is
specified in PSDabel by declaring the port pins,
and then writing an equation assigning the P LD I/
O to a port.

Address Out Mode

For MCUs with a multiplexed address/data bus,
Address Out Mode can be u sed to drive latched
addresses on to the port pins. These port pins can,
in turn, drive external devices. Either the output
enable or the corresponding bits of both the Direc­tion Register and Control Register must be set to
a 1 for pins to use Address Out Mode. This must
be done by the MCU at run-time. See Table 21 for
the address output pin assignments on Ports A
and B for various MCUs.

For non-multiplexed 8-bit bus m ode, addres s sig­nals (A7-A0) are available to Port B in Address Out
Mode.

Note: Do not d rive address signals with Address
Out Mode t o an external memory device if it is in­tended for the MCU to Boot from the externa l de­vice. The MCU must first Boot from PSD8XXFX
memory so the Direction and Control reg ister bits
can be set.

PSD8XXF2/3/4/5

50/103

Table 19. Port Operating Modes

Note: 1. Can be mult i pl exed with other I/O func tions.

Table 20. Port Operating Mode Settings

Note: 1. N/A = Not Applicable

2. The direction of the Port A,B,C, and D pins are controlled by the Direction Register ORed with the individual output enable product
term (.oe) from the CPLD AND Array.

3. Any of these three met hods enables the JTAG pins on Port C.

Port Mode Port A Port B Port C Port D

MCU I/O Yes Yes Yes Yes
PLD I/O

McellAB Outputs
McellBC Outputs
Additional Ext. CS Outputs
PLD Inputs

Yes
No
No
Yes

Yes
Yes
No
Yes

No
Yes
No
Yes

No
No
Yes
Yes

Address Out Yes (A7 – 0)

Yes (A7 – 0)
or (A15 – 8)

No No

Address In Yes Yes Yes Yes
Data Port Yes (D7 – 0) No No No
Peripheral I/O Yes No No No

JTAG ISP No No

Yes

1

No

Mode

Defined in

PSDabel

Defined in

PSD8XXFX

Configuration

Control

Register

Setting

Direction

Register

Setting

VM

Register

Setting

JTAG Enable

MCU I/O Declare pins only

N/A

1

0

1 = output,
0 = input

(Note

2

)

N/A N/A

PLD I/O Logic equations N/A N/A

(Note

2

)

N/A N/A

Data Port (Port A) N/A Specify bus type N/A N/A N/A N/A
Address Out

(Port A,B)

Declare pins only N/A 1

1 (Note

2

)

N/A N/A

Address In
(Port A,B,C,D)

Logic for equation
Input Macrocells

N/A N/A N/A N/A N/A

Peripheral I/O
(Port A)

Logic equations
(PSEL0 & 1)

N/A N/A N/A PIO bit = 1 N/A

JTAG ISP (Note

3

)

JTAGSEL

JTAG
Configuration

N/A N/A N/A JTAG_Enable

51/103

PSD8XXF2/3/4/5

Table 21. I/O Port Latched Address Output Assignments

Note: 1. N/A = Not Applicable.

Address In Mode

For MCUs that have more than 16 address sig­nals, the higher addresses can be connected to
Port A, B, C, and D. The address input can be
latched in the Input Macrocell (IMC) by Address
Strobe (ALE/AS, PD0). Any input that is inclu ded
in the DPLD equations for the SRAM, or primary or
secondary Flash memory is considered to be an
address input.

Data Port Mode

Port A can be used as a data bus port for a MCU
with a non-multiplexed address/data bus. The
Data Port is connected to the data bus of the MCU.
The general I/O functions are disabled in Port A if
the port is configured as a Data Port.

Peripheral I/O Mod e

Peripheral I/O mode can be used to interface with
external peripherals. In this mode, all of Port A

serves as a tri-state, bi-directional data buffer for
the MCU. Peripheral I/O Mode is enabled by set­ting Bit 7 of the VM Register to a 1. Figure 24
shows how Port A acts as a bi-directional buffer for
the MCU data bus if Peripheral I/O Mode is en­abled. An equation for PSEL0 and/or PSEL1 must
be written in PSDabel. The buffer is tri-stated
when PSEL0 or PSEL1 is not active.

JTAG In-System Programming (ISP)

Port C is JTAG compliant, and can be used for In­System Programming (ISP). You can multiplex
JTAG operations with other functions on Port C
because In-System Programming (ISP) is not per­formed in normal Operating mode. For more infor­mation on the JTAG Port, see the section ent itled
“PROGRAMMING IN-CIRCUIT USING THE
JTAG SERIAL INTERFACE”, on page 65.

Figure 24. Peripheral I/O Mode

MCU Port A (PA3-PA0) Port A (PA7-PA4) Port B (PB3-PB0) Port B (PB7-PB4)

8051XA (8-Bit)

N/A

1

Address a7-a4 Address a11-a8 N/A

80C251
(Page Mode)

N/A N/A Address a11-a8 Address a15-a12

All Other
8-Bit Multiplexed

Address a3-a0 Address a7-a4 Address a3-a0 Address a7-a4

8-Bit
Non-Multiplexed Bus

N/A N/A Address a3-a0 Address a7-a4

RD

PSEL0

PSEL1

PSEL

VM REGISTER BIT 7

WR

PA0-PA7

D0-D7

DATA BUS

AI02886

PSD8XXF2/3/4/5

52/103

Port Confi gu ra ti on R e g ist ers (PCR)

Each Port has a set of Port Configuration Regis­ters (PCR) used for configuration. The contents of
the registers can be accessed by the MCU through
normal READ/WRITE bus cycles at the addresses
given in Table 7. The addresses in Table 7 are the
offsets in hexadecimal from the base of the CSIOP
register.

The pins of a port are individually configurable and
each bit in the register controls its respective pin.
For example, Bit 0 in a register refers to Bit 0 of its
port. The three Port Configuration Registers
(PCR), shown in Table 22, are used for setting the
Port configurations. The default Power-up state for
each register in Table 22 is 00h.

Control Register. Any bit reset to 0 in t he Control
Register sets the corresponding port pin to MCU I/
O Mode, and a 1 sets it to Address Out Mode. The
default mode is MCU I/O. Only Ports A and B have
an associated Control Register.

Direction Register. The Direction Register, in
conjunction with the output enable (except for Port
D), controls the direction of data flow in the I/O
Ports. Any bit set to 1 in the Direction Register
causes the corresponding pin to be an output, and
any bit set to 0 causes it to be an input. The default
mode for all port pins is input.

Figure 25, page 54 a nd Figure 26 , page 55 s how
the Port Architecture diagrams for Ports A/B and
C, respectively. The direction of data flow for Ports
A, B, and C are controlled not only by the direction
register, but also by the output enable product
term from the PLD AND Array. If the output enable
product term is not active, the Direction Register
has sole control of a given pin’s direction.

An example of a configuration for a Port with the
three least significant bits set to output and the re­mainder set to input is shown i n Table 25. Since
Port D only contains three p ins (shown in Figure

28), the Direction Register for Port D has only t he
three least significant bits active.

Drive Select Register. The Drive Select Register
configures the pin driver as Ope n Drain or CM OS
for some port pins, and controls the slew rate for
the other port pins. An external pull-up resistor
should be used for pins configured as Open Drain.

A pin can be configured as Open Drain if its corre­sponding bit in the Drive Select Register is set to a

1. The default pin drive is CMOS.

Note that the slew rate is a measureme nt of the
rise and fall times of an output. A higher slew rate
means a faster output response and may create
more electrical noise. A pin operates in a high slew
rate when the corresponding bit in the Drive Reg­ister is set to 1. The default rate is slow slew.

Table 26 shows the Drive Regist er for P orts A, B,
C, and D. It summarizes which pins can be config­ured as Open Drain outputs and which pins the
slew rate can be set for.

Table 22. Port Configuration Registers (PCR)

Note: 1. See Tabl e 26 f or Drive Re gi ster bit defi nition.

Table 23. Port Pin Direction Control, Output
Enable P.T. Not Defined

Table 24. Port Pin Direction Control, Output
Enable P.T. Defined

Table 25. Port Direction Assignment Example

Register Name Port M CU Access

Control A ,B WRITE/READ
Direction A,B,C,D WRIT E/RE AD

Drive Select

1

A,B,C,D WRITE/READ

Direction Register Bit Port Pin Mode

0 Input
1 Output

Direction

Register Bit

Output Enable

P.T.

Port Pin Mode

0 0 Input
0 1 Output
1 0 Output
1 1 Output

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

0 0 0 0 0 1 1 1

53/103

PSD8XXF2/3/4/5

Table 26. Drive Register Pin Assignment

Note: 1. NA = Not Applicable.

Port Data Registers

The Port Data Registers, shown in Table 27, are
used by the MCU to write data to or read data from
the ports. Table 27 sho ws the register nam e, the
ports having each register type, and MCU access
for each register type. The registers are described
below.

Data In. Port pins are connected directly to the
Data In buffer. In MCU I/O inpu t mode , the pin in­put is read through the Data In buffer.

Data Out Register. Stores output data written by
the MCU in the MCU I /O output mode. The con­tents of the Register are driven out to the pins if the
Direction Register or the output enable product
term is set to 1. The contents of the register can
also be read back by the MCU.

Output Macrocells (O MC). The CPLD Output
Macrocells (OMC) occupy a location in the MCU’s
address space. The MCU can read the out put of
the Output Macrocells (OMC). If the OMC Mask
Register bits are not set, writing to the macrocell

loads data to the macrocell flip-flops. See the sec­tion entitled “PLDS”, on page 30.

OMC Mask Register. Each OMC Mask Register
bit corresponds to an Output Macrocell (OMC) flip­flop. When the OMC Mask Regi ster bit is set to a
1, loading data into the Output Macrocell (OMC)
flip-flop is blocked. The default value is 0 or un­blocked.

Input Macrocells (IMC). The Input Macrocells
(IMC) can be used to latch or store external inputs.
The outputs of the Input Macrocells (IMC) are rout­ed to the PLD in put bus, and can be read by the
MCU. See the section entitled “PLDS”, on page

30.
Enable Out. The Enable Out register can be read

by the MCU. It contains the output enable values
for a given port. A 1 indicates the dri ver is in output
mode. A 0 indicates the driver is in tri-state and the
pin is in input mode.

Table 27. Port Data Registers

Drive

Register

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Port A

Open
Drain

Open
Drain

Open
Drain

Open
Drain

Slew
Rate

Slew
Rate

Slew
Rate

Slew
Rate

Port B

Open
Drain

Open
Drain

Open
Drain

Open
Drain

Slew
Rate

Slew
Rate

Slew
Rate

Slew
Rate

Port C

Open
Drain

Open
Drain

Open
Drain

Open
Drain

Open
Drain

Open
Drain

Open
Drain

Open
Drain

Port D

NA

1

NA

1

NA

1

NA

1

NA

1

Slew
Rate

Slew
Rate

Slew
Rate

Register Name Port MCU Access

Data In A,B,C,D READ – input on pin
Data Out A,B,C,D WRITE/READ

Output Macrocell A,B,C

READ – outputs of macrocells
WRITE – loading macrocells flip-flop

Mask Macrocell A,B,C

WRITE/READ – prevents loading into a given

macrocell
Input Macrocell A,B,C READ – outputs of the Input Macrocells
Enable Out A,B,C READ – the output enable control of the port driver

PSD8XXF2/3/4/5

54/103

Ports A and B – Functionality and Structure

Ports A and B have similar functionality and struc­ture, as shown in Figure 25. The two ports can be
configured to perform one or more of the following
functions:

■ MCU I/O Mode

■ CPLD Output – Macrocells McellAB7-McellAB0

can be connected to Port A or Port B. McellBC7­McellBC0 can be connected to Port B or Port C.

■ CPLD Input – Via the Input Macrocells (IMC).

■ Latched Address output – Provide latched

address output as per Table 21.

■ Address In – Additional high address inputs

using the Input Macrocells (IMC).

■ Open Drain/Slew Rate – pins PA3-PA0 and

PB3-PB0 can be configured to fast slew rate,
pins PA7-PA4 and PB7-PB4 can be configured
to Open Drain Mode.

■ Data Port – Port A to D7-D0 for 8 bit non-

multiplexed bus

■ Multiplexed Address/Data port for certain types

of MCU bus interfaces.

■ Peripheral Mode – Port A only

Figure 25. Port A and Port B Structure

INTERNAL DATA BUS

DATA OUT

REG.

DQ

DGQ

DQ

DQ

WR

WR

WR

ADDRESS

MACROCELL OUTPUTS

ENABLE PRODUCT TERM (.OE

)

ALE

READ MUX

P
D
B

CPLD- INPUT

CONTROL REG.

DIR REG.

INPUT

MACROCELL

ENABLE OUT

DATA IN

OUTPUT

SELECT

OUTPUT

MUX

PORT

A OR B PIN

DATA OUT

ADDRESS

A[7:0] OR A[15:8

]

AI02887

55/103

PSD8XXF2/3/4/5

Port C – Functionality and Structure

Port C can be configured to perform one or more
of the following functions (see Figure 26):

■ MCU I/O Mode

■ CPLD Output – McellBC7-McellBC0 outputs

can be connected to Port B or Port C.

■ CPLD Input – via the Input Macrocells (IMC)

■ Address In – Additional high address inputs

using the Input Macrocells (IMC).

■ In-System Programming (ISP) – JTAG port can

be enabled for programming/erase of the
PSD8XXFX dev ice. (See the section entitled
“PROGRAMMING IN-CIRCUIT USING THE
JTAG SERIAL INTERFACE”, on page 65, for
more information on JTAG programming.)

■ Open Drain – Port C pins can be configured in

Open Drain Mode

■ Battery Backup features – PC2 can be

configured for a battery input supply, Voltage
Stand-by (V

STBY

).

PC4 can be configured as a Battery-on Indicator
(VBATON), indicating when V

CC

is less than

V

BAT

.

Port C does not support Address Out mode, and
therefore no Control Register is required.

Pin PC7 may be configured as the DBE input in
certain MCU bus interfaces.

Figure 26. Port C Structure

INTERNAL DATA BUS

DATA OUT

REG.

DQ

DQ

WR

WR

MCELLBC[7:0

]

ENABLE PRODUCT TERM (.OE

)

READ MUX

P

D

B

CPLD- INPUT

DIR REG.

INPUT

MACROCELL

ENABLE OUT

SPECIAL FUNCTION

1

SPECIAL FUNCTION

1

CONFIGURATION

BIT

DATA IN

OUTPUT
SELECT

OUTPUT

MUX

PORT C PIN

DATA OUT

AI02888B

PSD8XXF2/3/4/5

56/103

Port D – Functionality and Structure

Port D has three I/O pins. S ee F igure 27 a nd Fig­ure 28. This port does not support Address Out
mode, and therefore no Control Register is re­quired. Port D can be configured to perform one or
more of the following functions:

■ MCU I/O Mode

■ CPLD Output – External Chip Select (ECS0-

ECS2)

■ CPLD Input – direct input to the CPLD, no Input

Macr ocells (IMC)

■ Slew rate – pins can be set up for fast slew rate

Port D pins can be configured in PSDsoft Express
as input pins for other dedicated functions:

■ Address Strobe (ALE/AS, PD0)

■ CLKIN (PD1) as input to the macrocells flip-

flops and APD counter

■ PSD Chip Select In put (CSI, PD2). Driv ing th is

signal High disables the Flash memory, SRAM
and CSIOP.

Figure 27. Port D Structure

INTERNAL DATA BUS

DATA OUT

REG.

DQ

DQ

WR

WR

ECS[2:0

]

READ MUX

P
D
B

CPLD- INPUT

DIR REG.

DATA IN

ENABLE PRODUCT

TERM (.OE)

OUTPUT
SELECT

OUTPUT

MUX

PORT D PIN

DATA OUT

AI02889

57/103

PSD8XXF2/3/4/5

External Chip Select

The CPLD also provide s three External Chip S e­lect (ECS0-ECS2) outputs on Port D pins that can
be used to sele ct ext ernal devices . E ach E x ternal
Chip Select (ECS0-ECS2) consists of one product

term that can be configured active High or Low.
The output enable of the pin is controlled by either
the output enable product term or the Direction
Register. (See Figure 28.)

Figure 28. Port D External Chip Select Signals

PLD INPUT BUS

POLARITY

BIT

PD2 PIN

PT2

ECS2

DIRECTION

REGISTER

POLARITY

BIT

PD1 PIN

PT1

ECS1

ENABLE (.OE)

ENABLE (.OE)

DIRECTION

REGISTER

POLARITY

BIT

PD0 PIN

PT0

ECS0

ENABLE (.OE)

DIRECTION

REGISTER

CPLD AND ARRAY

AI02890

PSD8XXF2/3/4/5

58/103

POWER MANAGEMENT

All PSD8XXFX devices offer configurable power
saving options. These opt ions may be used indi­vidually or in combinations, as follows:

■ All memory blocks in a PSD8XXFX (primary and

secondary Flash memory, and SRAM) are built
with power management technology. In addition
to using special silicon design methodology,
power management technology puts the
memories into standby mode when address/
data inputs are not changing (zero DC current).
As soon as a transition occurs on an input, the
affected memory “wakes up”, changes and
latches its outputs, then goes back to standby.
The designer does

not

have to do anything
special to achieve memory standby mode when
no inputs are changing—it happens
automatically.

The PLD sections can also achieve Stand-by
mode when its inputs are not changing, as
described in the sections on the Power
Management Mode Registers (PMMR).

■ As with the Power Management mode, the

Automatic Power Down (APD) block allows the
PSD8XXFX to reduce to stand-by current
automatically. The APD Unit can also block
MCU address/data signals from reaching the
memories and PLDs. This feature is available
on all the devices of the PSD8XXFX family. The
APD Unit is described in more detail in the
sections entitled “Automatic Power-down (APD)
Unit and Power-down Mode”, on page 59.

Built in logic monitors the Address Strobe of the
MCU for activity. If there is no activity for a
certain time period (MCU is asleep), the APD
Unit initiates Power-down mode (if enabled).
Once in Power-down mode, all address/data
signals are blocked from reaching PSD8XXFX
memory and PLDs, and the memories are
deselected internally. This allows the memory

and PLDs to remain in standby mode even if the
address/data signals are changing state
externally (noise, other devices on the MCU
bus, etc.). Keep in mind that any unblocked PLD
input signals that are changing states keeps the
PLD out of Stand-by mode, but not the
memories.

■ PSD Chip Se lect Inp ut (C SI, PD2) can be used

to disable the internal memories, placing them
in standby mode even if inputs are changing.
This feature does not block any internal signals
or disable the PLDs. This is a good alternative
to using the APD Unit. There is a slight penalty
in memory access time when PSD Chip Select
Input (CSI

, PD2) makes its initial transition from

deselected to selected.

■ The PMMRs can be written by the MCU at run-

time to manage power. All PSD8XXFX supports
“blocking bits” in these registers that are set to
block designated signals from reaching both
PLDs. Current consumption of the PLDs is
directly related to the composite frequency of
the changes on their inputs (see Figure 32 and
Figure 33). Significant power savings can be
achieved by blocking signals that are not used
in DPLD or CPLD logic equations.

PSD8XXFX dev ices hav e a Turbo bit in
PMMR0. This bit can be set to turn the Turbo
mode off (the default is with Turbo mode turned
on). While Turbo mode is off, the PLDs can
achieve standby current when no PLD inputs
are changing (zero DC current). Even when
inputs do change, significant power can be
saved at lower frequencies (AC current),
compared to when Turbo mode is on. When the
Turbo mode is on, there is a significant DC
current component and the AC component is
higher.

59/103

PSD8XXF2/3/4/5

Automatic Power-down (APD) Unit and Power­down Mod e. The APD Unit, s hown i n Figure 29,

puts the PSD8XXFX into Power-down mode by
monitoring the activity of Address Strobe (ALE/AS,
PD0). If the APD Unit is enabled, as soon as activ­ity on Address Strobe (ALE/AS, PD0) stops, a four
bit counter starts counting. If Address Strobe
(ALE/AS, PD0) remains inactive for fifteen clock
periods of CLKIN (PD1), Power-down (PDN) goes
High, and the PSD8XXFX enters Power-down
mode, as discussed next.

Power-dow n Mode. By default, if you enable the
APD Unit, Power-down mode is automatically en­abled. The device enters Power-down mode if Ad­dress Strobe (ALE/AS, PD0) remains inactive f or
fifteen periods of CLKIN (PD1).

The following should be kept in mind when the
PSD8XXF X is in Power-down mo d e:

■ If Address Strobe (ALE/AS, PD0) starts pulsing

again, the PSD8XXFX returns to normal
Operating mode. The PSD8XXFX also returns
to normal Operating mode if either PSD Chip
Select Input (CSI

, PD2) is Low or the Reset

(RESET

) input is High.

■ The MCU address/data bus is blocked from all

memory and PLDs.

■ Various signals can be blocked (prior to Power-

down mode) from entering the PLDs by setting

the appropriate bits in the PMMR registers. The
blocked signals include MCU control signals
and the common CLKIN (PD1). Note that
blocking CLKIN (PD1) from the PLDs does not
block CLKIN (PD1) from the APD Unit.

■ All PSD8XXFX memories enter Standby mode

and are drawing standby current. However, the
PLD and I/O ports blocks do

not

go into Standby
Mode because you don’t want to have to wait for
the logic and I/O to “wake-up” before their
outputs can change. See Table 28 for Power­down mode effects on PSD8XXFX ports.

■ Typical standby current is of the order of

microamperes. These standby curren t values
assume that there are no transitions on any PLD
input.

Table 28. Po wer- d own Mode’s Eff ect on Ports

Figure 29. APD Unit

Table 29. PSD 8X X FX Ti m in g and Stand-by Current during Power-down Mode

Note: 1. Power-down does not aff ect the operat i on of the PLD. Th e PLD operati on i n this mode is based only on the Turbo bit.

2. Typica l c urrent consum ption assu ming no PLD inputs are changing stat e and the PLD Tur bo bit is 0.

Port Function Pin Level

MCU I/O No Change
PLD Out No Change
Address Out Undefined
Data Port Tri-State
Peripheral I/O Tri-State

Mode

PLD Propagation

Delay

Memory

Access Time

Access Recovery Time

to Normal Access

Typical Stand-by Current

5V V

CC

3V V

CC

Power-down

Normal t

PD

(Note 1)

No Access

t

LVDV

75 µA (Note

2

) 25 µA (Note 2)

APD EN
PMMR0 BIT 1=1

ALE

RESET

CSI

CLKIN

TRANSITION

DETECTION

EDGE

DETECT

APD

COUNTER

POWER DOWN
(

PDN

)

DISABLE BUS
INTERFACE

EEPROM SELECT
FLASH SELECT

SRAM SELECT

PD

CLR

PD

DISABLE
FLASH/EEPROM/SRAM

PLD

SELECT

AI02891

PSD8XXF2/3/4/5

60/103

For Users of the HC11 (or compatible). The
HC11 turns off its E clock when it sleeps. There­fore, if you are using an HC11 (or compatible) in
your design, and you wish to use the Power-down
mode, you must not connect the E clock to CLKIN
(PD1). You should instead connect a crystal oscil­lator to CLKIN (PD1). The crystal oscillator fre­quency must be

less than

15 times the frequency
of AS. The reason for this is that if the frequency is
greater than 15 times the frequency of AS, the
PSD8XXFX keeps going into Power-down mode.

Other Power Savi ng Options. The PSD8XXFX
offers other reduced power saving options that are
independent of the Power-down mode. Except for
the SRAM Stand-by and PSD Chip Select Input
(CSI

, PD2) features, they are enabled by setting

bits in PMMR0 and PMMR2.

Figure 30. Enable Power-down Flow Chart

Enable APD

Set PMMR0 Bit 1 = 1

PSD in Power

Down Mode

ALE/AS idle

for 15 CLKIN

clocks?

RESET

Yes

No

OPTIONAL

Disable desired inputs to PLD

by setting PMMR0 bits 4 and 5

and PMMR2 bits 2 through 6.

AI02892

61/103

PSD8XXF2/3/4/5

PLD Power M a nagem ent

The power and speed of the PLDs are controlled
by the Turbo bit (bit 3) in PMMR0. By set ting the
bit to 1, the Turbo mode is off and the P LDs con­sume the specified stand-by current when the in­puts are not switching for an extended time of
70ns. The propagation delay time is increased by
10ns after the Turbo bit is set to 1 (turned off) when
the inputs change at a composite frequency of less

than 15 MHz. When the Turbo bit is reset to 0
(turned on), the PLDs run at full power and speed.
The Turbo bit affects the PLD’s DC power, AC
power, and propagation delay.

Blocking MCU control signals with the bits of
PMMR2 can further reduce PLD AC power con­sump tion.

Table 30. Power Management Mode Registers PMMR0 (Note 1)

Note: 1. The bits of this register are cleared to zero following Power-up. Subsequent Reset (RESET) pulses do not clear th e registers.

Table 31. Power Management Mode Registers PMMR2 (Note 1)

Note: 1. The bits of this register are cleared to zero following Power-up. Subsequent Reset (RESET) pulses do not clear th e registers.

Bit 0 X 0 Not used, and should be set to zero.

Bit 1 APD Enable

0 = off Automatic Power-down (APD) is disabled.
1 = on Automatic Power-down (APD) is enabled.

Bit 2 X 0 Not used, and should be set to zero.

Bit 3 PLD Turbo

0 = on PLD Turbo mode is on
1 = off PLD Turbo mode is off, saving power.

Bit 4 PLD Array clk

0 = on

CLKIN (PD1) input to the PLD AND Array is connected. Every change of CLKIN
(PD1) Powers-up the PLD when Turbo bit is 0.

1 = off CLKIN (PD1) input to PLD AND Array is disconnected, saving power.

Bit 5 PLD MCell clk

0 = on CLKIN (PD1) input to the PLD macrocells is connected.

1 = off CLKIN (PD1) input to PLD macrocells is disconnected, saving power.
Bit 6 X 0 Not used, and should be set to zero.
Bit 7 X 0 Not used, and should be set to zero.

Bit 0 X 0 Not used, and should be set to zero.
Bit 1 X 0 Not used, and should be set to zero.

Bit 2

PLD Array
CNTL0

0 = on Cntl0 input to the PLD AND Array is connected.

1 = off Cntl0 input to PLD AND Array is disconnected, saving power.

Bit 3

PLD Array
CNTL1

0 = on Cntl1 input to the PLD AND Array is connected.

1 = off Cntl1 input to PLD AND Array is disconnected, saving power.

Bit 4

PLD Array
CNTL2

0 = on Cntl2 input to the PLD AND Array is connected.

1 = off Cntl2 input to PLD AND Array is disconnected, saving power.

Bit 5

PLD Array
ALE

0 = on ALE input to the PLD AND Array is connected.

1 = off ALE input to PLD AND Array is disconnected, saving power.

Bit 6

PLD Array
DBE

0 = on DBE input to the PLD AND Array is connected.

1 = off DBE input to PLD AND Array is disconnected, saving power.
Bit 7 X 0 Not used, and should be set to zero.

PSD8XXF2/3/4/5

62/103

SRAM Standby Mode (Battery Backup). The
PSD8XXFX supports a battery backup mode in
which the contents of the SRAM are retained in the
event of a power loss. The SRAM has Voltage
Stand-by (V

STBY

, PC2) that can be connected to

an external battery. When V

CC

becomes lower

than V

STBY

then the PSD8XXFX automatically

connects to Voltage Stand-by (V

STBY

, PC2) as a
power source to the SR AM. The SRAM Standby
Current (I

STBY

) is typically 0.5 µA. The SRAM data
retention voltage i s 2 V mini mum. T he Battery -on
Indicator (VBATON) can be routed to PC4. This
signal indicates when the V

CC

has dropped below

V

STBY

.

PSD Chip Select Input (CSI

, PD2 )

PD2 of Port D can b e configured in PSDsoft Ex­press as PSD Chip Select Input (CSI

). When Low,
the signal selects and enables the internal Flash
memory, EEPROM, SRAM, and I/O blocks for
READ or WRITE operations involving the
PSD8XXFX. A High on PSD Chip Select Input
(CSI

, PD2) disables the Flash memory, EEPROM,
and SRAM, and reduces the PSD8XXFX power
consumption. However, the P LD and I/O signals
remain operational when PSD Chip Select Input
(CSI

, PD2) is High.

There may be a timing pena lty when using PSD
Chip Select Input (CSI

, PD2) depending on the
speed grade of the PSD8XXFX that you are using.
See the timing parameter t

SLQV

in Table 60 or Ta-

ble 61.

Input Clock

The PSD8XXFX provides the option to turn off
CLKIN (PD1) to the PLD to save AC power con­sumption. CLKIN (PD1) is an input to the PLD
AND Array and the Output Macrocells (OMC).

During Power-down mode, or, if CLKIN (PD1) is
not being used as part of the PLD logic equation,
the clock should be disabled to save AC power.
CLKIN (PD1) is disconnected from the PLD AND
Array or the Macrocells block by setting bits 4 or 5
to a 1 in PMMR0.

Input Cont rol Si gn a l s

The PSD8XXFX provides the option to turn off the
input control signals (CNTL0, CNTL1, CNTL2, Ad­dress Strobe (ALE/AS, PD0) and DBE) to the PLD
to save AC power consumption. These control sig­nals are inputs to the PLD AND Array. During
Power-down mode, or, if any of them are not being
used as part of the PLD logic equation, these con­trol signals should be disabled to save AC power.
They are disconnected from the PLD AND Array
by setting bits 2, 3, 4, 5, and 6 to a 1 in PMMR2.

Table 32. APD Counter Operation

APD Enable Bit ALE PD Polarity ALE Level APD Counter

0 X X Not Counting
1 X Pulsing Not Counting
1 1 1 Counting (Generates PDN after 15 Clocks)
1 0 0 Counting (Generates PDN after 15 Clocks)

63/103

PSD8XXF2/3/4/5

RESET TIMING AND DEVICE STATUS AT RESET

Upon Power-up, the PSD8XXFX requires a Reset
(RESET

) pulse of duration t

NLNH-PO

after VCC is
steady. During this period, t he device lo ads inter­nal configurations, clears some of the registers
and sets the Flash me mory into Operating m ode.
After the rising edge of Reset (RESET

), the
PSD8XXFX remains in the Reset mode for an ad­ditional period, t

OPR

, before the first memory ac-

cess is allow ed.
The Flash memory is reset to the READ Mode

upon Power-up. Sector Select (FS0-FS7 and
CSBOOT0-CSBOOT3) must all be Low, Write
Strobe (WR

, CNTL0) High, during Power On Re­set for maximum security of the data contents and
to remove the possibility of a byte being written on
the first edge of Write Strobe (WR

, CNT L0). An y
Flash memory WRITE cycl e i n it i at i on i s pr eve n ted
automatically when V

CC

is below V

LKO

.

Warm Reset

Once the device is up and running, the device can
be reset with a pulse of a much shorter duration,
t

NLNH

. The same t

OPR

period is needed before the

device is operational after warm reset. Figure 31
shows the timing of the Power-up and warm reset.

I/O Pin, Register and PLD Status at Reset

Table 33 shows the I/O pin, register and PLD sta­tus during Power On Reset, warm reset and Pow­er-down mode. PLD outputs are always valid
during warm reset, and they are valid in Power On
Reset once the internal PSD8XXFX Configuration
bits are loaded. This loading of PSD8XXFX is
completed typically long before the V

CC

ramps up
to operating level. Once the PLD is active, the
state of the outputs are determined by the PSDa­bel equations.

Reset of Flash Memory Erase and Program
Cycles (on the PSD834Fx)

A Reset (RESET

) also resets the internal Flash
memory state machine. During a Flash memory
Program or Erase cycle, Reset (RESET

) termi­nates the cycle and returns the Flash mem ory to
the Read Mode within a period of t

NLNH-A

.

Figure 31. Reset (RESET

) Timing

t

NLNH-PO

t

OPR

AI02866b

RESET

t

NLNH

t

NLNH-A

t

OPR

V

CC

VCC(min)

Power-On Reset

Warm Reset

PSD8XXF2/3/4/5

64/103

Table 33. Status During Power-On Reset, Warm Reset and Power-down Mode

Note: 1. The SR_co d and Periph M ode bits in the VM Register are alwa ys cleared to 0 on Power- On Reset or Wa rm Reset.

Port Configuration Power-On Reset Warm Reset Power-down Mode

MCU I/O Input mode Input mode Unchanged

PLD Output

Valid after internal PSD
configuration bits are
loaded

Valid

Depends on inputs to PLD
(addresses are blocked in

PD mode)
Address Out Tri-stated Tri-stated Not defined
Data Port Tri-stated Tri-stated Tri-stated
Peripheral I/O Tri-stated Tri-stated Tri-stated

Register Power-On Reset Warm Reset Power-down Mode

PMMR0 and PMMR2 Cleared to 0 Unchanged Unchanged

Macrocells flip-flop status

Cleared to 0 by internal
Power-On Reset

Depends on .re and .pr
equations

Depends on .re and .pr

equations

VM Register

1

Initialized, based on the
selection in PSDsoft
Configuration menu

Initialized, based on the
selection in PSDsoft
Configuration menu

Unchanged

All other registers Cleared to 0 Cleared to 0 Unchanged

65/103

PSD8XXF2/3/4/5

PROGRAMMING IN-CIRCUIT USING THE JTAG SERIAL INTERFACE

The JTAG Serial Interface block can be enabled
on Port C (see Table 34). All memory blocks (pri­mary and secondary Flash memory), PLD logic,
and PSD8XXFX Configuration Register bits may
be programmed through the JTAG Serial Interface
block. A blank device can be mounted on a printed
circuit board and programmed using JTAG.

The standard JTAG signals (IEEE 1149.1) are
TMS, TCK, TDI, and TDO. Two additional signals,
TSTAT

and TERR, are opt ional JTAG ext ensions

used to speed up Program and Erase cycles.

By default, on a blank PSD8XXFX (as shipped
from the factory or after erasure), four pins on Port
C are enabled for the basic JTAG signals TMS,
TCK, TDI, and TDO

.

See Application Not e

AN1153

for more details on

JTAG In-System Programming (ISP).

Standard JTAG Signals

The standard JTAG signals (TMS, TCK, TDI, and
TDO) can be enabled by any of three different con­ditions that are logically ORed. When enabled,
TDI, TDO, TCK, and TMS are inputs, waiting for a
JTAG serial command from an external JTAG con­troller device (such as FlashLINK or Automated
Test Equipment). When t he e nabli ng command is
received, TDO be comes an ou tput and t he JTA G
channel is fully functional inside the PSD8XXFX.
The same command that enables the JTAG chan­nel may optionally enable the two additional JTAG
signals, TSTAT

and TERR.

The following symbolic logic equation specifies the
conditions enabling the four basic JTAG signals
(TMS, TCK, TDI, and TDO) on their respective
Port C pins. For purposes of discussion, the logic
label JTAG_ON is used. When JTAG_ON is true,
the four pins are enabled for JTAG. When
JTAG_ON is false, the four pins can be us ed for
general PSD8XXFX I/O.

JTAG_ON = PSDsoft_enabled +

/* An NVM configuration bit inside
the PSD is set by the designer in
the PSDsoft Express Configuration
utility. This dedicates the pins
for JTAG at all times (compliant
with IEEE 1149.1 */

Microcontroller_enabled +

/* The microcontroller can set a
bit at run-time by writing to the
PSD register, JTAG Enable. This
register is located at address
CSIOP + offset C7h. Setting the

JTAG_ENABLE bit in this register
will enable the pins for JTAG use.
This bit is cleared by a PSD reset
or the microcontroller. See Table
35 for bit definition. */

PSD_product_term_enabled;

/* A dedicated product term (PT)
inside the PSD can be used to en­able the JTAG pins. This PT has
the reserved name JTAGSEL. Once
defined as a node in PSDabel, the
designer can write an equation for
JTAGSEL. This method is used when
the Port C JTAG pins are multi­plexed with other I/O signals. It
is recommended to logically tie
the node JTAGSEL to the JEN\ sig­nal on the Flashlink cable when
multiplexing JTAG signals. See Ap­plication Note 1153 for details.
*/

The state of the PSD Reset (RESET

) signal does
not interrupt (or prevent) JTAG operations if the
JTAG pins are dedicated by an NVM configuration
bit (via PSDsoft Express). However, Reset (RE­SET) will prevent or interrupt JT AG operations if
the JTAG enable register is used to enable the
JTAG pins.

The PSD8XXFX supports JTAG In-System-Con­figuration (ISC) commands, but not Boundary
Scan. The PSDsoft Express software tool and
FlashLINK JTAG programming cable implement
the JTAG In-System-Configuration (ISC) com­mands. A definition of these JTAG In-System­Configuration (ISC) comman ds and sequenc es is
defined in a supplemental document available
from ST. This document is needed only as a refer­ence for designers who use a FlashLINK to pro­gram their PSD8XXFX.

Table 34. JTAG Port Signals

Port C Pin JTAG Signals Description

PC0 TMS Mode Select
PC1 TCK Clock
PC3 TSTAT

Status

PC4 TERR

Error Flag
PC5 TDI Serial Data In
PC6 TDO Serial Data Out

PSD8XXF2/3/4/5

66/103

JTAG Extensions

TSTAT

and TERR are two JTAG extension signals
enabled by an “ISC_ENABLE” command received
over the four standard JTAG signa ls (TMS, TCK,
TDI, and TDO). They are used to speed Program
and Erase cycles by indicating status on
PSD8XXFX signals instead of having to scan the
status out serially u sing the standard JTAG c han­nel. See Application Note

AN1153

.

TERR

indicates if an error has occurred when
erasing a sector or programming a byte in F lash
memory. This signal goes Low (active) when an
Error condition occurs, and stays Low until an
“ISC_CLEAR” command is executed or a chip Re­set (RESET

) pulse is received after an

“ISC_DISABLE” command.
TSTAT

behaves the same as Ready/Busy de­scribed in the section entitled “Ready/Busy (PC3)”,
on page 18. TS TAT

is High when the PSD8X X FX
device is in READ Mode (prima ry and secondary
Flash memory contents can be read). TSTAT

is
Low when Flash memory Program or Erase cycles
are in progress, and al so when dat a is being writ­ten to the secondary Flash memory.

TSTAT

and TERR can be configured as open­drain type signals duri ng a n “I S C_E NABLE” com­mand. This facilitates a wired-OR connection of
TSTAT

signals from m ultiple PSD8XXFX devices
and a wired-OR connection of TE RR

signals from

those same devices. This is useful when several

PSD8XXFX devices are “chained” together in a
JTAG environment.

Secur i t y and Flash mem ory Pr otection

When the security bit is set, the device cannot be
read on a Device Programmer or through the
JTAG Port. When using the JTAG Port, only a F ull
Chip Erase command is allowed.

All other Program, Erase and Verify commands
are blocked. Full Chip Erase returns the part to a
non-secured blank state. The Sec urity Bit can be
set in PSDsoft Express Configuration.

All primary and secondary Flash memory sectors
can individually be sector protected against era­sures. The sector protect bits can be set in PSD­soft Express Configuration.

INITIAL DELIVERY STATE

When delivered from ST, the PSD8XXFX device
has all bits in the memory and P LDs s et to 1. T he
PSD8XXFX Configuration R egister bits are set to

0. The code, configuration, and PLD logic are
loaded using the programming procedure. Infor­mation for programming the device is available di­rectly from ST. Please contact your local sales
representative.

Table 35. JTAG Enable Register

Note: 1. The state of Reset (RESET) does not interrupt (or prevent) JTAG operations if the JTAG signals are dedicated by an NVM Config-

uration bit (via PSDsoft Express). However, Reset (RESET

) preven ts or interr upts JTAG operations i f the JTAG en abl e register is

used to enabl e the JTAG signals.

Bit 0 JTAG_Enable

0 = off JTAG port is disabled.

1 = on JTAG port is enabled.
Bit 1 X 0 Not used, and should be set to zero.
Bit 2 X 0 Not used, and should be set to zero.
Bit 3 X 0 Not used, and should be set to zero.
Bit 4 X 0 Not used, and should be set to zero.
Bit 5 X 0 Not used, and should be set to zero.
Bit 6 X 0 Not used, and should be set to zero.
Bit 7 X 0 Not used, and should be set to zero.

67/103

PSD8XXF2/3/4/5

AC/DC PARAMETERS

These tables describe the AD and DC parameters
of the PSD8XXFX:

❏ DC Electrical Specification
❏ AC Timing Specification

■ PLD Timing

– Combi natorial Timing
– Synchronous Clock Mod e
– Asynchronous Clock Mode
– Input Macrocell Timing

■ MCU Timing

– READ Timing
–WRITE Timing
– Peripheral Mode Timing
– Power-down and Reset Timing

The following are issues c oncerning the param e­ters presented:

■ In the DC specification the supply current is

given for different modes of operation. Before
calculating the total power consumption,
determine the percentage of time that the
PSD8XXFX is in each mod e. Also, the supply
power is considerably different if the Turbo bit is

0.

■ The AC power component gives the PLD, Flash

memory, and SRAM mA/MHz specification.
Figure 32 and Figure 33 show the PLD mA/MHz
as a function of the number of Product Terms
(PT ) used.

■ In the PLD timing parameters, add the required

delay when Turbo bit is 0.

Figure 32. PLD I

CC

/Frequency Consumption (5 V range)

0

10

20

30

40

60

70

80

90

100

110

V

CC

= 5V

50

010155 20 25

HIGHEST COMPOSITE FREQUENCY AT PLD INPUTS (MHz)

I

CC

– (mA)

TURBO ON (100%)

TURBO ON (25%)

TURBO OFF

TURBO OFF

PT 100%
PT 25%

AI02894

PSD8XXF2/3/4/5

68/103

Figure 33. PLD ICC /Frequency Consumption (3 V range)

0

10

20

30

40

50

60

V

CC

= 3V

010155 20 25

I

CC

– (mA)

TURBO ON (100%)

TURBO ON (25%)

TURBO OFF

TURBO OFF

HIGHEST COMPOSITE FREQUENCY AT PLD INPUTS (MHz)

PT 100%
PT 25%

AI03100

69/103

PSD8XXF2/3/4/5

Table 36. Example of PSD8XXFX Typical Power Calculation at VCC = 5.0 V (Turbo Mode On)

Conditions

Highest Composite PLD input frequency

(Freq PLD) = 8 MHz

MCU ALE frequency (Freq ALE) = 4 MHz

% Flash memory
Access

= 80%

% SRAM access = 15%
% I/O access = 5% (no additional power above base)

Operational Mode s

% Normal = 10%
% Power-down Mode = 90%

Number of product terms used

(from fitter report) = 45 PT
% of total product terms = 45/182 = 24.7%

Turbo Mode = ON

Calculation (using typical values)

I

CC

total = Ipwrdown x %pwrdown + %normal x (ICC (ac) + ICC (dc))

= Ipwrdown x %pwrdown + % normal x (%flash x 2.5 mA/MHz x Freq ALE

+ %SRAM x 1.5 mA/MHz x Freq ALE
+ % PLD x 2 mA/MHz x Freq PLD
+ #PT x 400 µA/PT)

= 50 µA x 0.90 + 0.1 x (0.8 x 2.5 mA/MHz x 4 MHz

+ 0.15 x 1.5 mA/MHz x 4 MHz
+ 2 mA/MHz x 8 MHz

+ 45 x 0.4 mA/PT)
= 45 µA + 0.1 x (8 + 0.9 + 16 + 18 mA)
= 45 µA + 0.1 x 42.9
= 45 µA + 4.29 mA
= 4.34 mA

This is the operating power with no EEPROM WRITE or Flash memory Erase cycles in progress. Calculation is based
on I

OUT

= 0 mA.

PSD8XXF2/3/4/5

70/103

Table 37. Example of PSD8XXFX Typical Power Calculation at VCC = 5.0 V (Turbo Mode Off)

Conditions

Highest Composite PLD input frequency

(Freq PLD) = 8 MHz

MCU ALE frequency (Freq ALE) = 4 MHz

% Flash memory
Access

= 80%

% SRAM access = 15%
% I/O access = 5% (no additional power above base)

Operational Mode s

% Normal = 10%
% Power-down Mode = 90%

Number of product terms used

(from fitter report) = 45 PT
% of total product terms = 45/182 = 24.7%

Turbo Mode = Off

Calculation (using typical values)

I

CC

total = Ipwrdown x %pwrdown + %normal x (ICC (ac) + ICC (dc))

= Ipwrdown x %pwrdown + % normal x (%flash x 2.5 mA/MHz x Freq ALE

+ %SRAM x 1.5 mA/MHz x Freq ALE

+ % PLD x (from graph using Freq PLD))
= 50 µA x 0.90 + 0.1 x (0.8 x 2.5 mA/MHz x 4 MHz

+ 0.15 x 1.5 mA/MHz x 4 MHz

+ 24 mA)
= 45 µA + 0.1 x (8 + 0.9 + 24)
= 45 µA + 0.1 x 32.9
= 45 µA + 3.29 mA
= 3.34 mA

This is the operating power with no EEPROM WRITE or Flash memory Erase cycles in progress. Calculation is based
on I

OUT

= 0 mA.

71/103

PSD8XXF2/3/4/5

MAXIMUM RATI N G

Stressing the de vice above the rating l isted in t he
Absolute Maximum Ratings” table may cause per­manent damage to the device. T hese are stress
ratings only and operation of the device at t hese or
any other conditions ab ove thos e indicated i n the
Operating sections of this spec ification is not im-

plied. Exposure to Absolute Maximum Rating con­ditions for extended periods may affect device
reliability. Refer also to the STMicroelectronics
SURE Program and other relevant quality docu­ments.

Table 38. Absolute Maximum Ratings

Note: 1. IPC/JEDEC J-STD-020 A

2. JEDEC Std JESD22-A 114A (C1=1 00 pF, R1=1500 Ω, R2=500 Ω)

Symbol Parameter Min. Max. Unit

T

STG

Storage Temperature –65 125 °C

T

LEAD

Lead Temperature during Soldering (20 seconds max.)

1

235 °C

V

IO

Input and Output Voltage (Q = VOH or Hi-Z)

–0.6 7.0 V

V

CC

Supply Voltage –0.6 7.0 V

V

PP

Device Programmer Supply Voltage –0.6 14.0 V

V

ESD Electrostatic Discharge Voltage (Human Body model)

2

–2000 2000 V

PSD8XXF2/3/4/5

72/103

DC AND AC PARAMETERS

This section summarizes t he operating and mea­surement conditions, and the DC and AC charac­teristics of the device. The parameters i n the DC
and AC Characteristic tables that follow are de­rived from tests performed under the Measure-

ment Conditions summarized in the relevant
tables. Designers should c heck that the o perat ing
conditions in their circuit match the m easurement
conditions when relying on the quoted parame­ters.

Table 39. Operating Conditions (5V devices)

Table 40. Operating Conditions (3V devices)

Table 41. AC Measurement Conditions

Note: 1. Output Hi-Z i s defined as th e poi nt where da ta out is no longer driven.

Figure 34. AC Measurem ent I/O W av eform Fi gure 35. AC Me as urement Loa d Circuit

Table 42. Capacitance

Note: 1. Sampled only, not 100% tested.

2. Typical values are for T

A

= 25°C and nomi nal supply voltages.

Symbol Parameter Min. Max. Unit

V

CC

Supply Voltage 4.5 5.5 V

T

A

Ambient Operating Temperature (industrial) –40 85 °C
Ambient Operating Temperature (commercial) 0 70 °C

Symbol Parameter Min. Max. Unit

V

CC

Supply Voltage 3.0 3.6 V

T

A

Ambient Operating Temperature (industrial) –40 85 °C
Ambient Operating Temperature (commercial) 0 70 °C

Symbol Parameter Min. Max. Unit

C

L

Load Capacitance 30 pF

3.0V

0V

Test Point 1.5V

AI03103b

Device

Under Test

2.01 V

195 Ω

C

L

= 30 pF
(Including Scope and
Jig Capacitance)

AI03104b

Symbol Parameter Test Condition

Typ.

2

Max. Unit

C

IN

Input Capacitance (for input pins)

V

IN

= 0V

46

pF

C

OUT

Output Capacitance (for input/
output pins)

V

OUT

= 0V

812

pF

C

VPP

Capacitance (for CNTL2/VPP)V

PP

= 0V

18 25

pF

73/103

PSD8XXF2/3/4/5

Table 43. AC Symbols for PLD Timing

Example: t

AVLX

– Time from Address Valid to ALE Invalid.

Figure 36. Switching Waveforms – Key

Signal Letters Signal Behavior

A Address Input t Time
C CEout Output L Logic Level Low or ALE
D Input Data H Logic Level High

E E Input V Valid
G Internal WDOG_ON signal X No Longer a Valid Logic Level

I Interrupt Input Z Float

L ALE Input PW Pulse Width
N Reset Input or Output

P Port Signal Output
Q Output Data
RWR

, UDS, LDS, DS, IORD, PSEN Inputs
S Chip Select Input
TR/W

Input

W Internal PDN Signal

B

V

STBY

Output

M Output Macrocell

WAVEFORMS

INPUTS OUTPUTS

STEADY INPUT

MAY CHANGE FROM
HI TO LO

MAY CHANGE FROM
LO TO HI

DON'T CARE

OUTPUTS ONLY

STEADY OUTPUT

WILL BE CHANGING
FROM HI TO LO

WILL BE CHANGING
LO TO HI

CHANGING, STATE
UNKNOWN

CENTER LINE IS
TRI-STATE

AI03102

PSD8XXF2/3/4/5

74/103

Table 44. DC Characteristics (5V devices)

Note: 1. Reset (R E SE T ) has hyster esis. V

IL1

is valid at or below 0.2VCC –0.1. V

IH1

is valid at or above 0.8VCC.

2. CSI

deselect ed or intern al Power-down mode is active.

3. PLD is in non-Turbo mode, and none of the inputs are switching.

4. Pleas e see Figure 32 for the PLD current calcu lation.

5. I

OUT

= 0 mA

Symbol Parameter

Test Condition

(in addition to those in

Table 39)

Min. Typ. Max. Unit

V

IH

Input High Voltage

4.5 V < V

CC

< 5.5 V

2

VCC +0.5

V

V

IL

Input Low Voltage

4.5 V < V

CC

< 5.5 V

–0.5 0.8 V

V

IH1

Reset High Level Input Voltage

(Note

1

)

0.8V

CC

VCC +0.5

V

V

IL1

Reset Low Level Input Voltage

(Note

1

)

–0.5

0.2V

CC

–0.1

V

V

HYS

Reset Pin Hysteresis 0.3 V

V

LKO

VCC (min) for Flash Erase and

Program

2.5 4.2 V

V

OL

Output Low Voltage

I

OL

= 20 µA, VCC = 4.5 V

0.01 0.1 V

I

OL

= 8 mA, VCC = 4.5 V

0.25 0.45 V

V

OH

Output High Voltage Except

V

STBY

On

I

OH

= –20 µA, VCC = 4.5 V

4.4 4.49 V

I

OH

= –2 mA, VCC = 4.5 V

2.4 3.9 V

V

OH1

Output High Voltage V

STBY

On I

OH1

= 1 µA V

STBY

– 0.8

V

V

STBY

SRAM Stand-by Voltage 2.0

V

CC

V

I

STBY

SRAM Stand-by Current

V

CC

= 0 V

0.5 1 µA

I

IDLE

Idle Current (V

STBY

input) VCC > V

STBY

–0.1 0.1 µA

V

DF

SRAM Data Retention Voltage

Only on V

STBY

2V

I

SB

Stand-by Supply Current

for Power-down Mode

CSI

>VCC –0.3 V (Notes

2,3

)

50 200 µA

I

LI

Input Leakage Current

V

SS

< VIN < V

CC

–1 ±0.1 1 µA

I

LO

Output Leakage Current

0.45 < V

OUT

< V

CC

–10 ±5 10 µA

I

CC

(DC)

(Note 5)

Operating

Supply

Current

PLD Only

PLD_TURBO = Off,

f = 0 MHz (Note

5

)

0 µA/PT

PLD_TURBO = On,

f = 0 MHz

400 700 µA/PT

Flash memory

During Flash memory

WRITE/Erase Only

15 30 mA

Read only, f = 0 MHz 0 0 mA

SRAM f = 0 MHz 0 0 mA

I

CC

(AC)

(Note 5)

PLD AC Adder

note

4

Flash memory AC Adder 2.5 3.5

mA/

MHz

SRAM AC Adder 1.5 3.0

mA/

MHz

75/103

PSD8XXF2/3/4/5

Table 45. DC Characteristics (3V devices)

Note: 1. Reset (R E SE T ) has hyster esis. V

IL1

is valid at or below 0.2VCC –0.1. V

IH1

is valid at or above 0.8VCC.

2. CSI

deselect ed or internal PD i s ac tive.

3. PLD is in non-Turbo mode, and none of the inputs are switching.

4. Pleas e see Figure 33 for the PLD current calcu lation.

5. I

OUT

= 0 mA

Symbol Parameter Conditions Min. Typ. Max. U nit

V

IH

High Level Input Voltage

3.0 V < V

CC

< 3.6 V 0.7V

CC

VCC +0.5

V

V

IL

Low Level Input Voltage

3.0 V < V

CC

< 3.6 V

–0.5 0.8 V

V

IH1

Reset High Level Input Voltage

(Note

1

)

0.8V

CC

VCC +0.5

V

V

IL1

Reset Low Level Input Voltage

(Note

1

)

–0.5

0.2V

CC

–0.1

V

V

HYS

Reset Pin Hysteresis 0.3 V

V

LKO

VCC (min) for Flash Erase and

Program

1.5 2.2 V

V

OL

Output Low Voltage

I

OL

= 20 µA, VCC = 3.0 V

0.01 0.1 V

I

OL

= 4 mA, VCC = 3.0 V

0.15 0.45 V

V

OH

Output High Voltage Except

V

STBY

On

I

OH

= –20 µA, VCC = 3.0 V

2.9 2.99 V

I

OH

= –1 mA, VCC = 3.0 V

2.7 2.8 V

V

OH1

Output High Voltage V

STBY

On I

OH1

= 1 µA V

STBY

– 0.8

V

V

STBY

SRAM Stand-by Voltage 2.0

V

CC

V

I

STBY

SRAM Stand-by Current

V

CC

= 0 V

0.5 1 µA

I

IDLE

Idle Current (V

STBY

input) VCC > V

STBY

–0.1 0.1 µA

V

DF

SRAM Data Retention Voltage

Only on V

STBY

2V

I

SB

Stand-by Supply Current

for Power-down Mode

CSI

>VCC –0.3 V (Notes

2,3

)

25 100 µA

I

LI

Input Leakage Curren t

V

SS

< VIN < V

CC

–1 ±0.1 1 µA

I

LO

Output Leakage Current

0.45 < V

IN

< V

CC

–10 ±5 10 µA

I

CC

(DC)

(Note 5)

Operating

Supply

Current

PLD Only

PLD_TURBO = Off,

f = 0 MHz (Note

3

)

0 µA/PT

PLD_TURBO = On,

f = 0 MHz

200 400 µA/PT

Flash memory

During Flash memory

WRITE/Erase Only

10 25 mA

Read only, f = 0 MHz 0 0 mA

SRAM f = 0 MHz 0 0 mA

I

CC

(AC)

(Note 5)

PLD AC Adder

note

4

Flash memory AC Adder 1.5 2.0

mA/

MHz

SRAM AC Adder 0.8 1.5

mA/

MHz

PSD8XXF2/3/4/5

76/103

Figure 37. Input to Output Disable / Enable

Table 46. CPLD Combinatorial Timing (5V devices)

Note: 1. Fast Slew Rate output available o n P A3-PA0, PB3-PB0, and PD2-PD0. Decrement t i mes by given amount.

Table 47. CPLD Combinatorial Timing (3V devices)

Note: 1. Fast Slew Rate output available o n P A3-PA0, PB3-PB0, and PD2-PD0. Decrement t i mes by given amount.

Symbol Parameter Co nditi ons

-70 - 90 -1 5 Fast
PT

Aloc

Turbo

Off

Slew
rate

1

Unit

Min Max Min Max Min Max

t

PD

CPLD Input Pin/
Feedback to CPLD
Combinatorial Output

20 25 32 + 2 + 10 – 2 ns

t

EA

CPLD Input to CPLD
Output Enable

21 26 32 + 10 – 2 ns

t

ER

CPLD Input to CPLD
Output Disable

21 26 32 + 10 – 2 ns

t

ARP

CPLD Register Clear
or Preset Delay

21 26 33 + 10 – 2 ns

t

ARPW

CPLD Register Clear
or Preset Pulse Width

10 20 29 + 10 ns

t

ARD

CPLD Array Delay

Any

macrocell

11 16 22 + 2 ns

Symbol Parameter Conditions

-12 -15 -20

PT

Aloc

Turbo

Off

Slew
rate

1

Unit

Min Max Min Max Min Max

t

PD

CPLD Input Pin/
Feedback to CPLD
Combinatorial Output

40 45 50 + 4 + 20 – 6 ns

t

EA

CPLD Input to CPLD
Output Enable

43 45 50 + 20 – 6 ns

t

ER

CPLD Input to CPLD
Output Disable

43 45 50 + 20 – 6 ns

t

ARP

CPLD Register Clear
or
Preset Delay

40 43 48 + 20 – 6 ns

t

ARPW

CPLD Register Clear
or
Preset Pulse Width

25 30 35 + 20 ns

t

ARD

CPLD Array Delay

Any

macrocell

25 29 33 + 4 ns

tER tEA

INPUT

INPUT TO

OUTPUT

ENABLE/DISABLE

AI02863

77/103

PSD8XXF2/3/4/5

Figure 38. S ync h ronous Clo ck Mo de Ti m i ng – P LD

Table 48. CPLD Macrocell Synchronous Clock Mode Timing (5V devices)

Note: 1. Fast Slew Rate output available o n P A3-PA0, PB3-PB0, and PD2-PD0. Decrement t i mes by given amount.

2. CLKIN (PD1 ) t

CLCL

= tCH + tCL.

Symbol P arameter Conditions

-70 -9 0 -15 Fast
PT

Aloc

Turbo

Off

Slew
rate

1

Unit

Min Max Min Max Min Max

f

MAX

Maximum
Frequency
External
Feedback

1/(t

S+tCO

)

40.0 30.30 25.00 MHz

Maximum
Frequency
Internal
Feedback
(f

CNT

)

1/(t

S+tCO

–10)

66.6 43.48 31.25 MHz

Maximum
Frequency
Pipelined Data

1/(t

CH+tCL

)

83.3 50.00 35.71 MHz

t

S

Input Setup
Time

12 15 20 + 2 + 10 ns

t

H

Input Hold Time 0 0 0 ns

t

CH

Clock High Time Clock Input 6 10 15 ns

t

CL

Clock Low Time Clock Input 6 10 15 ns

t

CO

Clock to Output
Delay

Clock Input 13 18 22 – 2 ns

t

ARD

CPLD Array
Delay

Any macrocell 11 16 22 + 2 ns

t

MIN

Minimum Clock
Period

2

tCH+t

CL

12 20 30 ns

t

CH

t

CL

t

CO

t

H

t

S

CLKIN

INPUT

REGISTERED

OUTPUT

AI02860

PSD8XXF2/3/4/5

78/103

Table 49. CPLD Macrocell Synchronous Clock Mode Timing (3V devices)

Note: 1. Fast Slew Rate output available o n P A3-PA0, PB3-PB0, and PD2-PD0. Decrement t i mes by given amount.

2. CLKIN (PD1 ) t

CLCL

= tCH + tCL.

Symbol Parameter Conditions

-12 -15 -20

PT

Aloc

Turbo

Off

Slew
rate

1

Unit

Min Max Min Max Min Ma x

f

MAX

Maximum
Frequency
External Feedback

1/(t

S+tCO

)

22.2 18.8 15.8 MHz

Maximum
Frequency
Internal Feedback
(f

CNT

)

1/(tS+tCO–10)

28.5 23.2 18.8 MHz

Maximum
Frequency
Pipelined Data

1/(t

CH+tCL

)

40.0 33.3 31.2 MHz

t

S

Input Setup Time 20 25 30 + 4 + 20 ns

t

H

Input Hold Time 0 0 0 ns

t

CH

Clock High Time Clo ck Input 1 5 15 16 ns

t

CL

Clock Low Time Clock Input 10 15 16 ns

t

CO

Clock to Output
Delay

Clock Input 25 28 33 – 6 ns

t

ARD

CPLD Array Delay Any macrocell 25 29 33 + 4 ns

t

MIN

Minimum Clock
Period

2

tCH+t

CL

25 29 32 ns

79/103

PSD8XXF2/3/4/5

Figure 39. Asynchronous Reset / Preset

Figure 40. Asynchronous Clock Mode Timing (product term clock)

tARP

REGISTER

OUTPUT

tARPW

RESET/PRESET

INPUT

AI02864

tCHA

tCLA

tCOA

tHAtSA

CLOCK

INPUT

REGISTERED

OUTPUT

AI02859

PSD8XXF2/3/4/5

80/103

Table 50. CPLD Macrocell Asynchron ou s Clock Mode Ti ming (5V devic es)

Symbol Parameter Conditions

-70 -90 -15

PT

Aloc

Turbo

Off

Slew

Rate

Unit

Min Max Min Max Min Max

f

MAXA

Maximum
Frequency
External
Feedback

1/(t

SA+tCOA

)

38.4 26.32 21.27 MHz

Maximum
Frequency
Internal
Feedback
(f

CNTA

)

1/(t

SA+tCOA

–10)

62.5 35.71 27.78 MHz

Maximum
Frequency
Pipelined
Data

1/(t

CHA+tCLA

)

71.4 41.67 35.71 MHz

t

SA

Input Setup
Time

7 8 12 + 2 + 10 ns

t

HA

Input Hold
Time

81214 ns

t

CHA

Clock Input
High Time

9 12 15 + 10 ns

t

CLA

Clock Input
Low Time

9 12 15 + 10 ns

t

COA

Clock to
Output Delay

21 30 37 + 10 – 2 ns

t

ARDA

CPLD Array
Delay

Any macrocell 11 16 22 + 2 ns

t

MINA

Minimum
Clock Period

1/f

CNTA

16 28 39 ns

81/103

PSD8XXF2/3/4/5

Table 51. CPLD Macrocell Asynchron ou s Clock Mode Ti ming (3V devic es)

Symbol Parameter Conditions

-12 -15 -20

PT

Aloc

Turbo

Off

Slew

Rate

Unit

Min Max Min Max Min Max

f

MAXA

Maximum
Frequency
External
Feedback

1/(t

SA+tCOA

)

21.7 19.2 16.9 MHz

Maximum
Frequency
Internal
Feedback
(f

CNTA

)

1/(t

SA+tCOA

–10)

27.8 23.8 20.4 MHz

Maximum
Frequency
Pipelined Data

1/(t

CHA+tCLA

)

33.3 27 24.4 MHz

t

SA

Input Setup
Time

10 12 13 + 4 + 20 ns

t

HA

Input Hold Time 12 15 17 ns

t

CHA

Clock High Time 17 22 25 + 20 ns

t

CLA

Clock Low Time 13 15 16 + 20 ns

t

COA

Clock to Output
Delay

36 40 46 + 20 – 6 ns

t

ARD

CPLD Array
Delay

Any macrocell 25 29 33 + 4 ns

t

MINA

Minimum Clock
Period

1/f

CNTA

36 42 49 ns

PSD8XXF2/3/4/5

82/103

Figure 41. Input Macrocell Timing (product term clock)

Table 52. Input Macrocell Timing (5V devices)

Note: 1. Inputs fro m Port A, B, an d C relative to register/ latch cloc k f rom the PLD. ALE / AS latch ti m i ngs refer to t

AVLX

and t

LXAX

.

Table 53. Input Macrocell Timing (3 V device s)

Note: 1. Inputs from Port A, B, and C relative to register/latch clock from the PLD. ALE latch timings refer to t

AVLX

and t

LXAX

.

Symbol Parameter Conditions

-70 -90 -15

PT

Aloc

Turbo

Off

Unit

Min Max Min Max Min Max

t

IS

Input Setup Time

(Note

1

)

000 ns

t

IH

Input Hold Time

(Note

1

)

15 20 26 + 10 ns

t

INH

NIB Input High Time

(Note

1

)

91218 ns

t

INL

NIB Input Low Time

(Note

1

)

91218 ns

t

INO

NIB Input to Combinatorial
Delay

(Note

1

)

34 46 59 + 2 + 10 ns

Symbol Parameter Conditions

-12 -15 -20

PT

Aloc

Turbo

Off

Unit

Min Max Min Max Min Max

t

IS

Input Setup Time

(Note

1

)

000 ns

t

IH

Input Hold Time

(Note

1

)

25 25 30 + 20 ns

t

INH

NIB Input High Time

(Note

1

)

12 13 15 ns

t

INL

NIB Input Low Time

(Note

1

)

12 13 15 ns

t

INO

NIB Input to Combinatorial
Delay

(Note

1

)

46 62 70 + 4 + 20 ns

t

INH

t

INL

t

INO

t

IH

t

IS

PT CLOCK

INPUT

OUTPUT

AI03101

83/103

PSD8XXF2/3/4/5

Figure 42. READ Timing

Note: 1. t

AVLX

and t

LXAX

are not required for 80C251 in Page Mode or 80C51XA in Burst Mode.

t

AVLX

t

LXAX

1

t

LVLX

t

AVQV

t

SLQV

t

RLQV

t

RHQX

tRHQZ

t

ELTL

t

EHEL

t

RLRH

t

THEH

t

AVPV

ADDRESS

VALID

ADDRESS

VALID

DATA

VALID

DATA

VALID

ADDRESS OUT

ALE/AS

A/D

MULTIPLEXED

BUS

ADDRESS

NON-MULTIPLEXED

BUS

DATA

NON-MULTIPLEXED

BUS

CSI

RD

(PSEN, DS)

E

R/W

AI02895

PSD8XXF2/3/4/5

84/103

Table 54. READ Timing (5V devices)

Note: 1. RD timing has the same timing as DS, LDS, UDS, and PSEN signals.

2. RD

and PSEN have the same timing.

3. Any input used to select an internal PSD8XXFX function.

4. In multiplexed mod e, latched add resses gen erated from A DI O delay to address output on any Port.

5. RD

timing has the sam e timin g as DS, LDS, and UDS signals.

Symbol Parameter Conditions

-70 -90 -15

Turbo

Off

Unit

Min Max Min Max Min Max

t

LVLX

ALE or AS Pulse Width 15 20 28 ns

t

AVLX

Address Setup Time

(Note

3

)

4 6 10 ns

t

LXAX

Address Hold Time

(Note

3

)

7811 ns

t

AVQV

Address Valid to Data Valid

(Note

3

)

70 90 150 + 10 ns

t

SLQV

CS Valid to Data Valid 75 100 150 ns

t

RLQV

RD to Data Valid 8-Bit Bus

(Note

5

)

24 32 40 ns

RD

or PSEN to Data Valid

8-Bit Bus, 8031, 80251

(Note

2

)

31 38 45 ns

t

RHQX

RD Data Hold Time

(Note

1

)

000 ns

t

RLRH

RD Pulse Width

(Note

1

)

27 32 38 ns

t

RHQZ

RD to Data High-Z

(Note

1

)

20 25 30 ns

t

EHEL

E Pulse Width 27 32 38 ns

t

THEH

R/W Setup Time to Enable 6 10 18 ns

t

ELTL

R/W Hold Time After Enable 0 0 0 ns

t

AVPV

Address Input Valid to
Address Output Delay

(Note

4

)

20 25 30 ns

85/103

PSD8XXF2/3/4/5

Table 55. READ Timing (3V devices)

Note: 1. RD timing has the same timing as DS, LDS, UDS, and PSEN signals.

2. RD

and PSEN have the same timing for 8031.

3. Any input used to select an internal PSD8XXFX function.

4. In multiplexed mode latched address generated from ADIO delay to address output on any Port.

5. RD

timing has the sam e timin g as DS, LDS, and UDS signals.

Symbol Parameter Conditions

-12 -15 -20

Turbo

Off

Unit

Min Max Min Max Min Max

t

LVLX

ALE or AS Pulse Width 26 26 30 ns

t

AVLX

Address Setup Time

(Note

3

)

91012 ns

t

LXAX

Address Hold Time

(Note

3

)

91214 ns

t

AVQV

Address Valid to Data Valid

(Note

3

)

120 150 200 + 20 ns

t

SLQV

CS Valid to Data Valid 120 150 200 ns

t

RLQV

RD to Data Valid 8-Bit Bus

(Note

5

)

35 35 40 ns

RD

or PSEN to Data Valid 8-Bit Bus,

8031, 80251

(Note

2

)

45 50 55 ns

t

RHQX

RD Data Hold Time

(Note

1

)

000 ns

t

RLRH

RD Pulse Width 38 40 45 ns

t

RHQZ

RD to Data High-Z

(Note

1

)

38 40 45 ns

t

EHEL

E Pulse Width 40 45 52 ns

t

THEH

R/W Setup Time to Enable 15 18 20 ns

t

ELTL

R/W Hold Time After Enable 0 0 0 ns

t

AVPV

Address Input Valid to
Address Output Delay

(Note

4

)

33 35 40 ns

PSD8XXF2/3/4/5

86/103

Figure 43. WRITE Timing

t

AVLX

t

LXAX

t

LVLX

t

AVWL

t

SLWL

t

WHDX

t

WHAX

t

ELTL

t

EHEL

t

WLMV

t

WLWH

t

DVWH

t

THEH

t

AVPV

ADDRESS

VALID

ADDRESS

VALID

DATA
VALID

DATA
VALID

ADDRESS OUT

t

WHPV

STANDARD

MCU I/O OUT

ALE/AS

A/D

MULTIPLEXED

BUS

ADDRESS

NON-MULTIPLEXED

BUS

DATA

NON-MULTIPLEXED

BUS

CSI

WR

(DS)

E

R/ W

AI02896

87/103

PSD8XXF2/3/4/5

Table 56. WRITE Timing (5V devices)

Note: 1. Any input used to select an internal PSD8XXFX function.

2. In multiplexed mod e, latched add ress generated from ADI O delay to address output on any port.

3. WR

has th e same tim i ng as E, LD S , UDS, WRL, and WRH signals.

4. Assuming data is stable before active WRITE signal.

5. Assuming WRITE is active before data becomes valid.

6. TWHAX2 is the address hold time for DPLD inputs that are used to generate Sector Select signals for internal PSD8XXFX memory.

Symbol Parameter Conditions

-70 -90 -15
Unit

Min Max Min Max Min Max

t

LVLX

ALE or AS Pulse Width 15 20 28 ns

t

AVLX

Address Setup Time

(Note

1

)

4 6 10 ns

t

LXAX

Address Hold Time

(Note

1

)

7811ns

t

AVWL

Address Valid to Leading
Edge of WR

(Notes

1,3

)

81520ns

t

SLWL

CS Valid to Leading Edge of WR

(Note 3)

12 15 20 ns

t

DVWH

WR Data Setup Time

(Note

3

)

25 35 45 ns

t

WHDX

WR Data Hold Time

(Note

3

)

455ns

t

WLWH

WR Pulse Width

(Note

3

)

31 35 45 ns

t

WHAX1

Trailing Edge of WR to Address Invalid

(Note

3

)

6 8 10 ns

t

WHAX2

Trailing Edge of WR to DPLD Address
Invalid

(Note

3,6

)

000ns

t

WHPV

Trailing Edge of WR to Port Output
Valid Using I/O Port Data Register

(Note

3

)

27 30 38 ns

t

DVMV

Data Valid to Port Output Valid
Using Macrocell Regist er
Preset/Clea r

(Notes

3,5

)

42 55 65 ns

t

AVPV

Address Input Valid to Address
Output Delay

(Note

2

)

20 25 30 ns

t

WLMV

WR Valid to Port Output Valid Using
Macrocell Register Preset/Clear

(Notes

3,4

)

48 55 65 ns

PSD8XXF2/3/4/5

88/103

Table 57. WRITE Timing (3V devices)

Note: 1. Any input used to select an internal PSD8XXFX function.

2. In multiplexed mod e, latched add ress generated from ADI O delay to address output on any port.

3. WR

has th e same tim i ng as E, LD S , UDS, WRL, and WRH signals.

4. Assuming data is stable before active WRITE signal.

5. Assuming WRITE is active before data becomes valid.

6. TWHAX2 is the address hold time for DPLD inputs that are used to generate Sector Select signals for internal PSD8XXFX memory.

Symbol Parameter Conditions

-12 -15 -20
Unit

Min Max Min Max Min Max

t

LVLX

ALE or AS Pulse Width 26 26 30

t

AVLX

Address Setup Time

(Note

1

)

91012ns

t

LXAX

Address Hold Time

(Note

1

)

91214ns

t

AVWL

Address Valid to Leading
Edge of WR

(Notes

1,3

)

17 20 25 ns

t

SLWL

CS Valid to Leading Edge of WR

(Note 3)

17 20 25 ns

t

DVWH

WR Data Setup Time

(Note

3

)

45 45 50 ns

t

WHDX

WR Data Hold Time

(Note

3

)

7 8 10 ns

t

WLWH

WR Pulse Width

(Note

3

)

46 48 53 ns

t

WHAX1

Trailing Edge of WR to Address Invalid

(Note

3

)

10 12 17 ns

t

WHAX2

Trailing Edge of WR to DPLD Address
Invalid

(Note

3,6

)

000ns

t

WHPV

Trailing Edge of WR to Port Output
Valid Using I/O Port Data Register

(Note

3

)

33 35 40 ns

t

DVMV

Data Valid to Port Output Valid
Using Macrocell Register Preset/Clear

(Notes

3,5

)

70 70 80 ns

t

AVPV

Address Input Valid to Address
Output Delay

(Note

2

)

33 35 40 ns

t

WLMV

WR Valid to Port Output Valid Using
Macrocell Register Preset/Clear

(Notes

3,4

)

70 70 80 ns

89/103

PSD8XXF2/3/4/5

Table 58. Program, WRITE and Erase Times (5V devices)

Note: 1. Programmed to all zero before erase.

2. The poll i ng status, DQ7, is valid tQ7VQV time uni ts before the data byte, DQ 0-DQ7, is vali d for reading.

Table 59. Program, WRITE and Erase Times (3V devices)

Note: 1. Programmed to all zero before erase.

2. The poll i ng status, DQ7, is valid tQ7VQV time uni ts before the data byte, DQ 0-DQ7, is vali d for reading.

Symbol Parameter Min. Typ. Max. Unit

Flash Program 8.5 s
Flash Bulk Erase

1

(pre-programmed)

330s

Flash Bulk Erase (not pre-program med ) 5 s

t

WHQV3

Sector Erase (pre-programmed) 1 30 s

t

WHQV2

Sector Erase (not pre-programmed) 2.2 s

t

WHQV1

Byte Program 14 1200 µs
Program / Erase Cycles (per Sector) 100,000 cycles

t

WHWLO

Sector Erase Time-Out 100 µs

t

Q7VQV

DQ7 Valid to Output (DQ7-DQ0) Valid (Data Polling)

2

30 ns

Symbol Parameter Min. Typ. Max. Unit

Flash Program 8.5 s
Flash Bulk Erase

1

(pre-programmed)

330s

Flash Bulk Erase (not pre-program med ) 5 s

t

WHQV3

Sector Erase (pre-programmed) 1 30 s

t

WHQV2

Sector Erase (not pre-programmed) 2.2 s

t

WHQV1

Byte Program 14 1200 µs
Program / Erase Cycles (per Sector) 100,000 cycles

t

WHWLO

Sector Erase Time-Out 100 µs

t

Q7VQV

DQ7 Valid to Output (DQ7-DQ0) Valid (Data Polling)

2

30 ns

PSD8XXF2/3/4/5

90/103

Figure 44. Peripheral I/O READ Timing

Table 60. Port A Peripheral Data Mode READ Timing (5V devices)

Symbol Parameter Conditions

-70 -90 -15

Turbo

Off

Unit

Min Max Min Max Min Max

t

AVQV–PA

Address Valid to Data
Valid

(Note

3

)

37 39 45 + 10 ns

t

SLQV–PA

CSI Valid to Data Valid 27 35 45 + 10 ns

t

RLQV–PA

RD to Data Valid

(Notes

1,4

)

21 32 40 ns

RD

to Data Valid 8031 Mode 32 38 45 ns

t

DVQV–PA

Data In to Data Out Valid 22 30 38 ns

t

QXRH–PA

RD Data Hold Time 0 0 0 ns

t

RLRH–PA

RD Pulse Width

(Note

1

)

27 32 38 ns

t

RHQZ–PA

RD to Data High-Z

(Note

1

)

23 25 30 ns

t

QXRH

(PA)

t

RLQV

(PA)

t

RLRH

(PA)

t

DVQV

(PA)

t

RHQZ

(PA)

t

SLQV

(PA)

t

AVQV

(PA)

ADDRESS DATA VALID

ALE/AS

A/D BUS

RD

DATA ON PORT A

CSI

AI02897

91/103

PSD8XXF2/3/4/5

Table 61. Port A Peripheral Data Mode READ Timing (3V devices)

Symbol Parameter Conditions

-12 -15 -20

Turbo

Off

Unit

Min Max Min Max Min Max

t

AVQV–PA

Address Valid to Data Valid

(Note

3

)

50 50 50 + 20 ns

t

SLQV–PA

CSI Valid to Data Valid 37 45 50 + 20 ns

t

RLQV–PA

RD to Data Valid

(Notes

1,4

)

37 40 45 ns

RD

to Data Valid 8031 Mode 45 45 50 ns

t

DVQV–PA

Data In to Data Out Valid 38 40 45 ns

t

QXRH–PA

RD Data Hold Time 0 0 0 ns

t

RLRH–PA

RD Pulse Width

(Note

1

)

36 36 46 ns

t

RHQZ–PA

RD to Data High-Z

(Note

1

)

36 40 45 ns

PSD8XXF2/3/4/5

92/103

Figure 45. Peripheral I/O WRITE Timing

Table 62. Port A Peripheral Data Mode WRITE Timing (5V devices)

Note: 1. RD has the sam e t i m i n g as DS, LDS, UDS, and PSEN (in 8031 combined mode).

2. WR

has the same timing as the E, LDS, UDS, WRL, and WRH signals.

3. Any input used to select Port A Data Peripheral mode.

4. Data is al ready stab le on P o rt A.

5. Data stable on ADIO pins to data on Port A.

Table 63. Port A Peripheral Data Mode WRITE Timing (3V devices)

Note: 1. RD has the sam e t i m i n g as DS, LDS, UDS, and PSEN (in 8031 combined mode).

2. WR

has the same timing as the E, LDS, UDS, WRL, and WRH signals.

3. Any input used to select Port A Data Peripheral mode.

4. Data is al ready stab le on P o rt A.

5. Data stable on ADIO pins to data on Port A.

Symbol Parameter Conditions

-70 -90 -15
Unit

Min Max Min Max Min Max

t

WLQV–PA

WR to Data Propagation Delay

(Note

2

)

25 35 40 ns

t

DVQV–PA

Data to Port A Data Propagation Delay

(Note

5

)

22 30 38 ns

t

WHQZ–PA

WR Invalid to Port A Tri-state

(Note

2

)

20 25 33 ns

Symbol Parameter Conditions

-12 -15 -20
Unit

Min Max Min Max Min Max

t

WLQV–PA

WR to Data Propagation Delay

(Note

2

)

42 45 55 ns

t

DVQV–PA

Data to Port A Data Propagation Delay

(Note

5

)

38 40 45 ns

t

WHQZ–PA

WR Invalid to Port A Tri-state

(Note

2

)

33 33 35 ns

tDVQV (PA)

tWLQV (PA)

tWHQZ (PA)

ADDRESS DATA OUT

A/D BUS

WR

PORT A

DATA OUT

ALE/AS

AI02898

93/103

PSD8XXF2/3/4/5

Figure 46. Reset (RESET) Timing

Table 64. Reset (RESET

) Timing (5V devices)

Note: 1. Reset (R E SE T ) does not re set Flash memory Program or Erase cyc l es.

2. Warm res et aborts Flas h m emory Program or Eras e cy cles, and put s the device in READ Mode.

Table 65. Reset (RESET) Timing (3V devices)

Note: 1. Reset (R E SE T ) does not re set Flash memory Program or Erase cyc l es.

2. Warm res et aborts Flas h m emory Program or Eras e cy cles, and put s the device in READ Mode.

Table 66. V

STBYON

Timing (5V devices)

Note: 1. V

STBYON

timing is measured at VCC ramp rate of 2 ms.

Table 67. V

STBYON

Timing (3V devices)

Note: 1. V

STBYON

timing is measured at VCC ramp rate of 2 ms.

Symbol Parameter Conditions Min Max Unit

t

NLNH

RESET Active Low Time

1

150 ns

t

NLNH–PO

Power On Reset Active Low Time 1 ms

t

NLNH–A

Warm Reset (on the PSD834Fx)

2

25 µs

t

OPR

RESET High to Operational Device 120 ns

Symbol Parameter Conditions Min Max Unit

t

NLNH

RESET Active Low Time

1

300 ns

t

NLNH–PO

Power On Reset Active Low Time 1 ms

t

NLNH–A

Warm Reset (on the PSD834Fx)

2

25 µs

t

OPR

RESET High to Operational Device 300 ns

Symbol Parameter Conditions Min Typ Max Unit

t

BVBH

V

STBY

Detection to V

STBYON

Output High

(Note

1

)

20 µs

t

BXBL

V

STBY

Off Detection to V

STBYON

Output

Low

(Note 1)

20 µs

Symbol Parameter Conditions Min Typ Max Unit

t

BVBH

V

STBY

Detection to V

STBYON

Output High

(Note

1

)

20 µs

t

BXBL

V

STBY

Off Detection to V

STBYON

Output

Low

(Note 1)

20 µs

t

NLNH-PO

t

OPR

AI02866b

RESET

t

NLNH

t

NLNH-A

t

OPR

V

CC

VCC(min)

Power-On Reset

Warm Reset

PSD8XXF2/3/4/5

94/103

Figure 47. ISC Timing

Table 68. ISC Timing (5V devices)

Note: 1. For non-PLD Progra m ming, Erase or in ISC by- pass mode.

2. For Program or Erase PLD only.

Symbol Parameter Conditions

-70 -90 -15
Unit

Min Max Min Max Min Max

t

ISCCF

Clock (TCK, PC1) Frequency (except for
PLD)

(Note

1

)

20 18 14 MHz

t

ISCCH

Clock (TCK, PC1) High Time (except for
PLD)

(Note

1

)

23 26 31 ns

t

ISCCL

Clock (TCK, PC1) Low Time (except for
PLD)

(Note

1

)

23 26 31 ns

t

ISCCFP

Clock (TCK, PC1) Frequency (PLD only)

(Note

2

)

2 2 2 MHz

t

ISCCHP

Clock (TCK, PC1) High Time (PLD only)

(Note

2

)

240 240 240 ns

t

ISCCLP

Clock (TCK, PC1) Low Time (PLD only)

(Note

2

)

240 240 240 ns

t

ISCPSU

ISC Port Set Up Time 7 8 10 ns

t

ISCPH

ISC Port Hold Up Time 5 5 5 ns

t

ISCPCO

ISC Port Clock to Output 21 23 25 ns

t

ISCPZV

ISC Port High-Impedance to Valid Output 21 23 25 ns

t

ISCPVZ

ISC Port Valid Output to
High-Impedance

21 23 25 ns

ISCCH

TCK

TDI/TMS

ISC OUTPUTS/TDO

ISC OUTPUTS/TDO

t

ISCCL

t

ISCPH

t

ISCPSU

t

ISCPVZ

t

ISCPZV

t

ISCPCO

t

AI02865

95/103

PSD8XXF2/3/4/5

Table 69. ISC Timing (3V devices)

Note: 1. For non-PLD Progra m ming, Erase or in ISC by- pass mode.

2. For Program or Erase PLD only.

Table 70. Power-down Timing (5V devic es)

Note: 1. t

CLCL

is the period of CLKIN (P D1).

Table 71. Power-down Timing (3V devic es)

Note: 1. t

CLCL

is the period of CLKIN (P D1).

Symbol Parameter Conditions

-12 -15 -20
Unit

Min Max Min Max Min Max

t

ISCCF

Clock (TCK, PC1) Frequency (except for
PLD)

(Note

1

)

12 10 9 MHz

t

ISCCH

Clock (TCK, PC1) High Time (except for
PLD)

(Note

1

)

40 45 51 ns

t

ISCCL

Clock (TCK, PC1) Low Time (except for
PLD)

(Note

1

)

40 45 51 ns

t

ISCCFP

Clock (TCK, PC1) Frequency (PLD only)

(Note

2

)

2 2 2 MHz

t

ISCCHP

Clock (TCK, PC1) High Time (PLD only)

(Note

2

)

240 240 240 ns

t

ISCCLP

Clock (TCK, PC1) Low Time (PLD only)

(Note

2

)

240 240 240 ns

t

ISCPSU

ISC Port Set Up Time 12 13 15 ns

t

ISCPH

ISC Port Hold Up Time 5 5 5 ns

t

ISCPCO

ISC Port Clock to Output 30 36 40 ns

t

ISCPZV

ISC Port High-Impedance to Valid Output 30 36 40 ns

t

ISCPVZ

ISC Port Valid Output to
High-Impedance

30 36 40 ns

Symbol Parameter Conditions

-70 -90 -15
Unit

Min Max Min Max Min Max

t

LVDV

ALE Access Time from Power-down 80 90 150 ns

t

CLWH

Maximum Delay from
APD Enable to Internal PDN Valid
Signal

Using CLKIN

(PD1)

15 * t

CLCL

1

µs

Symbol Parameter Conditions

-12 -15 -20
Unit

Min Max Min Max Min Max

t

LVDV

ALE Access Time from Power-down 145 150 200 ns

t

CLWH

Maximum Delay from APD Enable to
Internal PDN Valid Signal

Using CLKIN

(PD1)

15 * t

CLCL

1

µs

PSD8XXF2/3/4/5

96/103

PACKAGE MECHANICAL

Figure 48. PQFP52 Connections Figure 49. PLCC52 Connections

Figure 50. PQFP52 - 52-pin Plastic, Quad, Flat Package Mech anical Drawing

Note: Drawing is not to scale.

39 AD15
38 AD14
37 AD13
36 AD12
35 AD11
34 AD10
33 AD9
32 AD8
31 V

CC

30 AD7
29 AD6
28 AD5
27 AD4

PD2
PD1
PD0
PC7
PC6
PC5
PC4
V

CC

GND
PC3
PC2
PC1
PC0

1
2
3
4
5
6
7
8
9
10
11
12
13

52515049484746454443424140

PB0

PB1

PB2

PB3

PB4

PB5

GND

PB6

PB7

CNTL1

CNTL2

RESET

CNTLO

14151617181920212223242526

PA7

PA6

PA5

PA4

PA3

GND

PA2

PA1

PA0

AD0

AD1

AD2

AD3

AI02858

PB0

PB1

PB2

PB3

PB4

PB5

GND

PB6

PB7

CNTL1

CNTL2

RESET

CNTL0

PA7

PA6

PA5

PA4

PA3

GND

PA2

PA1

PA0

AD0

AD1

AD2

AD3

AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
V

CC

AD7
AD6

AD5

AD4

PD2
PD1
PD0
PC7
PC6
PC5
PC4

V

CC

GND

PC3
PC2
PC1
PC0

8
9
10
11
12
13
14
15
16
17
18
19
20

46
45
44
43
42
41
40
39
38
37
36
35
34

21222324252627282930313233

47

48

49

50

51

52

1

2

3

4

5

6

7

AI02857

QFP-A

Nd

E1

CP

b

e

A2

A

N

LA1 α

D1

D

1

E

Ne

c

D2

E2

L1

97/103

PSD8XXF2/3/4/5

Table 72. PQFP52 - 52-pin Plastic, Quad, Flat Package Mechanical Dimensions

Symb.

mm inches

T yp. Min. Max. T yp. Min. Max.

A 2.35 0.093
A1 0.25 0.010
A2 2.00 1.80 2.10 0.079 0.077 0.083

b 0.22 0.38 0.009 0.015

c 0.11 0.23 0.004 0.009

D 13.20 13.15 13.25 0.520 0.518 0.522
D1 10.00 9.95 10.05 0.394 0.392 0.396
D2 7.80 – – 0.307 – –

E 13.20 13.15 13.25 0.520 0.518 0.522
E1 10.00 9.95 10.05 0.394 0.392 0.396
E2 7.80 – – 0.307 – –

e 0.65 – – 0.026

L 0.88 0.73 1.03 0.035 0.029 0.041
L1 1.60 – – 0.063

α 0° 7° 0° 7°

N52 52
Nd 13 13
Ne 13 13
CP 0.10 0.004

PSD8XXF2/3/4/5

98/103

Figure 51. PLCC52 - 52-lead Plastic Lead, Chip Carrier Package Mechanical Drawing

Note: Drawing is not to scale.

Table 73. PLCC52 - 52-lead Plastic Lead, Chip Carrier Package Mechanical Dimensions

Symbol

mm inches

T yp. Min. Max. Typ. Min. Max.

A 4.19 4.57 0.165 0.180
A1 2.54 2.79 0.100 0.110
A2 – 0.91 – 0.036

B 0.33 0.53 0.013 0.021
B1 0.66 0.81 0.026 0.032

C 0.246 0.261 0.0097 0.0103

D 19.94 20.19 0.785 0.795

D1 19.05 19.15 0.750 0.754
D2 17.53 18.54 0.690 0.730

E 19.94 20.19 0.785 0.795

E1 19.05 19.15 0.750 0.754
E2 17.53 18.54 0.690 0.730

e 1.27 – – 0.050 – –
R 0.89 – – 0.035 – –
N52 52

Nd 13 13
Ne 13 13

PLCC-B

D

E1 E

1 N

D1

CP

b

D2/E2

e

b1

A1

A

A2

D3/E3

M

L1

L

C

M1

99/103

PSD8XXF2/3/4/5

PART NUMBERING

Table 74. Ordering Information Scheme

For a list of available options (e.g., speed, package) or for further information on any aspect of this device,
please contact your nearest ST Sales Office.

Example: PSD8 1 3 F 2 V – 15 J 1 T

Device Type

PSD8 = 8-bit PSD with Register Logic
PSD9 = 8-bit PSD with Combinatorial Logic

SRAM Capacity

1 = 16 Kbit
3 = 64 Kbit
5 = 256 Kbit

Flash Memory Capacity

3 = 1 Mbit (128K x 8)
4 = 2 Mbit (256K x 8)

2nd Flash Memory

2 = 256 Kbit Flash memory + SRAM
3 = SRAM but no Flash memory
4 = 256 Kbit Flash memory but no SRAM
5 = no Flash memory + no SRAM

Operating Voltage

blank = V

CC

= 4.5 to 5.5V

V = V

CC

= 3.0 to 3.6V

Speed

70 = 70ns
90 = 90ns
12 = 120ns
15 = 150ns
20 = 200ns

Package

J = PLCC52
M = PQFP52

Temperature Rang e

blank = 0 to 70°C (commercial)
I = –40 to 85°C (industrial)

Option

T = Tape & Reel Packing

PSD8XXF2/3/4/5

100/103

APPENDIX A. PQFP52 PIN ASSIGNMENTS

Table 75. PQFP52 Connections (Figure 48)

Pin Number Pin Assignments

1 PD2
2 PD1
3 PD0
4 PC7
5 PC6
6 PC5
7 PC4
8

V

CC

9 GND
10 PC3
11 PC2
12 PC1
13 PC0
14 PA7
15 PA6
16 PA5
17 PA4
18 PA3
19 GND
20 PA2
21 PA1
22 PA0
23 AD0
24 AD1
25 AD2
26 AD3

Pin Number Pin Assignments

27 AD4
28 AD5
29 AD6
30 AD7
31

V

CC

32 AD8
33

AD9

34 AD10
35 AD11
36 AD12
37 AD13
38 AD14
39 AD15
40 CNTL0
41 RESET
42 CNTL2
43 CNTL1
44 PB7
45 PB6
46 GND
47 PB5
48 PB4
49 PB3
50 PB2
51 PB1
52 PB0