Page 1
1
PS8462 02/22/00
Features
• Low On-Resistance (100Ω typ.)
Minimizes Distortion and Error Voltages
• Single Supply Operation (±2.7V to ±8V)
• Improved Second Source for MAX395
• SPI/QSI, Microwire-Compatible Serial Interface
• Split-Supply Operation (+3V to +8V)
• On-Resistance Flatness: 10Ω Max.
• On-Resistance Matching Between Channels: 5Ω Max.
• TTL/CMOS Logic Compatible (w/+5V or ±5V supplies)
• Fast Switching Speed
• Break-Before-Make action eliminates momentary crosstalk
• Rail-to-Rail Analog Signal Range
• Low Power Consumption
• Narrow SOIC and QSOP Packages Minimize Board Area
• Asynchonous Reset (RS) Input
Applications
• Data Acquisition Systems
• Audio Switching and Routing
• Test Equipment
• PBX, PABX
• Telecommunication Systems
• Battery-Powered Systems
Description
The PS395 eight-channel, serially controlled, single-pole/singlethrow (SPST) analog switch offers eight separately controlled
switches that conduct equally well in either direction. ON-resistance (100Ω max.) is matched between switches to 5Ω max. and is
flat (10Ω max.) over the specified signal range.
These CMOS devices can operate continuously with dual power
supplies ranging from ±2.7V to ±8V or a single supply between
+2.7V and +16V. Each switch can handle rail-to-rail analog signals.
The off leakage current is only 0.1nA at +25°C or 5nA at +85°C.
Upon power-up, all switches are off, and the internal shift registers
are reset to zero. The PS395 is electrically equivalent to two PS391
quad switches controlled by a serial interface, and is pin compatible with the PS335.
The serial interface is compatible with SPI/QSPI and
Microwire. Functioning as a shift register, it allows data (at DIN)
to be clocked-in synchronously with the rising edge of clock
(SCLK). The shift registers output (DOUT) enables several PS395s
to be daisy chained.
All digital inputs have 0.8V to 2.4V logic thresholds, ensuring both
TTL- and CMOS-logic compatibility when using ±5V supplies or a
single +5V supply.
Pin Configurations
emaNnoitcnuF
KLCtupnIlatigiDkcolClaireS
+VtupnIegatloVylppuSgolanAevitisoP
ATAD
NI
tupnIlatigiDataDlaireS
DNGdnuorG
ON
0
ON
7
70sehctiwSgolanAnepOyllamroN
MOC
0
MOC
7
70sehctiwSgolanAnommoC
VtupnIegatloVylppuSgolanAevitageN
ATAD
TUO
tuptuOlatigiDataDlaireS
SRtupnIteseR
)TESER(
SCtupnIlatigiDtceleS-pihC
Pin Description
Note:
NO and COM pins are identical and interchangeble. Either may
be considered as an input or an output; signals pass equally
well in either direction.
PS395
Precision 8-Ch. 17V, SPST Switch
w/8-Bit Serial Decoded Control
16
15
14
13
8
1
2
3
4
5
6
7
9
10
11
12
17
24
23
22
21
20
19
18
CLK
V+
DATA
IN
GND
NO
0
COM
0
NO
1
COM
1
NO
2
COM
2
NO
3
COM
3
DIP/SO
EN
RS
DATA
OUT
V–
NO
7
COM
7
NO
6
COM
6
NO
5
COM
5
NO
4
COM
4
8-Bit
Decoding
Logic
SPI & QSPI are trademarks of Motorola, Inc. Microwire is a trademark
of National Semiconductor Corporation
Top View
PS395
Page 2
2
PS8462 02/22/00
PS395
Precision 8-Ch. 17V, SPST Switch
w/8-Bit Serial Decoded Control
Serial-Interface Truth Table
SR
stiBataD
noitcnuF
7D6D5D4D3D2D1D0D
0XXXXXXXX 0=0D–7D,neposehctiwsllA
10XXXXXXXSsehctiw7 )ffo(nepo
11XXXXXXX )no(desolc7sehctiwS
1X0XXXXXX )ffo(nepo6sehctiwS
1X1XXXXXX )no(desolc6sehctiwS
10X0XXXXX )ffo(nepo5sehctiwS
11X1XXXXX )no(desolc5sehctiwS
1XXX0XXXX )ffo(nepo4sehctiwS
1XXX1XXXX )no(desolc4sehctiwS
1XXXX0XXX )ffo(nepo3sehctiwS
1XXXX1XXX )no(desolc3sehctiwS
1XXXXX0XX )ffo(nepo2sehctiwS
1XXXXX1XX )no(desolc2sehctiwS
1XXXXXX0X )ffo(nepo1sehctiwS
1XXXXXX1X )no(desolc1sehctiwS
1XXXXXXX0 )ffo(nepo0sehctiwS
1XXXXXXX1 )no(desolc0sehctiwS
SPDT Truth Table
SR
stiBataD
noitcnuF
7D6D5D4D3D2D1D0D
0XXXXXXXX 0=0D–7D,neposehctiwsllA
101XXXXXX no6dnaffo7hctiwS
110XXXXXX no7dnaffo6hctiwS
1XX01XXXX no4dnaffo5hctiwS
1XX10XXXX no5dnaffo4hctiwS
1XXXX01XX no2dnaffo3hctiwS
1XXXX10XX no3dnaffo2hctiwS
1XXXXXX01 no0dnaffo1hctiwS
1XXXXXX10 no1dnaffo0hctiwS
Page 3
3
PS8462 02/22/00
PS395
Precision 8-Ch. 17V, SPST Switch
w/8-Bit Serial Decoded Control
Absolute Maximum Ratings
Voltages Referenced to GND
V+ ................................................................................ 0.3V, +17V
V ................................................................................ 17V, +0.3V
V+ to V- ........................................................................ -0.3V, +17V
SCLK, CS, DIN, DOUT, RESET ...................... -0.3V to (V+ + 0.3V)
NO, COM ..................................................... (V- - 2V) to (V+ + 2V)
Continuous Current into Any Terminal ............................. ±30mA
Peak Current, NO_ or COM_
(pulsed at 1ms,10% duty cycle) ....................................... ±100mA
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Continuous Power Dissipation (TA = +70°C)
Narrow Plastic DIP (derate 13.33mW/°C above +70°C) ...... 1067mW
Wide SO (derate 11.76mW/°C above +70°C) .....................941mW
Operating Temperature Ranges
PS395C_ G ................................................................ 0°C to +70°C
PS395E_ G .............................................................. -40°C to +85°C
Storage Temperature Range ................................ -65°C to +150°C
Lead Temperature (soldering, 10s) .................................... +300°C
retemaraPlobmySsnoitidnoC.niM
)2(
.pyT
)1(
.xaM
)2(
stinU
hctiwSgolanA
egnaRlangiSgolanA
)3(
V
,MOC
V
ON
E,CV+VV
ecnatsiseRnOON,MOCR
NO
,V5=V,V5=+V
V
MOC
I,V3±=
ON
Am1=
T
A
V52+=06001
Ω
E,C521
hctaMecnatsiseRnOON,MOC
slennahCneewteB
)2(
∆R
NO
,V5=V,V5=+V
V
MOC
I,V3±=
ON
Am1=
T
A
V52+=5
E,C01
ecnatsiseRnOON,MOC
ssentalF
)2(
R
)NO(TALF
I,V5=V,V5=+V
ON
Am1=
V
MOC
V3,V0,V3=
T
A
V52+=01
E,C51
tnerruCegakaeLffOON
)3(
I
)FFO(ON
,V5.5=V,V5.5=+V
V
MOC
V,V5.4=
ON
V5.4=
T
A
V52+=1.0200.01.0
An
E,C0.101
,V5.5=V,V5.5=+V
V
MOC
V,V5.4=
ON
V5.4=
T
A
V52+=1.0200.01.0
E,C0101
tnerruCegakaeLffOMOC
)3(
I
)FFO(MOC
,V5.5=V,V5.5=+V
V
MOC
V,V5.4=
ON
V5.4=
T
A
V52+=1.0200.01.0
E,C0.101
,V5.5=V,V5.5=+V
V
MOC
V,V5.4=
ON
V5.4=
T
A
V52+=1.0200.01.0
E,C0101
tnerruCegakaeLnOMOC
)3(
I
)NO(MOC
,V5.5=V,V5.5=+V
V
MOC
V=
ON
V5.4±=
T
A
V52+=2.010.02.0
E,C0202
O/IlatigiD
tupnITESER,SC,KLCS,NID
hgiHdlohserhTcigoLegatloV
V
HI
E,C
4.2
V
tupnITESER,SC,KLCS,NID
hgiHdlohserhTcigoLegatloV
V
LI
8.0
tupnITESER,SC,KLCS,NID
woLrohgiHcigoLtnerruC
I
HII,LI
V
NID
V,
KLCS
V,
SC
V4.2roV8.0=130.01
µA
hgiHcigoLegatloVtuptuOTUODV
TUOD
I
TUOD
Am8.0=8.2+V
V
woLcigoLegatloVtuptuOTUODV
TUOD
I
TUOD
Am6.1=04.0
siseretsyHtupnIKLCSKLCS
TSYH
001Vm
Electrical Specifications - Dual Supplies
(V± = +4.5V to +5.5V, V = 4.5V to 5.5V, TA= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at TA = +25°C.)
Page 4
4
PS8462 02/22/00
PS395
Precision 8-Ch. 17V, SPST Switch
w/8-Bit Serial Decoded Control
retemaraPlobmySsnoitidnoC.niM
)2(
.pyT
)1(
.xaM
)2(
stinU
scitsiretcarahCcimanyDhctiwS
emiTnO-nruTt
NO
SCfoegdegnisirmorF
T
A
V52+=002004
nσ
E,C005
emiTffO-nruTt
FFO
T
A
V52+=09004
E,C005
yaleDekaM-erofeB-kaerBt
MBB
T
A
V52+=551
noitcejnIegrahC
)4(
V
ETC
C
L
V,Fn1=
ON
R,V0=
S
0= Ω T
A
V52+=201Cp
ecnaticapaCffOONC
)FFO(ON
V
ON
=f,DNG=zHM1E,C2
FpecnaticapaCffOMOCC
)FFO(MOC
V
MOC
=f,DNG=zHM1T
A
V52+=251
ecnaticapaCffOhctiwSC
)NO(
V
MOC
V=
=ON
=f,DNGzHM1E,C8
noitalosIffOV
OSI
RL05= Ω C,
L
,Fp51=
V
ON
V1=
SMR
zHk001=f,
T
A
V52+=09
Bd
klatssorClennahC-ot-lennahCV
TC
RL05= Ω C,
L
,Fp51=
V
ON
V1=
SMR
zHk001=f,
E,C09<
ylppuSrewoP
egnaRylppuS-rewoPV,+VE,C3±8±V
tnerruCylppuS+V+I
,+VroV0=KLCS=SC=NID
+VroV0=TESER
T
A
V52+=702
µA
E,C03
tnerruCylppuSVI
,+VroV0=KLCS=SC=NID
+VroV0=TESER
T
A
V52+=11.01
E,C22
Electrical Specifications - Dual Supplies (continued)
(V± = +4.5V to +5.5V, V = 4.5V to 5.5V, TA= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at TA = +25°C.)
Page 5
5
PS8462 02/22/00
PS395
Precision 8-Ch. 17V, SPST Switch
w/8-Bit Serial Decoded Control
Timing Characteristics - Dual Supplies
(V± = ±4.5V to 5.5V, V = 4/5V, TA = T
MIN
to T
MAX
, unless otherwise noted. Typical values are TA = +25°C).
Notes:
1. The algebraic convention is used in this data sheet; the most negative value is shown in the minimum column.
2. ∆R
ON
= R
ON(MAX)
- R
ON(MIN)
. On-resistance match between channels and on-resistance flatness are guaranteed only with
specified voltages. Flatness is defined as the difference between the maximum and minimum value of on-resistance as
measured over the specified analog signal range.
3. Leakage parameters are 100% tested at maximum rated hot temperature and guaranteed by correlation at room temp.
4. Guaranteed by design.
5. Leakage testing at single supply is guaranteed by testing with dual supplies.
6. See Figure 5. Off isolation = 20log10 V
COM/VNO
, V
COM
= output. NO = input to off switch.
7. Between any two switches. See Figure 2.
retemaraPlobmySsnoitidnoC.niM
)1(
.pyT
)1(
.xaM
)1(
stinU
ecafretnIlatigiDlaireS
ycneuqerFKLCSf
KLCS
E,C
01.2zHM
emiTelcyCt
HC
t+
LC
084
sn
emiTdaeLSCt
SSC
042
emiTgaLSCt
2HSC
042
emiThgiHKLCSt
HC
091
emiTwoLKLCSt
LC
091
emiTputeSataDt
SD
00271
emiTdloHataDt
HD
071
KLCSgnillaFretfadilaVataDNID
)4(
t
OD
,TUODfo%01otKLCSfo%05
C
L
Fp01=
T
A
V52+=58
E,C004
TUODfoemiTesiR
)4(
t
RD
C,+Vfo%07ot+Vfo%02
L
Fp01=
001
KLCS,NIDtaemiTesiRelbawollA
)4(
t
RCS
2sn
TUODfoemiTllaF
)4(
t
FD
001
µs
KLCS,NIDtaemiTllaFelbawollA
)4(
t
FCS
2
sn
htdiWesluPmuminiMTESERt
WR
07
Page 6
6
PS8462 02/22/00
PS395
Precision 8-Ch. 17V, SPST Switch
w/8-Bit Serial Decoded Control
Electrical Characteristics - Single 5V Supply
(V+ = + 5V ± 10%, V- = 0V, GND = 0V, V
AH
= V
ENH
= +2.4, VAL = V
ENL
= +0.8V)
retemaraPlobmySsnoitidnoC.niM
)2(
.pyT
)1(
.xaM
)2(
stinU
hctiwSgolanA
egnaRlangiSgolanA
)3(
V
,MOC
V
ON
E,CV+VV
ecnatsiseRnOON,MOCR
NO
V,V5=+V
MOC
,V5.3=
I
ON
Am1=
T
A
V52+=521571
Ω
E,C522
tnerruCegakaeLffOON
)5,4(
I
)FFO(ON
V,V5.5=+V
MOC
,V5.4=
V
ON
V0=
T
A
V52+=1.0200.01.0
An
E,C0101
,V5.5=V,V5.5=+V
V
MOC
V,V5.4=
ON
V5.4=
T
A
V52+=1.0200.01.0
E,C0101
tnerruCegakaeLffOMOC
5,4(
I
)FFO(MOC
V,V5.5=+V
MOC
,V5.4=
V
ON
V0=
T
A
V52+=1.0200.01.0
E,C0101
,V5.5=V,V5.5=+V
V
MOC
V,V5.4=
ON
V5.4=
T
A
V52+=1.0200.01.0
E,C0101
tnerruCegakaeLnOMOC
)5,4(
I
)NO(MOC
V,V5.5=+V
MOC
V=
ON
V5.4=
T
A
V52+=2.020.02.0
E,C0202
O/IlatigiD
tupnITESER,SC,KLCS,NID
hgiHdlohserhTcigoLegatloV
V
HI
E,C
4.2
V
tupnITESER,SC,KLCS,NID
woLdlohserhTcigoLegatloV
V
LI
8.0
tupnITESER,SC,KLCS,NID
woLrohgiHcigoLtnerruC
I
HII,LI
V
NID
V,
KLCS
V,
SC
V4.2roV8.0=130.01
µA
hgiHcigoLegatloVtuptuOTUODV
TUOD
I
TUOD
Am8.0=8.2+V
V
woLcigoLegatloVtuptuOTUODV
TUOD
I
TUOD
Am6.1=04.0
siseretsyHtupnIKLCSKLCS
TSYH
001Vm
scitsiretcarahCcimanyDhctiwS
emiTnO-nruTt
NO
SCfoegdegnisirmorF
T
A
V52+=002004
sn
E,C005
emiTffO-nruTt
FFO
T
A
V52+=09004
E,C005
yaleDekaM-erofeB-kaerBt
MBB
T
A
V52+=51
noitcejnIegrahC
)4(
V
ETC
C
L
V,Fn1=
ON
R,V0=
S
0= Ω T
A
V52+=201Cp
noitalosIffO
)6(
V
OSI
R
L
C,Fn1=
L
,Fp51=
V
ON
V1=
SMR
,f 1= 0 zHk0
T
A
V52+=09
Bd
klatssorClennahC-ot-lennahC
)6(
V
TC
T
A
V52+=09<
ylppuSrewoP
tnerruCylppuSV,+V+I
roV0=KLCS=SC=NID
+VroV0=TESER,+V
T
A
V52+=702
µA
E,C03
Page 7
7
PS8462 02/22/00
PS395
Precision 8-Ch. 17V, SPST Switch
w/8-Bit Serial Decoded Control
Timing Characteristics - Single +5V Supply
(V+ = ±4.5V to 5.5V, V = 0V, TA = T
MIN
to T
MAX
, unless otherwise noted. Typical values are TA = +25°C).
Notes:
1. The algebraic convention is used in this data sheet; the most negative value is shown in the minimum column.
2. ∆R
ON
= R
ON(MAX)
- R
ON(MIN)
. On-resistance match between channels and on-resistance flatness are guaranteed only with
specified voltages. Flatness is defined as the difference between the maximum and minimum value of on-resistance as
measured over the specified analog signal range.
3. Leakage parameters are 100% tested at maximum rated hot temperature and guaranteed by correlation at room temp.
4. Guaranteed by design.
5. Leakage testing at single supply is guaranteed by testing with dual supplies.
6. See Figure 5. Off isolation = 20log10 V
COM/VNO
, V
COM
= output. NO = input to off switch.
7. Between any two switches. See Figure 2.
retemaraPlobmySsnoitidnoC.niM
)1(
.pyT
)1(
.xaM
)1(
stinU
ecafretnIlatigiDlaireS
ycneuqerFKLCSf
KLCS
E,C
01.2zHM
emiTelcyC
)4(
t
HC
t+
LC
084
sn
emiTdaeLSC
)4(
t
SSC
042
emiTgaLSC
)4(
t
2HSC
042
emiThgiHKLCS
)4(
t
HC
091
emiTwoLKLCS
)4(
t
LC
091
emiTputeSataD
)4(
t
SD
00271
emiTdloHataD
)4(
t
HD
071
KLCSgnillaFretfadilaVataDNID
)4(
t
OD
,TUODfo%01otKLCSfo%05
C
L
Fp01=
T
A
V52+=58
E,C004
TUODfoemiTesiR
)4(
t
RD
,+Vfo%07ot+Vfo%02
C
L
Fp01=
001
KLCS,NIDtaemiTesiRelbawollA
)4(
t
RCS
2sn
TUODfoemiTllaF
)4(
t
FD
001
µs
KLCS,NIDtaemiTllaFelbawollA
)4(
t
FCS
2
sn
htdiWesluPmuminiMTESERt
WR
07
Page 8
8
PS8462 02/22/00
PS395
Precision 8-Ch. 17V, SPST Switch
w/8-Bit Serial Decoded Control
Electrical Characteristics - Single +3V Supply
(V+ = +3.0V + 3.6V, V = 0V, T
MIN
to T
MAX
, unless otherwise noted. Typical values are at TA = +25°C)
retemaraPlobmySsnoitidnoC.niM
)2(
.pyT
)1(
.xaM
)2(
stinU
hctiwSgolanA
egnaRlangiSgolanA
)3(
V
,MOC
V
ON
E,CV+VV
ecnatsiseRnOON,MOCR
NO
V,0.3=+V
MOC
,V5.1=
I
ON
Am1=
T
A
V52+=072005
Ω
E,C006
tnerruCegakaeLffOON
)5,4(
I
)FFO(ON
V,V0.3=+V
MOC
,V3=
V
ON
V0=
T
A
V52+=1.0200.01.0
An
E,C55
V,V6.3=+V
MOC
,V0=
V
ON
V3=
T
A
V52+=1.0200.01.0
E,C55
tnerruCegakaeLffOMOC
5,4(
I
)FFO(MOC
V,V6.3=+V
MOC
,V3=
V
ON
V0=
T
A
V52+=1.0200.01.0
E,C55
V,V6.3=+V
MOC
,V0=
V
ON
V3=
T
A
V52+=1.0200.01.0
E,C55
tnerruCegakaeLnOMOC
)5,4(
I
)NO(MOC
V,V6.3=+V
MOC
,V3=
V
ON
V0=
T
A
V52+=1.0200.01.0
E,C0101
V,V6.3=+V
MOC
,V0=
V
ON
V3=
T
A
V52+=1.0200.01.0
E,C0101
O/IlatigiD
tupnITESER,SC,KLCS,NID
hgiHdlohserhTcigoLegatloV
V
HI
E,C
4.2
V
tupnITESER,SC,KLCS,NID
woLdlohserhTcigoLegatloV
V
LI
8.0
tupnI,SC,KLCS,NID
woLrohgiHcigoLtnerruC
I
HII,LI
V
NID
V,
KLCS
V,
SC
V4.2roV8.0=130.01
µA
hgiHcigoLegatloVtuptuOTUODV
TUOD
I
TUOD
Am1.0=8.2+V
V
woLcigoLegatloVtuptuOTUODV
TUOD
I
TUOD
Am6.1=04.0
siseretsyHtupnIKLCSKLCS
TSYH
001Vm
scitsiretcarahCcimanyDhctiwS
emiTnO-nruTt
NO
SCfoegdegnisirmorF
T
A
V52+=062006
sn
E,C008
emiTffO-nruTt
FFO
T
A
V52+=09003
E,C004
yaleDekaM-erofeB-kaerBt
MBB
T
A
V52+=51
noitcejnIegrahC
)4(
V
ETC
C
L
V,Fn1=
ON
R,V0=
S
0= Ω T
A
V52+=201Cp
noitalosIffO
)6(
V
OSI
RL05= Ω C,
L
,Fp51=
V
ON
V1=
SMR
,f 1= 0 zHk0
T
A
V52+=09
Bd
klatssorClennahC-ot-lennahC
)7(
V
TC
T
A
V52+=09<
ylppuSrewoP
tnerruCylppuSV,+V+I
roV0=KLCS=SC=NID
V5roV0=TESER,+V
T
A
V52+=602
µA
E,C03
Page 9
9
PS8462 02/22/00
PS395
Precision 8-Ch. 17V, SPST Switch
w/8-Bit Serial Decoded Control
retemaraPlobmySsnoitidnoC.niM
)1(
.pyT
)1(
.xaM
)1(
stinU
ecafretnIlatigiDlaireS
ycneuqerFKLCSf
KLCS
E,C
01.2zHM
emiTelcyC
)4(
t
HC
t+
LC
084
sn
emiTdaeLSC
)4(
t
SSC
042
emiTgaLSC
)4(
t
2HSC
042
emiThgiHKLCS
)4(
t
HC
091
emiTwoLKLCS
)4(
t
LC
091
emiTputeSataD
)4(
t
SD
00283
emiTdloHataD
)4(
t
HD
083
KLCSgnillaFretfadilaVataDNID
)4(
t
OD
,TUODfo%01otKLCSfo%05
C
L
Fp01=
T
A
V52+=051
E,C004
TUODfoemiTesiR
)4(
t
RD
,+Vfo%07ot+Vfo%02
C
L
Fp01=
001
KLCS,NIDtaemiTesiRelbawollA
)4(
t
RCS
2sn
TUODfoemiTllaF
)4(
t
FD
003
µs
KLCS,NIDtaemiTllaFelbawollA
)4(
t
FCS
2
sn
htdiWesluPmuminiMTESERt
WR
T
A
V52+=501
Timing Characteristics - Single +3V Supply
(V+ = ±3.0V to +3.6V, V = 0V, TA = T
MIN
to T
MAX
, unless otherwise noted. Typical values are TA = +25°C).
Notes:
1. The algebraic convention is used in this data sheet; the most negative value is shown in the minimum column.
2. ∆R
ON
= R
ON(MAX)
- R
ON(MIN)
. On-resistance match between channels and on-resistance flatness are guaranteed only with
specified voltages. Flatness is defined as the difference between the maximum and minimum value of on-resistance as
measured over the specified analog signal range.
3. Leakage parameters are 100% tested at maximum rated hot temperature and guaranteed by correlation at room temp.
4. Guaranteed by design.
5. Leakage testing at single supply is guaranteed by testing with dual supplies.
6. See Figure 5. Off isolation = 20log10 V
COM/VNO
, V
COM
= output. NO = input to off switch.
7. Between any two switches. See Figure 2.
Page 10
10
PS8462 02/22/00
PS395
Precision 8-Ch. 17V, SPST Switch
w/8-Bit Serial Decoded Control
Detailed Description
Basic Operation
The PS395s interface can be thought of as an 8-bit shift register
controlled by CS (Figure 7). While CS is low, input data appearing
at DIN is clocked into the shift register synchronously with SCLKs
rising edge. The data is an 8-bit word, each bit controlling one of
eight switches in the PS395. DOUT is the shift registers output,
with data appearing synchronously with SCLKs falling edge. Data
at DOUT is simply the input data delayed by eight clock cycles.
When shifting the input data, D7 is the first bit in and out of the
shift register. While shifting data, the switches remain in their previous configuration. When the eight bits of data have been shifted
in, CS is driven high. This updates the new switch configuration
and inhibits further data from entering the shift register. Transitions at DIN and SCLK have no effect when CS is high, and DOUT
holds the first input bit (D7) at its output.
More or less than eight clock cycles can be entered during the CS
low period. When this happens, the shift register will contain only
the last eight serial data bits, regardless of when they were en-
tered. On the rising edge of CS, all the switches will be set to the
corresponding states.
The PS395s three-wire serial interface is compatible with SPI,
QSPI, and Microwire standards. If inter-facing with a Motorola
processor serial interface, set CPOL = 0. The PS395 is considered a
slave device (Figures 2 and 7). Upon power-up, the shift register
contains all zeros, and all switches are off.
The latch that drives the analog switch is updated on the rising
edge of CS, regardless of SCLKs state. This meets all the SPI and
QSPI requirements.
Daisy Chaining
For a simple interface using several PS395s, daisy chain the shift
registers as shown in Figure 5. The CS pins of all devices are
connected together, and a stream of data is shifted through the
PS395s in series. When CS is brought high, all switches are updated simultaneously. Additional shift registers may be included
anywhere in series with the PS395 data chain.
t
CSH0
SCLK
DIN
DOUT
COM OUT
t
CSS
t
CL
t
DS
t
DH
t
DO
t
CSH1
t
OFF
t
CSH2
t
CLL
t
CH
Figure 1. Timing Diagram
Page 11
11
PS8462 02/22/00
PS395
Precision 8-Ch. 17V, SPST Switch
w/8-Bit Serial Decoded Control
8x1 Multiplexer
To use the PS395 as an 8x1 multiplexer, connect all common pins
together (COM0COM7) to form the mux output; the mux inputs
are NO0NO7.
The mux can be programmed normally, with only one channel selected for every eight clock pulses, or it can be programmed in a
fast mode, where channel changing occurs on each clock pulse. In
this mode, the channels are selected by sending a single high
pulse (corresponding to the selected channel) at DIN, and a corresponding CS low pulse for every eight clock pulses. As this is
clocked through the register by SCLK, each switch sequences one
channel at a time, starting with Channel 7.
Dual, Differential 4-Channel Multiplexer
To use the PS395 as a dual (4x2) mux, connect COM0COM3
together and connect COM4COM7 together, forming the two
outputs. The mux input pairs become NO0/NO4, NO1/NO5, NO2/
NO6, and NO3/NO7.
The mux can be programmed normally, with only one differential
channel selected for every eight clock pulses, or it can be programmed in a fast mode, where channel changing occurs on each
clock pulse.
In fast mode, the channels are selected by sending two high pulses
spaced four clock pulses apart (corresponding to the two selected
channels) at DIN, and a corresponding CS low pulse for each of
the first eight clock pulses. As this is clocked through the register
by SCLK, each switch sequences one differential channel at a
time, starting with channel 7/0. After the first eight bits have been
sent, subsequent channel sequencing can occur by repeating this
sequence or, even faster, by sending only one DIN high pulse and
one CS low pulse for each four clock pulses.
SPDT Switches
To use the PS395 as a quad, single-pole/double-throw (SPDT)
switch, connect COM0 to NO1, COM2 to NO3, COM4 to NO5, and
COM6 to NO7, forming the four common pins. Program these
four switches with pairs of instructions, as shown in SPST Truth
Table.
Reset Function
RESET is the internal reset pin. It is usually connected to a logic
signal or V+. Drive RESET low to open all switches and set the
contents of the internal shift register to zero simultaneously. When
RESET is high, the part functions normally and DOUT is sourced
from V+. RESET must not be driven beyond V+ or GND.
SK
SO
SI
I/O
Microwire
Port
PS395
CS
The DOUT-SI connection is not required for writing to
the PS395, but may be used for data-echo purposes.
DOUT
DIN
SCLK
MISO
MOSI
SCK
I/O
SPI
Port
PS395
CS
The DOUT-MISO connection is not required for writing to
the PS395, but may be used for data-echo purposes.
CPOL = 0, CPHA = 0
SCLK
DIN
DOUT
Figure 2. Connections for Microwire
Figure 3. Connections for SPI and QSPI
Figure 4. Daisy-Chained Connection
CS
SCLKSCLK SCLK
DINDIN DIN
To
Other
Serial
Devices
CS
CS
Page 12
12
PS8462 02/22/00
PS395
Precision 8-Ch. 17V, SPST Switch
w/8-Bit Serial Decoded Control
CS
DIN
SCLK
CS1
CS2
CS3
SCLKSCLK SCLK
DINDIN DIN
To
Other
Serial
Devices
CS
CS
Figure 5. Addressable Serial Interface
FOUR CLOCK
PULSES
SW4
DIN
SCLK
SW0
D4 D0
Figure 6. Differential Multiplexer Input Control
Power-Supply Considerations
Overview
The PS395 construction is typical of most CMOS analog switches.
It has three supply pins: V+, V-, and GND. V+ and V- are used to
drive the internal CMOS switches and to set the limits of the analog voltage on any switch. Reverse ESD-protection diodes are
internally connected between each analog signal pin and both V+
and V-. If any analog signal exceeds V+ or V-, one of these diodes
will conduct. During normal operation, these (and other) reversebiased ESD diodes leak, forming the only current drawn from
V+ or V-.
Virtually all the analog leakage current is through the ESD diodes.
Although the ESD diodes on a given signal pin are identical, and
therefore fairly well balanced, they are reverse biased differently.
Each is biased by either V+ or V- and the analog signal. This means
their leakages vary as the signal varies. The difference in the two
diode leakages to the V+ and V- pins constitutes the analog signal-path leakage current. All analog leakage current flows to the
supply terminals, not to the other switch terminal. This is why
both sides of a given switch can show leakage currents of either
the same or opposite polarity.
There is no connection between the analog signal paths and GND.
V+ and GND power the internal logic and logic-level translators,
and set both the input and output logic limits. The logic-level
translators convert the logic levels to switched V+ and V- signals
to drive the analog signal gates. This drive signal is the only connection between logic supplies (and signals) and the analog supplies. V+, and V- have ESD-protection diodes to GND. The logiclevel inputs and output have ESD protection to V+ and to GND.
The logic-level thresholds are CMOS and TTL compatible when
V+ is +5V. As V+ is raised, the threshold increases slightly. So
when V+ reaches +12V, the threshold is about 3.1V; slightly above
the TTL guaranteed high-level minimum of 2.8V, but still compatible with CMOS outputs.
Bipolar Supplies
The PS395 operates with bipolar supplies between ±3.0V and ±8V.
The V+ and V- supplies need not be symmetrical, but their sum
cannot exceed the absolute maximum rating of 17V. Do not connect
the PS395 V+ to +3V and connect the logic-level pins to TTL
logic-level signals. This exceeds the absolute maximum ratings
and can damage the part and/or external circuits.
Page 13
13
PS8462 02/22/00
PS395
Precision 8-Ch. 17V, SPST Switch
w/8-Bit Serial Decoded Control
Addressable Serial Interface
When several serial devices are configured as slaves, addressable
by the processor, DIN pins of each decode logic individually control CS of each slave device. When a slave is selected, its CS pin is
driven low, data is shifted in, and CS is driven high to latch the
data. Typically, only on slave is addressed at a time. DOUT is not
used.
Applications Information
Multiplexers
The PS395 can be used as a multiplexer.
Single Supply
The PS395 operates from a single supply between +3V and +16V
when V- is connected to GND. All of the bipolar precautions must
be observed.
Figure 7. Three-Wire Interface Timing
D0D0
D7
SCLK
DIN
CS
DOUT
D6 D5 D4
DATA BITS
D3 D2 D1 D0
SWITCHES
UPDATED
D7 D6 D5 D4 D3 D2 D1
DATA BITS FROM PREVIOUS DATA INPUT
traPegnaRerutarepmeTegakcaP-niP
BNC593SPC°07+otC°0piDcitsalPworraN42
GWC593SPC°07+otC°0OSediW42
GNE593SPC°058+otC°04piDcitsalPworraN42
GWE593SPC°058+otC°04OSediW42
High-Frequency Performance
In 50Ω systems, signal response is reasonably flat up to 50MHz
(see Typical Operating Characteristics). Above 20MHz, the onresponse has several minor peaks that are highly layout dependent. The problem is not turning the switch on, but turning it
off. The off-state switch acts like a capacitor and passes higher
frequencies with less attenuation. At 10MHz, off isolation is about
-45dB in 50Ω systems, becoming worse (approximately 20dB per
decade) as frequency increases. Higher circuit impedances also
make off isolation worse. Adjacent channel attenuation is about
3dB above that of a bare IC socket, and is due entirely to capacitive coupling.
Pericom Semiconductor Corporation
2380 Bering Drive San Jose, CA 95131 1-800-435-2336 Fax (408) 435-1100 http://www.pericom.com
Loading...