Datasheet PS223S Datasheet (Silicon Touch)

Page 1
PS222S
3-Channel Secondary Monitoring IC
Version : A.003 Issue Date : File Name : SP-PS222S-A.003.doc Total Pages : 13
2008/01/10
And an Additional 12V OCP Channel
新竹市科學園區展業一路 9 號 7 樓之 1
SILICON TOUCH TECHNOLOGY INC.
9-7F-1, Prosperity Road I, Science Based Industrial Park,
Hsin-Chu, Taiwan 300, R.O.C.
Tel:886-3-5645656 Fax:886-3-5645626
Page 2
PS222S
PS222S
3-Channel Secondary Monitoring IC
With Over-Current Protection
And an Additional 12V OCP Channel
General Description
PS222S is specially designed for switching power supply system. Four important functions of PS222S are the following: over-voltage protection, over-current protection, under-voltage protection and power good signal generating.
OVP/UVP (Over-Voltage/Under-Voltage Protection) monitors 3.3V, 5V and 12V to protect our power supply. FPO/ goes to high when one of these supply voltages exceeds their normal operation voltage range.
OCP (Over Current Protection) monitors IS33, IS5, IS12 input current sense. Composed of “Iref“ and “protection current range resistor”, an adjustable over-current condition helps users design OCP easily.
An additional OCP channel helps users monitor another 12V rail output current.
Power good signal generating can notify personal computer when power supply is ready or power supply is going to shutdown, therefore it can provide a reliable power supply environment.
Features
Over/Under-voltage protection and lock out
Over-current protection and lock out
Fault protection output with open drain output stage
Open drain power good output signal for power good input
Built-in 300mS power good delay
AC on 75mS delay for UV/OC protection
38mS PSON/ control de-bounce
73uS de-bounce for noise immunity
Wide power supply range (4.2V~16V)
Special care for AC power off
3-Channel Secondary Monitoring IC Version:A.003 Page 1
未經授權而逕予重製、複製、使用或公開本文件,行為人得被追究侵權之相關民刑事責任
Unauthorized reproduction, duplication, use or disclosure of this document will be deemed as infringement.
Page 3
f
f
f
f
f
f
Block Diagram
Vcc / VSx
VS12
VS5
VS33
ISX
IS12
IS5
IS33
155KΩ
9KΩ
16KΩ
58KΩ
13.5KΩ
18.5KΩ
38.5KΩ
23.5KΩ
28KΩ
Step Dow n
to near 2.5V
Iref X 8
Step Dow n
to near 2.5V
Iref X 8
Step Dow n
to near 2.5V
Iref X 8
Step Dow n
to near 2.5V
Iref X 8
Vre
Vre
Vre
Vre
Vre
Vre
VCCI
VCCI
VCCI
VCCI
VCCI
VCCI
12 UV
12 OV
5 UV
5 OV
3.3 UV
3.3 OV
VCCI
VCCI
VCCI
VCCI
Vcc OC
12 OC
5 OC
3.3 OC
delay
H : 20mS L : 4.5uS
De-bounce
delay
H : 75mS L : 4.5uS
Power On
Internal
Band-Gap Reference
73uS
De-bounce
Reset
Power
38mS
73uS
De-bounce
V CCI = 4V
Vref
1.25V
H : 4mS L : 4.5uS
POR
Clock
Generator
S Q R
delay
VCCI
1 0
Q
delay
H : 300mS L : 4.5uS
1.25V
R S
1MΩ
30KΩ
2KΩ
90KΩ 4.5V
VCCI
1.13V
VCCI
0.63V
VCCI
1.25V
VCCI
1MΩ
Constant Current
Source I
CLK
ref
PS222S
FPO/
VCC
PSON/
PGI
PGO
RI
GND
3-Channel Secondary Monitoring IC Version:A.003 Page 2
未經授權而逕予重製、複製、使用或公開本文件,行為人得被追究侵權之相關民刑事責任
Unauthorized reproduction, duplication, use or disclosure of this document will be deemed as infringement.
Page 4
Timing Chart
PS222S
VSx VS12 IS12 VS5 IS5 VS33 IS33
Vcc
PSON/
FPO/
PGI
ISx
PGO
AC
turn on
Td1 T
T
d2
UVP/OVP/OCP
protect
PSON/ turn on
b1
PSON/ turn off
T
d3
PSON/ turn on
AC
turn off
VPGI
1.25V
0.63V
Td1
Td2
OVP OVP/UVP/OCP
1.13V
OVP
3-Channel Secondary Monitoring IC Version:A.003 Page 3
未經授權而逕予重製、複製、使用或公開本文件,行為人得被追究侵權之相關民刑事責任
Unauthorized reproduction, duplication, use or disclosure of this document will be deemed as infringement.
Page 5
Pin Descriptions
Pin No PIN NAME Descriptions
1 PGI Power good input signal pin 2 GND Ground 3 FPO/ Inverted fault protection output ,open drain output stage 4 PSON/ Remote ON/OFF control input pin 5 IS12 12V(1) over current protection input pin 6 RI Current sense setting 7 ISx 12V(2) over current protection input pin 8 IS5 5.0V over current protection input pin
9 IS33 3.3V over current protection input pin 10 VS12 12V(1) over/under voltage protection input pin 11 VS33 3.3V over/under voltage protection in put pin 12 VS5 5.0V over/under voltage protection input pin 13 VCC / VSx Power supply 14 PGO Power good output signal pin , open drain output stage
PS222S
Absolute Maximum Ratings
Parameter Rating Unit
Storage Temperature (Tstg) -40 to +125 ° C Operating Temperature (Topr) -30 to +90 ° C Supply Voltage (VCC) VCC/VSx -0.5 to +16.0 V
Input Voltage Range (VI)
Output Voltage Range (VO)
Output Current for RI (IRI) RI 12.5 to 62.5 uA
ESD Susceptibility* (VESD)
* Human Body Model (HBM).
ISX, VS12, IS12 -0.5 to +16.0 V
VS5, IS5 -0.5 to +9.0 V
VS33, IS33 -0.5 to +7.0 V
PGI -0.5 to +16.0 V
PSON/ -0.5 to Vcc+0.5 V
FPO/ -0.5 to +16.0 V
PGO -0.5 to Vcc+0.5 V
PSON/, PGO > 5000 V
FPOB, VS12 > 2000 V
PGI, IS12, VS5 > 3000 V
Others > 4000 V
3-Channel Secondary Monitoring IC Version:A.003 Page 4
未經授權而逕予重製、複製、使用或公開本文件,行為人得被追究侵權之相關民刑事責任
Unauthorized reproduction, duplication, use or disclosure of this document will be deemed as infringement.
Page 6
PS222S
Electrical Characteristics, Vcc=12V, T
Power Supply Section
Parameter Conditions MIN TYP MAX Unit
Supply Volt age 4.2 5.0 16.0 V Supply Current VPSON/ = 5V 2 3 mA Power On Reset Threshold Voltage (VPOR) 3.2 3.4 3.6 V Power On Reset Hysteresis (VHYST) -0.15 -0.3 -0.45 V
Over-Voltage Section
Parameter Conditions MIN TYP MAX Unit
Over-Volt age Thre shold
VS33 3.7 3.9 4.1 V
VS12 13.1 13.8 14.5 V
= 25° C. (unless otherwise specified)
a
VS5 5.7 6.1 6.5 V
Under-Voltage Section
Under-Voltage Threshold
Over-Current Section
Offset Voltage (OCP Comparator)
Constant Current Generator Voltage (VRI) 1.20 1.25 1.30 V
Parameter Conditions MIN TYP MAX Unit
VS33 2.0 2.2 2.4 V
VS5 3.3 3.5 3.7 V
VS12 8.5 9.0 9.5 V
Parameter Conditions MIN TYP MAX Unit
VSx, ISx -5 -2 1 mV
VS33, IS33 -5 -2 1 mV
VS5, IS5 -5 -2 1 mV
VS12, IS12 -5 -2 1 mV
3-Channel Secondary Monitoring IC Version:A.003 Page 5
未經授權而逕予重製、複製、使用或公開本文件,行為人得被追究侵權之相關民刑事責任
Unauthorized reproduction, duplication, use or disclosure of this document will be deemed as infringement.
Page 7
Electrical Characteristics (Continued)
PSON/, Analog Input
Parameter Conditions MIN TYP MAX Unit
High-Level Input Voltage (VIH) 1.60 V Low-Level Input Voltage (VIL) 0.80 V
PGI, Analog Input
Parameter Conditions MIN TYP MAX Unit
Threshold Voltage for start Td1 1.16 1.25 1.33 V Threshold Voltage for start Td2 0.60 0.63 0.75 V Threshold V oltage for mask OC,UV 1.05 1.13 1.21 V Hysteresis (VHYST)*
* All of the comparator for PGI input in block diagram.
-20
PS222S
-50 -80 mV
PGO, Open Drain Digital Output
Parameter Conditions MIN TYP MAX Unit
Leakage Current (ILKG) VPGO=5V 5 uA Low Level Output Voltage (VOL) ISINK=4mA 0.3 V
FPO/, Open Drain Digital Output
Parameter Conditions MIN TYP MAX Unit
Leakage Current (ILKG) VFPO/=5V 5 uA Low Level Output Voltage (VOL) ISINK=6mA 0.3 V
Switching Characteristics
Parameter Conditions MIN TYP MAX Unit
PGI to PGO Delay Time (Td1) 200 300 400 mS Short Circuit Delay Time (Td2) 49 75 100 mS PGO to FPO/ Delay Time (Td3) 2 4 6 mS Over Current Delay Time (Td4) 13 20 27 mS PSON/ De-bounce Time (Tb1) 24 38 52 mS FPO/ Noise De-glitch Time (Tb2) 47 73 100 uS PGO Noise De-glitch Time (Tb3) 47 73 100 uS
, Vcc=12V, Ta = 25° C.
3-Channel Secondary Monitoring IC Version:A.003 Page 6
未經授權而逕予重製、複製、使用或公開本文件,行為人得被追究侵權之相關民刑事責任
Unauthorized reproduction, duplication, use or disclosure of this document will be deemed as infringement.
Page 8
Application
Typical 4 rails SPS (Dual 12V OCP)
S.P.S. Secondary Side
Coil
(1)
Coil
(2)
RS5
R
R
R
S33
S12(1)
S12(2)
PS222S
+5V Output
+3.3V Output+3.3V Coil
+12V
+12V
Output+12V
(1)
Output+12V
(2)
= or
+5V
SB
PSON
1K
D
I
R
R
5.6K
OS
1
PGI GND
2
FPO/
3
PSON/
4
IS12
5
RI
6
ISx
7
C
PSON
PGI
PGI
R
C
R
I
R
OC12(2)
OC12(1)
PS222S
R
OC33
PGO
VSx
VS5 VS33 VS12
IS33
IS5
0.1 uF
0.1 uF
R
OC5
R
4.7K
PGO
14 13 12 11 10
9 8
D
V
PGO
+5VSB
0.1 uF
0.1 uF
Cby
3-Channel Secondary Monitoring IC Version:A.003 Page 7
未經授權而逕予重製、複製、使用或公開本文件,行為人得被追究侵權之相關民刑事責任
Unauthorized reproduction, duplication, use or disclosure of this document will be deemed as infringement.
Page 9
Application (Continued)
Typical 3 rails SPS (Only one 12V OCP)
= or
S.P.S. Secondary Side
R
OC12
R
OC33
OC5
PS222S
RS5
R
S33
R
S12
R
+5V Output
+3.3V Output+3.3V Coil
+12V Output+12V Coil
R
4.7K
PGO
+5V
PSON
1
PGI GND
2
SB
1K
C
PSON
PGI
PGI
R
C
R
I
3 4 5 6 7
FPO/ PSON/ IS12 RI ISx
PS222S
PGO
VSx
VS5 VS33 VS12
IS33
IS5
0.1 uF
14 13 12 11 10
9 8
0.1 uF
PGO
+5VSB
0.1 uF
Cby
3-Channel Secondary Monitoring IC Version:A.003 Page 8
未經授權而逕予重製、複製、使用或公開本文件,行為人得被追究侵權之相關民刑事責任
Unauthorized reproduction, duplication, use or disclosure of this document will be deemed as infringement.
Page 10
μ
××=
×
×
Notes:
1. Zener diode or resistor or both of them can be used in component X.
2. The bypass capacitor Cby suggests to be 0.1uF~ 10uF and layout nearby pin VCC.
PS222S
3. The recommend sense values of R
S12(1)
, R
S12(2)
4. Over-Current Protection design example:
V
(1) AI
ref
20= ,
R
RI
I
I
RI
(2) RS5=0.002Ω , (3) If +5V OCP trip point is 20A,
25.1
μ
20
=Δ
()
Ω=== K
5.62
+
R
555
= 250
5μOC
×
5. GND path: (1) The GND path width is wider as far as it could. (2) The better grounding ability has better performance at surge test.
6. PS222S uses only one 12VOCP protection function: As “Typical 3 rails SPS” application circuit, the pin7(ISx) must be connected one resistor(Resistance>10kΩ or floating) to GND.
, RS5 and R
IRIV
8002.0
refOCVV
20002.0
208
are 0.002Ω.
S33
()
Ω=
3-Channel Secondary Monitoring IC Version:A.003 Page 9
未經授權而逕予重製、複製、使用或公開本文件,行為人得被追究侵權之相關民刑事責任
Unauthorized reproduction, duplication, use or disclosure of this document will be deemed as infringement.
Page 11
Package Specification
( 14-pin DIP )
PS222S
E
1
D
A
Seating Plane
A
L
1
b1
b
e
E
E
B
θ°
Dimension in mm Symbol Dimension in inch NOTE
Min Normal Max Min Normal Max
A
A
b
b
D E
E
e
e
L
θ°
5.33 0.210
0.38 0.015
1
1.52 0.06
0.46 0.018
1
18.67 19.18 19.69 0.735 0.755 0.775
7.62 0.300
6.00 6.30 6.60 0.236 0.248 0.260
1
2.54 0.100
7.32 9.53 0.288 0.375
b
2.54 3.81 0.100 0.150 0º 15º 15º
3-Channel Secondary Monitoring IC Version:A.003 Page 10
未經授權而逕予重製、複製、使用或公開本文件,行為人得被追究侵權之相關民刑事責任
Unauthorized reproduction, duplication, use or disclosure of this document will be deemed as infringement.
Page 12
PS222S
Package Specification
( 14-pin SOP )
B e
Seating Plane
(Continued)
D
E H
h x 45°
A
A
1
L
C
θ
Symbol
MIN. MAX. MIN. MAX. A 1.346 1.753 0.053 0.069 A1 0.102 0.254 0.004 0.01 B 0.330 0.508 0.013 0.020 C 0.190 0.250 0.0075 0.0098 e 1.27(TPY) 0.050(TYP) D 8.534 8.738 0.336 0.344 H 5.80 6.20 0.228 0.244 E 3.80 4.00 0.150 0.157 L 0.38 1.27 0.015 0.050 h 0.38(TPY) 0.015(TYP) θ 0° 8° 0° 8°
Dimension in mm
Dimension in inch
NOTE
3-Channel Secondary Monitoring IC Version:A.003 Page 11
未經授權而逕予重製、複製、使用或公開本文件,行為人得被追究侵權之相關民刑事責任
Unauthorized reproduction, duplication, use or disclosure of this document will be deemed as infringement.
Page 13
PS222S
The products listed herein are designed for ordinary electronic applications, such as electrical appliances, audio-visual equipment, communications devices and so on. Hence, it is advisable that the devices should not be used in medical instruments, surgical implants, aerospace machinery, nuclear power control systems, disaster/crime-prevention equipment and the like. Misusing those products may directly or indirectly endanger human life, or cause injury and property loss.
Silicon Touch Technology, Inc. will not take any responsibilities regarding the misusage of the products mentioned above. Anyone who purchases any products described herein with the above-mentioned intention or with such misused applications should accept full responsibility and indemnify. Silicon Touch Technology, Inc. and its distributors and all their officers and employees shall defend jointly and severally against any and all claims and litigation and all damages, cost and expenses associated with such intention and manipulation.
Silicon Touch Technology, Inc. reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete.
3-Channel Secondary Monitoring IC Version:A.003 Page 12
未經授權而逕予重製、複製、使用或公開本文件,行為人得被追究侵權之相關民刑事責任
Unauthorized reproduction, duplication, use or disclosure of this document will be deemed as infringement.
Page 14
Loading...