Page 1
SBSLITE™ Telecom Standard Product Data Sheet
PM8611
Preliminary
SBSLITE
Telecom Standard Product
Data Sheet
Preliminary
Issue 2: May 2001
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2010883, Issue 2
Page 2
SBSLITE™ Telecom Standard Product Data Sheet
Preliminary
Legal Information
Copyright
© 2001 PMC-Sierra, Inc.
The information is proprietary and confidential to PMC-Sierra, Inc., and for its customers’
internal use. In any event, you cannot reproduce any part of this document, in any form, without
the express written consent of PMC-Sierra, Inc.
PMC-2010883 (P1)
Disclaimer
None of the information contained in this document constitutes an express or implied warranty by
PMC-Sierra, Inc. as to the sufficiency, fitness or suitability for a particular purpose of any such
information or the fitness, or suitability for a particular purpose, merchantability, performance,
compatibility with other parts or systems, of any of the products of PMC-Sierra, Inc., or any
portion thereof, referred to in this document. PMC-Sierra, Inc. expressly disclaims all
representations and warranties of any kind regarding the contents or use of the information,
including, but not limited to, express and implied warranties of accuracy, completeness,
merchantability, fitness for a particular use, or non-infringement.
In no event will PMC-Sierra, Inc. be liable for any direct, indirect, special, incidental or
consequential damages, including, but not limited to, lost profits, lost business or lost data
resulting from any use of or reliance upon the information, whether or not PMC-Sierra, Inc. has
been advised of the possibility of such damage.
Trademarks
SBSLITE, NSE-20G, NSE-8G, SBI, SPECTRA, TEMUX-84, AAL1gator-32, and FREEDM-336
are trademarks of PMC-Sierra, Inc. S/UNI is a registered trademark of PMC-Sierra.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 1
Document ID: PMC-2010883, Issue 2
Page 3
SBSLITE™ Telecom Standard Product Data Sheet
Contacting PMC-Sierra
PMC-Sierra
8555 Baxter Place Burnaby, BC
Canada V5A 4V7
Tel: (604) 415-6000
Fax: (604) 415-6200
Document Information: document@pmc-sierra.com
Corporate Information: info@pmc-sierra.com
Technical Support: apps@pmc-sierra.com
Web Si te: http://www.pmc-sierra.com
Preliminary
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 2
Document ID: PMC-2010883, Issue 2
Page 4
SBSLITE™ Telecom Standard Product Data Sheet
Preliminary
Table of Contents
1 Features.......................................................................................................................9
2 Applications ............................................................................................................... 11
3 References ................................................................................................................12
4 Application Examples ................................................................................................ 13
5 Block Diagram ...........................................................................................................15
6 Loopback Configurations ...........................................................................................16
7 Description.................................................................................................................17
8 Pin Diagram ...............................................................................................................19
9 Pin Description........................................................................................................... 20
10 Functional Description ...............................................................................................34
10.1 SBI Bus Data Formats ......................................................................................34
10.2 Incoming SBI336 Timing Adapter......................................................................52
10.3 CAS Expanders................................................................................................. 52
10.4 Memory Switch Units ........................................................................................53
10.5 CAS Merging.....................................................................................................54
10.6 Incoming SBI336 Tributary Translator............................................................... 54
10.7 PRBS Processors .............................................................................................54
10.8 Transmit 8B/10B Encoders ...............................................................................55
10.9 Transmit Serializer ............................................................................................58
10.10 LVDS Transmitters ............................................................................................58
10.11 Clock Synthesis Unit .........................................................................................58
10.12 Transmit Reference Generator .........................................................................58
10.13 LVDS Receivers ................................................................................................ 59
10.14 Data Recovery Units .........................................................................................59
10.15 Receive 8B/10B Decoders................................................................................59
10.16 Outgoing SBI336S Tributary Translator ............................................................62
10.17 Outgoing SBI336 Timing Adapter......................................................................63
10.18 In-band Link Controller...................................................................................... 63
10.19 Microprocessor Interface ..................................................................................66
11 Normal Mode Register Description............................................................................71
12 Test Features Description........................................................................................240
12.1 Master Test and Test Configuration Registers ................................................240
12.2 JTAG Test Port ................................................................................................242
13 Operation .................................................................................................................254
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 3
Document ID: PMC-2010883, Issue 2
Page 5
SBSLITE™ Telecom Standard Product Data Sheet
Preliminary
13.1 “C1” Synchronization.......................................................................................254
13.2 Synchronized Control Setting Changes .......................................................... 255
13.3 Switch Setting Algorithm .................................................................................260
13.4 JTAG Support..................................................................................................267
14 Functional Timing.....................................................................................................272
14.1 Incoming SBI336 Bus Functional Timing ........................................................ 272
14.2 Incoming 77 MHz TelecomBus Functional Timing..........................................273
14.3 Transmit Serial LVDS Functional Timing ........................................................274
14.4 Receive Serial LVDS Functional Timing .........................................................275
14.5 Outgoing 77.76 MHz TelecomBus Functional Timing .....................................277
14.6 Outgoing SBI336 Functional Timing ...............................................................277
15 Absolute Maximum Ratings ..................................................................................... 279
16 D. C. Characteristics................................................................................................280
17 Microprocessor Interface Timing Characteristics ....................................................281
18 A.C. Timing Characteristics .....................................................................................284
18.1 SBSLITE Incoming Bus Timing.......................................................................284
18.2 SBSLITE Receive Bus Timing ........................................................................285
18.3 SBSLITE Outgoing Bus Timing.......................................................................286
18.4 SBSLITE Transmit Bus Timing........................................................................287
18.5 JTAG Port Interface.........................................................................................288
19 Ordering and Thermal Information ..........................................................................289
19.1 Ordering Information .......................................................................................289
19.2 Thermal Information ........................................................................................289
20 Mechanical Information ........................................................................................... 290
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 4
Document ID: PMC-2010883, Issue 2
Page 6
SBSLITE™ Telecom Standard Product Data Sheet
Preliminary
List of Figures
Figure 1 OC-48 T1/E1 ADM (Individually Drop/Add any T1/E1 in STS-48)....................13
Figure 2 OC-48 T1/E1 ADM (Drop/Add up to STS-48 at STS-1 Granularity) ................. 13
Figure 3 Any-Service-Any-Port NxDS0 TDM Access Solution........................................14
Figure 4 Any-Service-Any-Port T1/E1 Channelized PHY Card.......................................14
Figure 5 SBSLITE Block Diagram ...................................................................................15
Figure 6 Loopback Block Diagram .................................................................................. 16
Figure 7 Pin Diagram (Bottom View)...............................................................................19
Figure 8 Character Alignment State Machine .................................................................60
Figure 9 Frame Alignment State Machine.......................................................................62
Figure 10 In-Band Signaling Channel Message Format .................................................64
Figure 11 In-Band Signaling Channel Header Format....................................................65
Figure 12 Input Observation Cell (IN_CELL) ................................................................252
Figure 13 Output Cell (OUT_CELL) ..............................................................................252
Figure 14 Bidirectional Cell (IO_CELL) .........................................................................253
Figure 15 Layout of Output Enable and Bidirectional Cells...........................................253
Figure 16 “C1” Synchronization Control........................................................................255
Figure 17 TEMUX-84™/SBSLITE™/NSE/SBSLITE™/AAL1gator-32™ system
DS0 Switching with CAS...............................................................................256
Figure 18 CAS Multiframe Timing .................................................................................257
Figure 19 Switch Timing DSOs with CAS .....................................................................257
Figure 20 TEMUX-84/SBSLITE/NSE/SBSLITE/FREEDM-336 System DS0
Switching no CAS .........................................................................................258
Figure 21 Switch Timing - DSOs without CAS ..............................................................259
Figure 22 Non DS0 Switch Timing ................................................................................260
Figure 23 Example Graph .............................................................................................262
Figure 24 Time:Space:Time Switching in one NSE-20G and four Single-Ported
SBSs .............................................................................................................263
Figure 25 Example Graph .............................................................................................264
Figure 26 Example Problem..........................................................................................265
Figure 27 Merged Graph ...............................................................................................265
Figure 28 Relabeled Graph ........................................................................................... 266
Figure 29 Boundary Scan Architecture .........................................................................268
Figure 30 TAP Controller Finite State Machine.............................................................269
Figure 31 Incoming SBI336 Functional Timing .............................................................272
Figure 32 Incoming 77 MHz TelecomBus Functional Timing .......................................274
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 5
Document ID: PMC-2010883, Issue 2
Page 7
SBSLITE™ Telecom Standard Product Data Sheet
Preliminary
Figure 33 Incoming TelecomBus to LVDS Functional Timing ......................................274
Figure 34 Incoming SBI Bus to LVDS Timing with DS0 Switching ...............................275
Figure 35 Receive LVDS Link Timing ...........................................................................276
Figure 36 Outgoing Synchronization Timing .................................................................276
Figure 37 Outgoing 77.76 MHz TelecomBus Functional Timing ..................................277
Figure 38 Outgoing SBI336 Functional Timing .............................................................278
Figure 39 Microprocessor Interface Read Timing .........................................................281
Figure 40 Microprocessor Interface Write Timing .........................................................283
Figure 41 SBSLITE Incoming Timing ............................................................................ 285
Figure 42 SBSLITE Receive Timing..............................................................................286
Figure 43 SBSLITE Outgoing Timing ............................................................................ 287
Figure 44 SBSLITE Transmit Timing.............................................................................287
Figure 45 JTAG Port Interface Timing...........................................................................288
Figure 46 160 Pin PBGA 15 x 15 mm Body .................................................................. 290
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 6
Document ID: PMC-2010883, Issue 2
Page 8
SBSLITE™ Telecom Standard Product Data Sheet
Preliminary
List of Tables
Table 1 Structure for Carrying Multiplexed Links ............................................................35
Table 2 T1/TVT1.5 Tributary Column Numbering ........................................................... 35
Table 3 E1/TVT2 Tributary Column Numbering .............................................................. 36
Table 4 T1/E1 Link Rate Information...............................................................................37
Table 5 T1/E1 Clock Rate Encoding ...............................................................................37
Table 6 DS3/E3 Link Rate Information............................................................................38
Table 7 DS3/E3 Clock Rate Encoding ............................................................................38
Table 8 T1 Framing Format.............................................................................................39
Table 9 T1 Channel Associated Signaling Bits ...............................................................41
Table 10 E1 Framing Format ..........................................................................................42
Table 11 E1 Channel Associated Signaling Bits ............................................................. 44
Table 12 DS3 Framing Format........................................................................................45
Table 13 DS3 Block Format ............................................................................................ 45
Table 14 DS3 Multi-frame Stuffing Format......................................................................45
Table 15 E3 Framing Format ..........................................................................................46
Table 16 E3 Frame Stuffing Format ................................................................................47
Table 17 Transparent VT1.5/TU11 Format .....................................................................48
Table 18 Transparent VT2/TU12 Format ........................................................................49
Table 19 Fractional Rate Format.....................................................................................51
Table 20 Structure for Carrying Multiplexed Links in SBI336..........................................52
Table 21 SBI336S Character Encoding ..........................................................................55
Table 22 Serial TelecomBus Character Encoding ..........................................................57
Table 23 In-band Message Header Fields ...................................................................... 65
Table 24 Test Mode Register Memory Map .................................................................. 240
Table 25 Instruction Register (Length - 3 bits) ..............................................................242
Table 26 Identification Register.....................................................................................243
Table 27 Boundary Scan Register ................................................................................244
Table 28 Absolute Maximum Ratings............................................................................279
Table 29 D.C Characteristics ........................................................................................280
Table 30 Microprocessor Interface Read Access (Figure 39).......................................281
Table 31 Microprocessor Interface Write Access (Figure 40) .......................................283
Table 32 SBSLITE Incoming Timing (Figure 41) ..........................................................284
Table 33 SBSLITE Receive Timing (Figure 42) ............................................................285
Table 34 SBSLITE Outgoing Timing (Figure 43) ..........................................................286
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 7
Document ID: PMC-2010883, Issue 2
Page 9
SBSLITE™ Telecom Standard Product Data Sheet
Preliminary
Table 35 SBSLITE Transmit Timing (Figure 44) ...........................................................287
Table 36 JTAG Port Interface (Figure 45) ..................................................................... 288
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 8
Document ID: PMC-2010883, Issue 2
Page 10
1 Features
• The PM8611 SBI336 Bus Serializer (SBSLITE™) is a:
° Scalable Bandwidth Interconnect (SBI™) converter and Time Division Multiplexer
(TDM) SBI switch.
° Byte-wide 77.76 MHz SBI336 bus to 777.6 MHz serial SBI336S converter.
° DS0, NxDS0, T1, E1, TVT1.5, TVT2, DS3 and E3 granular SBI336 to serial SBI336S
switch. Supports subrate link switching with the restriction that subrate links must be
symmetric in both the transmit and receive directions.
° Byte-wide 77.76 MHz TelecomBus to serial 777.6 MHz TelecomBus converter. This
requires the TelecomBus J1 byte to be in a fixed location corresponding to a value of 0 or
522 which is immediately following the C1 octets:
° VT1.5, VT2, STS-1 77.76 MHz TelecomBus to serial TelecomBus switch.
• Can be used with the Narrowband Switch Elements, NSE-20G, to implement a DS0
granularity SBI Memory:Space:Memory switch scalable to 20 Gbit/s and NSE-8G, to
implement a switch scalable to 8 Gbit/s. In TelecomBus mode, a 20 Gbit/s VT1.5/VT2
granularity Memory:Space:Memory switch can be implemented.
SBSLITE™ Telecom Standard Product Data Sheet
Preliminary
• Integrates two independent DS0 granularity Memory Switches. One switch is placed
between the incoming 77.76 MHz byte-wide SBI336 bus and the transmit working and
protect Serial SBI336S link. The transmit working and protect links transmit the same data.
The other switch is placed between the receive working or protect Serial SBI336S link and
the outgoing 77.76 MHz byte-wide SBI336 bus.
• Provides 125 µS nominal latency in DS0 mode. Channel Associated Signaling (CAS) latency
through the SBSLITE in DS0 mode is two T1 multiframe (6 mS) or two E1 multiframe (4
mS).
• Provides less than 16 µS nominal latency in TelecomBus mode or SBI mode without DS0
level switching.
• Permits any receive or incoming byte from an input port to be mapped to any outgoing or
transmit byte, respectively, on the associated output port through the Memory switch.
• Supports redundant working and protect serial SBI336S links in support of a redundant
Memory:Space:Memory switch with the NSE.
• Encodes and decodes byte-wide SBI336 bus control signals for all SBI supported link types
and clock modes for transport over the serial SBI336S interface.
• Encodes data from the Incoming SBI336 bus or TelecomBus stream to a working and protect
777.6 Mbit/s LVDS serial links with 8B/10B-based encoding.
• Decodes data from a working and protect 777.6 MHz low voltage differential serializer
(LVDS) serial links with 8B/10B-based encoding to the Outgoing SBI336 bus or TelecomBus
stream.
• In SBI mode, switches CAS bits with all DS0 data.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 9
Document ID: PMC-2010883, Issue 2
Page 11
SBSLITE™ Telecom Standard Product Data Sheet
Preliminary
• Uses 8B/10B-based line coding protocol on the serial links to provide transition density
guarantee and DC balance and to offer a greater control character vocabulary than the
standard 8B/10B protocol.
• Provides optional pseudo-random bit sequence (PRBS) generation for each outgoing LVDS
serial data link for off-line link verification. PRBS can be inserted with STS-1 granularity.
• Provides PRBS detection for each incoming LVDS serial link for off-line link verification.
PRBS is verified with STS-1 granularity.
• Provides pins to coordinate updating of the connection map of the memory switch blocks in
the local device, peer SBSLITE devices and companion NSE switch device.
• Can communicate with the NSE switch device over an in-band communications channel in
the LVDS links. This channel includes mechanisms for central control and configuration.
• Derives all internal timing from a single 77.76 MHz system clock to a system frame pulse.
• Implemented in 1.8 V/3.3 V 0.18 µm CMOS and packaged in a 160 ball 15 mm x 15 mm
PBGA.
• Consumes low power at 1.4 W.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 10
Document ID: PMC-2010883, Issue 2
Page 12
2 Applications
• T1/E1 SONET/SDH Cross-connects
• T1/E1 SONET/SDH Add-Drop Multiplexers
• OC-48 Multiservice Access Multiplexers
• Channelized OC-12/OC-48 Any Service Any Port Switches
• Serial Backplane Board Interconnect
• Shelf to Shelf Cabled Serial Interconnect
• Voice Gateways
SBSLITE™ Telecom Standard Product Data Sheet
Preliminary
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 11
Document ID: PMC-2010883, Issue 2
Page 13
3 References
1. IEEE 802.3, “Carrier Sense Multiple Access with Collision Detection (CSMA/CD) Access
Method and Physical Layer Specifications”, Section 36.2, 1998.
2. A.X. Widmer and P.A. Franaszek, “A DC-Balanced, Partitioned-Block, 8B/10B Transmission
Code,” IBM Journal of Research and Development, Vol. 27, No 5, September 1983, pp 440-
451.
3. U.S. Patent No. 4,486,739, P.A. Franaszek and A.X. Widmer, “Byte Oriented DC Balanced
(0,4) 8B/10B Partitioned Block Transmission Code,” December 4, 1984.
4. Telcordia - SONET Transport Systems: Common Generic Criteria, GR-253-CORE, Issue 2,
Revision 2, January 1999.
5. ITU, Recommendation G.707 - "Digital Transmission Systems – Terminal equipments -
General", March 1996.
SBSLITE™ Telecom Standard Product Data Sheet
Preliminary
6. ITU, Recommendation O.151 – “Error Performance Measuring Equipment Operating at the
Primary Rate and Above", October 1992.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 12
Document ID: PMC-2010883, Issue 2
Page 14
4 Application Examples
Figure 1 and Figure 2 show a PM8611 SBI336 Bus Serializer-lite (SBSLITE) connected to a
TelecomBus to implement a T1 or E1 Add/Drop function. When connected to the TelecomBus,
the SBSLITE with a PM8620 or PM8621 Narrowband Switching Element (NSE-8G™ or NSE20G™) implements a T1/E1 Memory:Space:Memory switch. The SBSLITE requires all path
pointer justifications to be translated into tributary pointer movements so that J1 is fixed to the
location following C1 or H3. In both examples J1 alignment is performed with the TUPP-622.
Switching within the SBSLITE and NSE is utilizing the Transparent Virtual Tributary, TVT,
mapping across the serial SBI336S LVDS links.
Figure 1 OC-48 T1/E1 ADM (Individually Drop/Add any T1/E1 in STS-48)
SBSLITE™ Telecom Standard Product Data Sheet
Preliminary
SPECTRA-
2488
4 X
TUPP-
622
4 X
SBSLITE
NSE
4 X
SBSLITE
SBS
4 X
TUPP-
622
1 X
TEMAP
-84
Figure 2 OC-48 T1/E1 ADM (Drop/Add up to STS-48 at STS-1 Granularity)
SPECTRA-
2488
TBS TBS
TBS
4 X
TUPP-
622
4 X
SBSLITE
NSE
SPECTRA-
2488
4 X
SBSLITE
4 X
SBSLITE
4 X
SBSLITE
4 X
SBSLITE
TEMUX84
TEMUX84
TEMUX84
TEMUX84
TEMUX84
TEMUX84
TEMUX84
TEMUX84
TEMUX84
TEMUX84
TEMUX84
TEMUX84
TEMUX84
TEMUX84
TEMUX84
TEMUX84
SPECTRA-
2488
11 X
OCTLIU
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 13
Document ID: PMC-2010883, Issue 2
Page 15
SBSLITE™ Telecom Standard Product Data Sheet
Preliminary
Figure 3 and Figure 4 show examples of the SBS and SBSLITE when used to implement high
density T1/E1 Channelized Physical Interface cards and NxDS0 Multiservice access cards also
using SBS and NSE devices. DS0, NxDS0, T1, E1, Transparent VTs, E3, DS3 and subrate rate
links can be switched between the physical layer and layer 2 devices using the SBS, SBSLITE
and NSE devices.
Figure 3 Any-Service-Any-Port NxDS0 TDM Access Solution
4 X
SBSLITE
SBS
NSE
SBS
SBS
FREEDM-
336
4 X
IMA-84
12 X
AAL1gator-
32
11 X
OCTLIU
Serial
Clock and
Data
Figure 4 Any-Service-Any-Port T1/E1 Channelized PHY Card
TBS
4 X
TEMUX-84
SBSLITE
4 X
Any-PHY
(Packet)
Any-PHY
(Cell)
Any-PHY
(Cell)
Processors
DSP
SPECTRA-
2488
TBS
TBS
TBS
TBS
4 X
TEMUX-84
4 X
TEMUX-84
4 X
TEMUX-84
4 X
SBSLITE
NSE
4 X
SBSLITE
4 X
SBSLITE
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 14
Document ID: PMC-2010883, Issue 2
Page 16
5 Block Diagram
Figure 5 SBSLITE Block Diagram
SBSLITE™ Telecom Standard Product Data Sheet
Preliminary
IDATA[7:0]
IDP
IPL
IV5
IC1FP
ITPL
ITAIS
SREFCLK
SYSCLK
JUST_REQ
ODATA[7:0]
ODP
OPL
OV5
OC1FP
OTPL
OTAIS
Incoming
SBI336
Timing
Adaptor
(ISTA)
Outgoing
SBI336
Timing
Adaptor
(OSTA)
Incoming
CAS
Expand
(ICASE)
Outgoing
CAS
Merge
(OCASM)
ICMP
Incoming
Memory
Switch
Unit
(IMSU)
Outgoing
Memory
Switch
Unit
(OMSU)
Incoming
CAS
Merge
(ICASM)
Outgoing
CAS
Expand
(OCASE)
Incoming
SBI
Tributary
Translator
(ISTT)
Outgoing
SBI
Tributary
Translator
(OSTT)
1/2
Working
PRBS
Processor
(WPP)
1/2
Protect
PRBS
Processor
(PPP)
1/2
Working
PRBS
Processor
(WPP)
1/2
Protect
PRBS
Processor
(PPP)
IUSER
1/2
Working
In-Band
Link
Controller
(WILC)
1/2
Protect
In-Band
Link
Controller
(PILC)
1/2
Working
In-Band
Link
Controller
(WILC)
1/2
Protect
In-Band
Link
Controller
(PILC)
Transmit
Working
8B/10B
Encoder
(TW8E)
Transmit
Protect
8B/10B
Encoder
(TP8E)
Receive
Working
8B/10B
Decoder
(RW8D)
Receive
Protect
8B/10B
Decoder
(RP8D)
Transmit
Working
Serializer
(TWPS)
Transmit
Protect
Serializer
(TPPS)
Tx
Ref
Working
Data
Recovery
Unit
(WDRU)
Protect
Data
Recovery
Unit
(PDRU)
TC1FP
Transmit
Working
LVDS
Interface
(TWLV)
Transmit
Protect
LVDS
Interface
(TPLV)
Clock
Synthesis
Unit
Receive
Working
LVDS
Interface
(RWLV)
Receive
Protect
LVDS
Interface
(RPLV)
TPWRK
TNWRK
TPPROT
TNPROT
RPWRK
RNWRK
RPPROT
RNPROT
Microprocessor Interface
A[8:0]
OCMP
D[15:0]
WRB
RDB
ALE
INTB
OUSER
RWSEL
RC1FP
CSB
RSTB
JTAG
TDI
TCK
TMS
TRSTB
TDO
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 15
Document ID: PMC-2010883, Issue 2
Page 17
6 Loopback Configurations
Figure 6 Loopback Block Diagram
SBSLITE™ Telecom Standard Product Data Sheet
Preliminary
IDATA[7:0]
IDP
IPL
IV5
IC1FP
ITPL
ITAIS
SREFCLK
SYSCLK
JUST_REQ
ODATA[7:0]
ODP
OPL
OV5
OC1FP
OTPL
OTAIS
Incoming
SBI336
Timing
Adaptor
(ISTA)
Outgoing
SBI336
Timing
Adaptor
(OSTA)
Incoming
CAS
Expand
(ICASE)
Outgoing
CAS
Merge
(OCASM)
ICMP
Incoming
Memory
Switch
Unit
(IMSU)
Outgoing
Memory
Switch
Unit
(OMSU)
Incoming
CAS
Merge
(ICASM)
Outgoing
CAS
Expand
(OCASE)
Incoming
SBI
Tributary
Translator
(ISTT)
Outgoing
SBI
Tributary
Translator
(OSTT)
1/2
Working
PRBS
Processor
(WPP)
1/2
Protect
PRBS
Processor
(PPP)
1/2
Working
PRBS
Processor
(WPP)
1/2
Protect
PRBS
Processor
(PPP)
IUSER
1/2
Working
In-Band
Link
Controller
(WILC)
1/2
Protect
In-Band
Link
Controller
(PILC)
1/2
Working
In-Band
Link
Controller
(WILC)
1/2
Protect
In-Band
Link
Controller
(PILC)
Transmit
Working
8B/10B
Encoder
(TW8E)
Transmit
Protect
8B/10B
Encoder
(TP8E)
Receive
Working
8B/10B
Decoder
(RW8D)
Receive
Protect
8B/10B
Decoder
(RP8D)
Transmit
Working
Serializer
(TWPS)
Transmit
Protect
Serializer
(TPPS)
Tx
Ref
Working
Data
Recovery
Unit
(WDRU)
Protect
Data
Recovery
Unit
(PDRU)
TC1FP
Transmit
Working
LVDS
Interface
(TWLV)
Transmit
Protect
LVDS
Interface
(TPLV)
Clock
Synthesis
Unit
Receive
Working
LVDS
Interface
(RWLV)
Receive
Protect
LVDS
Interface
(RPLV)
TPWRK
TNWRK
TPPROT
TNPROT
RPWRK
RNWRK
RPPROT
RNPROT
Microprocessor Interface
A[8:0]
OCMP
D[15:0]
WRB
RDB
ALE
INTB
OUSER
RWSEL
RC1FP
CSB
RSTB
JTAG
TDI
TCK
TMS
TRSTB
TDO
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 16
Document ID: PMC-2010883, Issue 2
Page 18
7 Description
The PM8611 SBI336 Bus Serializer, SBSLITE, is a monolithic integrated circuit that implements
conversion between a byte-serial 77.76 MHz SBI336 bus and redundant 777.6 Mbit/s bit-serial
8B/10B-base SBI336S bus. In TelecomBus mode, the SBSLITE implements conversion between
a 77.76 MHz TelecomBus format and a redundant 777.6 Mbit/s bit-serial 8B/10B-base serial
TelecomBus format. In line with the bus conversion is a DS0 granular switch allowing any input
DS0 to be output on any output DS0.
The SBSLITE can be used to connect and switch high density T1/E1 framer devices supporting
an SBI bus with link layer devices supporting an SBI bus over a serial backplane. Putting a
Narrowband Switch Element (NSE) between the framer and link layer devices allows
construction of up to 20 Gbit/s NxDS0 switches.
In the ingress direction, the SBSLITE connects an incoming 77.76 MHz SBI336 stream to a pair
of redundant serial SBI336S LVDS links through a DS0 memory switch. In TelecomBus mode,
an incoming 77.76 MHz TelecomBus that has the J1 path fixed and all high order pointer
justifications converted to tributary pointer justifications can be switched through a VT granular
switch to a pair of redundant serial LVDS TelecomBus format links. The incoming data is
encoded into an extended set of 8B/10B characters and transferred onto two redundant 777.6
Mbit/s serial LVDS links. SBI or TelecomBus frame boundaries, pointer justification events and
master timing controls are marked by 8B/10B control characters. Incoming synchronized payload
envelopes (SPEs) may be optionally overwritten with the locally generated X
pattern for diagnosis of downstream equipment. The PRBS processor is configurable to handle
any combination of SPEs and can be inserted independently into either of the redundant LVDS
links. A DS0 memory switch provides arbitrary mapping of streams on the incoming SBI336 bus
stream to the working and protect LVDS links at DS0 granularity. In TelecomBus mode, a
VT1.5/VT2 memory switch provides arbitrary mapping of tributaries on the incoming
TelecomBus stream to the working and protect LVDS links. Multi-cast is supported.
SBSLITE™ Telecom Standard Product Data Sheet
Preliminary
23
+ X18 + 1 PRBS
In the egress direction, the SBSLITE connects two independent 777.6 Mbit/s serial LVDS links to
an outgoing SBI336 Bus. Each link contains a constituent SBI336S stream. Bytes on the links
are carried as 8B/10B characters. The SBSLITE decodes the characters into data and control
signals for a single 77.76 MHz SBI336 bus. Alternatively the SBSLITE decodes two independent
777.6 Mbit/s TelecomBus formatted serial LVDS links characters into a single 77.76 MHz
TelecomBus. A PRBS processor is provided to monitor the decoded payload for the X
23
+ X18 + 1
pattern in each SPE. The PRBS processor is configurable to handle any combination of
synchronized payload envelopes (SPEs) in the serial LVDS link. Data on the outgoing SBI336
bus stream may be sourced from either of the LVDS links.
An In-band signaling link over the serial LVDS links allows this device to be controlled by a
companion switching device, the Narrowband Switching Element, PM8620 NSE-20G. This link
can be used as communication link between a central processor and the local microprocessor.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 17
Document ID: PMC-2010883, Issue 2
Page 19
SBSLITE™ Telecom Standard Product Data Sheet
Preliminary
Two loopbacks are provided on the SBSLITE. The transmit 8B/10B-to-receive 8B/10B loopback
allows data entering on the incoming bus to be looped back from the output of the TW8E and
TP8E to the input of the RW8D and RP8D, respectively. Only the data looped back on the active
link (working or protection) will make it back to the outgoing bus. The transmit-to-receive
loopback allows data entering on the incoming bus to be looped back from the output of the
ICASM to the input of the OCASE and then returned to the outgoing bus.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 18
Document ID: PMC-2010883, Issue 2
Page 20
SBSLITE™ Telecom Standard Product Data Sheet
8 Pin Diagram
The SBSLITE is packaged in a 160-pin PBGA package having a body size of 15 mm by 15 mm
and a ball pitch of 1 mm.
Figure 7 Pin Diagram (Bottom View)
14 13 12 11 10 9 8 7 6 5 4 3 2 1
Preliminary
A
B
C
D
E
F
G
H
J
K
L
M
DVDDO SYSCLK DVDDI VSS DVDDO OTPL VSS ODATA[4] DVDDI ODATA[0] DVDDO DVDDO
IDATA[0] VSS SREFCLK VSS ICMP VSS OV5 ODATA[6] VSS ODATA[2] VSS VSS RESK VSS
IDATA[3] IDATA[1] IDATA[2] VSS DVDDQ OC1FP DVDDO ODATA[7] DVDDO VSS ODP TC1FP RES AVDH
IDATA[6] IDATA[4] IDATA[5] OCMP VSS OPL OTAIS ODATA[5] ODATA[3] ODATA[1] AVDH VSS TNPROT TPPROT
IDP DVDDO VSS IDATA[7] VSS AVDH TPWRK TNWRK
IPL IV5 IC1FP ITPL ATB0 ATB1 RPWRK RNWRK
VSS DVDDI INTB ITAIS GND GND AVDL VSS RPPROT RNPROT
DVDDO TCK TDO VSS GND GND AVDL AVDQ VSS CSU_AVD
TDI DVDDQ TRSTB TMS AVDL AVDL VSS VSS
OUSER2 NC JUST_REQVSS VSS VSS DVDDI VSS
A[1] DVDDI VSS A[0] D[2] D[6] VSS VSS D[10] IUSER2 D[15] VSS ALE DVDDI
A[2] A[3] A[6] D[0] D[4] VSS D[8] VSS D[11] VSS DVDDO WRB CSB RDB
A
B
C
D
E
F
G
H
H
J
K
L
M
A[4] A[5] VSS A[8] D[3] DVDDO D[7] D[9] D[13] D[14] RC1FP RWSEL DVDDO DVDDO
N
P
DVDDO A[7] D[1] D[5] DVDDI DVDDQ DVDDO D[12] DVDDI VSS RSTB VS S
N
P
14 13 12 11 10 9 8 7 6 5 4 3 2 1
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 19
Document ID: PMC-2010883, Issue 2
Page 21
9 Pin Description
SBSLITE™ Telecom Standard Product Data Sheet
Preliminary
Pin Name Type Pin
No.
Receive Serial Data Interface (5 Signals)
RPWRK
RNWRK
RPPROT
RNPROT
RC1FP Input N4
Analog
LVDS
Input
Analog
LVDS
Input
F2
F1
G2
G1
Function
Receive Working Serial Data. In SBI336 mode, the differential
receive working serial data link (RPWRK/RNWRK) carries the
receive 77.76 MHz SBI336 data from an upstream working source,
in bit serial format, SBI336S.
In TelecomBus mode, RPWRK/RNWRK carries the receive 77.76
MHz TelecomBus from an upstream working source, in bit serial
format.
Data on RPWRK/RNWRK is encoded in an 8B/10B format
extended from IEEE Std. 802.3. The 8B/10B character bit ‘a’ is
transmitted first and the bit ‘j’ is transmitted last.
RPWRK/RNWRK are nominally 777.6 Mbit/s data streams.
Receive Protect Serial Data. In SBI336 mode, the differential
receive protect serial data link (RPPROT/RNPROT) carries the
receive 77.76 MHz SBI336 data from an upstream protect source,
in bit serial format, SBI336S.
In TelecomBus mode, RPPROT/RNPROT carries the receive
77.76 MHz TelecomBus from an upstream protection source, in bit
serial format.
Data on RPPROT/RNPROT is encoded in an 8B/10B format
extended from IEEE Std. 802.3. The 8B/10B character bit ‘a’ is
transmitted first and the bit ‘j’ is transmitted last.
RPPROT/RNPROT are nominally 777.6 Mbit/s data streams.
Receive Serial Frame Pulse. The receive serial SBI336S frame
pulse signal (RC1FP) provides system timing of the receive serial
interface.
When using the receive serial interface, RC1FP is set high once
every multiframe (4 frames for SBI without CAS, 48 frames for SBI
with CAS, and 4 frames for TelecomBus), or multiple thereof. The
RC1FP_DLY[13:0] bits (register 007H) are used to align the C1
frame boundary 8B/10B character on the receive serial interface
(RPWRK/RNWRK and RPPROT/RNPROT) with RC1FP.
RC1FP is sampled on the rising edge of SYSCLK.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 20
Document ID: PMC-2010883, Issue 2
Page 22
SBSLITE™ Telecom Standard Product Data Sheet
Preliminary
Pin Name Type
Outgoing SBI Bus (68 Signals)
OC1FP Tristate
Output
ODATA[7]
ODATA[6]
ODATA[5]
ODATA[4]
ODATA[3]
ODATA[2]
ODATA[1]
ODATA[0]
ODP Tristate
Tristate
Output
Output
Pin
No.
C9
C7
B7
D7
A6
D6
B5
D5
A4
C4
Function
Outgoing C1 Frame Pulse (OC1FP). This signal indicates the first
C1 octet on the outgoing SBI or TelecomBus.
In SBI336 mode:
This signal also indicates multiframe alignment which occurs every
4 frames, therefore this signal is pulsed every fourth C1 octet to
produce a 2 KHz multiframe signal.
When using the SBI bus in synchronous mode the OC1FP signal
indicates T1 and E1 signaling multiframe alignment by pulsing on
48 SBI frame boundaries. This must be done if CAS is to be
switched along with the data.
In TelecomBus mode:
This signal may also be pulsed to indicate the J1 byte position and
the byte following J1. The J1 byte position is locked to an offset of
either 0 or 522. The byte following J1 is used to indicate
multiframe alignment and is only pulsed once every 4 frames
marking the frame with the V1s.
OC1FP is updated on the rising edge of SREFCLK.
Outgoing Data (ODATA[7:0]). The Outgoing Data buse,
ODATA[7:0], is a time division multiplexed buses which transport
tributaries by assigning them to fixed octets within the SBI or
TelecomBus structure.
ODATA[7:0] are updated on the rising edge of SREFCLK.
Outgoing Bus Data Parity (ODP). The outgoing data parity signal
carries the even or odd parity for the outgoing bus. In SBI336
modes, the parity calculation for ODP encompasses the
ODATA[7:0], OPL and OV5 signals. In TelecomBus mode, the
parity calculation encompasses the ODATA[7:0] and optionally the
OC1FP and OPL signals.
ODP is updated on the rising edge of SREFCLK.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 21
Document ID: PMC-2010883, Issue 2
Page 23
SBSLITE™ Telecom Standard Product Data Sheet
Preliminary
Pin Name Type
OPL Tristate
Output
OV5 Tristate
Output
Pin
No.
D9
B8
Function
Outgoing Bus Payload (OPL). The outgoing payload signal, OPL,
indicates valid tributary data within the SBI bus. In TelecomBus
mode, this signal indicates valid path payload.
In SBI336 mode:
This active high signal is asserted during all octets making up a
tributary which includes all octets shaded grey in the framing
format tables. This signal goes high during the V3 or H3 octet
within a tributary to accommodate negative timing adjustments
between the tributary rate and the fixed SBI bus structure. This
signal goes low during the octet after the V3 or H3 octet within a
tributary to accommodate positive timing adjustments between the
tributary rate and the fixed SBI bus structure. For fractional rate
links this signal indicates that the current octet is carrying valid data
when high.
In locked TVT mode, this signal must be driven in the same
manner as for floating TVTs.
In TelecomBus mode:
This signal distinguishes between transport overhead bytes and
synchronous payload bytes. OPL is set high to mark each payload
byte on ODATA[7:0] and is set low to mark each transport
overhead byte.
OPL is updated on the rising edge of SREFCLK.
Outgoing Bus Payload Indicator (OV5). The active high signal,
OV5, locates the position of the floating payload for each tributary
within the outgoing SBI336 or TelecomBuses.
In SBI336 mode:
This active high signal locates the position of the floating payloads
for each tributary within the SBI336 structure. Timing differences
between the port timing and the bus timing are indicated by
adjustments of this payload indicator relative to the fixed bus
structure. All movements indicated by this signal must be
accompanied by appropriate adjustments in the OPL signal.
In locked TVT mode or fractional rate link mode this signal may be
driven but must be ignored by the receiving device.
In TelecomBus mode:
This signal identifies tributary payload frame boundaries on the
outgoing data bus. OV5 is set high to mark the V5 bytes on the
bus.
OV5 is updated on the rising edge of SREFCLK.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 22
Document ID: PMC-2010883, Issue 2
Page 24
SBSLITE™ Telecom Standard Product Data Sheet
Preliminary
Pin Name Type
Pin
No.
JUST_REQ Bidir K12
JUST_REQ[1]
(continued)
OTPL Tristate
Output
OTAIS
Tristate
Output
A8
D8
Function
Shared Bus Justification Request (JUST_REQ). The SBI Bus
Justification Request signal, JUST_REQ, is used to speed up, slow
down or maintain the minimal rate of a slave timed SBI device.
When the SBSLITE is configured to be connected to a physical
layer device, JUST_REQ is an input aligned with the incoming bus.
When the SBSLITE is configured to be connected to a link layer
device, JUST_REQ is an output aligned with the outgoing bus.
This active high signal, JUST_REQ, indicates negative timing
adjustments on the SBI bus when asserted high during the V3 or
H3 octet, depending on the tributary type. In response to this the
slave timed SBI device should send an extra byte in the V3 or H3
octet of the next frame along with a valid payload signal indicating
a negative justification.
This signal indicates positive timing adjustments on the
corresponding SBI bus when asserted high during the octet
following the V3 or H3 octet, depending on the tributary type. The
slave timed SBI device should respond to this by not sending an
octet during the V3 or H3 octet of the next frame along with a valid
payload signal indicating a positive justification.
For fractional rate links this signal is asserted high during any
available information byte to indicate to the slave timed SBI device
that the timing master device is able to accept another byte of data.
For every byte that this signal is asserted high the slave device is
expected to send a valid byte of data.
All timing adjustments from the slave timed device in response to
the justification request must still set the payload and payload
indicators appropriately for timing adjustments.
JUST_REQ is not used when configured for TelecomBus mode.
JUST_REQ is asserted or sampled on the rising edge of
SREFCLK.
Outgoing Tributary Payload (OTPL). This signal is used to
indicate tributary payload when configured for TelecomBus and is
held low when configured for an SBI336 bus.
OTPL is set high during valid VC11 and VC12 bytes of the
Outgoing bus. OTPL is set low for all transport overhead bytes,
high order path overhead bytes, fixed stuff column bytes and
tributary transport overhead bytes (V1,V2,V3,V4).
OTPL is updated on the rising edge of SREFCLK.
Outgoing Tributary Alarm Indication Signal (OTAIS). This signal
indicates tributaries in low order path AIS state for the Outgoing
TelecomBus and is held low when configured for an SBI336 bus.
OTAIS is set high when the tributary on the Outgoing bus is in AIS
state and is set low when the tributary is out of AIS state.
OTAIS is updated on the rising edge of SREFCLK.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 23
Document ID: PMC-2010883, Issue 2
Page 25
SBSLITE™ Telecom Standard Product Data Sheet
Preliminary
Pin Name Type
Pin
No.
Incoming SBI Bus (56 Signals)
IC1FP Input F12
IDATA[7]
IDATA[6]
IDATA[5]
IDATA[4]
IDATA[3]
IDATA[2]
IDATA[1]
IDATA[0]
IDP Input E14
Input E11
D14
D12
D13
C14
C12
C13
B14
Function
Incoming C1 Frame Pulse (IC1FP). This signal indicates the first
C1 octet on the incoming SBI336 or TelecomBus.
In SBI336 mode:
This signal also indicates multiframe alignment which occurs every
4 frames, therefore this signal is pulsed every fourth C1 octet to
produce a 2 KHz multiframe signal. The frame pulse does not
need to be repeated every 2 KHz as the SBSLITE will flywheel in
its absence.
When using the SBI bus in synchronous mode the IC1FP signal
can be used to indicate T1 and E1 multiframe alignment by pulsing
on 48 SBI frame boundaries. This must be done if CAS is to be
switched along with the data.
In TelecomBus mode:
This signal may also be pulsed to indicate the J1 byte position and
the byte following J1. The J1 byte position must be locked to an
offset of either 0 or 522. The byte following J1 is used to indicate
multiframe alignment and should only pulse once every 4 frames
marking the frame with the V1s.
IC1FP is sampled on the rising edge of SREFCLK.
Incoming Bus Data (IDATA[7:0]). The Incoming data bus,
IDATA[7:0], is a time division multiplexed buses which transports
tributaries by assigning them to fixed octets within the SBI336 or
TelecomBus structure.
Multiple SBI336 devices can drive this bus at uniquely assigned
tributary columns within the SBI/SBI336 bus structure.
IDATA[7:0] is sampled on the rising edge of SREFCLK.
Incoming Bus Data Parity (IDP). The Incoming data parity signal
carries the even or odd parity for the Incoming bus. In SBI336
modes, the parity calculation encompasses the IDATA[7:0], IPL
and IV5 signals. In TelecomBus mode, the parity calculation
encompasses the IDATA[7:0] and optionally the IC1FP and IPL
signals.
Multiple SBI336 devices can drive this signal at uniquely assigned
tributary columns within the SBI336 bus structure. This parity signal
is intended to detect multiple sources in the column assignment.
IDP is sampled on the rising edge of SREFCLK.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 24
Document ID: PMC-2010883, Issue 2
Page 26
SBSLITE™ Telecom Standard Product Data Sheet
Preliminary
Pin Name Type
Pin
No.
IPL Input F14
IV5 Input F13
Function
Incoming Bus Payload (IPL). The IPL signal indicates valid
tributary data within the SBI336 bus. In TelecomBus mode, this
signal indicates valid path payload.
In SBI336 mode:
This active high signal is asserted during all octets making up a
tributary which includes all octets shaded grey in the framing
format tables. This signal goes high during the V3 or H3 octet
within a tributary to accommodate negative timing adjustments
between the tributary rate and the fixed SBI336 structure. This
signal goes low during the octet following the V3 or H3 octet within
a tributary to accommodate positive timing adjustments between
the tributary rate and the fixed SBI336 structure. For fractional rate
links this signal indicates that the current octet is carrying valid data
when high.
Multiple SBI336 devices can drive this signal at uniquely assigned
tributary columns within the SBI336 structure.
For locked TVTs, this signal must be driven in the same manner as
for floating TVTs.
In TelecomBus mode:
This signal distinguishes between transport overhead bytes and
the synchronous payload bytes. IPL is set high to mark each
payload byte on IDATA[7:0] and is set low to mark each transport
overhead byte..
IPL is sampled on the rising edge of SREFCLK.
Incoming Bus Payload Indicator (IV5). This signal locates the
position of the floating payload for each tributary of the incoming
SBI336 or TelecomBuses.
In SBI336 mode:
This active high signal locates the position of the floating payloads
for each tributary within the SBI336 structure. Timing differences
between the port timing and the bus timing are indicated by
adjustments of this payload indicator relative to the fixed bus
structure. All movements indicated by this signal must be
accompanied by appropriate adjustments in the IPL signal.
Multiple SBI336 devices can drive this signal at uniquely assigned
tributary columns within the SBI336 structure.
For locked TVTs, this signal must either be driven in the same
manner as for floating TVTs or held low.
In TelecomBus mode:
This signal identifies tributary payload frame boundaries on the
incoming data bus. IV5 is set high to mark the V5 bytes on the
bus.
IV5 is sampled on the rising edge of SREFCLK.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 25
Document ID: PMC-2010883, Issue 2
Page 27
SBSLITE™ Telecom Standard Product Data Sheet
Preliminary
Pin Name Type
Pin
No.
ITPL Input F11
ITAIS Input G11
Transmit Serial Data Interface (5 Signals)
TPWRK
TNWRK
TPPROT
TNPROT
TC1FP Output C3
Analog
LVDS
Output
Analog
LVDS
Output
E2
E1
D1
D2
Function
Incoming Tributary Payload (ITPL). This signal is used to
indicate tributary payload when configured for TelecomBus and is
unused when configured for an SBI336 bus.
ITPL is set high during valid VC11 and VC12 bytes of the Incoming
bus. ITPL is set low for all transport overhead bytes, high order
path overhead bytes, fixed stuff column bytes and tributary
transport overhead bytes (V1,V2,V3,V4).
ITPL is sampled on the rising edge of SREFCLK.
Incoming Tributary Alarm Indication Signal (ITAIS). This signal
indicates tributaries in low order path AIS state for the Incoming
TelecomBus and is unused when configured for an SBI336 bus.
ITAIS is set high when the tributary on the Incoming bus is in AIS
state and is set low when the tributary is out of AIS state.
ITAIS is sampled on the rising edge of SREFCLK.
Transmit Working Serial Data. In SBI336 mode, the differential
transmit working serial data link (TPWRK/TNWRK) carries a
transmit 77.76 MHz SBI336 data stream to a downstream working
sink, in bit serial format, SBI336S.
In TelecomBus mode, TPWRK/TNWRK carries the transmit 77.76
MHz TelecomBus data stream to a downstream working sink, in bit
serial format.
Data on TPWRK/TNWRK is encoded in an 8B/10B format
extended from IEEE Std. 802.3. The 8B/10B character bit ‘a’ is
transmitted first and the bit ‘j’ is transmitted last.
TPWRK/TNWRK are nominally 777.6 Mbit/s data streams.
Transmit Protect Serial Data. In SBI336 mode, the differential
transmit protect serial data link (TPPROT/TNPROT) carries a
transmit 77.76 MHz SBI336 data stream to a downstream protect
sink, in bit serial format, SBI336S.
In TelecomBus mode, TPPROT/TNPROT carries the transmit
77.76 MHz TelecomBus data stream to a downstream protection
sink, in bit serial format.
Data on TPPROT/TNPROT is encoded in an 8B/10B format
extended from IEEE Std. 802.3. The 8B/10B character bit ‘a’ is
transmitted first and the bit ‘j’ is transmitted last.
TPPROT/TNPROT are nominally 777.6 Mbit/s data streams.
Transmit Serial SBI Frame Pulse. The transmit serial SBI frame
pulse signal (TC1FP) provides system timing of the transmit serial
interface.
TC1FP is set high to indicate that the C1 frame boundary 8B/10B
character has been serialized out on the transmit working serial
data link (TPWRK/TNWRK) and the transmit protection serial data
link (TPPROT/ TNPROT). TC1FP is output every 4 frame for SBI
mode without CAS and for TelecomBus mode. TC1FP is output
every 48 frames for SBI mode with CAS.
TC1FP is updated on the rising edge of SYSCLK.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 26
Document ID: PMC-2010883, Issue 2
Page 28
SBSLITE™ Telecom Standard Product Data Sheet
Preliminary
Pin Name Type
Pin
No.
Microprocessor Interface (30 Signals)
CSB Input M2
RDB Input M1
WRB Input M3
D[15]
D[14]
D[13]
D[12]
D[11]
D[10]
D[9]
D[8]
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
A[8]/TRS
A[7]
A[6]
A[5]
A[4]
A[3]
A[2]
A[1]
A[0]
ALE Input L2
I/O L4
N5
N6
P6
M6
L6
N7
M8
N8
L9
P10
M10
N10
L10
P11
M11
Input
N11
P12
M12
N13
N14
M13
M14
L14
L11
Function
Chip Select Bar. The active low chip select signal (CSB) controls
microprocessor access to registers in the SBSLITE device. CSB is
set low during SBSLITE Microprocessor Interface Port register
accesses. CSB is set high to disable microprocessor accesses.
If CSB is not required (i.e. register accesses controlled using RDB
and WRB signals only), CSB should be connected to an inverted
version of the RSTB input.
Read Enable Bar. The active low read enable bar signal (RDB)
controls microprocessor read accesses to registers in the SBSLITE
device. RDB is set low and CSB is also set low during SBSLITE
Microprocessor Interface Port register read accesses. The
SBSLITE drives the D[15:0] bus with the contents of the addressed
register while RDB and CSB are low.
Write Enable Bar. The active low write enable bar signal (WRB)
controls microprocessor write accesses to registers in the SBSLITE
device. WRB is set low and CSB is also set low during SBSLITE
Microprocessor Interface Port register write accesses. The
contents of D[15:0] are clocked into the addressed register on the
rising edge of WRB while CSB is low.
Microprocessor Data Bus. The bi-directional data bus, D[15:0] is
used during SBSLITE Microprocessor Interface Port register reads
and write accesses. D[15] is the most significant bit of the data
words and D[0] is the least significant bit.
Microprocessor Address Bus. The microprocessor address bus
(A[8:0]) selects specific Microprocessor Interface Port registers
during SBSLITE register accesses.
A[8] is also the Test Register Select (TRS) address pin and selects
between normal and test mode register accesses. TRS is set high
during test mode register accesses, and is set low during normal
mode register accesses.
Address Latch Enable. The address latch enable signal (ALE) is
active high and latches the address bus (A[11:0]) when it is set low.
The internal address latches are transparent when ALE is set high.
ALE allows the SBSLITE to interface to a multiplexed address/data
bus. ALE has an integral pull up resistor.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 27
Document ID: PMC-2010883, Issue 2
Page 29
SBSLITE™ Telecom Standard Product Data Sheet
Preliminary
Pin Name Type
Pin
No.
INTB Open
Drain
Output
General Function (9 Signals)
SYSCLK Input A12
SREFCLK Input B12
ICMP Input B10
G12
Function
Interrupt Request Bar. The active low interrupt enable signal
(INTB) output goes low when an SBSLITE interrupt source is active
and that source is unmasked. INTB returns high when the interrupt
is acknowledged via an appropriate register access. INTB is an
open drain output.
SBI System Clock. The 77 MHz SBI reference clock signal,
SYSCLK, is the master clock for the SBSLITE device. SYSCLK is
a 77.76 MHz clock, with a nominal 50% duty cycle. RC1FP,
OCMP and RWSEL are sampled on the rising edge of SYSCLK.
TC1FP is updated on the rising edge of SYSCLK.
SBI Reference Clock. The SBI reference clock, SREFCLK, is a
reference for the incoming and outgoing SBI bus and TelecomBus
interfaces. SREFCLK is a 77.76 MHz clock with a nominal 50%
duty cycle. IC1FP, IDATA[7:0], IDP, IPL, IV5, ITPL, ITAIS,
JUST_REQ and ICMP are sampled on the rising edge of
SREFCLK. OC1FP, ODATA[7:0], ODP, OPL, OV5, OTPL, OTAIS
and JUST_REQ are updated on the rising edge of SYSCLK.
This signal should be tied to SYSCLK.
Incoming Connection Memory Page. The incoming connection
memory page select signal, ICMP, controls the selection of the
connection memory page in the Incoming Memory Switch Unit,
IMSU. When ICMP is set high, connection memory page 1 is
selected. When ICMP is set low, connection memory page 0 is
selected.
The byte location during which ICMP is sampled is dependant on
the mode of operation.
4-Frame SBI336 mode:
ICMP is sampled at the C1 byte position of the incoming bus on the
first frame of the 4-frame multiframe (marked by IC1FP). Changes
to the connection memory page selection is synchronized to the
frame boundary of the next four frame multiframe.
48-Frame SBI336 mode:
ICMP is sampled at the C1 byte position of the incoming bus on the
first frame of the 48-frame multiframe (marked by IC1FP).
Changes to the connection memory page selection is synchronized
to the frame boundary of the next 48-frame multiframe.
TelecomBus mode:
ICMP is sampled at the C1 byte position of every frame on the
incoming bus (marked by IC1FP). Changes to the connection
memory pate selection are synchronized to the frame boundary of
the next frame.
CMP is sampled on the rising edge of SREFCLK.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 28
Document ID: PMC-2010883, Issue 2
Page 30
SBSLITE™ Telecom Standard Product Data Sheet
Preliminary
Pin Name Type
Pin
No.
OCMP Input D11
RWSEL Input N3
IUSER2 Input L5
OUSER2 Output K14
RSTB Input P3
Function
Outgoing Connection Memory Page. The outgoing connection
memory page select signal, OCMP, controls the selection of the
connection memory page in the Outgoing Memory Switch Unit,
OMSU. When OCMP is set high, connection memory page 1 is
selected. When OCMP is set low, connection memory page 0 is
selected.
The byte location during which OCMP is sampled is dependant on
the mode of operation.
4-Frame SBI336 mode:
OCMP is sampled at the C1 byte position of the receive bus on the
first frame of the 4-frame multiframe (marked by RC1FP).
Changes to the connection memory page selection is synchronized
to the frame boundary of the next four frame multiframe.
48-Frame SBI336 mode:
OCMP is sampled at the C1 byte position of the receive bus on the
first frame of the 48-frame multiframe (marked by RC1FP).
Changes to the connection memory page selection is synchronized
to the frame boundary of the next 48-frame multiframe.
TelecomBus mode:
OCMP is sampled at the C1 byte position of every frame on the
receive bus (marked by RC1FP). Changes to the connection
memory pate selection are synchronized to the frame boundary of
the next frame.
OCMP is sampled on the rising edge of SYSCLK.
Receive Working Serial Data Select. The receive working serial
data select signal, RWSEL, selects between sourcing outgoing
data, ODATA[7:0], from the receive working serial data link,
RPWRK/RNWRK, or the receive protect serial data link,
RPPROT/RNPROT. When RWSEL is set high, the working serial
bus is selected. When RWSEL is set low, the protect serial bus is
selected. RWSEL is sampled at the C1 byte location as defined by
the receive serial interface frame pulse signal, RC1FP. Changes
to the selection of the working and protect serial streams are
synchronized to the SBI frame boundary of the next frame.
RWSEL is sampled on the rising edge of SYSCLK.
Input In-band Link User Signal. The input in-band link user
signal, IUSER2, provides external control over one of the bits in the
in-band link. The USER[2] bit in the header of the in-band
signaling channel of both the working and protection serial links will
reflect the state of this input.
IUSER2 an asynchronous signal and is internally synchronized to
SYSCLK.
Output In-Band Link User Signal. The output in-band link user
signal, OUSER2, reflects the state of the USER[2] bit in the header
of the in-band signaling channel of either the working or the
protection serial link, whichever is active.
OUSER2 is an asynchronous output.
Reset Enable Bar. The active low reset signal, RSTB, provides an
asynchronous SBSLITE reset. RSTB is a Schmitt triggered input
with an integral pull-up resistor.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 29
Document ID: PMC-2010883, Issue 2
Page 31
SBSLITE™ Telecom Standard Product Data Sheet
Preliminary
Pin Name Type
Pin
No.
JTAG Interface (5 Signals)
TCK Input H13
TMS Input J11
TDI Input J14
TDO Tristate H12
TRSTB Input J12
Analog Reference Resistors (2 Signals)
RES
RESK Analog
Analog Test Bus (2 Signals)
ATB0 Analog F4
Analog
Input
Input
C2
B2
Function
Test Clock. The JTAG test clock signal, TCK, provides timing for
test operations that are carried out using the IEEE P1149.1 test
access port.
Test Mode Select. The JTAG test mode select signal, TMS,
controls the test operations that are carried out using the IEEE
P1149.1 test access port. TMS is sampled on the rising edge of
TCK. TMS has an integral pull-up resistor.
Test Data Input. The JTAG test data input signal, TDI, carries test
data into the SBSLITE via the IEEE P1149.1 test access port. TDI
is sampled on the rising edge of TCK. TDI has an integral pull-up
resistor.
Test Data Output. The JTAG test data output signal, TDO, carries
test data out of the SBSLITE via the IEEE P1149.1 test access
port. TDO is updated on the falling edge of TCK. TDO is a tri-state
output which is inactive except when scanning of data is in
progress.
Test Reset Bar. The active low JTAG test reset signal, TRSTB,
provides an asynchronous SBSLITE test access port reset via the
IEEE P1149.1 test access port. TRSTB is a Schmitt triggered input
with an integral pull-up resistor.
Note that when TRSTB is not being used, it must be connected to
the RSTB input.
Reference Resistor Connection (RES). An off-chip 3.16kΩ ±1%
resistor is connected between this positive resistor reference pin
and a Kelvin ground pin, RESK. An on-chip negative feedback path
will force the 0.8V VREF Voltage onto RES, therefore forcing
252uA of current to flow through the resistor.
Reference Resistor Connection (RESK). An off-chip 3.16kΩ ±1%
resistor is connected between the positive resistor reference pin,
RESK, and this Kelvin ground pin. An on-chip negative feedback
path will force the 0.8V VREF Voltage onto RESK, therefore forcing
252uA of current to flow through the resistor.
Analog test pin (ATB0). This pin is used for PMC-Sierra validation
and testing. This pin must be grounded.
ATB1 Analog F3
Analog High Voltage Power (5 Signals)
CSU_AVDH Power H1
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 30
Document ID: PMC-2010883, Issue 2
Analog test pin (ATB1). This pin is used for PMC-Sierra validation
and testing. This pin must be grounded.
CSU Analog Power (CSU_AVDH). This pin should be connected
to a well-decoupled +3.3 V DC supply.
Page 32
SBSLITE™ Telecom Standard Product Data Sheet
Preliminary
Pin Name Type
Pin
No.
AVDH[2]
AVDH[1]
AVDH[0]
AVDQ Power H3
Analog Low Voltage Power (4 Signals)
AVDL[3]
AVDL[2]
AVDL[1]
AVDL[0]
Digital Core Power (8 Signals)
DVDDI[7]
DVDDI[6]
DVDDI[5]
DVDDI[4]
DVDDI[3]
DVDDI[2]
DVDDI[1]
DVDDI[0]
Digital I/O Power (14 Signals)
DVDDO[13]
DVDDO[12]
DVDDO[11]
DVDDO[10]
DVDDO[9]
DVDDO[8]
DVDDO[7]
DVDDO[6]
DVDDO[5]
DVDDO[4]
DVDDO[3]
DVDDO[2]
DVDDO[1]
DVDDO[0]
Digital I/O Quiet Power (3 Signals)
DVDDQ[2:0] Power P8
Power C1
D4
E3
Power
Power K2
Power N1
G4
H4
J3
J4
L1
P5
P9
L13
G13
A11
A5
N2
M4
P7
N9
P13
H14
E13
A13
A9
C8
C6
A3
A2
J13
C10
Function
Analog Power (AVDH[2:0]). These pins should be connected to a
well-decoupled +3.3 V DC supply.
Analog Quiet Power (AVDQ). This pin should be connected to a
well decoupled +3.3 V DC supply.
Analog Power (AVDL[3:0]). These pins should be connected to a
well-decoupled +1.8 V DC supply. Each AVDL pin requires
individual filtering.
Digital Core Power (DVDDI[7:0]). The digital core power pins
should be connected to a well-decoupled +1.8 V DC supply.
Digital I/O Power (DVDDO[13:0]). The digital I/O power pins
should be connected to a well-decoupled +3.3 V DC supply.
Digital I/O Quite Power (DVDDQ[2:0]). The digital I/O quite power
pins should be connected to a well-decoupled +3.3 V DC supply.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 31
Document ID: PMC-2010883, Issue 2
Page 33
SBSLITE™ Telecom Standard Product Data Sheet
Preliminary
Pin Name Type
Pin
Function
No.
Ground (35 Signals)
VSS[34]
VSS[33]
VSS[32]
VSS[31]
VSS[30]
VSS[29]
VSS[28]
VSS[27]
VSS[26]
VSS[25]
VSS[24]
VSS[23]
VSS[22]
VSS[21]
VSS[20]
VSS[19]
VSS[18]
VSS[17]
VSS[16]
VSS[15]
VSS[14]
VSS[13]
VSS[12]
VSS[11]
VSS[10]
VSS[9]
VSS[8]
VSS[7]
VSS[6]
VSS[5]
VSS[4]
VSS[3]
VSS[2]
VSS[1]
VSS[0]
GND Thermal
NC No Connect K13 The No Connect pin must be left floating.
Notes on Pin Description
1. All SBSLITE inputs and bi-directionals except the LVDS links present minimum capacitive loading and
operate at TTL (Vdd reference) logic levels.
2. Inputs RSTB, ALE, TMS, TDI and TRSTB have internal pull-up resistors.
3. All SBSLITE outputs have 8 mA drive capability.
4. The DVDDI and AVDL power pins are not internally connected to each other. Failure to connect these
pins externally may cause malfunction or damage to the SBSLITE.
5. The AVDH, AVDQ, CSU_AVDH, DVDDO and DVDDQ power pins are not internally connected to each
other. Failure to connect these pins externally may cause malfunction or damage to the SBSLITE.
6. The DVDDI, DVDDO, DVDDQ, AVDH, AVDQ, CSU_AVDH and AVDL power pins all share a common
ground.
Ground B1
D3
E4
G3
H2
J1
J2
K1
K3
K4
L3
P2
P4
M5
L7
M7
L8
M9
N12
L12
K11
H11
G14
E12
B13
B11
C11
A10
D10
B9
A7
B6
C5
B4
B3
G7
Vias
G8
H7
H8
Ground (VSS[34:0]). The ground pins, VSS[34:0], should be
connected to GND.
The Thermal Vias (GND) pins are used to improve thermal
conductance of the device package. They should be connected to
the PCB ground plane. The GND pins are not electrically
connected to the other ground pins of the package.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 32
Document ID: PMC-2010883, Issue 2
Page 34
SBSLITE™ Telecom Standard Product Data Sheet
Preliminary
7. To prevent damage to the SBSLITE and to ensure proper operation, power must be applied
simultaneously to all 3.3 V power pins followed by power to all the 1.8 V power pins followed by input
pins driven by signals.
8. To prevent damage to the SBSLITE, power must first be removed from input pins followed by the
removal of power from all the 1.8 V power supply pins followed by the simultaneous removal of power
from all the 3.3 V power pins.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 33
Document ID: PMC-2010883, Issue 2
Page 35
10 Functional Description
10.1 SBI Bus Data Formats
The 19.44 MHz SBI bus is a multi-point to multi-point bus. Since each SBS SBI interface
handles the full SBI bus capacity, it will be more common for a single SBS to talk to multiple
devices over the SBI bus, but there is nothing in the SBS that would prevent the SBS from
sharing an SBI bus with other SBI devices.
10.1.1 SBI Multiplexing Structure
The SBI structure uses a locked SONET/SDH structure to fix the position of the TU-3 relative to
the STS-3/STM-1. The SBI is also of fixed frequency and alignment as determined by the
reference clock (SREFCLK19) and frame indicator signal (IC1FP). Frequency deviations are
compensated by adjusting the location of the T1/E1/DS3/E3/TVT1.5/TVT2 channels using
floating tributaries as determined by the V5 indicator and payload signals (IV5[x] and IPL[x]).
TVTs also allow for synchronous operation where SONET/SDH tributary pointers are carried
within the SBI structure in place of the V5 indicator and payload signals (IV5[x] and IPL[x]).
Fractional links use as many bytes as required within a given synchronous payload envelope
(SPE) using the payload signals to indicate bytes carrying valid data.
SBSLITE™ Telecom Standard Product Data Sheet
Preliminary
Table 1 shows the bus structure for carrying T1, E1, TVT1.5, TVT2, DS3, E3 and Fractional
tributaries in a SDH STM-1 like format. Up to 84 T1s, 63 E1s, 84 TVT1.5s, 63 TVT2s, 3 DS3s,
3 E3s or 3 Fractional rate links are carried within the octets labeled SPE1, SPE2 and SPE3 in
columns 16-270. All other octets are unused and are of fixed position. The frame signal (IC1FP)
occurs during the octet labeled C1 in Row 1 column 7.
The multiplexed links are separated into three SPEs called SPE1, SPE2 and SPE3. Each envelope
carries up to 28 T1s, 21 E1, 28 TVT1.5s, 21 TVT2s, a DS3, an E3 or a Fractional link. SPE1
carries the T1s numbered 1,1 through 1,28, E1s numbered 1,1 through 1,21, DS3 number 1,1, E3
number 1,1 or Fractional link 1,1. SPE2 carries T1s numbered 2,1 through 2,28, E1s numbered
2,1 through 2,21, DS3 number 2,1, E3 number 2,1 or Fractional link 2,1. SPE3 carries T1s
numbered 3,1 through 3,28, E1s numbered 3,1 through 3,21, DS3 number 3,1, E3 number 3,1 or
Fractional link 3,1. TVT1.5s are numbered the same as T1 tributaries and TVT2s are numbered
the same as E1 tributaries.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 34
Document ID: PMC-2010883, Issue 2
Page 36
SBSLITE™ Telecom Standard Product Data Sheet
Table 1 Structure for Carrying Multiplexed Links
SBI Column
1 6 7 8 15 16 17 18 19 268 269 270
Row 1
-
-
2
- - - - - SPE1 SPE2 SPE3 SPE1 SPE1 SPE2 SPE3
9
-C1-
•••
---
•••
- SPE1 SPE2 SPE3 SPE1
•••
- SPE1 SPE2 SPE3 SPE1
•••
SPE1 SPE2 SPE3
•••
SPE1 SPE2 SPE3
•••
1 233 56667 909090
SPE Column
The mappings for each link type are rigidly defined, however the mix of links transported across
the bus at any one time is flexible. Each SPE, comprising 85 columns numbered 6 through 90,
operates independently allowing a mix of T1s, E1s, TVT1.5s, TVT2s, DS3s, E3s or Fractional
links. For example, SPE1 could transport a single DS3, SPE2 could transport a single E3 and
SPE3 could transport either 28 T1s or 21 E1s. Each SPE is restricted to carrying a single tributary
type. SBI columns 16-18 are unused for T1, E1, TVT1.5 and TVT2 tributaries.
Preliminary
Tributary Numbering
Tributary numbering for T1 and E1 uses the SPE number, followed by the tributary number
within that SPE and are numbered sequentially. Table 2 and Table 3 show the T1 and E1 column
numbering and relates the tributary number to the SPE column numbers and overall SBI column
structure. Numbering for DS3 or E3 follows the same naming convention even though there is
only one DS3 or E3 per SPE. TVT1.5s and TVT2s follow the same numbering conventions as T1
and E1 tributaries respectively. SBI columns 16-18 are unused for T1, E1, TVT1.5 and TVT2
tributaries.
Table 2 T1/TVT1.5 Tributary Column Numbering
T1# SPE1 Column SPE2 Column SPE3 Column SBI Column
1,1 7,35,63 19,103,187
2,1 7,35,63 20,104,188
3,1 7,35,63 21,105,189
1,2 8,36,64 22,106,190
2,2 8,36,64 23,107,191
•••
1,28 34,62,90 100,184,268
2,28 34,62,90 101,185,269
3,28 34,62,90 102,186,270
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 35
Document ID: PMC-2010883, Issue 2
Page 37
Table 3 E1/TVT2 Tributary Column Numbering
E1# SPE1 Column SPE2 Column SPE3 Column SBI Column
1,1 7,28,49,70 19,82,145,208
2,1 7,28,49,70 20,83,146,209
3,1 7,28,49,70 21,84,147,210
1,2 8,29,50,71 22,85,148,211
2,2 8,29,50,71 23,86,149,212
•••
1,21 27,48,69,90 79,142,205,268
2,21 27,48,69,90 80,143,206,269
3,21 27,48,69,90 81,144,207,270
10.1.2 SBI Timing Master Modes
The SBI is a synchronous bus which is timed to a reference 19.44 MHz clock and a 2 KHz frame
pulse (8 KHz is easily derived from the 2 KHz and 19.44 MHz clock). All sources and sinks of
data on this bus are timed to the reference clock and frame pulse.
SBSLITE™ Telecom Standard Product Data Sheet
Preliminary
The data format on the data bus allows for compensating between clock differences on the PHY,
SBI and Link Layer devices. This is achieved by floating data structures within the SBI format.
Timing is communicated across the SBI bus by floating data structures within the bus. Payload
indicator signals in the SBI control the position of the floating data structure and therefore the
timing. When sources are running faster than the SBI the floating payload structure is advanced
by an octet be passing an extra octet in the V3 octet locations (H3 octet for DS3 and E3
mappings). When the source is slower than the SBI the floating payload is retarded by leaving the
octet after the V3 or H3 octet unused. Both these rate adjustments are indicated by the SBI
control signals.
On the Drop bus, all timing is sourced from the PHY and is passed onto the Link Layer device by
the arrival rate of data over the SBI.
On the Add bus, timing can be controlled by either the PHY or the Link Layer device by
controlling the payload and by making justification requests. When the Link Layer device is the
timing master the PHY device gets its transmit timing information from the arrival rate of data
across the SBI. When the PHY device is the timing master it signals the Link Layer device to
speed up or slow down with justification request signals. The PHY timing master indicates a
speedup request to the Link Layer by asserting the justification request signal high during the V3
or H3 octet. When this is detected by the Link Layer it will advance the channel by inserting data
in the next V3 or H3 octet as described above. The PHY timing master indicates a slowdown
request to the Link Layer by asserting the justification request signal high during the octet after
the V3 or H3 octet. When detected by the Link Layer it will retard the channel by leaving the
octet following the next V3 or H3 octet unused. Both advance and retard rate adjustments take
place in the frame or multi-frame following the justification request.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 36
Document ID: PMC-2010883, Issue 2
Page 38
The SBI bus supports a synchronous SBI mode for T1 and E1 links. In this mode the DS0s or
timeslots within the T1 or E1 tributaries are fixed to the locations shown in the T1 and E1
mappings. Effectively synchronous mode locks the V5 in the octet following the V1 octet and
does not allow the tributaries to float relative to SREFCLK19.
10.1.3 SBI Link Rate Information
The SBI bus provides a method for carrying link rate information. This is optional on a per
channel basis. Two methods are specified, one for T1 and E1 channels and the second for DS3
and E3 channels. Link rate information is not available for TVTs. These methods use the
reference 19.44 MHz SBI clock and the IC1FP frame synchronization signal to measure channel
clock ticks and clock phase for transport across the bus.
The T1 and E1 method allows for a count of the number of T1 or E1 rising clock edges between
two IC1FP frame pulses. This count is encoded in ClkRate[1:0] to indicate that the nominal
number of clocks, one more than nominal or one less than nominal should be generated during
the IC1FP period. This method also counts the number of 19.44 MHz clock rising edges after
sampling IC1FP high to the next rising edge of the T1 or E1 clock, giving the ability to control
the phase of the generated clock. The link rate information passed across the SBI bus via the V4
octet and is shown in Table 4. Table 5 shows the encoding of the clock count, ClkRate[1:0],
passed in the link rate octet.
SBSLITE™ Telecom Standard Product Data Sheet
Preliminary
Table 4 T1/E1 Link Rate Information
C1FP
REFCLK
T1/E1 CLK
Clock Count
Link Rate Octet Bit # 7 6 5:4 3:0
T1/E1 Format ALM 0 ClkRate[1:0] Phase[3:0]
Table 5 T1/E1 Clock Rate Encoding
ClkRate[1:0] T1 Clocks / 2 KHz E1 Clocks / 2 KHz
“00” – Nominal 772 1024
“01” – Fast 773 1025
“1x” – Slow 771 1023
•••
•••
•••
Phase
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 37
Document ID: PMC-2010883, Issue 2
Page 39
SBSLITE™ Telecom Standard Product Data Sheet
Preliminary
The DS3 and E3 method for transferring link rate information across the SBI passes the encoded
count of DS3/E3 clocks between C1FP pulses in the same method used for T1/E1 tributaries, but
does not pass any phase information. The other difference from T1/E1link rate is that
ClkRate[1:0] indicates whether the nominal number of clocks are generated or if four fewer or
four extra clocks are generated during the C1FP period. The format of the DS3/E3 link rate octet
is shown in Table 6. This is passed across the SBI via the Linkrate octet which follows the H3
octet in the column, see Table 12 and Table 15. Table 7 shows the encoding of the clock count,
ClkRate[1:0], passed in the link rate octet.
Table 6 DS3/E3 Link Rate Information
Link Rate Octet Bit # 7 6 5:4 3:0
DS3/E3 Format ALM 0 ClkRate[1:0] Unused
Table 7 DS3/E3 Clock Rate Encoding
ClkRate[1:0] DS3 Clocks / 2 KHz E3 Clocks / 2 KHz
“00” – Nominal 22368 17184
“01” – Fast 22372 17188
“1x” – Slow 22364 17180
10.1.4 Alarms
This specification provides a method for transferring alarm conditions across the SBI bus. This is
optional on a per tributary basis and is valid for T1, E1, DS3, E3 tributaries but not valid for
transparent VTs nor Fractional links.
Table 4 and Table 6 show the alarm indication bit, ALM, as bit 7 of the Link Rate Octet. Devices
which do not support alarm indications should set this bit to 0. When not enabled the value of this
bit must be ignored by the receiving device.
The presence of an alarm condition is indicated by the ALM bit set high in the Link Rate Octet.
The absence of an alarm condition is indicated by the ALM bit set low in the Link Rate Octet.
The ALM bit is transparent to the SBS.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 38
Document ID: PMC-2010883, Issue 2
Page 40
10.1.5 T1 Tributary Mapping
Table 8 shows the format for mapping 84 T1s within the SPE octets. The DS0s and framing bits
within each T1 are easily located within this mapping for channelized T1 applications. It is
acceptable for the framing bit to not carry a valid framing bit on the Add Bus since the physical
layer device will provide this information. Unframed T1s use the exact same format for mapping
84 T1s into the SBI except that the T1 tributaries need not align with the frame bit and DS0
locations. The V1,V2 and V4 octets are not used to carry T1 data and are either reserved or used
for control across the interface. When enabled, the V4 octet is the Link Rate octet of Tables 1 and
3. It carries alarm and clock phase information across the SBI bus. The V1 and V2 octets are
unused and should be ignored by devices listening to the SBI bus. The V5 and R octets do not
carry any information and are fixed to a zero value. The V3 octet carries a T1 data octet but only
during rate adjustments as indicated by the V5 indicator signals, IV5 and OV5, and payload
signals, IPL and OPL. The PPSSSSFR octets carry channel associated signaling (CAS) bits and
the T1 framing overhead. The DS0 octets are the 24 DS0 channels making up the T1 link.
The V1,V2,V3 and V4 octets are fixed to the locations shown. All the other octets, shown shaded
for T1#1,1, float within the allocated columns maintaining the same order and moving a
maximum of one octet per 2 KHz multi-frame. The position of the floating T1 is identified via the
V5 Indicator signals, IV5 and OV5, which locate the V5 octet. When the T1 tributary rate is faster
than the SBI nominal T1 tributary rate, the T1 tributary is shifted ahead by one octet which is
compensated by sending an extra octet in the V3 location. When the T1 tributary rate is slower
than the nominal SBI tributary rate the T1 tributary is shifted by one octet which is compensated
by inserting a stuff octet in the octet immediately following the V3 octet and delaying the octet
that was originally in that position.
SBSLITE™ Telecom Standard Product Data Sheet
Preliminary
Table 8 T1 Framing Format
COL # T1#1,1 T1#2,1-3,28 T1#1,1 T1#2,1-3,28 T1#1,1 T1#2,1-3,28
ROW # 1-18 19 20-102 103 104-186 187 188-270
1 Unused V1 V1 V5 - PPSSSSFR -
2 Unused DS0#1 - DS0#2 - DS0#3 -
3 Unused DS0#4 - DS0#5 - DS0#6 -
4 Unused DS0#7 - DS0#8 - DS0#9 -
5 Unused DS0#10 - DS0#11 - DS0#12 -
6 Unused DS0#13 - DS0#14 - DS0#15 -
7 Unused DS0#16 - DS0#17 - DS0#18 -
8 Unused DS0#19 - DS0#20 - DS0#21 -
9 Unused DS0#22 - DS0#23 - DS0#24 -
1 Unused V2 V2 R - PPSSSSFR -
2 Unused DS0#1 - DS0#2 - DS0#3 -
3 Unused DS0#4 - DS0#5 - DS0#6 -
4 Unused DS0#7 - DS0#8 - DS0#9 -
5 Unused DS0#10 - DS0#11 - DS0#12 -
6 Unused DS0#13 - DS0#14 - DS0#15 -
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 39
Document ID: PMC-2010883, Issue 2
Page 41
SBSLITE™ Telecom Standard Product Data Sheet
Preliminary
COL # T1#1,1 T1#2,1-3,28 T1#1,1 T1#2,1-3,28 T1#1,1 T1#2,1-3,28
ROW # 1-18 19 20-102 103 104-186 187 188-270
7 Unused DS0#16 - DS0#17 - DS0#18 -
8 Unused DS0#19 - DS0#20 - DS0#21 -
9 Unused DS0#22 - DS0#23 - DS0#24 -
1 Unused V3 V3 R - PPSSSSFR -
2 Unused DS0#1 - DS0#2 - DS0#3 -
3 Unused DS0#4 - DS0#5 - DS0#6 -
4 Unused DS0#7 - DS0#8 - DS0#9 -
5 Unused DS0#10 - DS0#11 - DS0#12 -
6 Unused DS0#13 - DS0#14 - DS0#15 -
7 Unused DS0#16 - DS0#17 - DS0#18 -
8 Unused DS0#19 - DS0#20 - DS0#21 -
9 Unused DS0#22 - DS0#23 - DS0#24 -
1 Unused V4 V4 R - PPSSSSFR -
2 Unused DS0#1 - DS0#2 - DS0#3 -
3 Unused DS0#4 - DS0#5 - DS0#6 -
4 Unused DS0#7 - DS0#8 - DS0#9 -
5 Unused DS0#10 - DS0#11 - DS0#12 -
6 Unused DS0#13 - DS0#14 - DS0#15 -
7 Unused DS0#16 - DS0#17 - DS0#18 -
8 Unused DS0#19 - DS0#20 - DS0#21 -
9 Unused DS0#22 - DS0#23 - DS0#24 -
The P1P0S1S2S3S4FR octet carries T1 framing in the F bit and channel associated signaling in the
and S1S2S3S4bits. Channel associated signaling is optional. The R bit is reserved and is set to
P
1P0
0. The P
bits are used to indicate the phase of the channel associated signaling and the S1S2S3S
1P0
bits are the channel associated signaling bits for the 24 DS0 channels in the T1. Table 9 shows the
channel associated signaling bit mapping and how the phase bits locate the sixteen state CAS
mapping as well as T1 frame alignment for super frame and extended superframe formats. When
using four state CAS then the signaling bits are A1-A24, B1-B24, A1-B24, B1-B24 in place of
are A1-A24, B1-B24, C1-C24, D1-D24. When using 2 state CAS there are only A1-A24
signaling bits.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 40
Document ID: PMC-2010883, Issue 2
4
Page 42
SBSLITE™ Telecom Standard Product Data Sheet
Table 9 T1 Channel Associated Signaling Bits
SF ESF
S
1
A1 A2 A3 A4 F1 M1 00
A5 A6 A7 A8 S1 C1 00
A9 A10 A11 A12 F2 M2 00
A13 A14 A15 A16 S2 F1 00
A17 A18 A19 A20 F3 M3 00
A21 A22 A23 A24 S3 C2 00
B1 B2 B3 B4 F4 M4 01
B5 B6 B7 B8 S4 F2 01
B9 B10 B11 B12 F5 M5 01
B13 B14 B15 B16 S5 C3 01
B17 B18 B19 B20 F6 M6 01
B21 B22 B23 B24 S6 F3 01
C1 C2 C3 C4 F1 M7 10
C5 C6 C7 C8 S1 C4 10
C9 C10 C11 C12 F2 M8 10
C13 C14 C15 C16 S2 F4 10
C17 C18 C19 C20 F3 M9 10
C21 C22 C23 C24 S3 C5 10
D1 D2 D3 D4 F4 M10 11
D5 D6 D7 D8 S4 F5 11
D9 D10 D11 D12 F5 M11 11
D13 D14 D15 D16 S5 C6 11
D17 D18 D19 D20 F6 M12 11
D21 D22 D23 D24 S6 F6 11
S
2
S
3
S
4
FFP
Preliminary
1 P0
T1 tributary asynchronous timing is compensated via the V3 octet as described in Section 10.1.2.
T1 tributary link rate adjustments are optionally passed across the SBI via the V4 octet as
described in section 10.1.3. T1 tributary alarm conditions are optionally passed across the SBI
bus via the link rate octet in the V4 location as described in Sections 10.1.3 and 10.1.4.
The SBI bus allows for a synchronous T1 mode of operation. In this mode the T1 tributary
mapping is fixed to that shown in Table 8 and rate justifications are not possible using the V3
octet. The clock rate information within the link rate octet in the V4 location is not used in
synchronous mode.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 41
Document ID: PMC-2010883, Issue 2
Page 43
10.1.6 E1 Tributary Mapping
Table 10 shows the format for mapping 63 E1s within the SPE octets. The timeslots and framing
bits within each E1 are easily located within this mapping for channelized E1 applications. It is
acceptable for the framing bits to not carry valid framing information on the Add Bus since the
physical layer device will provide this information. Unframed E1s use the exact same format for
mapping 63 E1s into the SBI except that the E1 tributaries need not align with the timeslot
locations associated with channelized E1 applications. The V1,V2 and V4 octets are not used to
carry E1 data and are either reserved used for control information across the interface. When
enabled, the V4 octet carries clock phase information across the SBI. The V1 and V2 octets are
unused and should be ignored by devices listening to the SBI bus. The V5 and R octets do not
carry any information and are fixed to a zero value. The V3 octet carries an E1 data octet but
only during rate adjustments as indicated by the V5 indicator signals, IV5 and OV5, and payload
signals, IPL and OPL. The PP octets carry channel associated signaling phase information and E1
frame alignment. TS#0 through TS#31 make up the E1 channel.
The V1,V2,V3 and V4 octets are fixed to the locations shown. All the other octets, shown shaded
for E1#1,1, float within the allocated columns maintaining the same order and moving a
maximum of one octet per 2 KHz multi-frame. The position of the floating E1 is identified via
the V5 Indicator signals, IV5 and OV5, which locate the V5 octet. When the E1 tributary rate is
faster than the E1 tributary nominal rate, the E1 tributary is shifted ahead by one octet which is
compensated by sending an extra octet in the V3 location. When the E1 tributary rate is slower
than the nominal rate the E1 tributary is shifted by one octet which is compensated by inserting a
stuff octet in the octet immediately following the V3 octet and delaying the octet that was
originally in that position.
SBSLITE™ Telecom Standard Product Data Sheet
Preliminary
Table 10 E1 Framing Format
COL # E1#1,1 #2,1-3,21 E1#1,1 #2,1-3,21 E1#1,1 #2,1-3,21 E1#1,1 #2,1-3,21
ROW
1 Unused V1 V1 V5 - PP - TS#0 -
2 Unused TS#1 - TS#2 - TS#3 - TS#4 -
3 Unused TS#5 - TS#6 - TS#7 - TS#8 -
4 Unused TS#9 - TS#10 - TS#11 - TS#12 -
5 Unused TS#13 - TS#14 - TS#15 - TS#16 -
6 Unused TS#17 - TS#18 - TS#19 - TS#20 -
7 Unused TS#21 - TS#22 - TS#23 - TS#24 -
8 Unused TS#25 - TS#26 - TS#27 - TS#28 -
9 Unused TS#29 - TS#30 - TS#31 - R -
1 Unused V2 V2 R - PP - TS#0 -
2 Unused TS#1 - TS#2 - TS#3 - TS#4 -
3 Unused TS#5 - TS#6 - TS#7 - TS#8 -
4 Unused TS#9 - TS#10 - TS#11 - TS#12 -
5 Unused TS#13 - TS#14 - TS#15 - TS#16 -
6 Unused TS#17 - TS#18 - TS#19 - TS#20 -
1-18 19 20-81 82 83-144 145 146-207 208 209-270
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 42
Document ID: PMC-2010883, Issue 2
Page 44
SBSLITE™ Telecom Standard Product Data Sheet
Preliminary
COL # E1#1,1 #2,1-3,21 E1#1,1 #2,1-3,21 E1#1,1 #2,1-3,21 E1#1,1 #2,1-3,21
ROW
7 Unused TS#21 - TS#22 - TS#23 - TS#24 -
8 Unused TS#25 - TS#26 - TS#27 - TS#28 -
9 Unused TS#29 - TS#30 - TS#31 - R -
1 Unused V3 V3 R - PP - TS#0 -
2 Unused TS#1 - TS#2 - TS#3 - TS#4 -
3 Unused TS#5 - TS#6 - TS#7 - TS#8 -
4 Unused TS#9 - TS#10 - TS#11 - TS#12 -
5 Unused TS#13 - TS#14 - TS#15 - TS#16 -
6 Unused TS#17 - TS#18 - TS#19 - TS#20 -
7 Unused TS#21 - TS#22 - TS#23 - TS#24 -
8 Unused TS#25 - TS#26 - TS#27 - TS#28 -
9 Unused TS#29 - TS#30 - TS#31 - R -
1 Unused V4 V4 R - PP - TS#0 -
2 Unused TS#1 - TS#2 - TS#3 - TS#4 -
3 Unused TS#5 - TS#6 - TS#7 - TS#8 -
4 Unused TS#9 - TS#10 - TS#11 - TS#12 -
5 Unused TS#13 - TS#14 - TS#15 - TS#16 -
6 Unused TS#17 - TS#18 - TS#19 - TS#20 -
7 Unused TS#21 - TS#22 - TS#23 - TS#24 -
8 Unused TS#25 - TS#26 - TS#27 - TS#28 -
9 Unused TS#29 - TS#30 - TS#31 - R -
1-18 19 20-81 82 83-144 145 146-207 208 209-270
When using CAS, TS#16 carries the ABCD signaling bits and the timeslots 17 through 31 are
renumbered 16 through 30. The PP octet is 0h for all frames except for the frame which carries
the CAS for timeslots 15/30 at which time the PP octet is C0h. The first octet of the CAS multiframe, RRRRRRRR, is reserved and should be ignored by the receiver when CAS signaling is
enabled. Table 11 shows the format of timeslot 16 when carrying channel associated signaling.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 43
Document ID: PMC-2010883, Issue 2
Page 45
SBSLITE™ Telecom Standard Product Data Sheet
Table 11 E1 Channel Associated Signaling Bits
TS#16[7:4] TS#16[3:0] PP
RRRR RRRR 00
ABCD1 ABCD16 00
ABCD2 ABCD17 00
ABCD3 ABCD18 00
ABCD4 ABCD19 00
ABCD5 ABCD20 00
ABCD6 ABCD21 00
ABCD7 ABCD22 00
ABCD8 ABCD23 00
ABCD9 ABCD24 00
ABCD10ABCD2500
ABCD11ABCD2600
ABCD12ABCD2700
ABCD13ABCD2800
ABCD14ABCD2900
ABCD15ABCD30C0
Preliminary
E1 tributary asynchronous timing is compensated via the V3 octet as described in section 10.1.2.
E1 tributary link rate adjustments are optionally passed across the SBI via the V4 octet as
described in section 10.1.3. E1 tributary alarm conditions are optionally passed across the SBI
bus via the link rate octet in the V4 location as described in Sections 10.1.3 and 10.1.4.
The SBI bus allows for a synchronous E1 mode of operation. In this mode the E1 tributary
mapping is fixed to that shown in Table 10 and rate justifications are not possible using the V3
octet. The clock rate information within the link rate octet in the V4 location is not used in
synchronous mode.
10.1.7 DS3 Tributary Mapping
Table 12 shows a DS3 tributary mapped within the first SPE, SPE1. The V5 indicator pulse
identifies the V5 octet. The DS3 framing format does not follow an 8 KHz frame period so the
floating DS3 multi-frame located by the V5 indicator, shown in heavy border grey region in Table
12, will jump around relative to the H1 frame on every pass. In fact the V5 indicator will often be
asserted twice per H1 frame, as is shown by the second V5 octet in Table 12. The V5 indicator
and payload signals indicate negative and positive rate adjustments which are carried out by
either putting a data byte in the H3 octet or leaving empty the octet after the H3 octet.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 44
Document ID: PMC-2010883, Issue 2
Page 46
Table 12 DS3 Framing Format
SBSLITE™ Telecom Standard Product Data Sheet
Preliminary
ROW
1
2
3
4
5
6
7
8
9
SPE
COL #
SBI
COL#
1,4,7,10
Unused H1 V5 DS3 DS3 DS3 DS3
Unused H2 DS3 DS3 DS3 DS3 DS3
Unused H3 DS3 DS3 DS3 DS3 DS3
Unused
Unused Unused DS3 DS3 DS3 DS3 DS3
Unused Unused DS3 DS3 DS3 DS3 DS3
Unused Unused DS3 DS3 DS3 DS3 DS3
Unused Unused DS3 DS3 V5 DS3 DS3
Unused Unused DS3 DS3 DS3 DS3 DS3
13 16
Linkrat
e
DS3
1
DS3 DS3 DS3 DS3 DS3
DS3
2-56
•••
DS3
57
184
DS3
58-84
•••
DS3
Col 85
268
Because the DS3 tributary rate is less than the rate of the grey region, padding octets are
interleaved with the DS3 tributary to make up the difference in rate. Interleaved with every DS3
multi-frame are 35 stuff octets, one of which is the V5 octet. These 35 stuff octets are spread
evenly across seven DS3 subframes. Each DS3 subframe is eight blocks of 85 bits. The 85 bits
making up a DS3 block are padded out to be 11 octets. Table 13 shows the DS3 block 11 octet
format where R indicates a stuff bit, F indicates a DS3 framing bit and I indicates DS3
information bits. Table 14 shows the DS3 multi-frame format that is packed into the grey region
of Table 12. In this table V5 indicates the V5 octet which is also a stuff octet, R indicates a stuff
octet and B indicates the 11 octet DS3 block. Each row in Table 14 is a DS3 multi-frame. The
DS3 multi-frame stuffing format is identical for 5 multi-frames and then an extra stuff octet after
the V5 octet is added every sixth frame.
Table 13 DS3 Block Format
Octet # 1 234567891011
Data RRRFIIII 8*I 8*I 8*I 8*I 8*I 8*I 8*I 8*I 8*I 8*I
Table 14 DS3 Multi-frame Stuffing Format
V5 4*R 8*B 5*R 8*B 5*R 8*B 5*R 8*B 5*R 8*B 5*R 8*B 5*R 8*B
V5 4*R 8*B 5*R 8*B 5*R 8*B 5*R 8*B 5*R 8*B 5*R 8*B 5*R 8*B
V5 4*R 8*B 5*R 8*B 5*R 8*B 5*R 8*B 5*R 8*B 5*R 8*B 5*R 8*B
V5 4*R 8*B 5*R 8*B 5*R 8*B 5*R 8*B 5*R 8*B 5*R 8*B 5*R 8*B
V5 4*R 8*B 5*R 8*B 5*R 8*B 5*R 8*B 5*R 8*B 5*R 8*B 5*R 8*B
V5 5*R 8*B 5*R 8*B 5*R 8*B 5*R 8*B 5*R 8*B 5*R 8*B 5*R 8*B
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 45
Document ID: PMC-2010883, Issue 2
Page 47
DS3 asynchronous timing is compensated via the H3 octet as described in section 10.1.2. DS3
link rate adjustments are optionally passed across the SBI via the Linkrate octet as described in
section 10.1.3. DS3 alarm conditions are optionally passed across the SBI bus via the Linkrate
octet as described in Sections 10.1.3 and 10.1.4.
10.1.8 E3 Tributary Mapping
Table 15 shows a E3 tributary mapped within the first SPE, SPE1. The V5 indicator pulse
identifies the V5 octet. The E3 framing format does not follow an 8 KHz frame period so the
floating frame located by the V5 indicator and shown in grey in Table 15, will jump around
relative to the H1 frame on every pass. In fact the V5 indicator will be asserted two or three times
per H1 frame, as is shown by the second and third V5 octet in Table 15. The V5 indicator and
payload signals indicate negative and positive rate adjustments which are carried out by either
putting a data byte in the H3 octet or leaving empty the octet after the H3 octet.
Table 15 E3 Framing Format
SBSLITE™ Telecom Standard Product Data Sheet
Preliminary
SPE
COL #
SBI
COL#
ROW
1,4,7,10
Unused H1 V5 E3 E3 E3 E3 E3 E3
1
Unused H2 E3 E3 E3 E3 E3 E3 E3
2
Unused H3 E3 E3 E3 E3 E3 E3 E3
3
Unused LinkrateE3 E3 V5 E3 E3 E3 E3
4
Unused Unused E3 E3 E3 E3 E3 E3 E3
5
Unused Unused E3 E3 E3 E3 E3 E3 E3
6
Unused Unused E3 E3 E3 E3 V5 E3 E3
7
Unused Unused E3 E3 E3 E3 E3 E3 E3
8
Unused Unused E3 E3 E3 E3 E3 E3 E3
9
13 16
E31E3
2-18E319E320-
•••
70
38
•••
E339E3
4084
130
•••
E3
85
268
Because the E3 tributary rate is less than the rate of the grey region, padding octets are
interleaved with the E3 tributary to make up the difference in rate. Interleaved with every E3
frame is an alternating pattern of 81 and 82 stuff octets, one of which is the V5 octet. These 81 or
82 stuff octets are spread evenly across the E3 frame. Each E3 subframe is 48 octet which is
further broken into 4 equal blocks of 12 octets each. Table 16 shows the alternating E3 frame
stuffing format that is packed into the grey region of Table 15. Note that there are 6 stuff octets
after the V5 octet in one frame and 5 stuff octets after the V5 octet in the next frame. In this table
V5 indicates the V5 octet which is also a stuff octet, R indicates a stuff octet, D indicates an E3
data octet, FAS indicates the first byte of the 10 bit E3 Frame Alignment Signal.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 46
Document ID: PMC-2010883, Issue 2
Page 48
Table 16 E3 Frame Stuffing Format
V5 6*R FAS 11*D 5*R 12*D 5*R 12*D 5*R 12*D
5*R FAS 11*D 5*R 12*D 5*R 12*D 5*R 12*D
5*R FAS 11*D 5*R 12*D 5*R 12*D 5*R 12*D
5*R FAS 11*D 5*R 12*D 5*R 12*D 5*R 12*D
V5 5*R FAS 11*D 5*R 12*D 5*R 12*D 5*R 12*D
5*R FAS 11*D 5*R 12*D 5*R 12*D 5*R 12*D
5*R FAS 11*D 5*R 12*D 5*R 12*D 5*R 12*D
5*R FAS 11*D 5*R 12*D 5*R 12*D 5*R 12*D
E3 asynchronous timing is compensated via the H3 octet as described in section 10.1.2. E3 link
rate adjustments are optionally passed across the SBI via the Linkrate octet as described in
section 10.1.3. E3 alarm conditions are optionally passed across the SBI bus via the Linkrate octet
as described in Sections 10.1.3 and 10.1.4.
10.1.9 Transparent VT1.5/TU11 Mapping
SBSLITE™ Telecom Standard Product Data Sheet
Preliminary
VT1.5 and TU11 virtual tributaries, TVT1.5s, are transported across the SBI bus in a similar
manner to the T1 tributary mapping. Table 17 shows the transparent structure where “I” is used to
indicate information bytes. There are two options when carrying virtual tributaries on the SBI
bus, the primary difference being how the floating V5 payload is located.
The first option is locked TVT mode which carries the entire VT1.5/TU11 virtual tributary
indicated by the shaded region in Table 17. Locked is used to indicate that the location of the
V1,V2 pointer is locked. The virtual tributary must have a valid V1,V2 pointer to locate the V5
payload. In this mode the V5 indicator and payload signals, IV5, OV5, IPL and OPL, may be
generated but must be ignored by the receiving device. In locked mode timing is always sourced
by the transmitting side, therefore justification requests are not used and the JUST_REQ signal is
ignored. Other than the V1 and V2 octets which must carry valid pointers, all octets can carry
data in any format. The location of the V1,V2,V3 and V4 octets is fixed to the locations shown in
Table 17.
The second option is floating TVT mode which carries the payload comprised of the V5 and I
octets within the shaded region of Table 17. In this mode the V1,V2 pointers are still in a fixed
location and may be valid but are ignored by the receiving device. The V5 indicator and payload
signals, IV5, OV5, IPL and OPL, must be valid and are used to locate the floating payload. The
justification request signal can be used to control the timing on the add bus. The V3 octets are
used to accommodate justification requests. The location of the V1,V2,V3 and V4 octets is fixed
to the locations shown in Table 17.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 47
Document ID: PMC-2010883, Issue 2
Page 49
SBSLITE™ Telecom Standard Product Data Sheet
Table 17 Transparent VT1.5/TU11 Format
COL # VT1.5#1,1 #2,1-3,28 VT1.5#1,1 #2,1-3,28 VT1.5#1,1 #2,1-3,28
ROW # 1-18 19 20-102 103 104-186 187 188-270
1 Unused V1 V1 V5 - I -
2 Unused I - I - I -
3 Unused I - I - I -
4 Unused I - I - I -
5 Unused I - I - I -
6 Unused I - I - I -
7 Unused I - I - I -
8 Unused I - I - I -
9 Unused I - I - I -
1 Unused V2 V2 I - I -
2 Unused I - I - I -
3 Unused I - I - I -
4 Unused I - I - I -
5 Unused I - I - I -
6 Unused I - I - I -
7 Unused I - I - I -
8 Unused I - I - I -
9 Unused I - I - I -
1 Unused V3 V3 I - I -
2 Unused I - I - I -
3 Unused I - I - I -
4 Unused I - I - I -
5 Unused I - I - I -
6 Unused I - I - I -
7 Unused I - I - I -
8 Unused I - I - I -
9 Unused I - I - I -
1 Unused V4 V4 I - I -
2 Unused I - I - I -
3 Unused I - I - I -
4 Unused I - I - I -
5 Unused I - I - I -
6 Unused I - I - I -
7 Unused I - I - I -
8 Unused I - I - I -
9 Unused I - I - I -
Preliminary
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 48
Document ID: PMC-2010883, Issue 2
Page 50
10.1.10 Transparent VT2/TU12 Mapping
VT2 and TU12 virtual tributaries, TVT2s, are transported across the SBI bus in a similar manner
to the E1 tributary mapping. Table 18 shows the transparent structure where “I” is used to
indicate information bytes. There are two options when carrying virtual tributaries on the SBI
bus, the primary difference being how the floating V5 payload is located.
The first option is locked TVT mode that carries the entire VT2/TU12 virtual tributary indicated
by the shaded region in Table 18. Locked is used to indicate that the location of the V1,V2 pointer
is locked. The virtual tributary must have a valid V1,V2 pointer to locate the V5 payload. In this
mode the V5 indicator and payload signals, IV5, OV5, IPL and OPL, are optionally generated but
must be ignored by the receiving device. In locked mode timing is always sourced by the
transmitting side, therefore justification requests are not used and the JUST_REQ signal is
ignored. Other than the V1 and V2 octets which are carrying valid pointers, all octets can carry
data in any format. The location of the V1,V2,V3 and V4 octets is fixed to the locations shown in
Table 18.
The second option is floating TVT mode that carries the payload comprised of the V5 and I octets
within the shaded region of Table 18. In this mode the V1,V2 pointers are still in a fixed location
and may be valid but are ignored by the receiving device. The V5 indicator and payload signals,
IV5, OV5, IPL and OPL, must be valid and are used to locate the floating payload. The
justification request signal can be used to control the timing on the add bus. The V3 octet is used
to accommodate justification requests. The location of the V1,V2,V3 and V4 octets is fixed to the
locations shown in Table 18.
SBSLITE™ Telecom Standard Product Data Sheet
Preliminary
Table 18 Transparent VT2/TU12 Format
COL # E1#1,1 #2,1-3,21 E1#1,1 #2,1-3,21 E1#1,1 #2,1-3,21 E1#1,1 #2,1-3,21
ROW
1 Unused V1 V1 V5 - I - I -
2 Unused I - I - I - I -
3 Unused I - I - I - I -
4 Unused I - I - I - I -
5 Unused I - I - I - I -
6 Unused I - I - I - I -
7 Unused I - I - I - I -
8 Unused I - I - I - I -
9 Unused I - I - I - I -
1 Unused V2 V2 I - I - I -
2 Unused I - I - I - I -
3 Unused I - I - I - I -
4 Unused I - I - I - I -
5 Unused I - I - I - I -
6 Unused I - I - I - I -
7 Unused I - I - I - I -
1-18 19 20-81 82 83-144 145 146-207 208 209-270
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 49
Document ID: PMC-2010883, Issue 2
Page 51
SBSLITE™ Telecom Standard Product Data Sheet
COL # E1#1,1 #2,1-3,21 E1#1,1 #2,1-3,21 E1#1,1 #2,1-3,21 E1#1,1 #2,1-3,21
ROW
8 Unused I - I - I - I -
9 Unused I - I - I - I -
1 Unused V3 V3 I - I - I -
2 Unused I - I - I - I -
3 Unused I - I - I - I -
4 Unused I - I - I - I -
5 Unused I - I - I - I -
6 Unused I - I - I - I -
7 Unused I - I - I - I -
8 Unused I - I - I - I -
9 Unused I - I - I - I -
1 Unused V4 V4 I - I - I -
2 Unused I - I - I - I -
3 Unused I - I - I - I -
4 Unused I - I - I - I -
5 Unused I - I - I - I -
6 Unused I - I - I - I -
7 Unused I - I - I - I -
8 Unused I - I - I - I -
9 Unused I - I - I - I -
1-18 19 20-81 82 83-144 145 146-207 208 209-270
Preliminary
10.1.11 Fractional Rate Tributary Mapping
The Fractional Rate SBI mapping is intended for support of data services over fractional DS3 or
similar links. A fractional rate link is mapped into any SPE octet as defined in Table 1. Table 19
shows all the available information (I) octets useable for carrying a Fractional rate link mapped to
a single SPE. There are no V1 to V5 bytes nor frame alignment signals in a fractional rate link.
The Add bus and Drop bus payload signals, IPL and OPL, indicate when a fractional rate
information byte contains valid data or is empty. The fractional rate link Add bus can have the
timing master be either the PHY or the Link Layer device. When the PHY is the timing master the
JUST_REQ signal from the PHY communicates the transmit rate to the Link Layer device. The
JUST_REQ signal is asserted during any of the available fractional rate link octets to indicate that
the PHY can accept another byte of data. For every byte that is marked with the JUST_REQ
signal the Link Layer device should respond with a valid byte to the PHY within a short time. The
PHY accepts data from the Link Layer device whenever it sees valid data as indicated by the IPL
or OPL signal, whether it is timing master or slave.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 50
Document ID: PMC-2010883, Issue 2
Page 52
Table 19 Fractional Rate Format
SBSLITE™ Telecom Standard Product Data Sheet
Preliminary
SPE
Fractional1Fractional
COL #
SBI COL#
ROW
1
2
3
4
5
6
7
8
9
1,4,7,10,13 16
Unused I I I
Unused I I I
Unused I I I
Unused I I I
Unused I I I
Unused I I I
Unused I I I
Unused I I I
Unused I I I
10.1.12 SBI336 Bus Format
The 77.76 MHz SBI336 bus is exactly four interleaved 19.44 MHz SBI buses. There is a slight
difference between the two formats to accommodate the increased clock rate. Instead of using the
common Add/Drop C1FP alignment of the SBI bus to reference the JUST_REQ signal, the Drop
bus C1FP alignment is used. This aids 77.76 MHz bus timing by allowing buffering and retiming
logic to be put between SBI336 devices. This change also aids construction of larger SBI cross
connect systems using smaller buffers between devices by controlling the C1 frame alignment
independently in each direction.
2-84
•••
•••
••••••
Fractional
Col 85
268
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 51
Document ID: PMC-2010883, Issue 2
Page 53
10.1.13 SBI336 Multiplexing Structure
Table 20 Structure for Carrying Multiplexed Links in SBI336
SBI Column
1 24 25 26 60 61 62 63 64 65 66 67 68 1078 1079 1080
Row
1-
2-
-C1-
•••
---
•••
•••
•••
1,SPE1 2,SPE1 3,SPE1 4,SPE1 1,SPE2 2,SPE2 3,SPE2 4,SPE2
-
1,SPE1 2,SPE1 3,SPE1 4,SPE1 1,SPE2 2,SPE2 3,SPE2 4,SPE2
-
SBSLITE™ Telecom Standard Product Data Sheet
Preliminary
2,SPE3 3,SPE3 4,SPE3
•••
2,SPE3 3,SPE3 4,SPE3
•••
9- --- -
1 233 566 666666 909090
SPE Column
1,SPE1 2,SPE1 3,SPE1 4,SPE1 1,SPE2 2,SPE2 3,SPE2 4,SPE2
Table 20 shows how 12 SPEs are multiplexed into a 77.76 MHz SBI336 bus. The structure is
exactly the same as byte interleaving four 19.44 MHz SBI buses. 1,SPE1 identifies SPE1 from
the first SBI equivalent bus, 2,SPE1 identifies SPE1 from the second SBI equivalent bus, and so
on. All tributary mapping formats are exactly the same as for the 19.44 MHz SBI bus with the
only difference that there are four times the number of tributaries. Tributary numbering appends
the equivalent SBI number to the original SBI numbering. For example, the first T1 in a SBI bus
would be numbered T1 #1,1 whereas the first T1 in a SBI336 bus would be numbered T1 #1,1,1.
Likewise the second T1 in a SBI bus would be T1 #2,1 whereas the second T1 in a SBI336 bus
would be T1 #2,1,1.
10.2 Incoming SBI336 Timing Adapter
The Incoming SBI336 Timing Adapter (ISTA) provides a multiplexing function of four incoming
19.44 MHz SBI or TelecomBuses into a 77.76 MHz SBI336 or TelecomBus. This involves simple
column multiplexing of the four incoming SBI or TelecomBuses. The timing adapter block also
provides a transparent mode when the incoming interface is already in SBI336 or 77.76 MHz
TelecomBus format.
When the SBS is connected to an 19.44 MHz SBI physical layer device, the justification request
signal, JUST_REQ, is an input to the SBS and is aligned to the outgoing bus. This block realigns the justification request signal from the outgoing frame alignment, marked by OC1FP, to
the internal incoming SBI336 frame alignment. When the SBS is connected to a 19.44 MHz SBI
link layer device or any 77.76 MHz SBI336 device, no re-alignment of the justification request is
required by this block.
2,SPE3 3,SPE3 4,SPE3
•••
10.3 CAS Expanders
The Channel Associated Signaling Expander blocks, ICASE and OCASE, pull the CAS
information from the SBI336 formatted bus on a tributary basis so that it can be switched through
the memory switch with the DS0 data. For tributaries enabled for DS0 switching, the CAS bits
are double buffered on a signaling multiframe boundary and repeated along side the tributary data
for the duration of the multiframe. This function is enabled on a per tributary basis and can be
used for T1 and E1 tributaries simultaneously across SBI SPEs. This block adds one T1
multiframe (24 frames) or one E1 multiframe (16 frames) of latency to the CAS bits.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 52
Document ID: PMC-2010883, Issue 2
Page 54
10.4 Memory Switch Units
The Memory Switch Unit blocks, IMSU and OMSU, provide DS0 or column switching of the
SBI336 or 77.76 MHz TelecomBus. Any input byte (or column) can be switched to any output
byte (or column). Four bits of CAS and three or four bits of control information are switched
along with the data byte. In SBI336 mode, the control signals are PL, V5 and JUST_REQ. In
TelecomBus mode, the control signals are PL, TPL, V5 and TAIS.
In DS0 switch mode, the data entering the MSU is stored in two alternating pages of memory.
Each page contains one complete frame (9720 bytes) of data. One of these alternating pages is
currently filling while the other is currently full. Data exiting the MSU is extracted from the
currently full page. As a consequence, the MSU imposes a nominal switching latency of 1
frame (125us). The selection of bytes to fill each output port requires a switching connection
memory. Control is required for each of the 9720 bytes in the output SBI336 frame. Complete
specification of an output byte requires 14 bits to specify which of the 9720 input bytes to use.
Dual copies of this control memory are required to provide hitless frame boundary switchover.
In column switch mode, the same switching principle described above is used, but less memory is
required. Data entering the MSU is stored in two alternating pages of memory. Each page
contains one row (1080 bytes) of data. In this mode, the nominal latency is 1 row if a frame (<15
µs). The switching connection memory for the output port requires control for each of the 1080
columns in the frame. Complete specification of an output column requires 11 bits to specify
which of the 1080 input columns to use. Dual copies of this control memory are required to
provide hitless frame boundary switchover.
SBSLITE™ Telecom Standard Product Data Sheet
Preliminary
Each MSU can be independently bypassed for reduced latency or debugging purposes.
10.4.1 Data Buffer
The Data Buffer block contains a double buffer structure for each frame consisting of a data byte,
4-bits of Channel Associated Signaling information and 4 bits of control information necessary
for identifying valid data and timing.
10.4.2 Connection Memory
The Connection Memory sub-block contains two pages of mapping configuration, page 0 and
page 1. One page is designated the active page and the other the stand-by page. Selection
between which page is to be active and which is to be stand-by is controlled by the ICMP signal
(for the IMSU) and OCMP signal (for the OMSU). The Connection Memory sub-block samples
the value on the ICMP signal at the C1 byte position as defined by the incoming frame pulse
signal, IC1FP. The Connection Memory sub-block samples the value on the OCMP signal at the
C1 byte position as defined by the receive serial interface frame pulse signal, RC1FP. Swaps
between the active/standby status of the two pages are synchronized to the first A1 byte of the
next frame or multiframe. This arrangement allows all devices in a cross-connect system to be
updated in a coordinated fashion. Consequently, DS0 streams or tributaries not being assigned
new positions are unaffected by page swaps.
The CMP input signals can be overridden by register configuration or by the SBI336S inband link
channel.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 53
Document ID: PMC-2010883, Issue 2
Page 55
SBSLITE™ Telecom Standard Product Data Sheet
10.5 CAS Merging
The Channel Associated Signaling Merge blocks, ICASM and OCASM, insert the CAS signaling
information into the SBI bus on a tributary basis. CAS signaling channels within the SBI bus are
constructed out of the available CAS bits for T1 and E1 SBI tributaries that are enabled for CAS
signaling. The resulting CAS signaling channel replaces the octets of the SBI bus where the new
CAS signaling is to be inserted. This block adds one T1 multiframe (24 frames) or one E1
multiframe (16 frames) of latency to the CAS bits.
10.6 Incoming SBI336 Tributary Translator
The Incoming SBI336 Tributary Translator block, ISTT, translates all SBI336 timing and
Channel Associated Signaling information for all tributaries into SBI336S format. The output
from this block is a 77.76 MHz SBI336 stream with all tributaries and control signals encoded
into an internal format that closely resembles the serial SBI336S format.
This block translates all tributary types into a form that is easy for the 8B/10B encoder to handle
in a more generic form. A control RAM keeps the current configuration for each of the incoming
SBI bus tributaries so that it can perform the translation function.
Preliminary
Common to all tributaries is identification of the first C1 byte. There are unique mappings of the
8B/10B codes for the supported SBI and SBI336 bus link types: Asynchronous T1/E1,
Synchronous (locked) T1/E1, Transparent VT1.5/VT2, DS3/E3 and Fractional rate links. Much of
the identification and mapping of a link into serial SBI format is based on the C1 frame pulse and
a tributaries location relative to that C1 pulse. In addition to the C1FP identification this block
identifies multiframe alignment, valid payload, pointer movements for floating tributaries and
timing control for encoding into the 8B/10B serial SBI format.
This block is transparent in TelecomBus mode.
10.7 PRBS Processors
The Working and Protection PRBS Processor blocks, WPP and PPP, provides in-service and offline PRBS generation and detection for diagnostics of the equipment downstream of the two
LVDS links. Each PRBS Processor has the capacity to source and monitor PRBS data for the
associated Working or Protection Serial SBI336S stream with a granularity of unchannelized SBI
SPEs of TelecomBus STS-1s.
10.7.1 PRBS Generator
The PRBS generator sub-block optionally overwrites the data originating from the incoming data
streams, IDATA[4:1][7:0]. When enabled, the PRBS generator sub-block inserts synchronous
payload envelope, SPE bytes into the serial transmit links. The inserted data is derived from an
internal linear feedback shift register (LFSR) with a polynomial of X
23
+ X18 + 1.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 54
Document ID: PMC-2010883, Issue 2
Page 56
10.7.2 PRBS Detector
The PRBS detector sub-block monitors the SPE bytes in the incoming data stream. The incoming
data is compared against the expected value derived from an internal linear feedback shift register
(LFSR) with a polynomial of X
23
+ X18 + 1. If the incoming data fails to match the expected
value for three consecutive bytes, the PRBS detector sub-block will enter out-of-synchronization
(OOS) state. The LFSR will be re-initialized using the incoming data bytes. The new LFSR seed
is confirmed by comparison with subsequent incoming data bytes. The PRBS detector sub-block
will exit the OOS state when the incoming data matches the LFSR output for three consecutive
bytes. The PRBS detector sub-block will remain in the OOS state and re-load the LFSR if
confirmation failed. The PRBS sub-block counts PRBS byte errors and optionally generates
interrupts when it enters and exits the OOS state.
10.8 Transmit 8B/10B Encoders
The Transmit 8B/10B Encoder blocks, TW8E and TP8E, construct an 8B/10B character stream
from an incoming translated SBI336 bus or TelecomBus carrying an STS-12/STM-4 equivalent
stream.
SBSLITE™ Telecom Standard Product Data Sheet
Preliminary
In SBI mode, these blocks encode the SBI336S stream as shown in Table 21. When configured
for Synchronous mode for DS0 switching, the 8B/10B encoder transmits CAS signaling
multiframe alignment across the SBI336S interface by generating a C1FP character every 48
frame times. When not configured for DS0 switching the C1FP character is sent every 4 frames.
10.8.1 SBI336S 8B/10B Character Encoding
Table 21 shows the mapping of SBI336S bus control bytes and signals into 8B/10B control
characters. The linkrate octet in location V4, V1 and V2, the in-band programming channel, the
V3 octet when it contains data are all carried as data. Justification requests for master timing are
carried in the V5 character so there are three V5 characters used, nominal, negative timing
adjustment request, positive timing adjustment request.
Table 21 SBI336S Character Encoding
Code Group
Name
Common to All Link Types
K28.5 001111 1010 110000 0101 IC1FP=’b1
K23.7- 111010 1000 - Overhead Bytes (columns 1-60 or 1-72
Asynchronous T1/E1 Links
K27.7- 110110 1000 - V5 byte, no justification request
K28.7- 001111 1000 - V5 byte, negative justification request
K29.7- 101110 1000 - V5 byte, positive justification request
Curr. RDabcdei fghj
Curr. RD+
abcdei fghj
Encoded Signals
Description
C1FP frame and multiframe alignment
except for C1 and in-band programming
channel), V3 or H3 byte except during
negative justification, byte after V3 or H3
byte during positive justification, unused
bytes in fraction rate links
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 55
Document ID: PMC-2010883, Issue 2
Page 57
SBSLITE™ Telecom Standard Product Data Sheet
Preliminary
Code Group
Name
Synchronous T1/E1 Links
K27.7- 110110 1000 - V5 byte
Asynchronous DS3/E3 Links
K27.7- 110110 1000 - V5 byte, no justification request
K28.7- 001111 1000 - V5 byte, negative justification request*
K29.7- 101110 1000 - V5 byte, positive justification request*
Fractional Rate Links
K28.7- 001111 1000 - V5 byte, send one extra byte request**
K29.7- 101110 1000 - V5 byte, send one less byte request**
Floating Transparent Virtual Tributaries
K27.7- 110110 1000 -
K27.7+ - 001001 0111 V5 byte
K28.7- 001111 1000 -
K28.7+ - 110000 0111 V5 byte
K29.7- 101110 1000 -
K29.7+ - 010001 0111 V5 byte
K30.7- 011110 1000 -
K30.7+ - 100001 0111 V5 byte
Note
1. Note there can be multiple V5s per SBI frame when in DS3 or E3 mode but only one justification can
occur per SBI frame. Positive and negative justification request through V5 required by the SBI336S
interface should be limited to one per frame.
Curr. RDabcdei fghj
Curr. RD+
abcdei fghj
Encoded Signals
Description
V5 byte
IV5=1,
IDATA[0,4] = ERDI[1:0] = ‘b00, IDATA[5] =
REI = ‘b0
IV5=1,
IDATA[0,4] = ERDI[1:0] = ‘b00, IDATA[5] =
REI = ‘b1
V5 byte
IV5=1,
IDATA[0,4] = ERDI[1:0] = ‘b01, IDATA[5] =
REI = ‘b0
IV5=1,
IDATA[0,4] = ERDI[1:0] = ‘b01, IDATA[5] =
REI = ‘b1
V5 byte
IV5=1,
IDATA[0,4] = ERDI[1:0] = ‘b10, IDATA[5] =
REI = ‘b0
IV5=1,
IDATA[0,4] = ERDI[1:0] = ‘b10, IDATA[5] =
REI = ‘b1
V5 byte
IV5=1,
IDATA[0,4] = ERDI[1:0] = ‘b11, IDATA[5] =
REI = ‘b0
IV5=1,
IDATA[0,4] = ERDI[1:0] = ‘b11, IDATA[5] =
REI = ‘b1
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 56
Document ID: PMC-2010883, Issue 2
Page 58
SBSLITE™ Telecom Standard Product Data Sheet
2. Note fractional rate links are symmetric in the transmit and receive direction over SBI336S. When using
clock slave mode with a fractional rate link the clock master makes single byte adjustments to the
slaves rate once per frame.
10.8.2 Serial TelecomBus 8B/10B Character Encoding
Table 22 shows the mapping of TelecomBus control bytes and signals into 8B/10B control
characters. When the TelecomBus control signals conflict each other, the 8B/10B control
characters are generated according to the sequence of the table, with the characters at the top of
the table taking precedence over those lower in the table.
Table 22 Serial TelecomBus Character Encoding
Preliminary
Code Group
Name
High Order Path Termination (HPT) Mode
K28.5 001111 1010 110000 0101 IC1FP=’b1
K28.0- 001111 0100 - IPL=’b0
K28.0+ - 110000 1011 IPL=’b0
K28.6 001111 0110 110000 1001 IC1FP=’b1,
Low Order Path Termination (LPT) Mode
K28.4+ - 110000 1101 ITAIS=’b1
K27.7- 110110 1000 -
K27.7+ - 001001 0111
K28.7- 001111 1000 -
K28.7+ - 110000 0111
Curr. RDabcdei fghj
Curr. RD+
abcdei fghj
Encoded Signals
Description
IPL=’b0
C1FP frame and multiframe alignment
High-order path H3 byte position, no
negative justification event.
High-order path PSO byte position, positive
justification event.
IPL=’b1
High-order path frame alignment (J1).
Low-order path AIS.
IV5=’b1,
IDATA[0,4] = ERDI[1:0] = ‘b00, IDATA[5] =
REI = ‘b0
Low order path frame alignment. ERDI
and REI are encoded in the V5 byte.
IV5=’b1,
IDATA[0,4] = ERDI[1:0] = ‘b00, IDATA[5] =
REI = ‘b1
Low order path frame alignment. ERDI
and REI are encoded in the V5 byte.
IV5=’b1,
IDATA[0,4] = ERDI[1:0] = ‘b01, IDATA[5] =
REI = ‘b0
Low order path frame alignment. ERDI
and REI are encoded in the V5 byte.
IV5=’b1,
IDATA[0,4] = ERDI[1:0] = ‘b01, IDATA[5] =
REI = ‘b1
Low order path frame alignment. ERDI
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 57
Document ID: PMC-2010883, Issue 2
Page 59
SBSLITE™ Telecom Standard Product Data Sheet
Preliminary
Code Group
Name
K29.7- 101110 1000 - IV5=’b1,
K29.7+ - 010001 0111 IV5=’b1,
K30.7- 011110 1000 - IV5=’b1,
K30.7+ - 100001 0111
K23.7- 111010 1000 000101 0111 ITPL=’b0
Curr. RDabcdei fghj
Curr. RD+
abcdei fghj
Encoded Signals
Description
and REI are encoded in the V5 byte.
IDATA[0,4] = ERDI[1:0] = ‘b10, IDATA[5] =
REI = ‘b0
Low order path frame alignment. ERDI
and REI are encoded in the V5 byte.
IDATA[0,4] = ERDI[1:0] = ‘b10, IDATA[5] =
REI = ‘b1
Low order path frame alignment. ERDI
and REI are encoded in the V5 byte.
IDATA[0,4] = ERDI[1:0] = ‘b11, IDATA[5] =
REI = ‘b0
Low order path frame alignment. ERDI
and REI are encoded in the V5 byte.
IV5=’b1,
IDATA[0,4] = ERDI[1:0] = ‘b11, IDATA[5] =
REI = ‘b1
Low order path frame alignment. ERDI
and REI are encoded in the V5 byte.
Non low-order path payload bytes.
10.9 Transmit Serializer
The Transmit Serializer blocks, TWPS and TPPS, convert 8B/10B characters to bit-serial format.
The Transmit Working Serializer, TWPS, generates a serial stream for the working transmit
LVDS link, TPWRK/TNWRK. The Transmit Protect Serializer, TPPS, generates a serial stream
for the protect transmit LVDS link, TPPROT/TNPROT.
10.10 LVDS Transmitters
The LVDS Transmitters, TWLV and TPLV, convert 8B/10B encoded digital bit-serial streams to
LVDS signaling levels. The Transmit Working LVDS Interface, TWLV, drives the working
transmit LVDS links, TPWRK/TNWRK. The Transmit Protect LVDS Interface block, TPLV,
drives the protect transmit LVDS link, TPPROT/TNPROT.
10.11 Clock Synthesis Unit
The Clock Synthesis Unit (CSU) block generates the 777.6 MHz clock for the transmit and
receive LVDS links.
10.12 Transmit Reference Generator
The Transmit Voltage Reference Generator block generates bias voltages and currents for the
LVDS Transmitters.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 58
Document ID: PMC-2010883, Issue 2
Page 60
10.13 LVDS Receivers
The LVDS Receivers, RWLV and RPLV, convert LVDS signaling levels to 8B/10B encoded
digital bit-serial. The Receive Working LVDS Interface block, RWLV, connects to the working
receive LVDS links, RPWRK/RNWRK. The Receive Protect LVDS Interface block, RPLV,
connects to the protect receive LVDS link RPPROT/RNPROT.
10.14 Data Recovery Units
The Data Recovery Units, WDRU and PDRU, monitor the receive LVDS link for transitions to
determine the extent of bit cycles on the link. It then adjusts its internal timing to sample the link
in the middle of the data “eye”. WDRU retrieves data from the working receive LVDS link,
RPWRK/RNWRK. PDRU processes the protect receive LVDS link, RPPROT/RNPROT.
The DRU block also converts the serial stream into 10-bit words. The words are constructed
from ten consecutive received bits without regard to 8B/10B character boundaries.
10.15 Receive 8B/10B Decoders
SBSLITE™ Telecom Standard Product Data Sheet
Preliminary
The Receive 8B/10B serial SBI336S Bus decoders, RW8D and RP8D, frame to the receive
stream to find 8B/10B character boundaries. It also contains a FIFO to bridge between the timing
domain of the receive LVDS links and the system clock timing domain. The RW8D block
performs framing and elastic store functions on data retrieved from the working receive LVDS
link, RPWRK/RNWRK. The RP8D block processes data on the protect receive LVDS link,
RPPROT/RNPROT.
10.15.1 FIFO Buffer
The FIFO buffer sub-block provides isolation between the timing domain of the associated
receive LVDS link and that of the system clock, SYSCLK. The FIFO also provides a retiming
function to allow individual links in a multi-SBS system to have varying interconnect delay. This
eases timing distribution and synchronization in large systems. Data with arbitrary alignment to
8B/10B characters are written into a 10-bit by 24-word deep FIFO at the link clock rate. Data is
read from the FIFO at every SYSCLK cycle.
10.15.2 Serial SBI336S and TelecomBus Alignment
The alignment functionality preformed by each receiver can be broken down into two parts,
character alignment and frame alignment. Character alignment finds the 8B/10B character
boundary in the arbitrarily aligned incoming data. Frame alignment finds SBI336S or
TelecomBus frame and multiframe boundaries within the Serial link.
The character and frame alignment are expected to be robust enough for operation over a cabled
interconnect.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 59
Document ID: PMC-2010883, Issue 2
Page 61
10.15.3 Character Alignment Block
Character alignment locates character boundaries in the incoming 8B/10B data stream. The
character alignment algorithm may be in one of two states, in-character-alignment state and outof-character-alignment state. The two states of the character alignment algorithm is shown in
Figure 8.
When the character alignment state machine is in the out-of-character-alignment state, it
maintains the current alignment, while searching for a C1FP character. If it finds the C1FP
character it will re-align to the C1FP character and move to the in-character-alignment state. The
C1FP character is found by searching for the 8B/10B C1FP character, K28.5+ or K28.5-,
simultaneously in ten possible bit locations. While in the in-character-alignment state, the state
machine monitors LCVs. If 5 or more LCVs are detected within a 15 character window the
character alignment state machine transitions to out-of-character-alignment state. The special
characters listed in Table 21 and Table 22 are ignored for LCV purposes. Upon return to incharacter-alignment state the LCV count is cleared.
Figure 8 Character Alignment State Machine
SBSLITE™ Telecom Standard Product Data Sheet
Preliminary
out-of-
character-
alignment
5-in-15 LCVs
incharacteralignment
Found C1FP Character
10.15.4 Frame Alignment
Frame alignment locates SBI or TelecomBus frame and multiframe boundaries in the incoming
8B/10B data stream. The frame alignment state machine may be in one of two states, in-framealignment state and out-of-frame-alignment state. Each SBI336S frame is 125 µS in duration.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 60
Document ID: PMC-2010883, Issue 2
Page 62
SBSLITE™ Telecom Standard Product Data Sheet
Preliminary
In SBI mode: Encoded over the SBI336S frame alignment is SBI336S multiframe alignment that
is every four SBI336S frames or 500 µS. When carrying DS0 traffic in synchronous mode,
signaling multiframe alignment is also necessary and is also encoded over SBI336S alignment.
Signaling multiframe alignment is every 24 frames for T1 links and every 16 frames for E1 links,
therefore signaling multiframe alignment covering both T1 and E1 multiframe alignment is every
48 SBI336S frames or 6 ms. Therefore C1FP characters are sent every four or every 48 frames.
In TelecomBus mode: Encoded over the serial link is the tributary multiframe alignment which is
every 4 frames or 500 µS. Multiframe alignment is required so that a downstream device can
extract the T1 or E1 data from the tributary. The multiframe information is preserved by only
sending out C1FP characters every four frames.
The frame alignment state machine establishes frame alignment over the link and is based on the
frame and not the multiframe alignments. When the frame alignment state machine is in the outof-frame-alignment state, it maintains the current alignment, while searching for a C1FP
character. When it finds the C1FP character the state machine transitions to the in-framealignment state. While in the in-frame-alignment state the state machine monitors out-of-place
C1FP characters. Out-of-place C1FP characters are identified by maintaining a frame counter
based on the C1FP character. The counter is initialized by the C1FP character when in the out-ofcharacter-alignment state, and is unaffected in the in-character-alignment state. If 3 consecutive
C1FPs have been found that do not agree with the expected location as defined by the frame
counter, the state will change to out-of-frame-alignment state.
The frame alignment state machine is also sensitive to character alignment. When the character
alignment state machine is in the out-of-character-alignment state, the frame alignment state
machine is forced out-of-alignment, and is held in that state until the character alignment state
machine transitions to the in-character alignment state.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 61
Document ID: PMC-2010883, Issue 2
Page 63
Figure 9 Frame Alignment State Machine
3 consecutive out-of-place
C1FPs or
out-of-character alignment
SBSLITE™ Telecom Standard Product Data Sheet
Preliminary
out-offrame-
alignment
Found C1FP and
not (out-of-character alignment)
10.15.5 SBI336S Multiframe Alignment
SBI336S multiframe alignment is communicated across the link by controlling the frequency of
the C1FP character. The most frequent transmission of the C1FP character is every four SBI336S
frame times. This is the SBI336S multiframe and is used when there are no synchronous
tributaries requiring signalling multiframe alignment on the SBI336S bus. When there are
synchronous tributaries on the SBI336S bus the C1FP character is transmitted every 48 frame
times. This is the CAS signaling multiframe and is the lowest common multiple of the 24 frame
T1 multiframe and the 16 frame E1 multiframe.
in-frame-
alignment
The SBI336S multiframe and signaling multiframe alignment is based a free running multiframe
counter that is reset with each C1FP character received. Under normal operating conditions each
received C1FP character will coincide with the free running multiframe counter. SBI336S
multiframe alignment is always required, SBI336S signaling multiframe alignment is optional
and only required when synchronous tributaries are supported with DS0 level switching.
10.16 Outgoing SBI336S Tributary Translator
The Outgoing SBI Tributary Translator block, OSTT, processes all timing information and
Channel Associated Signaling information for the tributaries on the outgoing SBI Bus or buses.
Input to this block is a 77 MHz SBI stream with all tributaries encoded in an internal format that
closely resembles the serial SBI format.
This block is transparent in TelecomBus mode.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 62
Document ID: PMC-2010883, Issue 2
Page 64
10.16.1 Outgoing SBI336S Translation
This block translates the generic internal SBI format to the external SBI format. A control RAM
keeps the current configuration of the outgoing SBI bus(es) and the tributaries carried so that it
can perform the translation function.
Common to all tributaries is identification of the first C1 byte. There are unique mappings of the
8B/10B codes for the supported SBI bus link types: Asynchronous T1/E1, Synchronous (locked)
T1/E1, Transparent VT1.5/VT2, DS3/E3 and Fractional rate links. Much of the identification and
mapping of a link from serial SBI format is based on the OC1FP frame pulse and a tributaries
location relative to that C1 reference. In addition to the OC1FP identification this block identifies
multiframe alignment, valid payload, pointer movements for floating tributaries and timing
control for decoding from the 8B/10B serial SBI format.
10.17 Outgoing SBI336 Timing Adapter
The Outgoing SBI336 Timing Adapter, OSTA, provides a demultiplexing from a 77.76 MHz
SBI336 or TelecomBus to four outgoing 19.44 MHz SBI or TelecomBuses. The outgoing timing
adapter block also provides a transparent mode when the outgoing interface is already in 77.76
MHz SBI336 or TelecomBus format.
SBSLITE™ Telecom Standard Product Data Sheet
Preliminary
When the SBS is connected to a 19.44 MHz SBI link layer device the justification request signal,
JUST_REQ, is an output from the SBS and is aligned to the incoming bus. This block re-aligns
the internal justification request signal from the internal outgoing SBI336 frame alignment to the
incoming SBI frame alignment, marked by IC1FP. When the SBS is connected to a 19.44 MHz
SBI physical layer device or any 77.76 MHz SBI336 device, no re-alignment of the justification
request is required by this block.
10.18 In-band Link Controller
In order to permit centralized control of distributed NSE/SBSLITE fabrics from the NSE
microprocessor interface (for applications in which NSEs are located on fabric cards, and
SBSLITEs are located on multiple line cards), an in-band signaling channel is provided between
the NSE and the SBSLITE over the Serial interface. Each NSE can control up to 32 SBSLITEs
which are attached by the LVDS links. The NSE/SBSLITE in-band channel is full duplex, but the
NSE has active control of the link.
The SBSLITE contains two independent In-Band Link Controllers. One ILC is connected to the
Working Transmit Serial LVDS Link and the other is connected to the Protection Transmit Serial
LVDS Link.
The in-band channel is carried in the first 36 columns of four rows of the SBI or TelecomBus
structure, rows 3, 6, 7 and 8. The overall in-band channel capacity is thus 36*4*64kb/s =
9.216Mb/s. Each 36 bytes per row allocated to the in-band signaling channel is its own in-band
message between the end points. Four bytes of each 36 byte inband message are reserved for endto-end control information and error protection, leaving 8.192Mb/s available for user data transfer
between the end points.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 63
Document ID: PMC-2010883, Issue 2
Page 65
SBSLITE™ Telecom Standard Product Data Sheet
Preliminary
The data transferred between the end points has no fixed format, effectively providing a clear
channel for packet transfer between the attached microprocessors at each of the LVDS link
terminating devices. Using the microprocessor interface, the user is able to send and receive any
packet up to 32 bytes in length. The first two bytes of each 36 byte message contains a header and
the last two bytes of the message is a CRC-16 which detects errors in the message.
This in-band channel is expected to be used almost entirely to carry out switching control changes
in the SBSLITEs. To configure a DS0 in an SBSLITE device most often requires a local
microprocessor to write to one memory location consisting of a 16-bit address and a 16-bit data.
Using this as a baseline and assuming an efficient use of the in-band channel bandwidth we can
set a maximum of (32bytes/row * 4 rows/frame * 8000 frames/sec / 4 bytes/write) 256,000 DS0
configurations per second.
Considering that configuring a T1 when switching DS0s requires 27 DS0 writes indicates that the
in-band signaling channel bandwidth sets maximum limit of over 9000 T1 configurations per
second. In real life these limits will not be achieved but this shows that the in-band link should
not be the bottleneck. In TelecomBus mode this same configuration will require only 3 writes per
T1 link.
In N+1 protected architectures it is likely that full configuration of a port card will be necessary
during the switchover. This would require the entire connection memory be reconfigured.
Assuming connections for overhead bytes are also reconfigured, the fastest that a complete
reconfiguration can take place is 9720 register writes which equates to (9720 writes * 4
bytes/write / (32 bytes/row * 4 rows/frame * 8000 frames/second)) 38 milliseconds. It is also
possible that the spare card could hold all the connection configurations for all the port cards it is
protecting locally, for even faster switch over.
10.18.1 In-Band Signaling Channel Fixed Overhead
The In-Band Link Controller block generates and terminates two bytes of fixed header and a
CRC-16 per every 36 byte in-band message. The two byte header provides control and status
between devices at the ends of the LVDS link. The CRC-16 is calculated over the entire 34 byte
in-band message and provides the terminating end the ability to detect errors in the in-band
message. The format of the in-band message and header bytes is shown in Figure 10 and Figure
11.
Figure 10 In-Band Signaling Channel Message Format
1 byte 1 byte 32 bytes 2 bytes
Header1 Header2 Free Format Information CRC-16
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 64
Document ID: PMC-2010883, Issue 2
Page 66
SBSLITE™ Telecom Standard Product Data Sheet
Figure 11 In-Band Signaling Channel Header Format
Header1
Bit 7 Bit 6 Bit 5 Bit4 Bit3 Bit2 Bit1 Bit 0
Valid Link[1:0] Page[1:0] User[2:0]
Header2
Bit 7 Bit 6 Bit 5 Bit4 Bit3 Bit2 Bit1 Bit 0
Aux[7:0]
Table 23 In-band Message Header Fields
Field Name Received by the SBSLITE Transmitted by the SBSLITE
Valid Message slot contains a valid
message(1) or is empty(0). If empty
this message will not be put into Rx
Message FIFO (other header
information processed as usual)
Link[1:0]# Each bit indicates which Link to use,
working(0) or Protect(1). Other
algorithms are possible in indicate
Working or Protect over these 2 bits.
Page[1:0]# Each bit indicates which configuration
page to use, page (1) or page (0) for
the corresponding MSU. Page[1]
controls the IMSU configuration page
and Page[0] controls the OMSU
configuration page.
User[2:0]# User defined bits which may be read
through the microprocessor interface.
User[2] is also output from the
SBSLITE on the OUSER2 pin.
Aux[7:0]# User defined auxiliary register
indication.
Message slot contains a valid
message(1) or is empty(0). The
header and CRC bytes are
transmitted regardless of the state of
this bit.
Each bit shows current Link in use,
working(0) or Protect(1). Other
algorithms are possible in indicate
Working or Protect over these 2 bits.
These bits are transmitted
immediately.
Each bit shows current control page in
use, page (1) or page (0) for the
corresponding MSU. Page[1]
indicates the IMSU configuration page
and Page[0] indicates the OMSU
configuration page
Only transmitted from the beginning of
the first message of the frame
User defined bits. User[2] is sourced
from the IUSER2 input to the
SBSLITE. User[1:0] are sourced from
an internal register.
Transmitted immediately.
User defined auxiliary register
indication.
Transmitted immediately.
Preliminary
#Change in these bits(received side) will not be processed if the received message CRC-16
indicates an error.
Interrupts can be generated when CRC errors are detected or the USER or LINK bits change
state. There is no inherent flow control provided by the In-Band Link Controller. The attached
microprocessor is able to provide flow control via interrupts when the in-band message first-in
first out (FIFO) overflows and via the USER bits in the header.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 65
Document ID: PMC-2010883, Issue 2
Page 67
As each message arrives, the CRC-16 and valid bit is checked; if the valid bit is not set the
message is discarded, if it fails the CRC check it is flagged as being in error and an interrupt is
generated if enabled. If the CRC-16 is OK, regardless of the valid bit, the Page Link, User and
Aux bits are passed on immediately. If the FIFO erroneously overflows, an interrupt is generated.
10.19 Microprocessor Interface
The Microprocessor Interface block provides normal and test mode registers, and logic required
to connect to the microprocessor interface. The normal mode registers are required for normal
operation, and test mode registers are used to enhance testability of the SBSLITE.
Address Register
000H SBSLITE Master Reset
001H SBSLITE Master Configuration
002H SBSLITE Revision/Part Number
003H SBSLITE Part Number/Manufacturer ID
004H SBSLITE Master Bypass
005H SBSLITE Master SPE Control #1
006H SBSLITE Master SPE Control #2
007H SBSLITE Receive Synchronization Delay
008H SBSLITE In-Band Link User Bits
009H – 00FH SBSLITE Reserved
010H SBSLITE Master Interrupt Source
011H SBSLITE Interrupt Register
012H SBSLITE Interrupt Enable Register
013H SBSLITE Loopback Configuration
014H SBSLITE Master Clock Monitor #1, Accumulation Trigger
015H SBSLITE Master Clock Monitor #2
016H SBSLITE Master Interrupt Enable Register
017H SBSLITE Free User Register
020H ISTA Incoming Parity Configuration
021H ISTA Incoming Parity Status
022H ISTA TelecomBus Configuration
023H ISTA Reserved
024H – 027H Reserved
028H IMSU Configuration
029H IMSU Interrupt Status and Memory Page Update
02AH IMSU Indirect Time Switch Address
02BH IMSU Indirect Time Switch Data
02CH – 02FH Reserved
030H ICASM CAS Enable Indirect Address
031H ICASM CAS Enable Indirect Control
032H ICASM CAS Enable Indirect Data
SBSLITE™ Telecom Standard Product Data Sheet
Preliminary
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 66
Document ID: PMC-2010883, Issue 2
Page 68
SBSLITE™ Telecom Standard Product Data Sheet
033H ICASM Reserved
034H – 037H Reserved
038H ISTT Control RAM Indirect Access Address Register
039H ISTT Control RAM Indirect Access Control Register
03AH ISTT Control RAM Indirect Access Data Register
03BH ISTT Reserved
03CH – 03FH Reserved
040H OSTT Control RAM Indirect Access Address Register
041H OSTT Control RAM Indirect Access Control Register
042H OSTT Control RAM Indirect Access Data Register
043H OSTT Reserved
044H – 047H Reserved
048H OMSU Configuration
049H OMSU Interrupt Status and Memory Page Update
04AH OMSU Indirect Time Switch Address
04BH OMSU Indirect Time Switch Data
04CH – 04FH Reserved
050H OCASM Indirect Address
051H OCASM Indirect Control
052H OCASM Indirect Data
053H OCASM Reserved
054H – 05FH Reserved
060H OSTA Outgoing Configuration and Parity
061H OSTA Outgoing J1 Configuration
062H OSTA Outgoing V1 Configuration
063H OSTA H1-H2 Pointer Value
064H OSTA Alternate H1-H2 Pointer Value
065H OSTA H1-H2 Pointer Selection
066H OSTA Reserved
067H OSTA Reserved
068H OSTA Reserved
069H – 06FH OSTA Reserved
070H WPP Indirect Address
071H WPP Indirect Data
072H WPP Generator Payload Configuration
073H WPP Monitor Payload Configuration
074H WPP Monitor Byte Error Interrupt Status
075H WPP Monitor Byte Error Interrupt Enable
076H Reserved
077H Reserved
078H Reserved
079H WPP Monitor Synchronization Interrupt Status
Preliminary
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 67
Document ID: PMC-2010883, Issue 2
Page 69
SBSLITE™ Telecom Standard Product Data Sheet
07AH WPP Monitor Synchronization Interrupt Enable
07BH WPP Monitor Synchronization State
07CH WPP Performance Counters Transfer Trigger
07DH – 07FH WPP Reserved
080H PPP Indirect Address
081H PPP Indirect Data
082H PPP Generator Payload Configuration
083H PPP Monitor Payload Configuration
084H PPP Monitor Byte Error Interrupt Status
085H PPP Monitor Byte Error Interrupt Enable
086H Reserved
087H Reserved
088H Reserved
089H PPP Monitor Synchronization Interrupt Status
08AH PPP Monitor Synchronization Interrupt Enable
08BH PPP Monitor Synchronization State
08CH PPP Performance Counters Transfer Trigger
08DH – 08FH PPP Reserved
090H WILC Transmit Message FIFO Data High
091H WILC Transmit Message FIFO Data Low
092H WILC Reserved
093H WILC Transmit Control
094H WILC Reserved
095H WILC Transmit Status and FIFO Synch
096H WILC Receive Message FIFO Data High
097H WILC Receive Message FIFO Data Low
098H WILC Reserved
099H WILC Receive Control
09AH WILC Receive Auxiliary
09BH WILC Receive Status and FIFO Synch
09CH WILC Reserved
09DH WILC Interrupt Enable and Control
09EH WILC Reserved
09FH WILC Interrupt Reason
0A0H PILC Transmit Message FIFO Data High
0A1H PILC Transmit Message FIFO Data Low
0A2H PILC Reserved
0A3H PILC Transmit Control
0A4H PILC Reserved
0A5H PILC Transmit Status and FIFO Synch
0A6H PILC Receive Message FIFO Data High
0A7H PILC Receive Message FIFO Data Low
Preliminary
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 68
Document ID: PMC-2010883, Issue 2
Page 70
SBSLITE™ Telecom Standard Product Data Sheet
0A8H PILC Reserved
0A9H PILC Receive Control
0AAH PILC Receive Auxiliary
0ABH PILC Receive Status and FIFO Synch
0ACH PILC Reserved
0ADH PILC Interrupt Enable and Control
0AEH PILC Reserved
0AFH PILC Interrupt Reason
0B0H TW8E Control and Status
0B1H TW8E Interrupt Status
0B2H TW8E Timeslot Configuration #1
0B3H TW8E Timeslot Configuration #2
0B4H TW8E Test Pattern
0B5H TW8E Analog Control
0B6H – 0B7H TW8E Reserved
0B8H TP8E Control and Status
0B9H TP8E Interrupt Status
0BAH TP8E Timeslot Configuration #1
0BBH TP8E Timeslot Configuration #2
0BCH TP8E Test Pattern
0BDH TP8E Analog Control
0BEH – 0BFH TP8E Reserved
0C0H RW8D Control and Status
0C1H RW8D Interrupt Status
0C2H RW8D Line Code Violation Count
0C3H RW8D Analog Control #1
0C4H – 0C7H RW8D Reserved
0C8H RP8D Control and Status
0C9H RP8D Interrupt Status
0CAH RP8D Line Code Violation Count
0CBH RP8D Analog Control
0CCH – 0CFH RP8D Reserved
0D0H CSTR Control
0D1H CSTR Interrupt Enable and Status
0D2H CSTR Interrupt Indication
0D3H CSTR Reserved
0D4H – 0DFH Reserved
0E0H REFDLL Configuration
0E1H REFDLL Reserved
0E2H REFDLL Reserved
0E3H REFDLL Control Status
0E4H – 0E7H Reserved
Preliminary
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 69
Document ID: PMC-2010883, Issue 2
Page 71
0E8H SYSDLL Configuration
0E9H SYSDLL Reserved
0EAH SYSDLL Reserved
0EBH SYSDLL Control Status
0ECH – 0FFH Reserved
100H SBSLITE Master Test
101H – 1FFH Reserved for Test
Note
1. For all register accesses, CSB must be set low.
SBSLITE™ Telecom Standard Product Data Sheet
Preliminary
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 70
Document ID: PMC-2010883, Issue 2
Page 72
SBSLITE™ Telecom Standard Product Data Sheet
11 Normal Mode Register Description
Normal mode registers are used to configure and monitor the operation of the SBSLITE. Normal
mode registers (as opposed to test mode registers) are selected when A[8] is set low.
Notes on Normal Mode Register Bits
1. Writing values into unused register bits has no effect. However, to ensure software
compatibility with future, feature-enhanced versions of this product, unused register bits must
be written with logic zero. Reading back unused bits can produce either a logic one or a logic
zero; hence, unused register bits should be masked off by software when read.
2. All configuration bits that can be written into can also be read back. This allows the
processor controlling the SBSLITE to determine the programming state of the block.
3. Writeable normal mode register bits are cleared to logic zero upon reset unless otherwise
noted.
4. Writing into read-only normal mode register bit locations does not affect SBSLITE operation
unless otherwise noted.
Preliminary
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 71
Document ID: PMC-2010883, Issue 2
Page 73
SBSLITE™ Telecom Standard Product Data Sheet
Register 000H: SBSLITE Master Reset
Bit Type Function Default
Bit 15 Unused 0
Bit 14 Unused 0
Bit 13 Unused 0
Bit 12 Unused 0
Bit 11 Unused 0
Bit 10 Unused 0
Bit 9 Unused 0
Bit 8 Unused 0
Bit 7 Unused 0
Bit 6 Unused 0
Bit 5 R/W Reserved 0
Bit 4 R/W Reserved 0
Bit 3 R/W Reserved 0
Bit 2 R/W Reserved 0
Bit 1 R/W ARESET 0
Bit 0 R/W DRESET 0
Preliminary
Reserved
These bits must be set low for proper operation of the SBSLITE.
ARESET
The analogue reset bit (ARESET) allows the analogue circuitry in the SBSLITE to be reset
and disabled under software control. When the ARESET bit is set high, all SBSLITE
analogue circuitry is held in reset and disabled. This bit is not self-clearing. Therefore, it
must be set low to bring the affected circuitry out of reset and enable it. Holding SBSLITE in
analogue reset state places it into a low power, disabled mode. A hardware reset clears the
ARESET bit, thus negating the analogue software reset.
DRESET
The digital reset bit (DRESET) allows the digital circuitry in the SBSLITE to be reset under
software control. When the DRESET bit is set high, all SBSLITE digital circuitry is held in
reset with the exception of this register. This bit is not self-clearing. Therefore, it must be set
low to bring the affected circuitry out of reset. Holding SBSLITE in digital reset state places
it into a low power, digital stand-by mode. A hardware reset clears the DRESET bit, thus
negating the digital software reset.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 72
Document ID: PMC-2010883, Issue 2
Page 74
SBSLITE™ Telecom Standard Product Data Sheet
Register 001H: SBSLITE Master Configuration
Bit Type Function Default
Bit 15 Unused 0
Bit 14 R/W ICMP_SRC[1] 0
Bit 13 R/W ICMP_SRC[0] 0
Bit 12 R/W ICMP_VAL 0
Bit 11 Unused 0
Bit 10 R/W OCMP_SRC[1] 0
Bit 9 R/W OCMP_SRC[0] 0
Bit 8 R/W OCMP_VAL 0
Bit 7 R/W RWSEL_SRC 0
Bit 6 R/W RWSEL_VAL 1
Bit 5 R/W Reserved[1] 0
Bit 4 R/W COLUMN_MODE 0
Bit 3 R/W PHY_SBI 1
Bit 2 R/W MF_48 0
Bit 1 R/W TELECOM_BUS 0
Bit 0 R/W Reserved[0] 0
Preliminary
ICMP_SRC[1:0]
The ICMP_SRC[1:0] bits select the source for the incoming connection memory page
information.
ICMP_SRC[1:0] Source
00 ICMP_VAL register bit
01 ICMP input pin
10 PAGE bit from the active ILC (as determined by the
RWSEL_VAL bit or RWSEL input)
11 Reserved
ICMP_VAL
The ICMP_VAL bit controls the selection of the connection memory page in each Incoming
Memory Switch Unit, IMSU. When ICMP_VAL is a logic one, connection memory page 1 is
selected. When ICMP_VAL is a logic zero, connection memory page 0 is selected.
ICMP_VAL is sampled at the C1 byte position as defined by the incoming frame pulse signal
(IC1FP). Changes to the connection memory page selection are synchronized to the frame
boundary of the next frame (in TelecomBus mode), 4 frame multiframe (in SBI mode without
CAS), or 48 frame multiframe (in SBI mode with CAS). This bit is only used when
ICMP_SRC[1:0] = ‘b00.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 73
Document ID: PMC-2010883, Issue 2
Page 75
SBSLITE™ Telecom Standard Product Data Sheet
Preliminary
OCMP_SRC[1:0]
The OCMP_SRC[1:0] bits select the source for the outgoing connection memory page
information.
OCMP_SRC[1:0] Source
00 OCMP_VAL register bit
01 OCMP input pin
10 PAGE bit from the active ILC (as determined by the
RWSEL_VAL bit or RWSEL input)
11 Reserved
OCMP_VAL
The OCMP_VAL bit controls the selection of the connection memory page in each Outgoing
Memory Switch Unit, OMSU. When OCMP_VAL is a logic one, connection memory page 1
is selected. When OCMP_VAL is a logic zero, connection memory page 0 is selected.
OCMP_VAL is sampled at the C1 byte position as defined by the receive frame pulse signal
(RC1FP). Changes to the connection memory page selection are synchronized to the frame
boundary of the next frame (in TelecomBus mode), 4 frame multiframe (in SBI mode without
CAS), or 48 frame multiframe (in SBI mode with CAS). This bit is only used when
OCMP_SRC[1:0] = ‘b00.
RWSEL_SRC
The RWSEL_SRC bit selects the source for the selection of which link, the working or the
protect, is active. When RWSEL_SRC is a logic zero, the RWSEL_VAL register bit is used
as the source for selecting the active link. When RWSEL_SRC is a logic one, the RWSEL
input is used as the source for selecting the active link.
RWSEL_VAL
The RWSEL_VAL bit selects between the receive working and protect links when the
RWSEL_SRC is a logic zero. When RWSEL_VAL is a logic one, the working link is
selected and the SBSLITE listens to the data from the RPWRK and RNWRK inputs. When
RWSEL_VAL is a logic zero, the protect link is selected and the SBSLITE listens to the data
from the RPPROT and RNPROT inputs. This bit has no effect when the RWSEL_SRC bit is
a logic one or when the parallel interface is used (PARALLEL_MODE = ‘b1).
Reserved[1]
This bit must be set to a logic zero for correct operation of the SBSLITE.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 74
Document ID: PMC-2010883, Issue 2
Page 76
SBSLITE™ Telecom Standard Product Data Sheet
COLUMN_MODE
The COLUMN_MODE bit selects between column switching and DS0 switching. When
COLUMN_MODE is set to a logic one, column switching is enabled and the SBSLITE is
configured to switch columns within the SBI336 or TelecomBus. When COLUMN_MODE
is set to a logic zero, DS0 switching is enabled and the SBSLITE is configured to switch
DS0’s within the SBI336 bus. DS0 switching is not permitted in TelecomBus mode.
PHY_SBI
The PHY_SBI bit configures the direction of the JUST_REQ input/output signals on the
incoming and outgoing buses. When PHY_SBI is set to a logic one, the SBSLITE is
configured to be connected to a PHY device and the JUST_REQ signal is an input. When
PHY_SBI is set to a logic zero, the SBSLITE is configured to be connected to a Link layer
device and the JUST_REQ signal is an output.
MF_48
Preliminary
The MF_48 bit selects between 4 frame multiframe mode or 48 frame multiframe mode on
the SBI336 bus. When MF_48 is a logic one, 48 frame mode is selected. IC1FP is expected
once every 48 frames and OC1FP is output every 48 frames, indicating CAS signaling
multiframe alignment. When MF_48 is a logic zero, 4 frame mode is selected. IC1FP is
expected once every 4 frames and OC1FP is output every 4 frames. This bit has no effect
when in TelecomBus mode (TELECOM_BUS = ‘b1).
TELECOM_BUS
The TELECOM_BUS bit selects between TelecomBus and SBI bus modes on the incoming
and outgoing buses. When TELECOM_BUS is set to a logic one, TelecomBus mode is
selected and all frame pulses must mark C1J1V1 positions. When TELECOM_BUS is set to
a logic zero, SBI bus mode is selected and the all frame pulses only mark the C1 position.
Reserved[0]
This bit must be set to a logic one for proper operation of the SBSLITE.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 75
Document ID: PMC-2010883, Issue 2
Page 77
SBSLITE™ Telecom Standard Product Data Sheet
Register 002H: SBSLITE Version/Part Number
Bit Type Function Default
Bit 15 R VERSION[3] 0
Bit 14 R VERSION[2] 0
Bit 13 R VERSION[1] 0
Bit 12 R VERSION[0] 0
Bit 11 R PART_NUMBER[15] 1
Bit 10 R PART_NUMBER[14] 0
Bit 9 R PART_NUMBER[13] 0
Bit 8 R PART_NUMBER[12] 0
Bit 7 R PART_NUMBER[11] 0
Bit 6 R PART_NUMBER[10] 1
Bit 5 R PART_NUMBER[9] 1
Bit 4 R PART_NUMBER[8] 0
Bit 3 R PART_NUMBER[7] 0
Bit 2 R PART_NUMBER[6] 0
Bit 1 R PART_NUMBER[5] 0
Bit 0 R PART_NUMBER[4] 1
Preliminary
VERSION[3:0]
The VERSION[3:0] bits report the binary revision number of the SBSLITE silicon.
PART_NUMBER[15:4]
The PART NUMBER[15:4] bits represent the 12 most significant bits of the part number of
the SBSLITE device.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 76
Document ID: PMC-2010883, Issue 2
Page 78
SBSLITE™ Telecom Standard Product Data Sheet
Register 003H: SBSLITE Part Number/Manufacturer ID
Bit Type Function Default
Bit 15 R PART_NUMBER[3] 0
Bit 14 R PART_NUMBER[2] 0
Bit 13 R PART_NUMBER[1] 0
Bit 12 R PART_NUMBER[0] 1
Bit 11 R MANUFACTURER_ID[10] 0
Bit 10 R MANUFACTURER_ID[9] 0
Bit 9 R MANUFACTURER_ID[8] 0
Bit 8 R MANUFACTURER_ID[7] 0
Bit 7 R MANUFACTURER_ID[6] 1
Bit 6 R MANUFACTURER_ID[5] 1
Bit 5 R MANUFACTURER_ID[4] 0
Bit 4 R MANUFACTURER_ID[3] 0
Bit 3 R MANUFACTURER_ID[2] 1
Bit 2 R MANUFACTURER_ID[1] 1
Bit 1 R MANUFACTURER_ID[0] 0
Bit 0 R JID 1
Preliminary
PART_NUMBER[3:0]
The PART NUMBER[3:0] bits represent the 4 least significant bits of the part number of the
SBSLITE device.
MANUFACTURER_ID[10:0]
The MANUFACTURER ID[10:0] bits represent the 11 bit manufacturer’s code assigned to
PMC-Sierra, Inc. for inclusion in the JTAG Boundary Scan Identification Code. For more
information on JTAG Boundary Scan, refer to Section 12.
JID
The JID bit is bit 0 in the JTAG identification code.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 77
Document ID: PMC-2010883, Issue 2
Page 79
SBSLITE™ Telecom Standard Product Data Sheet
Register 004H: SBSLITE Master Bypass Register
Bit Type Function Default
Bit 15 Unused 0
Bit 14 Unused 0
Bit 13 Unused 0
Bit 12 Unused 0
Bit 11 Unused 0
Bit 10 Unused 0
Bit 9 Unused 0
Bit 8 Unused 0
Bit 7 Unused 0
Bit 6 Unused 0
Bit 5 R/W IMSU_BYPASS 0
Bit 4 R/W ICASE_BYPASS 0
Bit 3 R/W ICASM_BYPASS 0
Bit 2 R/W OMSU_BYPASS 0
Bit 1 R/W OCASE_BYPASS 0
Bit 0 R/W OCASM_BYPASS 0
Preliminary
IMSU_BYPASS
The IMSU_BYPASS bit is used to bypass the functionality of the IMSU block. When
IMSU_BYPASS is a logic one, the incoming memory switch is bypassed and the incoming
data bus is passed to the transmit data bus unmodified. This eliminates the one frame delay
through the IMSU and places the IMSU in a low power mode. When IMSU_BYPASS is a
logic zero, the IMSU is not bypassed and must be configured.
ICASE_BYPASS
The ICASE_BYPASS bit is used to bypass the functionality of the ICASE block. When
ICASE_BYPASS is a logic one, the incoming CAS extractor is bypassed and the CAS bits
are not extracted from the SBI336 bus. This places the ICASE block in a low power mode.
When ICASE_BYPASS is a logic zero, the ICASE is not bypassed and the CAS bits are
extracted from the SBI336 bus.
ICASM_BYPASS
The ICASM_BYPASS bit is used to bypass the functionality of the ICASM block. When
ICASM_BYPASS is a logic one, the incoming CAS merge block is bypassed and the CAS
bits are not inserted into the SBI336 bus. This places the ICASM block in a low power
mode. When ICASM_BYPASS is a logic zero, the ICASM is not bypassed and the CAS bits
are inserted into the SBI336 bus.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 78
Document ID: PMC-2010883, Issue 2
Page 80
SBSLITE™ Telecom Standard Product Data Sheet
Preliminary
OMSU_BYPASS
The OMSU_BYPASS bit is used to bypass the functionality of the OMSU block. When
OMUS_BYPASS is a logic one, the outgoing memory switch is bypassed and the receive
data bus is passed to the outgoing data bus unmodified. This eliminates the one frame delay
through the OMSU and places the OMSU in a low power mode. When OMSU_BYPASS is a
logic zero, the OMSU is not bypassed and must be configured.
OCASE_BYPASS
The OCASE_BYPASS bit is used to bypass the functionality of the OCASE block. When
OCASE_BYPASS is a logic one, the transmit CAS extractor is bypassed and the CAS bits are
not extracted from the SBI336 bus. This places the OCASE block in a low power mode.
When OCASE_BYPASS is a logic zero, the OCASE is not bypassed and the CAS bits are
extracted from the SBI336 bus.
OCASM_BYPASS
The OCASM_BYPASS bit is used to bypass the functionality of the OCASM block. When
OCASM_BYPASS is a logic one, the transmit CAS merge block is bypassed and the CAS
bits are not inserted into the SBI336 bus. This places the OCASM block in a low power
mode. When OCASM_BYPASS is a logic zero, the OCASM is not bypassed and the CAS
bits are inserted into the SBI336 bus.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 79
Document ID: PMC-2010883, Issue 2
Page 81
SBSLITE™ Telecom Standard Product Data Sheet
Register 005H: SBSLITE Master SPE Control #1
Bit Type Function Default
Bit 15 Unused 0
Bit 14 Unused 0
Bit 13 Unused 0
Bit 12 Unused 0
Bit 11 Unused 0
Bit 10 Unused 0
Bit 9 Unused 0
Bit 8 Unused 0
Bit 7 R/W SBI4_SPE3_TYP[1] 0
Bit 6 R/W SBI4_SPE3_TYP[0] 0
Bit 5 R/W SBI3_SPE3_TYP[1] 0
Bit 4 R/W SBI3_SPE3_TYP[0] 0
Bit 3 R/W SBI2_SPE3_TYP[1] 0
Bit 2 R/W SBI2_SPE3_TYP[0] 0
Bit 1 R/W SBI1_SPE3_TYP[1] 0
Bit 0 R/W SBI1_SPE3_TYP[0] 0
Preliminary
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 80
Document ID: PMC-2010883, Issue 2
Page 82
SBSLITE™ Telecom Standard Product Data Sheet
Register 006H: SBSLITE Master SPE Control #2
Bit Type Function Default
Bit 15 R/W SBI4_SPE2_TYP[1] 0
Bit 14 R/W SBI4_SPE2_TYP[0] 0
Bit 13 R/W SBI3_SPE2_TYP[1] 0
Bit 12 R/W SBI3_SPE2_TYP[0] 0
Bit 11 R/W SBI2_SPE2_TYP[1] 0
Bit 10 R/W SBI2_SPE2_TYP[0] 0
Bit 9 R/W SBI1_SPE2_TYP[1] 0
Bit 8 R/W SBI1_SPE2_TYP[0] 0
Bit 7 R/W SBI4_SPE1_TYP[1] 0
Bit 6 R/W SBI4_SPE1_TYP[0] 0
Bit 5 R/W SBI3_SPE1_TYP[1] 0
Bit 4 R/W SBI3_SPE1_TYP[0] 0
Bit 3 R/W SBI2_SPE1_TYP[1] 0
Bit 2 R/W SBI2_SPE1_TYP[0] 0
Bit 1 R/W SBI1_SPE1_TYP[1] 0
Bit 0 R/W SBI1_SPE1_TYP[0] 0
Preliminary
SBIx_SPEy_TYP[1:0]
The SBIx_SPEy_TYP[1:0] bits select the SPE type for the specified SPE within the specified
SBI bus. The types for each SPE are independently configured with possible types being T1,
E1, DS3/E3 and fractional rate links. These bits only have an effect when in SBI mode
(TELECOM_BUS = ‘b0 in the SBS Master Configuration Register). The setting for
SBIx_SPEy_TYP[1:0] are:
SBIx_SPEy_TYP[1:0] Payload Type
00 T1
01 E1
10 DS3/E3
11 Fractional Rate
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 81
Document ID: PMC-2010883, Issue 2
Page 83
SBSLITE™ Telecom Standard Product Data Sheet
Register 007H: SBSLITE Receive Synchronization Delay
Bit Type Function Default
Bit 15 R TIP 0
Bit 14 Unused 0
Bit 13 R/W RC1FPDLY[13] 0
Bit 12 R/W RC1FPDLY[12] 0
Bit 11 R/W RC1FPDLY[11] 0
Bit 10 R/W RC1FPDLY[10] 0
Bit 9 R/W RC1FPDLY[9] 0
Bit 8 R/W RC1FPDLY[8] 0
Bit 7 R/W RC1FPDLY[7] 0
Bit 6 R/W RC1FPDLY[6] 0
Bit 5 R/W RC1FPDLY[5] 0
Bit 4 R/W RC1FPDLY[4] 0
Bit 3 R/W RC1FPDLY[3] 0
Bit 2 R/W RC1FPDLY[2] 0
Bit 1 R/W RC1FPDLY[1] 0
Bit 0 R/W RC1FPDLY[0] 0
Preliminary
TIP
The transfer in progress bit (TIP) reports the status of latching performance monitor counting
into holding registers. TIP is set high when a transfer is initiated by a write access to the
SBSLITE Master Signal Monitor #1, Accumulation Trigger Register (014H). It is set low
when all the counters in the SBSLITE have transferred their values to holding registers. The
updated counts are now available for reading at the designated registers.
RC1FPDLY[13:0]
The receive transport frame delay bits (RC1FPDLY[13:0]) controls the delay, in SYSCLK
cycles, inserted by the SBSLITE before processing the C1 characters delivered by the receive
serial data links. RC1FPDLY should be set such that after the specified delay the active
receive link should have delivered the C1 character. The relationships between RC1FP,
RC1FPDLY and the receive serial links is described in the Functional Timing section.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 82
Document ID: PMC-2010883, Issue 2
Page 84
SBSLITE™ Telecom Standard Product Data Sheet
Register 008H: SBSLITE In-Bank Link User Bits
Bit Type Function Default
Bit 15 Unused 0
Bit 14 Unused 0
Bit 13 Unused 0
Bit 12 Unused 0
Bit 11 Unused 0
Bit 10 Unused 0
Bit 9 Unused 0
Bit 8 Unused 0
Bit 7 Unused 0
Bit 6 Unused 0
Bit 5 Unused 0
Bit 4 Unused 0
Bit 3 R/W TXWUSER[1] 0
Bit 2 R/W TXWUSER[0] 0
Bit 1 R/W TXPUSER[1] 0
Bit 0 R/W TXPUSER[0] 0
Preliminary
TXWUSER[1:0]
The Transmit Working USER bits (TXWUSER[1:0]) contain the values to be inserted in the
USER[1:0] bits in the header of the working in-band signaling channel.
TXPUSER[1:0]
The Transmit Protection USER bits (TXWUSER[1:0]) contain the values to be inserted in the
USER[1:0] bits in the header of the protection in-band signaling channel.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 83
Document ID: PMC-2010883, Issue 2
Page 85
SBSLITE™ Telecom Standard Product Data Sheet
Register 010H: SBSLITE Master Interrupt Source
Bit Type Function Default
Bit 15 Unused 0
Bit 14 R SBS_INT X
Bit 13 R IMSU_INT X
Bit 12 R OMSU_INT X
Bit 11 R REFDLL_INT X
Bit 10 R SYSDLL_INT X
Bit 9 R CSTR_INT X
Bit 8 R TW8E_INT X
Bit 7 R TP8E_INT X
Bit 6 R RW8D_INT X
Bit 5 R RP8D_INT X
Bit 4 R WPP_INT X
Bit 3 R PPP_INT X
Bit 2 R WILC_INT X
Bit 1 R PILC_INT X
Bit 0 R ISTA_INT X
Preliminary
SBS_INT
If the SBS_INT bit is a logic one, an interrupt has been generated by the top level circuitry.
The SBSLITE Interrupt register must be read to clear this interrupt.
IMSU_INT
If the IMSU_INT bit is a logic one, an interrupt has been generated by the IMSU block. The
IMSU Interrupt register must be read to clear this interrupt.
OMSU_INT
If the OMSU_INT bit is a logic one, an interrupt has been generated by the OMSU block.
The OMSU Interrupt register must be read to clear this interrupt.
REFDLL_INT
If the REFDLL_INT bit is a logic one, an interrupt has been generated by the REFDLL block.
The REFDLL Interrupt register must be read to clear this interrupt.
SYSDLL_INT
If the SYSDLL_INT bit is a logic one, an interrupt has been generated by the SYSDLL block.
The SYSDLL Interrupt register must be read to clear this interrupt.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 84
Document ID: PMC-2010883, Issue 2
Page 86
SBSLITE™ Telecom Standard Product Data Sheet
Preliminary
CSTR_INT
If the CSTR_INT bit is a logic one, an interrupt has been generated by the CSTR block. The
CSTR Interrupt register must be read to clear this interrupt.
TW8E_INT
If the TW8E_INT bit is a logic one, an interrupt has been generated by the TW8E block. The
TW8E Interrupt register must be read to clear this interrupt.
TPPP_INT
If the TP8E_INT bit is a logic one, an interrupt has been generated by the TP8E block. The
TP8E Interrupt register must be read to clear this interrupt.
RW8D_INT
If the RW8D_INT bit is a logic one, an interrupt has been generated by the RW8D block.
The RW8D Interrupt register must be read to clear this interrupt.
RP8D_INT
If the RP8D_INT bit is a logic one, an interrupt has been generated by the RP8D block. The
RP8D Interrupt register must be read to clear this interrupt.
WPP_INT
If the WPP_INT bit is a logic one, an interrupt has been generated by the WPP block. The
WPP Interrupt register must be read to clear this interrupt.
PPP_INT
If the PPP_INT bit is a logic one, an interrupt has been generated by the PPP block. The PPP
Interrupt register must be read to clear this interrupt.
WILC_INT
If the WILC_INT bit is a logic one, an interrupt has been generated by the WILC block. The
WILC Interrupt register must be read to clear this interrupt.
PILC_INT
If the PILC_INT bit is a logic one, an interrupt has been generated by the PILC block. The
PILC Interrupt register must be read to clear this interrupt.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 85
Document ID: PMC-2010883, Issue 2
Page 87
SBSLITE™ Telecom Standard Product Data Sheet
ISTA_INT
If the ISTA_INT bit is a logic one, an interrupt has been generated by the ISTA block. The
ISTA Interrupt register must be read to clear this interrupt.
Preliminary
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 86
Document ID: PMC-2010883, Issue 2
Page 88
SBSLITE™ Telecom Standard Product Data Sheet
Register 011H: SBSLITE Interrupt Register
Bit Type Function Default
Bit 15 Unused 0
Bit 14 Unused 0
Bit 13 Unused 0
Bit 12 Unused 0
Bit 11 Unused 0
Bit 10 Unused 0
Bit 9 Unused 0
Bit 8 Unused 0
Bit 7 Unused 0
Bit 6 R ICMP_INT X
Bit 5 R OCMP_INT X
Bit 4 R Reserved X
Bit 3 R Reserved X
Bit 2 R Reserved X
Bit 1 R Reserved X
Bit 0 R Reserved X
Preliminary
ICMP_INT
The ICMP_INT bit is set to a logic one when the ICMP input is sampled by the SBSLITE. In
TelecomBus mode, ICMP is sampled during the first C1 position of every frame, as marked
by IC1FP. In SBI mode, ICMP is sampled during the first C1 position of every 4 or 48 frame
multiframe, as marked by IC1FP. This interrupt may be helpful in scheduling configuration
page changes in the IMSU. This interrupt is enabled with the ICMPE bit in the SBSLITE
Interrupt Enable register. This interrupt bit will be cleared when read.
OCMP_INT
The OCMP_INT bit is set to a logic one when the OCMP input is sampled by the SBSLITE.
In TelecomBus mode, OCMP is sampled during the first C1 position of every frame, as
marked by RC1FP. In SBI mode, OCMP is sampled during the first C1 position of every 4 or
48 frame multiframe, as marked by RC1FP. This interrupt may be helpful in scheduling
configuration page changes in the OMSU. This interrupt is enabled with the OCMPE bit in
the SBSLITE Interrupt Enable register. This interrupt bit will be cleared when read.
Reserved
The Reserved bits should be ignored when this register is read.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 87
Document ID: PMC-2010883, Issue 2
Page 89
SBSLITE™ Telecom Standard Product Data Sheet
Register 012H: SBSLITE Interrupt Enable Register
Bit Type Function Default
Bit 15 Unused 0
Bit 14 Unused 0
Bit 13 Unused 0
Bit 12 Unused 0
Bit 11 Unused 0
Bit 10 Unused 0
Bit 9 Unused 0
Bit 8 Unused 0
Bit 7 Unused 0
Bit 6 R/W ICMPE 0
Bit 5 R/W OCMPE 0
Bit 4 R/W Reserved 0
Bit 3 R/W Reserved 0
Bit 2 R/W Reserved 0
Bit 1 R/W Reserved 0
Bit 0 R/W Reserved 0
Preliminary
ICMPE
The ICMPE interrupt enable bit (ICMPE) is an active high interrupt enable. When ICMPE is
set to a logic one, an interrupt will be asserted on the INTB output when the ICMP_INT bit in
the SBSLITE Interrupt Register is set high. When ICMPE is set to a logic zero, The
ICMP_INT bit will not cause an interrupt.
OCMPE
The OCMPE interrupt enable bit (OCMPE) is an active high interrupt enable. When OCMPE
is set to a logic one, an interrupt will be asserted on the INTB output when the OCMP_INT
bit in the SBSLITE Interrupt Register is set high. When OCMPE is set to a logic zero, The
OCMP_INT bit will not cause an interrupt.
Reserved
The Reserved bits must be set to a logic zero.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 88
Document ID: PMC-2010883, Issue 2
Page 90
SBSLITE™ Telecom Standard Product Data Sheet
Register 013H: SBSLITE Loopback Configuration
Bit Type Function Default
Bit 15 Unused 0
Bit 14 Unused 0
Bit 13 Unused 0
Bit 12 Unused 0
Bit 11 Unused 0
Bit 10 Unused 0
Bit 9 Unused 0
Bit 8 Unused 0
Bit 7 Unused 0
Bit 6 Unused 0
Bit 5 Unused 0
Bit 4 Unused 0
Bit 3 Unused 0
Bit 2 R/W Reserved 0
Bit 1 R/W T82R8LOOP 0
Bit 0 R/W T2RLOOP 0
Preliminary
Reserved
The Reserved bit must be set to a logic zero.
T82R8LOOP
The T82R8LOOP bit enables a diagnostic loopback from the transmit 8B/10B encoded bus to
the receive 8B/10B encoded bus. When T82R8LOOP is a logic one, the entire SBI336 or
TelecomBus is looped back from the output of the TW8E and TP8E to the input of the RW8D
and RP8D, respectively. When T82R8LOOP is a logic zero, no loopback is performed.
T2RLOOP
The T2RLOOP bit enables a diagnostic loopback from the transmit interface to the receive
interface. When T2RLOOP is a logic one, the entire SBI336 or TelecomBus is looped back
from the output of the ICASM to the input of the OCASE. When T2RLOOP is a logic zero,
no loopback is performed.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 89
Document ID: PMC-2010883, Issue 2
Page 91
SBSLITE™ Telecom Standard Product Data Sheet
Register 014H: SBSLITE Master Signal Monitor #1, Accumulation Trigger
Bit Type Function Default
Bit 15 Unused 0
Bit 14 Unused 0
Bit 13 Unused 0
Bit 12 Unused 0
Bit 11 Unused 0
Bit 10 R Reserved X
Bit 9 R Reserved X
Bit 8 R Reserved X
Bit 7 R Reserved X
Bit 6 R RC1FPA X
Bit 5 R SYSCLKA X
Bit 4 R SREFCLKA X
Bit 3 R Reserved X
Bit 2 R Reserved X
Bit 1 R Reserved X
Bit 0 R IC1FPA X
Preliminary
This register provides activity monitoring on major SBSLITE inputs. When a monitored input
makes a low to high transition, the corresponding register bit is set high. The bit will remain high
until this register is read, at which point, all the bits in this register are cleared. Bits that depend
on multiple inputs making a low to high transition must have each input make a low to high
transition between subsequent reads before the activity bit will be set high. The corresponding
register bit reading low indicates a lack of transitions. This register should be read periodically to
detect for stuck at conditions.
Writing to this register delimits the accumulation intervals in the various performance monitor
accumulation registers. Counts accumulated in those registers are transferred to holding registers
where they can be read. The counters themselves are then cleared to begin accumulating events
for a new accumulation interval. To prevent loss of data, accumulation intervals must be 1.0
second or shorter. The bits in this register are not affected by write accesses.
Reserved
The Reserved bits should be ignored when this register is read.
RC1FPA
The RC1FP active bit (RC1FPA) detects low to high transitions on the RC1FP input.
RC1FPA is set high on a rising edge of RC1FP, and is set low when this register is read.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 90
Document ID: PMC-2010883, Issue 2
Page 92
SBSLITE™ Telecom Standard Product Data Sheet
Preliminary
SYSCLKA
The SYSCLK active bit (SYSCLKA) detects low to high transitions on the SYSCLK input.
SYSCLKA is set high on a rising edge of SYSCLK, and is set low when this register is read.
SREFCLKA
The SREFCLK active bit (SREFCLKA) detects low to high transitions on the SREFCLK
input. SREFCLKA is set high on a rising edge of SREFCLK, and is set low when this
register is read.
IC1FPA
The IC1FP active bit (IC1FPA) detects low to high transitions on the IC1FP input. IC1FPA is
set high on a rising edge of IC1FP, and is set low when this register is read.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 91
Document ID: PMC-2010883, Issue 2
Page 93
SBSLITE™ Telecom Standard Product Data Sheet
Register 015H: SBSLITE Master Signal Monitor #2
Bit Type Function Default
Bit 15 R Reserved X
Bit 14 R Reserved X
Bit 13 R Reserved X
Bit 12 R ITPLA X
Bit 11 R Reserved X
Bit 10 R Reserved X
Bit 9 R Reserved X
Bit 8 R IV5A X
Bit 7 R Reserved X
Bit 6 R Reserved X
Bit 5 R Reserved X
Bit 4 R IPLA X
Bit 3 R Reserved X
Bit 2 R Reserved X
Bit 1 R Reserved X
Bit 0 R IDATAA X
Preliminary
This register provides activity monitoring on major SBSLITE inputs. When a monitored input
makes a low to high transition, the corresponding register bit is set high. The bit will remain high
until this register is read, at which point, all the bits in this register are cleared. Bits that depend
on multiple inputs making a low to high transition must have each input make a low to high
transition between subsequent reads before the activity bit will be set high. The corresponding
register bit reading low indicates a lack of transitions. This register should be read periodically to
detect for stuck at conditions.
ITPLA
The ITPL active bit (ITPLA) detects low to high transitions on the ITPL input. ITPLA is set
high when a rising edge has been observed on the ITPL input, and is set low when this
register is read.
IV5A
The IV5 active bit (IV5A) detects low to high transitions on the IV5 input. IV5A is set high
when a rising edge has been observed on the IV5 input, and is set low when this register is
read.
IPLA
The IPL active bit (IPLA) detects low to high transitions on the IPL input. IPLA is set high
when a rising edge has been observed on the IPL input, and is set low when this register is
read.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 92
Document ID: PMC-2010883, Issue 2
Page 94
SBSLITE™ Telecom Standard Product Data Sheet
IDATAA
The IDATA active bit (IDATAA) detects low to high transitions on the IDATA input bus.
IDATAA is set high when rising edges have been observed on all the signals on the
IDATA[7:0] bus, and is set low when this register is read.
Preliminary
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 93
Document ID: PMC-2010883, Issue 2
Page 95
SBSLITE™ Telecom Standard Product Data Sheet
Register 016H: SBSLITE Master Interrupt Enable
Bit Type Function Default
Bit 15 R/W INTE 0
Bit 14 R/W SBSE 0
Bit 13 R/W IMSUE 0
Bit 12 R/W OMSUE 0
Bit 11 R/W REFDLLE 0
Bit 10 R/W SYSDLLE 0
Bit 9 R/W CSTRE 0
Bit 8 R/W TW8EE 0
Bit 7 R/W TP8EE 0
Bit 6 R/W RW8DE 0
Bit 5 R/W RP8DE 0
Bit 4 R/W WPPE 0
Bit 3 R/W PPPE 0
Bit 2 R/W WILCE 0
Bit 1 R/W PILCE 0
Bit 0 R/W ISTAE 0
Preliminary
SBS_INT
If the SBS_INT bit is a logic one, an interrupt has been generated by the top level circuitry.
The SBSLITE Interrupt register must be read to clear this interrupt.
IMSU_INT
If the IMSU_INT bit is a logic one, an interrupt has been generated by the IMSU block. The
IMSU Interrupt register must be read to clear this interrupt.
OMSU_INT
If the OMSU_INT bit is a logic one, an interrupt has been generated by the OMSU block.
The OMSU Interrupt register must be read to clear this interrupt.
REFDLL_INT
If the REFDLL_INT bit is a logic one, an interrupt has been generated by the REFDLL block.
The REFDLL Interrupt register must be read to clear this interrupt.
SYSDLL_INT
If the SYSDLL_INT bit is a logic one, an interrupt has been generated by the SYSDLL block.
The SYSDLL Interrupt register must be read to clear this interrupt.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 94
Document ID: PMC-2010883, Issue 2
Page 96
SBSLITE™ Telecom Standard Product Data Sheet
Preliminary
CSTR_INT
If the CSTR_INT bit is a logic one, an interrupt has been generated by the CSTR block. The
CSTR Interrupt register must be read to clear this interrupt.
TW8E_INT
If the TW8E_INT bit is a logic one, an interrupt has been generated by the TW8E block. The
TW8E Interrupt register must be read to clear this interrupt.
TPPP_INT
If the TP8E_INT bit is a logic one, an interrupt has been generated by the TP8E block. The
TP8E Interrupt register must be read to clear this interrupt.
RW8D_INT
If the RW8D_INT bit is a logic one, an interrupt has been generated by the RW8D block.
The RW8D Interrupt register must be read to clear this interrupt.
RP8D_INT
If the RP8D_INT bit is a logic one, an interrupt has been generated by the RP8D block. The
RP8D Interrupt register must be read to clear this interrupt.
WPP_INT
If the WPP_INT bit is a logic one, an interrupt has been generated by the WPP block. The
WPP Interrupt register must be read to clear this interrupt.
PPP_INT
If the PPP_INT bit is a logic one, an interrupt has been generated by the PPP block. The PPP
Interrupt register must be read to clear this interrupt.
WILC_INT
If the WILC_INT bit is a logic one, an interrupt has been generated by the WILC block. The
WILC Interrupt register must be read to clear this interrupt.
PILC_INT
If the PILC_INT bit is a logic one, an interrupt has been generated by the PILC block. The
PILC Interrupt register must be read to clear this interrupt.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 95
Document ID: PMC-2010883, Issue 2
Page 97
SBSLITE™ Telecom Standard Product Data Sheet
ISTA_INT
If the ISTA_INT bit is a logic one, an interrupt has been generated by the ISTA block. The
ISTA Interrupt register must be read to clear this interrupt.
Preliminary
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 96
Document ID: PMC-2010883, Issue 2
Page 98
SBSLITE™ Telecom Standard Product Data Sheet
Register 017H: SBSLITE Free User Register
Bit Type Function Default
Bit 15 Unused 0
Bit 14 Unused 0
Bit 13 Unused 0
Bit 12 Unused 0
Bit 11 Unused 0
Bit 10 Unused 0
Bit 9 Unused 0
Bit 8 Unused 0
Bit 7 R/W FREE[7] 0
Bit 6 R/W FREE[6] 0
Bit 5 R/W FREE[5] 0
Bit 4 R/W FREE[4] 0
Bit 3 R/W FREE[3] 0
Bit 2 R/W FREE[2] 0
Bit 1 R/W FREE[1] 0
Bit 0 R/W FREE[0] 0
Preliminary
FREE[7:0]
The software ID register (FREE) holds whatever value is written into it. Reset clears the
contents of this register. This register has no impact on the operation of the SBSLITE.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 97
Document ID: PMC-2010883, Issue 2
Page 99
SBSLITE™ Telecom Standard Product Data Sheet
Register 020H: ISTA Incoming Parity Configuration
Bit Type Function Default
Bit 15 R/W Reserved 0
Bit 14 R/W Reserved 0
Bit 13 R/W Reserved 0
Bit 12 R/W IPE 0
Bit 11 R/W Reserved 0
Bit 10 R/W Reserved 0
Bit 9 R/W Reserved 0
Bit 8 R/W INCLIC1 0
Bit 7 R/W Reserved 0
Bit 6 R/W Reserved 0
Bit 5 R/W Reserved 0
Bit 4 R/W INCLIPL 0
Bit 3 R/W Reserved 0
Bit 2 R/W Reserved 0
Bit 1 R/W Reserved 0
Bit 0 R/W IOP 0
Preliminary
Reserved
The Reserved bits must be set to a logic zero.
IPE
The incoming parity interrupt enable bit (IPE) is an active high interrupt enable. When IPE is
set to a logic one, the occurrence of a parity error on the incoming bus will cause an interrupt
to be asserted on the INTB output. When IPE is set to a logic zero, incoming parity errors
will not cause and interrupt.
INCLIPL
The INCLIPL bit controls whether the IPL input signal participates in the incoming parity
calculations. When INCLIPL is set to a logic one, the parity signal includes the IPL input.
When INCLIPL is set to a logic zero, parity is calculated without regard to the state of IPL.
These bits only take effect when in TelecomBus mode.
INCLIC1
The INCLIC1 bit controls whether the IC1FP input signal participates in the incoming parity
calculations. When INCLIC1 is set to a logic one, the parity signal includes the IC1FP input.
When INCLIC1 is set to a logic zero, parity is calculated without regard to the state of IC1FP.
These bits only take effect when in TelecomBus mode.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 98
Document ID: PMC-2010883, Issue 2
Page 100
SBSLITE™ Telecom Standard Product Data Sheet
IOP
The incoming odd parity bit (IOP) control the expected parity on the incoming bus. When
IOP is set to a logic one, the expected parity on the IDP input is odd. When IOP is set to a
logic zero, the parity is even. In SBI bus mode, the parity calculation encompasses the
IDATA[7:0], IPL and IV5 signals. In TelecomBus mode, the parity calculation encompasses
the IDATA[7:0] and optionally IPL and IC1FP as determined by the INCLIPL and INCLIC1
bits.
Preliminary
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 99
Document ID: PMC-2010883, Issue 2
Loading...