PMC-1990114 ISSUE 6 84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER
PM7385 FREEDM-84A672
WITH ANY-PHY PACKET INTERFACE
PM7385
FREEDM™-84A672
FRAME ENGINE AND DATALINK
MANAGER 84A672
DATA SHEET
PROPRIETARY AND CONFIDENTIAL
ISSUE 6: AUGUST 2001
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
Page 2
DATA SHEET
PMC-1990114 ISSUE 6 84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER
PM7385 FREEDM-84A672
WITH ANY-PHY PACKET INTERFACE
REVISION HISTORY
Issue No. Issue Date Details of Change
Issue 1 Jan 7, 1999 Creation of Document.
Issue 2 July 8, 1999 Update as per issue 3 of the engineering document (PMC-
981263).
Issue 3 January, 2000 Update as per issue 4 of the engineering document (PMC-
981263), for GCA release.
Issue 4 June 2000 Re-issue to coincide with production release of Rev C of
device. Minor corrections and changes to some DC and AC
timing parameters.
Issue 5 October 2000 Re-issue to coincide with Issue 6 of the Eng Doc.
DEFAULT_DRV register bit changed to PERM_DRV and
description changed. (See PREP #4938.) Change bars have
been kept to show both Issue 4 and Issue 5 changes.
Issue 6 August 2001 Patent information included. Change bars apply to previous
issue.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE i
Page 3
DATA SHEET
PMC-1990114 ISSUE 6 84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER
TABLE 43 – FREEDM-84A672 THERMAL INFORMATION ............................233
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE viii
Page 10
DATA SHEET
PMC-1990114 ISSUE 6 84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER
PM7385 FREEDM-84A672
WITH ANY-PHY PACKET INTERFACE
1 FEATURES
· Single-chip multi-channel HDLC controller with a 50 MHz, 16 bit “Any-PHY”
Packet Interface (APPI) for transfer of packet data using an external
controller.
· Supports up to 672 bi-directional HDLC channels assigned to a maximum of
84 channelised or unchannelised links conveyed via a Scaleable Bandwidth
Interconnect (SBI) interface.
· Data on the SBI interface is divided into 3 Synchronous Payload Envelopes
(SPEs). Each SPE can be configured independently to carry data for either
28 T1/J1 links, 21 E1 links, or 1 unchannelised DS-3 link.
· Links in an SPE can be configured individually to operate in clear channel
mode, in which case, all framing bit locations are assumed to be carrying
HDLC data.
· Links in an SPE can be configured individually to operate in channelised
mode, in which case, the number of time-slots assigned to an HDLC channel
is programmable from 1 to 24 (for T1/J1 links) and from 1 to 31 (for E1 links).
· Supports three bi-directional HDLC channels each assigned to an
unchannelised link with arbitrary rate link of up to 51.84 MHz when SYSCLK
is running at 45 MHz. Each link may be configured individually to replace one
of the SPEs conveyed on the SBI interface.
· For each channel, the HDLC receiver supports programmable flag sequence
detection, bit de-stuffing and frame check sequence validation. The receiver
supports the validation of both CRC-CCITT and CRC-32 frame check
sequences.
· For each channel, the receiver checks for packet abort sequences, octet
aligned packet length and for minimum and maximum packet length. The
receiver supports filtering of packets that are larger than a user specified
maximum value.
· Alternatively, for each channel, the receiver supports a transparent mode
where each octet is transferred transparently on the receive APPI. For
channelised links, the octets are aligned with the receive time-slots.
· For each channel, time-slots are selectable to be in 56 kbits/s format or 64
kbits/s clear channel format.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 1
Page 11
DATA SHEET
PMC-1990114 ISSUE 6 84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER
PM7385 FREEDM-84A672
WITH ANY-PHY PACKET INTERFACE
· For each channel, the HDLC transmitter supports programmable flag
sequence generation, bit stuffing and frame check sequence generation. The
transmitter supports the generation of both CRC-CCITT and CRC-32 frame
check sequences. The transmitter also aborts packets under the direction of
the external controller or automatically when the channel underflows.
· Alternatively, for each channel, the transmitter supports a transparent mode
where each octet is inserted transparently from the transmit APPI. For
channelised links, the octets are aligned with the transmit time-slots.
· Supports per-channel configurable APPI burst sizes of up to 256 bytes for
transfers of packet data.
· The FREEDM maintains packet level performance metrics such as number of
received packets, number of received packets with frame check sequence
errors, number of transmitted packets, number of receive aborted packets,
and number of transmit aborted packets.
· Provides 32 Kbytes of on-chip memory for partial packet buffering in both the
transmit and the receive directions. This memory may be configured to
support a variety of different channel configurations from a single channel with
32 Kbytes of buffering to 672 channels, each with a minimum of 48 bytes of
buffering.
· Provides a 16 bit microprocessor interface for configuration and status
monitoring.
· Provides a standard 5 signal P1149.1 JTAG test port for boundary scan board
test purposes.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 2
Page 12
DATA SHEET
PMC-1990114 ISSUE 6 84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER
PM7385 FREEDM-84A672
WITH ANY-PHY PACKET INTERFACE
2 APPLICATIONS
· IETF PPP interfaces for routers
· Frame Relay interfaces for ATM or Frame Relay switches and multiplexors
· FUNI or Frame Relay service inter-working interfaces for ATM switches and
multiplexors.
· Internet/Intranet access equipment.
· Packet-based DSLAM equipment.
· Packet over SONET.
· PPP over SONET.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 3
Page 13
DATA SHEET
PMC-1990114 ISSUE 6 84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER
PM7385 FREEDM-84A672
WITH ANY-PHY PACKET INTERFACE
3 REFERENCES
1. International Organization for Standardization, ISO Standard 3309-1993,
“Information Technology – Telecommunications and information exchange between
systems – High-level data link control (HDLC) procedures – Frame structure”,
December 1993.
2. RFC-1662 – “PPP in HDLC-like Framing” Internet Engineering Task Force, July
1994.
3. PMC-1981125 – “High Density T1/E1 Framer with Integrated VT/TU Mapper and
M13 Multiplexer (TEMUX) Data Sheet”, PMC-Sierra Inc.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 4
Page 14
DATA SHEET
PMC-1990114 ISSUE 6 84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER
PM7385 FREEDM-84A672
WITH ANY-PHY PACKET INTERFACE
4 BLOCK DIAGRAM
]
0
:
2
1
[
R
D
K
L
D
C
A
X
X
T
T
l
a
i
t
C
r
L
a
)
D
P
N
/
H
t
r
O
i
o
M
m
s
s
s
P
(
n
e
c
a
r
o
r
T
P
l
t
i
e
m
n
s
n
n
a
a
h
r
C
T
]
0
:
5
1
]
]
[
0
0
:
:
Y
A
2
2
T
T
[
[
Y
A
2
1
D
A
A
D
X
R
P
P
T
T
T
T
t
i
Y
t
e
H
m
k
s
P
c
-
n
y
a
a
r
n
P
T
A
r
)
e
f
2
f
7
u
6
B
L
t
e
D
k
H
c
T
a
(
P
)
r
2
e
7
n
6
g
S
i
s
A
s
C
A
T
(
D
P
R
P
X
T
e
c
a
f
r
e
t
n
I
R
O
X
O
R
S
E
M
E
T
T
T
T
)
2
7
6
I
P
A
T
(
t
r
o
P
G
A
T
J
r
o
s
s
e
e
c
c
a
f
o
r
r
e
p
t
o
n
r
I
c
i
M
TDO
TDI
TCK
TMS
TRS TB
INTB
RDB
WRB
CSB
ALE
A[11:2]
D[15:0]
SYSCLK
RSTB
PMCTEST
]
]
0
:
0
:
5
2
1
[
[
R
D
K
L
D
C
A
X
X
R
R
Y
A
T
T
B
A
N
A
D
E
X
P
R
R
R
Y
t
e
v
e
H
i
k
P
e
c
-
c
y
a
e
n
P
R
A
D
P
R
P
X
R
e
c
a
f
r
e
t
n
I
C
L
D
H
e
v
i
e
c
e
R
e
v
i
e
c
e
R
R
L
O
O
A
R
X
E
V
M
E
S
R
R
R
R
)
2
7
6
I
P
A
R
(
l
a
i
t
r
a
P
/
r
o
s
s
e
c
o
r
P
l
e
n
n
a
h
C
R
r
e
)
e
f
c
2
f
u
B
t
e
k
c
a
P
r
e
n
g
i
s
s
A
r
n
7
o
a
6
t
i
L
m
n
r
D
o
o
f
H
r
M
R
e
(
P
)
2
7
6
S
A
C
R
(
SPE1_EN
SPE2_EN
SPE3_EN
REFCLK
FASTCLK
C1FP
C1FPOUT
]
0
:
2
[
K
L
C
R
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 5
O
O
S
I
P
I
B
S
]
]
0
:
2
[
D
R
L
0
:
P
7
D
[
A
T
A
D
D
O
S
S
I
I
P
P
I
I
B
B
S
S
t
c
I
a
r
B
t
S
x
E
5
P
V
D
D
D
O
O
P
I
S
I
B
S
]
L
5
0
:
P
V
7
A
A
[
A
T
A
D
A
O
P
P
I
I
S
S
I
I
B
B
S
S
t
r
I
e
B
s
S
n
I
]
]
]
P
E
Q
D
E
A
R
_
T
S
U
J
A
0
0
0
:
:
:
V
I
T
C
A
A
2
2
1
[
[
[
T
K
D
L
T
C
C
E
T
T
E
D
A
Page 15
DATA SHEET
PMC-1990114 ISSUE 6 84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER
PM7385 FREEDM-84A672
WITH ANY-PHY PACKET INTERFACE
5 DESCRIPTION
The PM7385 FREEDM-84A672 Frame Engine and Datalink Manager device is a
monolithic integrated circuit that implements HDLC processing for a maximum of
672 bi-directional channels.
The FREEDM-84A672 may be configured to support channelised T1/J1/E1 or
unchannelised traffic on up to 84 links conveyed via a Scaleable Bandwidth
Interconnect (SBI) interface. The SBI interface transports data in three
Synchronous Payload Envelopes (SPEs), each of which may be configured
independently to carry either 28 T1/J1 links, 21 E1 links or a single DS-3 link.
For channelised T1/J1/E1 links, the FREEDM-84A672 allows up to 672 bidirectional HDLC channels to be assigned to individual time-slots within each
independently timed T1/J1 or E1 link. The channel assignment supports the
concatenation of time-slots (N x DS0) up to a maximum of 24 concatenated timeslots for a T1/J1 link and 31 concatenated time-slots for an E1 link. Time-slots
assigned to any particular channel need not be contiguous within a T1/J1 or E1
link. Unchannelised DS-3 links are assigned to a single HDLC channel.
Additionally, links may be configured independently to operate in an unframed or
“clear channel” mode, in which the bit periods which are normally reserved for
framing information in fact carry HDLC data. In unframed mode, links operate as
unchannelised (i.e. the entire link is assigned to a single HDLC channel)
regardless of link rate.
The FREEDM-84A672 supports mixing of channelised T1/J1/E1 and
unchannelised or unframed links. The total number of channels in each direction
is limited to 672. The maximum possible data rate over all links is 134.208 Mbps
(which occurs with three DS-3 links running in unframed mode).
The FREEDM-84A672 supports three independently timed bidirectional clock/
data links, each carrying a single unchannellised HDLC stream. The links can be
of arbitrary frame format and can operate at up to 51.84 MHz provided SYSCLK
is running at 45 MHz. When activated, each link replaces one of the SPEs
conveyed on the SBI interface. (The maximum possible data rate when all three
clock/data links are activated is 155.52 Mbps.)
The FREEDM-84A672 provides a low latency “Any-PHY” packet interface (APPI)
to allow an external controller direct access into the 32 Kbyte partial packet
buffers. Up to seven FREEDM-84A672 devices may share a single APPI. For
each of the transmit and receive APPI, the external controller is the master of the
FREEDM-84A672 device sharing the APPI from the point of view of device
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 6
Page 16
DATA SHEET
PMC-1990114 ISSUE 6 84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER
PM7385 FREEDM-84A672
WITH ANY-PHY PACKET INTERFACE
selection. The external controller is also the master for channel selection in the
transmit direction. In the receive direction, however, each FREEDM-84A672
device retains control over selection of its respective channels. The transmit and
receive APPI is made up of three groups of functional signals – polling, selection
and data transfer. The polling signals are used by the external controller to
interrogate the status of the transmit and receive 32 Kbyte partial packet buffers.
The selection signals are used by the external controller to select a FREEDM84A672 device, or a channel within a FREEDM-84A672 device, for data transfer.
The data transfer signals provide a means of transferring data across the APPI
between the external controller and a FREEDM-84A672 device.
In the receive direction, polling and selection are done at the device level.
Polling is not decoupled from selection, as the receive address pins serve as
both a device poll address and to select a FREEDM-84A672 device. In response
to a positive poll, the external controller may select that FREEDM-84A672 device
for data transfer. Once selected, the FREEDM-84A672 prepends an in-band
channel address to each partial packet transfer across the receive APPI to
associate the data with a channel. A FREEDM-84A672 must not be selected
after a negative poll response.
In the transmit direction, polling is done at the channel level. Polling is
completely decoupled from selection. To increase the polling bandwidth, up to
two channels may be polled simultaneously. The polling engine in the external
controller runs independently of other activity on the transmit APPI. In response
to a positive poll, the external controller may commence partial packet data
transfer across the transmit APPI for the successfully polled channel of a
FREEDM-84A672 device. The external controller must prepend an in-band
channel address to each partial packet transfer across the transmit APPI to
associate the data with a channel.
In the receive direction, the FREEDM-84A672 performs channel assignment and
packet extraction and validation. For each provisioned HDLC channel, the
FREEDM-84A672 delineates the packet boundaries using flag sequence
detection, and performs bit de-stuffing. Sharing of opening and closing flags, as
well as sharing of zeros between flags are supported. The resulting packet data
is placed into the internal 32 Kbyte partial packet buffer RAM. The partial packet
buffer acts as a logical FIFO for each of the assigned channels. An external
controller transfers partial packets out of the RAM, across the receive APPI bus,
into host packet memory. The FREEDM-84A672 validates the frame check
sequence for each packet, and verifies that the packet is an integral number of
octets in length and is within a programmable minimum and maximum lengths.
Receive APPI bus latency may cause one or more channels to overflow, in which
case, the packets are aborted. The FREEDM-84A672 reports the status of each
packet on the receive APPI at the end of each packet transfer.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 7
Page 17
DATA SHEET
PMC-1990114 ISSUE 6 84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER
PM7385 FREEDM-84A672
WITH ANY-PHY PACKET INTERFACE
Alternatively, in the receive direction, the FREEDM-84A672 supports a
transparent operating mode. For each provisioned transparent channel, the
FREEDM-84A672 directly transfers the received octets onto the receive APPI
verbatim. If the transparent channel is assigned to a channelised link, then the
octets are aligned to the received time-slots.
In the transmit direction, an external controller provides packets to transmit using
the transmit APPI. For each provisioned HDLC channel, an external controller
transfers partial packets, across the transmit APPI, into the internal 32 Kbyte
transmit partial packet buffer. The partial packets are read out of the partial
packet buffer by the FREEDM-84A672 and a frame check sequence is optionally
calculated and inserted at the end of each packet. Bit stuffing is performed
before being assigned to a particular link. The flag or idle sequence is
automatically inserted when there is no packet data for a particular channel.
Sequential packets are optionally separated by a single flag (combined opening
and closing flag) or up to 128 flags. Zeros between flags are not shared in the
transmit direction although, as stated previously, they are accepted in the receive
direction. Transmit APPI bus latency may cause one or more channels to
underflow, in which case, the packets are aborted. The FREEDM-84A672
generates an interrupt to notify the host of aborted packets. For normal traffic, an
abort sequence is generated, followed by inter-frame time fill characters (flags or
all-ones bytes) until a new packet is sourced on the transmit APPI. The
FREEDM-84A672 will not attempt to re-transmit aborted packets.
Alternatively, in the transmit direction, the FREEDM-84A672 supports a
transparent operating mode. For each provisioned transparent channel, the
FREEDM-84A672 directly inserts the transmitted octets provided on the transmit
APPI. If the transparent channel is assigned to a channelised link, then the
octets are aligned to the transmitted time-slots. If a channel underflows due to
excessive transmit APPI bus latency, an abort sequence is generated, followed
by inter-frame time fill characters (flags or all-ones bytes) to indicate idle channel.
Data resumes immediately when the FREEDM-84A672 receives new data on the
transmit APPI.
The FREEDM-84A672 is configured, controlled and monitored using the
microprocessor interface. The FREEDM-84A672 is implemented in low power
2.5 Volt 0.25 mm CMOS technology. All FREEDM-84A672 I/O are 3.3 volt
tolerant. The FREEDM-84A672 is packaged in a 352 pin enhanced ball grid
array (SBGA) package.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 8
Page 18
DATA SHEET
PM7385 FREEDM-84A672
PMC-1990114 ISSUE 6 84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER
WITH ANY-PHY PACKET INTERFACE
6 PIN DIAGRAM
The FREEDM-84A672 is manufactured in a 352 pin enhanced ball grid array
(SBGA) package.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 9
Page 19
DATA SHEET
PMC-1990114 ISSUE 6 84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER
PM7385 FREEDM-84A672
WITH ANY-PHY PACKET INTERFACE
7 PIN DESCRIPTION
Table 1 – SBI Interface Signals (30)
Pin Name Type Pin
Function
No.
REFCLK Input AB3 The SBI reference clock signal (REFCLK)
provides reference timing for the SBI ADD
and DROP busses.
REFCLK is nominally a 50% duty cycle clock
of frequency 19.44 MHz ±50ppm.
FASTCLK Input Y1 The high-speed reference clock signal
(FASTCLK) is used by the FREEDM-84A672
to generate an internal clock for use when
processing DS-3 links.
FASTCLK is nominally a 50% duty cycle,
±50ppm clock having one of the following
frequencies: 51.84 MHz, 44.928 MHz or
66 MHz.
C1FP Input AE5 The C1 octet frame pulse signal (C1FP)
provides frame synchronisation for devices
connected via an SBI interface. C1FP must
be asserted for 1 REFCLK cycle every 500 µs
or multiples thereof (i.e. every 9720 n
REFCLK cycles, where n is a positive
integer). All devices interconnected via an
SBI interface must be synchronised to a
C1FP signal from a single source.
C1FP is sampled on the rising edge of
REFCLK.
Note – If the SBI bus is being operated in
synchronous mode [Ref. 3], C1FP must be
asserted for 1 REFCLK cycle every 6 ms or
multiples thereof.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 10
Page 20
DATA SHEET
PMC-1990114 ISSUE 6 84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER
Pin Name Type Pin
Function
PM7385 FREEDM-84A672
WITH ANY-PHY PACKET INTERFACE
No.
C1FPOUT Output AA4 The C1 octet frame pulse output signal
(C1FPOUT) may be used to provide frame
synchronisation for devices interconnected
via an SBI interface. C1FPOUT is asserted
for 1 REFCLK cycle every 500 µs (i.e. every
9720 REFCLK cycles). If C1FPOUT is used
for synchronisation, it must be connected to
the C1FP inputs of all the devices connected
to the SBI interface.
C1FPOUT is updated on the rising edge of
REFCLK.
Note – The C1FPOUT pulse generated by
FREEDM-84A672 is not suitable for use in
systems in which the SBI bus is operated in
synchronous mode [Ref. 3].
The SBI DROP bus data signals
(DDATA[7:0]) contain the time division
multiplexed receive data from the up to 84
independently timed links. Data from each
link is transported as a tributary within the SBI
TDM bus structure. Multiple PHY devices
can drive the SBI DROP bus at uniquely
assigned tributary column positions.
DDATA[7:0] are sampled on the rising edge of
REFCLK.
DDP Input AC6 The SBI DROP bus parity signal (DDP)
carries the even or odd parity for the DROP
bus signals. The parity calculation
encompasses the DDATA[7:0], DPL and DV5
signals.
Multiple PHY devices can drive DDP at
uniquely assigned tributary column positions.
This parity signal is intended to detect
accidental PHY source clashes in the column
assignment.
DDP is sampled on the rising edge of
REFCLK.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 11
Page 21
DATA SHEET
PMC-1990114 ISSUE 6 84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER
Pin Name Type Pin
Function
PM7385 FREEDM-84A672
WITH ANY-PHY PACKET INTERFACE
No.
DPL Input AD1 The SBI DROP bus payload signal (DPL)
indicates valid data within the SBI TDM bus
structure. This signal is asserted during all
octets making up a tributary. This signal may
be asserted during the V3 or H3 octet within a
tributary to accommodate negative timing
adjustments between the tributary rate and
the fixed TDM bus structure. This signal may
be deasserted during the octet following the
V3 or H3 octet within a tributary to
accommodate positive timing adjustments
between the tributary rate and the fixed TDM
bus structure.
Multiple PHY devices can drive DPL at
uniquely assigned tributary column positions.
DPL is sampled on the rising edge of
REFCLK.
DV5 Input AE4 The SBI DROP bus payload indicator signal
(DV5) locates the position of the floating
payloads for each tributary within the SBI
TDM bus structure. Timing differences
between the port timing and the TDM bus
timing are indicated by adjustments of this
payload indicator relative to the fixed TDM
bus structure.
Multiple PHY devices can drive DV5 at
uniquely assigned tributary column positions.
All movements indicated by this signal must
be accompanied by appropriate adjustments
in the DPL signal.
DV5 is sampled on the rising edge of
REFCLK.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 12
Page 22
DATA SHEET
PMC-1990114 ISSUE 6 84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER
The SBI ADD bus data signals (ADATA[7:0])
contain the time division multiplexed transmit
data from the up to 84 independently timed
links. Data from each link is transported as a
tributary within the SBI TDM bus structure.
Multiple link layer devices can drive the SBI
ADD bus at uniquely assigned tributary
column positions. ADATA[7:0] are tristated
when the FREEDM-84A672 is not outputting
data on a particular tributary column.
ADATA[7:0] are updated on the rising edge of
REFCLK.
ADP Tristat
e
Output
AD5 The SBI ADD bus parity signal (ADP) carries
the even or odd parity for the ADD bus
signals. The parity calculation encompasses
the ADATA[7:0], APL and AV5 signals.
Multiple link layer devices can drive this
signal at uniquely assigned tributary column
positions. ADP is tristated when the
FREEDM-84A672 is not outputting data on a
particular tributary column. This parity signal
is intended to detect accidental link layer
source clashes in the column assignment.
ADP is updated on the rising edge of
REFCLK.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 13
Page 23
DATA SHEET
PMC-1990114 ISSUE 6 84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER
Pin Name Type Pin
Function
PM7385 FREEDM-84A672
WITH ANY-PHY PACKET INTERFACE
No.
APL Tristat
e
Output
AC2 The SBI ADD bus payload signal (APL)
indicates valid data within the SBI TDM bus
structure. This signal is asserted during all
octets making up a tributary. This signal may
be asserted during the V3 or H3 octet within a
tributary to accommodate negative timing
adjustments between the tributary rate and
the fixed TDM bus structure. This signal may
be deasserted during the octet following the
V3 or H3 octet within a tributary to
accommodate positive timing adjustments
between the tributary rate and the fixed TDM
bus structure.
Multiple link layer devices can drive this
signal at uniquely assigned tributary column
positions. APL is tristated when the
FREEDM-84A672 is not outputting data on a
particular tributary column.
AV5 Tristat
e
output
APL is updated on the rising edge of
REFCLK.
AB4 The SBI ADD bus payload indicator signal
(AV5) locates the position of the floating
payloads for each tributary within the SBI
TDM bus structure. Timing differences
between the port timing and the TDM bus
timing are indicated by adjustments of this
payload indicator relative to the fixed TDM
bus structure.
Multiple link layer devices can drive this
signal at uniquely assigned tributary column
positions. AV5 is tristated when the
FREEDM-84A672 is not outputting data on a
particular tributary column.
AV5 is updated on the rising edge of
REFCLK.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 14
Page 24
DATA SHEET
PMC-1990114 ISSUE 6 84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER
Pin Name Type Pin
Function
PM7385 FREEDM-84A672
WITH ANY-PHY PACKET INTERFACE
No.
AJUST_REQ Input AC12 The SBI ADD bus justification request signal
(AJUST_REQ) is used to speed up or slow
down the output data rate of the FREEDM84A672.
Negative timing adjustments are requested by
asserting AJUST_REQ during the V3 or H3
octet, depending on the tributary type. In
response to this the FREEDM-84A672 will
send an extra byte in the V3 or H3 octet of
the next frame along with a valid APL
indicating a negative justification.
Positive timing adjustments are requested by
asserting AJUST_REQ during the octet
following the V3 or H3 octet, depending on
the tributary type. FREEDM-84A672 will
respond to this by not sending an octet during
the octet following the V3 or H3 octet of the
next frame and deasserting APL to indicate a
positive justification.
AJUST_REQ is sampled on the rising edge of
REFCLK.
AACTIVE Output AF4 The SBI ADD bus active indicator signal
(AACTIVE) is asserted whenever FREEDM84A672 is driving the SBI ADD bus signals,
ADATA[7:0], ADP, APL and AV5.
All other Link Layer devices driving the SBI
ADD bus should monitor this signal (to detect
multiple sources accidentaly driving the bus)
and should cease driving the bus whenever a
conflict is detected.
AACTIVE is updated on the rising edge of
REFCLK.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 15
Page 25
DATA SHEET
PMC-1990114 ISSUE 6 84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER
Pin Name Type Pin
Function
PM7385 FREEDM-84A672
WITH ANY-PHY PACKET INTERFACE
No.
ADETECT[0]
ADETECT[1]
Input AD12
AF12
The SBI ADD bus conflict detection signals
(ADETECT[1:0]) may be connected to the
AACTIVE outputs of other link layer devices
sharing the SBI ADD bus. FREEDM-84A672
will immediately tristate the SBI ADD bus
signals ADATA[7:0], ADP, APL and AV5 if
either of ADETECT[1] and ADETECT[0] is
asserted.
ADETECT[1:0] are asynchronous inputs.
Table 2 – Clock/Data Interface Signals (15)
Pin Name Type Pin
Function
No.
RCLK[0]
RCLK[1]
RCLK[2]
RD[0]
RD[1]
RD[2]
Input T1
R2
P3
Input R4
R3
R1
The receive line clock signals (RCLK[2:0])
contain the recovered line clock for the 3
independently timed links. RCLK[n] must be
externally gapped during the bits or time-slots
that are not part of the transmission format
payload (i.e. not part of the HDLC packet).
RCLK[2:0] is nominally a 50% duty cycle
clock between 0 and 51.84 MHz.
The RCLK[n] inputs are invalid and should be
tied low when their associated link is not
configured for operation (i.e. SPEn_EN input
is high).
The receive data signals (RD[2:0]) contain the
recovered line data for the 3 independently
timed links. RD[2:0] contain HDLC packet
data. For certain transmission formats,
RD[2:0] may contain place holder bits or timeslots. RCLK[n] must be externally gapped
during the place holder positions in the RD[n]
stream. The FREEDM-84A672 supports a
maximum data rate of 51.84 Mbit/s on each
link. RD[2:0] are sampled on the rising edge
of the corresponding RCLK[2:0].
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 16
Page 26
DATA SHEET
PMC-1990114 ISSUE 6 84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER
Pin Name Type Pin
Function
PM7385 FREEDM-84A672
WITH ANY-PHY PACKET INTERFACE
No.
TCLK[0]
TCLK[1]
TCLK[2]
Input AB1
AA3
AC1
The transmit line clock signals (TCLK[2:0])
contain the transmit clocks for the 3
independently timed links. TCLK[n] must be
externally gapped during the bits or time-slots
that are not part of the transmission format
payload (i.e. not part of the HDLC packet).
TCLK[2:0] is nominally a 50% duty cycle
clock between 0 and 51.84 MHz.
The TCLK[n] inputs are invalid and should be
tied low when their associated link is not
configured for operation (i.e. SPEn_EN input
is high).
TD[0]
TD[1]
TD[2]
Output AA2
Y4
AB2
The transmit data signals (TD[2:0]) contain
the transmit data for the 3 independently
timed links. TD[2:0] contain HDLC packet
data. For certain transmission formats,
TD[2:0] may contain place holder bits or timeslots. TCLK[n] must be externally gapped
during the place holder positions in the TD[n]
stream. The FREEDM-84A672 supports a
maximum data rate of 51.84 Mbit/s on each
link.
TD[2:0] are updated on the falling edge of the
corresponding TCLK[2:0] clock.
SPE1_EN
SPE2_EN
SPE3_EN
Input Y2
AA1
W4
The Synchronous Payload Envelope Enable
signals (SPEn_EN) configure the operation of
the clock/data inputs and the SBI Interface.
When SPEn_EN is low, the corresponding
Synchronous Payload Envelope conveyed on
the SBI interface is unused and the
corresponding independently timed link
(signals RCLK[n-1], RD[n-1], TCLK[n-1] and
TD[n-1]) is enabled. When SPEn_EN is high,
the corresponding Synchronous Payload
Envelope conveyed on the SBI interface is
enabled and the corresponding independently
timed link is disabled.
SPEn_EN are asynchronous inputs.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 17
Page 27
DATA SHEET
PMC-1990114 ISSUE 6 84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER
PM7385 FREEDM-84A672
WITH ANY-PHY PACKET INTERFACE
Table 3 – Any-PHY Packet Interface Signals (70)
Pin Name Type Pin
Function
No.
TXCLK Input H26 The transmit clock signal (TXCLK) provides
timing for the transmit Any-PHY packet
interface. TXCLK is a nominally 50% duty
cycle, 25 to 50 MHz clock.
The transmit address signals (TXADDR[12:0])
provide a channel address for polling a transmit
channel FIFO. The 10 least significant bits
provide the channel number (0 to 671) while the
3 most significant bits select one of seven
possible FREEDM-84A672 devices sharing a
single external controller. (One address is
reserved as a null address.) The Tx APPI of
each FREEDM-84A672 device is identified by
the base address in the TAPI672 Control
register.
The TXADDR[12:0] signals are sampled on the
rising edge of TXCLK.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 18
Page 28
DATA SHEET
PMC-1990114 ISSUE 6 84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER
Pin Name Type Pin
Function
PM7385 FREEDM-84A672
WITH ANY-PHY PACKET INTERFACE
No.
TPA1[0]
TPA1[1]
TPA1[2]
TPA2[0]
TPA2[1]
TPA2[2]
Tristate
Output
D26
F23
E24
D25
C26
B23
The transmit packet available signals (TPA1[2:0]
and TPA2[2:0]) reflects the status of a poll of
two transmit channel FIFOs. TPA1[2:0] returns
the polled results for channel address ‘n’
provided on TXADDR[12:0] and TPA2[2:0]
returns the polled results for channel address
‘n+1’. TPAn[2] reports packet underrun events
and TPAn[1:0] report the fill state of the transmit
channel FIFO. TPAn[2] is set high when one or
more packets has underrun on the channel and
a further data transfer has occurred since it was
last polled. When TPAn[2] is set low, no packet
has underrun on the channel since the last poll.
TPAn[1:0] are coded as follows:
TPAn[1:0] = “11” => Starving
TPAn[1:0] = “10” => (Reserved)
TPAn[1:0] = “01” => Space
TPAn[1:0] = “00” => Full
A “Starving” polled response indicates that the
polled transmit channel FIFO is at risk of
underflowing and should be supplied with data
as soon as possible. A “Space” polled response
indicates that the polled transmit channel FIFO
can accept XFER[3:0] plus one blocks (16 bytes
per block) of data. A “Full” polled response
indicates that the polled transmit channel FIFO
cannot accept XFER[3:0] plus one blocks of
data. (XFER[3:0] is a per-channel
programmable value – see description of
register 0x38C.)
It is the responsibility of the external controller to
prevent channel underflow conditions by
adequately polling each channel before data
transfer.
TPAn[2:0] are tristate during reset and when a
device address other than the FREEDM84A672’s base address is provided on
TXADDR[12:10].
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 19
Page 29
DATA SHEET
PMC-1990114 ISSUE 6 84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER
Pin Name Type Pin
Function
PM7385 FREEDM-84A672
WITH ANY-PHY PACKET INTERFACE
No.
TPAn[2:0] are updated on the rising edge of
TXCLK.
TRDY Tristate
Output
U26 The transmit ready signal (TRDY) indicates the
ability of the transmit Any-PHY packet interface
(APPI) to accept data. When TRDY is set low,
the transmit APPI is unable to accept further
data. When TRDY is set high, data provided on
the transmit APPI will be accepted by the
FREEDM-84A672 device.
TRDY is asserted one TXCLK cycle after TSX is
sampled high. TRDY is asserted by the
FREEDM-84A672 device which was selected by
the in-band channel address on TXDATA[15:0]
when TSX was sampled high. If TRDY is driven
low, the external controller must hold the data
on TXDATA[15:0] until TRDY is driven high.
TRDY may be driven low for 0 or more TXCLK
cycles before it is driven high. TRDY is always
driven tristate one TXCLK cycle after it is driven
high.
TRDY is tristate during reset.
TRDY is updated on the rising edge of TXCLK.
It is recommended that TRDY be connected
externally to a weak pull-up, e.g. 10 kW.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 20
Page 30
DATA SHEET
PMC-1990114 ISSUE 6 84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER
The transmit data signals (TXDATA[15:0])
contain the transmit Any-PHY packet interface
(APPI) data provided by the external controller.
Data must be presented in big endian order, i.e.
the byte in TXDATA[15:8] is transmitted by the
FREEDM-84A672 before the byte in
TXDATA[7:0].
The first word of each data transfer contains an
address to identify the device and channel
associated with the data being transferred. This
prepended address must be qualified with the
TSX signal. The 10 least significant bits provide
the channel number (0 to 671) while the 3 most
significant bits select one of seven possible
FREEDM-84A672 devices sharing a single
external controller. (One address is reserved as
a null address.) The FREEDM-84A672 will not
respond to channel addresses outside the range
0 to 671, nor to device addresses other than the
base address stored in the TAPI672 Control
register.
The second and any subsequent words of each
data transfer contain packet data.
The TXDATA[15:0] signals are sampled on the
rising edge of TXCLK.
TXPRTY Input M23 The transmit parity signal (TXPRTY) reflects the
odd parity calculated over the TXDATA[15:0]
signals. TXPRTY is only valid when
TXDATA[15:0] are valid.
TXPRTY is sampled on the rising edge of
TXCLK.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 21
Page 31
DATA SHEET
PMC-1990114 ISSUE 6 84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER
Pin Name Type Pin
Function
PM7385 FREEDM-84A672
WITH ANY-PHY PACKET INTERFACE
No.
TSX Input M24 The transmit start of transfer signal (TSX)
denotes the start of data transfer on the transmit
APPI. When the TSX signal is sampled high,
the sampled word on the TXDATA[15:0] signals
contain the device and channel address
associated with the data to follow. When the
TSX signal is sampled low, the sampled word
on the TXDATA[15:0] signals do not contain a
device/channel address.
The TSX signal is sampled on the rising edge of
TXCLK.
TEOP Input T26 The transmit end of packet signal (TEOP)
denotes the end of a packet. TEOP is only valid
during data transfer. When TEOP is sampled
high, the data on TXDATA[15:0] is the last word
of a packet. When TEOP is sampled low, the
data on TXDATA[15:0] is not the last word of a
packet.
TEOP is sampled on the rising edge of TXCLK.
TMOD Input R23 The transmit word modulo signal (TMOD)
indicates the size of the current word on
TXDATA[15:0]. TMOD is only valid when TEOP
is sampled high. When TMOD is sampled high
and TEOP is sampled high, only the
TXDATA[15:8] signals contain valid data and the
TXDATA[7:0] signals are invalid. When TMOD
is sampled low and TEOP is sampled high, the
complete word on TXDATA[15:0] contains valid
data. TMOD must be set low when TEOP is set
low.
TMOD is sampled on the rising edge of TXCLK.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 22
Page 32
DATA SHEET
PMC-1990114 ISSUE 6 84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER
Pin Name Type Pin
Function
PM7385 FREEDM-84A672
WITH ANY-PHY PACKET INTERFACE
No.
TERR Input T25 The transmit error signal (TERR) indicates that
the current packet is errored and should be
aborted. TERR is only valid when TEOP is
sampled high. When TERR is sampled high
and TEOP is sampled high, the current packet is
errored and the FREEDM-84A672 will respond
accordingly. When TERR is sampled low and
TEOP is sampled high, the current packet is not
errored. TERR must be set low when TEOP is
set low.
TERR is sampled on the rising edge of TXCLK.
RXCLK Input AE23 The receive clock signal (RXCLK) provides
timing for the receive Any-PHY packet interface
(APPI). RXCLK is a nominally 50% duty cycle,
25 to 50 MHz clock.
RXADDR[0]
RXADDR[1]
RXADDR[2]
Input AF23
AC21
AD22
The receive address signals (RXADDR[2:0])
serve two functions – device polling and device
selection. When polling, the RXADDR[2:0]
signals provide an address for polling a
FREEDM-84A672 device for receive data
available in any one of its 672 channels. Polling
results are returned on the RPA tristate output.
During selection, the address on the
RXADDR[2:0] signals is qualified with the RENB
signal to select a FREEDM-84A672 device
enabling it to output data on the receive APPI.
Note that up to seven FREEDM-84A672
devices may share a single external controller
(one address is reserved as a null address).
The Rx APPI of each FREEDM-84A672 device
is identified by the base address in the RAPI672
Control register.
The RXADDR[2:0] signals are sampled on the
rising edge of RXCLK.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 23
Page 33
DATA SHEET
PMC-1990114 ISSUE 6 84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER
Pin Name Type Pin
Function
PM7385 FREEDM-84A672
WITH ANY-PHY PACKET INTERFACE
No.
RPA Tristate
Output
U25 The receive packet available signal (RPA)
reflects the status of a poll on the receive APPI
of a FREEDM-84A672 device. When RPA is set
high, the polled FREEDM-84A672 device has
XFER[3:0] plus one blocks (16 bytes per block)
of data to transfer, or alternatively, a smaller
amount of data which includes an end of packet.
When RPA is set low, the polled FREEDM84A672 device does not have data ready to
transfer. (XFER[3:0] is a per-channel
programmable value – see description of
register 0x208.)
A FREEDM-84A672 device must not be
selected for receive data transfer unless it has
been polled and responded that it has data
ready to transfer.
When the RXADDR[2:0] inputs match the base
address in the RAPI672 Control register, that
FREEDM-84A672 device drives RPA one
RXCLK cycle after sampling RXADDR[2:0].
RPA is tristate during reset and when a device
address other than the FREEDM-84A672’s base
address is provided on RXADDR[2:0].
RPA is updated on the rising edge of RXCLK.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 24
Page 34
DATA SHEET
PMC-1990114 ISSUE 6 84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER
Pin Name Type Pin
Function
PM7385 FREEDM-84A672
WITH ANY-PHY PACKET INTERFACE
No.
RENB Input T23 The receive enable signal (RENB) qualifies the
RXADDR[2:0] signals for selection of a
FREEDM-84A672 device. When RENB is
sampled high and then low in consecutive
RXCLK cycles, the address on RXADDR[2:0]
during the cycle when RENB is sampled high
selects a FREEDM-84A672 device enabling it to
output data on the receive APPI. The Rx APPI
of each FREEDM-84A672 device is identified by
the base address in the RAPI672 Control
register.
The polling function of the RXADDR[2:0] and
RPA signals operates regardless of the state of
RENB.
RENB may also be used to throttle the
FREEDM-84A672 during data transfer on the
Rx APPI. When the FREEDM-84A672 samples
RENB high during data transfer, the FREEDM84A672 will pause the data transfer and tri-state
the receive APPI outputs (except RPA) until
RENB is returned low. Since the Any-PHY bus
specification does not support deselection
during data transfers, the address on the
RXADDR[2:0] inputs during the cycle before
RENB is returned low must either re-select the
same FREEDM-84A672 device or be a null
address.
To commence data transfer, RENB must be
sampled low following device selection.
It is the responsibility of the external controller to
prevent overflow by providing each FREEDM84A672 device on an Any-PHY point to multipoint bus sufficient bandwidth through selection.
RENB is sampled on the rising edge of RXCLK.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 25
Page 35
DATA SHEET
PMC-1990114 ISSUE 6 84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER
The receive data signals (RXDATA[15:0])
contain the receive Any-PHY packet interface
(APPI) data output by the FREEDM-84A672
when selected. Data is presented in big endian
format, i.e. the byte in RXDATA[15:8] was
received by the FREEDM-84A672 before the
byte in RXDATA[7:0].
The first word of each data transfer (when RSX
is high) contains an address to identify the
device and channel associated with the data
being transferred. The 10 least significant bits
(RXDATA[9:0]) contain the channel number (0 to
671) and the 3 most significant bits
(RXDATA[15:13]) contain the device base
address. The second and any subsequent
words of each data transfer contain valid data.
The FREEDM-84A672 may be programmed to
overwrite RXDATA[7:0] of the final word of each
packet transfer (REOP is high) with the status of
packet reception when that packet is errored
(RERR is high). This status information is bit
mapped as follows:
The RXDATA[15:0] signals are tristated when
the FREEDM-84A672 device is not selected via
the RENB signal.
The RXDATA[15:0] signals are updated on the
rising edge of RXCLK.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 26
Page 36
DATA SHEET
PMC-1990114 ISSUE 6 84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER
Pin Name Type Pin
Function
PM7385 FREEDM-84A672
WITH ANY-PHY PACKET INTERFACE
No.
RXPRTY Tristate
Output
W26 The receive parity signal (RXPRTY) reflects the
odd parity calculated over the RXDATA[15:0]
signals. RXPRTY is driven/tristated at the same
time as RXDATA[15:0].
RXPRTY is updated on the rising edge of
RXCLK.
RSX Tristate
Output
AA25 The receive start of transfer signal (RSX)
denotes the start of data transfer on the receive
APPI. When the RSX signal is set high, the 3
most significant bits on the RXDATA[15:0]
signals contain the FREEDM-84A672 device
address and the 10 least significant bits on the
RXDATA[15:0] signals contain the channel
address associated with the data to follow. Valid
device addresses are in the range 0 through 7
(with one address reserved as a null address)
and valid channel addresses are in the range 0
through 671. When the RSX signal is sampled
low, the word on the RXDATA[15:0] signals does
not contain a device and channel address.
REOP Tristate
V26 The receive end of packet signal (REOP)
Output
RSX is tristated when the FREEDM-84A672
device is not selected via the RENB signal.
RSX is updated on the rising edge of RXCLK.
It is recommended that RSX be connected
externally to a weak pull-down, e.g. 10 kW.
denotes the end of a packet. REOP is only valid
during data transfer. When REOP is set high,
RXDATA[15:0] contains the last data byte of a
packet. When REOP is set low, RXDATA[15:0]
does not contain the last data byte of a packet.
REOP is tristated when the FREEDM-84A672
device is not selected via the RENB signal.
REOP is updated on the rising edge of RXCLK.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 27
Page 37
DATA SHEET
PMC-1990114 ISSUE 6 84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER
Pin Name Type Pin
Function
PM7385 FREEDM-84A672
WITH ANY-PHY PACKET INTERFACE
No.
RMOD Tristate
Output
U24 The receive word modulo signal (RMOD)
indicates the size of the current word on
RXDATA[15:0]. When RDAT[15:0] does not
contain the last byte of a packet (REOP set
low), RMOD is set low. When RMOD is set high
and REOP is set high, RXDATA[15:8] contains
the last data byte of a packet. When RMOD is
set low and REOP is set high, RXDATA[7:0]
contains the last byte of the packet, or
optionally, the error status byte. The behavior of
RMOD relates only to packet data and is
unaffected when the FREEDM-84A672 device is
programmed to overwrite RXDATA[7:0] with
status information when errored packets are
received.
RERR Tristate
V25 The receive error signal (RERR) indicates that
Output
RMOD is tristated when the FREEDM-84A672
device is not selected via the RENB signal.
RMOD is updated on the rising edge of RXCLK.
the current packet is errored and should be
discarded. When RDAT[15:0] does not contain
the last byte of a packet (REOP set low), RERR
is set low. When RERR is set high and REOP is
set high, the current packet is errored. When
RERR is set low and REOP is set high, the
current packet is not errored.
The FREEDM-84A672 may be programmed to
overwrite RXDATA[7:0] of the final word of each
packet transfer (REOP set high) with the status
of packet reception when that packet is errored
(RERR is high).
RERR is tristated when the FREEDM-84A672
device is not selected via the RENB signal.
RERR is updated on the rising edge of RXCLK.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 28
Page 38
DATA SHEET
PMC-1990114 ISSUE 6 84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER
Pin Name Type Pin
Function
PM7385 FREEDM-84A672
WITH ANY-PHY PACKET INTERFACE
No.
RVAL Tristate
Output
T24 The receive data valid (RVAL) is asserted when
packet data is being output on RXDATA[15:0]. It
is deasserted whenever the FREEDM-84A672
device is selected, but not outputting packet
data on RXDATA[15:0]. (E.g., when RSX is high
and address/channel prepend is being output on
RXDATA[15:0], RVAL is deasserted.)
RVAL is tristated when the FREEDM-84A672
device is not selected via the RENB signal.
RVAL is updated on the rising edge of RXCLK.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 29
Page 39
DATA SHEET
PMC-1990114 ISSUE 6 84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER
The bi-directional data signals (D[15:0]) provide
a data bus to allow the FREEDM-84A672 device
to interface to an external micro-processor.
Both read and write transactions are supported.
The microprocessor interface is used to
configure and monitor the FREEDM-84A672
ALE Input A16 The address latch enable signal (ALE) latches
the A[11:2] signals during the address phase of
a bus transaction. When ALE is set high, the
address latches are transparent. When ALE is
set low, the address latches hold the address
provided on A[11:2].
ALE has an integral pull-up resistor.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 30
Page 40
DATA SHEET
PMC-1990114 ISSUE 6 84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER
Pin Name Type Pin
Function
PM7385 FREEDM-84A672
WITH ANY-PHY PACKET INTERFACE
No.
WRB Input C15 The write strobe signal (WRB) qualifies write
accesses to the FREEDM-84A672 device.
When CSB is set low, the D[15:0] bus contents
are clocked into the addressed register on the
rising edge of WRB.
RDB Input B15 The read strobe signal (RDB) qualifies read
accesses to the FREEDM-84A672 device.
When CSB is set low, the FREEDM-84A672
device drives the D[15:0] bus with the contents
of the addressed register on the falling edge of
RDB.
CSB Input A15 The chip select signal (CSB) qualifies read/write
accesses to the FREEDM-84A672 device. The
CSB signal must be set low during read and
write accesses. When CSB is set high, the
microprocessor interface signals are ignored by
the FREEDM-84A672 device.
INTB Open-
C14 The interrupt signal (INTB) indicates that an
Drain
Output
If CSB is not required (register accesses
controlled only by WRB and RDB) then CSB
should be connected to an inverted version of
the RSTB signal.
interrupt source is active and unmasked. When
INTB is set low, the FREEDM-84A672 device
has an active interrupt that is unmasked. When
INTB is tristate, no interrupts are active, or an
active interrupt is masked. Please refer to the
register description section of this document for
possible interrupt sources and masking.
It is the responsibility of the external
microprocessor to read the status registers in
the FREEDM-84A672 device to determine the
exact cause of the interrupt.
INTB is an open drain output.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 31
Page 41
DATA SHEET
PMC-1990114 ISSUE 6 84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER
PM7385 FREEDM-84A672
WITH ANY-PHY PACKET INTERFACE
Table 5 – Miscellaneous Interface Signals (111)
Pin Name Type Pin
Function
No.
SYSCLK Input L1 The system clock (SYSCLK) provides timing for
the core logic. SYSCLK is nominally a 50% duty
cycle clock of frequency 45 MHz ±50ppm.
RSTB Input E3 The active low reset signal (RSTB) signal
provides an asynchronous FREEDM-84A672
reset. RSTB is an asynchronous input. When
RSTB is set low, all FREEDM-84A672 registers
are forced to their default states. In addition, all
SBI, APPI and µP interface output pins are forced
tristate and will remain tristated until RSTB is set
high.
PMCTEST Input AE22The PMC production test enable signal
(PMCTEST) places the FREEDM-84A672 is test
mode. When PMCTEST is set high, production
test vectors can be executed to verify
manufacturing via the test mode interface signals
TA[11:0], TA[12]/TRS, TRDB, TWRB and
TDAT[15:0]. PMCTEST must be tied low for
normal operation.
TCK Input U4 The test clock signal (TCK) provides timing for
test operations that can be carried out using the
IEEE P1149.1 test access port. TMS and TDI are
sampled on the rising edge of TCK. TDO is
updated on the falling edge of TCK.
TMS Input W1 The test mode select signal (TMS) controls the
test operations that can be carried out using the
IEEE P1149.1 test access port. TMS is sampled
on the rising edge of TCK. TMS has an integral
pull up resistor.
TDI Input V3 The test data input signal (TDI) carries test data
into the FREEDM-84A672 via the IEEE P1149.1
test access port. TDI is sampled on the rising
edge of TCK.
TDI has an integral pull up resistor.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 32
Page 42
DATA SHEET
PMC-1990114 ISSUE 6 84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER
Pin Name Type Pin
Function
PM7385 FREEDM-84A672
WITH ANY-PHY PACKET INTERFACE
No.
TDO Tristate
Output
W2 The test data output signal (TDO) carries test
data out of the FREEDM-84A672 via the IEEE
P1149.1 test access port. TDO is updated on the
falling edge of TCK. TDO is a tristate output
which is inactive except when scanning of data is
in progress.
TRSTB Input V2 The active low test reset signal (TRSTB) provides
an asynchronous FREEDM-84A672 test access
port reset via the IEEE P1149.1 test access port.
TRSTB is an asynchronous input with an integral
pull up resistor.
Note that when TRSTB is not being used, it must
be connected to the RSTB input.
NC1-103 Open These pins must be left unconnected.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 33
Page 43
DATA SHEET
PMC-1990114 ISSUE 6 84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER
The test mode address bus (TA[11:0]) selects
specific registers during production test
(PMCTEST set high) read and write accesses.
In normal operation (PMCTEST set low), these
signals should be grounded.
TA[12]/TRS Input B9 The test register select signal (TA[12]/TRS)
selects between normal and test mode register
accesses during production test (PMCTEST set
high). TRS is set high to select test registers
and is set low to select normal registers. In
normal operation (PMCTEST set low), this
signal should be grounded.
TRDB Input C8 The test mode read enable signal (TRDB) is set
low during FREEDM-84A672 register read
accesses during production test (PMCTEST set
high). The FREEDM-84A672 drives the test
data bus (TDAT[15:0]) with the contents of the
addressed register while TRDB is low. In normal
operation (PMCTEST set low), this signal should
be tied to logic 1.
TWRB Input B8 The test mode write enable signal (TWRB) is set
low during FREEDM-84A672 register write
accesses during production test (PMCTEST set
high). The contents of the test data bus
(TDAT[15:0]) are clocked into the addressed
register on the rising edge of TWRB. In normal
operation (PMCTEST set low), this signal should
be tied to logic 1.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 34
Page 44
DATA SHEET
PMC-1990114 ISSUE 6 84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER
The bi-directional test mode data bus
(TDAT[15:0]) carries data read from or written to
FREEDM-84A672 registers during production
test (PMCTEST set high). In normal operation
(PMCTEST set low), these signals should be left
The VSS[28:1] DC ground pins should be
connected to ground. They provide a ground
reference for the 3.3 V rail. They also
provide a ground reference for the 2.5 V rail.
Notes on Pin Description:
1. All FREEDM-84A672 inputs and bi-directionals present minimum capacitive
loading and are 3.3V tolerant.
2. All FREEDM-84A672 outputs and bi-directionals have 8 mA drive capability
except TDO, which has 4 mA drive capability.
3. All FREEDM-84A672 outputs can be tristated under control of the IEEE
P1149.1 test access port, even those which do not tristate under normal
operation. All outputs and bi-directionals are 3.3 V tolerant when tristated.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 37
Page 47
DATA SHEET
PMC-1990114 ISSUE 6 84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER
PM7385 FREEDM-84A672
WITH ANY-PHY PACKET INTERFACE
4. All inputs with the exception of the Any-PHY interface are Schmitt triggered.
Inputs ALE, TMS, TDI and TRSTB have internal pull-up resistors.
5. Power to the VDD3V3 pins should be applied before power to the VDD2V5
pins is applied. Similarly, power to the VDD2V5 pins should be removed
before power to the VDD3V3 pins is removed.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 38
Page 48
DATA SHEET
PMC-1990114 ISSUE 6 84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER
The Scaleable Bandwidth Interconnect is a synchronous, time-division
multiplexed bus designed to transfer, in a pin-efficient manner, data belonging to
a number of independently timed links of varying bandwidth. The bus is timed to
a reference 19.44MHz clock and a 2 kHz or 166.7Hz frame pulse. All sources
and sinks of data on the bus are timed to the reference clock and frame pulse.
Timing is communicated across the Scaleable Bandwidth Interconnect by floating
data structures. Payload indicator signals in the SBI control the position of the
floating data structure and therefore the timing. When sources are running faster
than the SBI the floating payload structure is advanced by an octet by passing an
extra octet in the V3 octet locations (H3 octet for DS3 mappings). When the
source is slower than the SBI the floating payload is retarded by leaving the octet
after the V3 or H3 octet unused. Both these rate adjustments are indicated by
the SBI control signals.
An SBI interface consists of a DROP BUS and an ADD BUS. On the DROP BUS
all timing is sourced from the PHY and is passed onto the FREEDM-84A672 by
the arrival rate of data over the SBI. On the ADD BUS timing can be controlled
by either the PHY or the FREEDM-84A672. When the FREEDM-84A672 is the
timing master, the PHY device determines its transmit timing information from the
arrival rate of data across the SBI. When the PHY device is the timing master, it
signals the FREEDM-84A672 to speed up or slow down with justification request
signals. The PHY timing master indicates a speedup request to the Link Layer
by asserting the justification request signal high during the V3 or H3 octet. When
this is detected by the FREEDM-84A672 it will advance the channel by inserting
data in the next V3 or H3 octet as described above. The PHY timing master
indicates a slowdown request to the FREEDM-84A672 by asserting the
justification request signal high during the octet after the V3 or H3 octet. The
FREEDM-84A672 responds by leaving the octet following the next V3 or H3 octet
unused. Both advance and retard rate adjustments take place in the frame or
multi-frame following the justification request.
The SBI multiplexing structure is modeled on the SONET/SDH standards. The
SONET/SDH virtual tributary structure is used to carry T1/J1 and E1 links.
Unchannelized DS3 payloads follow a byte synchronous structure modeled on
the SONET/SDH format.
The SBI structure uses a locked SONET/SDH structure fixing the position of the
TUG-3/TU-3 relative to the STS-3/STM-1 transport frame. The SBI is also of fixed
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 39
Page 49
DATA SHEET
PMC-1990114 ISSUE 6 84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER
PM7385 FREEDM-84A672
WITH ANY-PHY PACKET INTERFACE
frequency and alignment as determined by the reference clock (REFCLK) and
frame indicator signal (C1FP). Frequency deviations are compensated by
adjusting the location of the T1/J1/E1/DS3 channels using floating tributaries as
determined by the V5 indicator and payload signals (DV5, AV5, DPL and APL).
The multiplexed links are separated into three Synchronous Payload Envelopes.
Each envelope may be configured independently to carry up to 28 T1/J1s, 21
E1s or a DS3.
8.2 High-Level Data Link Control (HDLC) Protocol
Figure 1 shows a diagram of the synchronous HDLC protocol supported by the
FREEDM-84A672 device. The incoming stream is examined for flag bytes
(01111110 bit pattern) which delineate the opening and closing of the HDLC
packet. The packet is bit de-stuffed which discards a “0” bit which directly follows
five contiguous “1” bits. The resulting HDLC packet size must be a multiple of an
octet (8 bits) and within the expected minimum and maximum packet length
limits. The minimum packet length is that of a packet containing two information
bytes (address and control) and FCS bytes. For packets with CRC-CCITT as
FCS, the minimum packet length is four bytes while those with CRC-32 as FCS,
the minimum length is six bytes. An HDLC packet is aborted when seven
contiguous “1” bits (with no inserted “0” bits) are received. At least one flag byte
must exist between HDLC packets for delineation. Contiguous flag bytes, or all
ones bytes between packets are used as an “inter-frame time fill”. Adjacent flag
bytes may share zeros.
Figure 1 – HDLC Frame
FlagInformationFCSFlag
HDLC Packet
The CRC algorithm for the frame checking sequence (FCS) field is either a
CRC-CCITT or CRC-32 function. Figure 2 shows a CRC encoder block diagram
using the generating polynomial g(X) = 1 + g
X + g2X2 +…+ g
1
CRC-CCITT FCS is two bytes in size and has a generating polynomial g(X) = 1 +
5
X
+ X12 + X16. The CRC-32 FCS is four bytes in size and has a generating
+ X26 + X32. The first FCS bit received is the residue of the highest term.
+ X
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 40
n-1
Flag
n-1
X
+ Xn. The
Page 50
DATA SHEET
PMC-1990114 ISSUE 6 84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER
PM7385 FREEDM-84A672
WITH ANY-PHY PACKET INTERFACE
Figure 2 – CRC Generator
g
1
D
0
LSBMSB
D
1
8.3 SBI Extracter and PISO
g
2
Parity Check Digits
g
n-1
D
2
D
n-1
Message
The SBI receive circuitry consists of an SBI Extract block and three SBI Parallel
to Serial Converter (SBI PISO) blocks. The SBI Extract block receives data from
the SBI DROP BUS and converts it to an internal parallel bus format. The
received data is then converted to serial bit streams by the PISO blocks. Each
PISO block processes one of the three Synchronous Payload Envelopes (SPEs)
conveyed on the SBI DROP BUS.
The SBI Extract block may be configured to enable or disable reception of
individual tributaries within the SBI DROP bus. Individual tributaries may also be
configured to operate in framed or unframed mode.
Each PISO block processes data from one SPE on the internal parallel bus and
generates either 28 serial data streams at T1/J1 rate, 21 streams at E1 rate or a
single stream at DS-3 rate. These serial streams are then processed by the
Receive Channel Assigner block.
8.4 Receive Channel Assigner
The Receive Channel Assigner block (RCAS672) processes up to 84 serial links.
When receiving data from the SBI PISO blocks, links may be configured to
support channelised T1/J1/E1 traffic, unchannelised DS-3 traffic or unframed
traffic at T1/J1, E1 or DS-3 rates. When receiving data from the RCLK/RD
inputs, links 0, 1 and 2 support unchannelised data at arbitary rates up to 51.84
Mbps.
Each link is independent and has its own associated clock. For each link, the
RCAS672 performs a serial to parallel conversion to form data bytes. The data
bytes are multiplexed, in byte serial format, for delivery to the Receive HDLC
Processor / Partial Packet Buffer block (RHDL672) at SYSCLK rate. In the event
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 41
Page 51
DATA SHEET
PMC-1990114 ISSUE 6 84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER
PM7385 FREEDM-84A672
WITH ANY-PHY PACKET INTERFACE
where multiple streams have accumulated a byte of data, multiplexing is
performed on a fixed priority basis with link #0 having the highest priority and link
#83 the lowest.
The 84 RCAS links have a fixed relationship to the SPE and tributary numbers on
the SBI DROP BUS as shown in the following table.
Table 8 – SBI SPE/Tributary to RCAS Link Mapping
SBI
SPE
No.
SBI
Trib.
No.
RCAS
Link
No.
SBI
SPE
No.
SBI
Trib.
No.
RCAS
Link
No.
SBI
SPE
No.
SBI
Trib.
No.
RCAS
Link
No.
1 1 0 2 1 1 3 1 2
1 2 3 2 2 4 3 2 5
1 3 6 2 3 7 3 3 8
1 4 9 2 4 10 3 4 11
1 5 12 2 5 13 3 5 14
1 6 15 2 6 16 3 6 17
1 7 18 2 7 19 3 7 20
1 8 21 2 8 22 3 8 23
1 9 24 2 9 25 3 9 26
1 10 27 2 10 28 3 10 29
1 11 30 2 11 31 3 11 32
1 12 33 2 12 34 3 12 35
1 13 36 2 13 37 3 13 38
1 14 39 2 14 40 3 14 41
1 15 42 2 15 43 3 15 44
1 16 45 2 16 46 3 16 47
1 17 48 2 17 49 3 17 50
1 18 51 2 18 52 3 18 53
1 19 54 2 19 55 3 19 56
1 20 57 2 20 58 3 20 59
1 21 60 2 21 61 3 21 62
1 22 63 2 22 64 3 22 65
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 42
Page 52
DATA SHEET
PMC-1990114 ISSUE 6 84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER
SBI
SPE
No.
SBI
Trib.
No.
RCAS
Link
No.
SBI
SPE
No.
SBI
Trib.
No.
RCAS
Link
No.
SBI
SPE
No.
PM7385 FREEDM-84A672
WITH ANY-PHY PACKET INTERFACE
SBI
Trib.
No.
RCAS
Link
No.
1 23 66 2 23 67 3 23 68
1 24 69 2 24 70 3 24 71
1 25 72 2 25 73 3 25 74
1 26 75 2 26 76 3 26 77
1 27 78 2 27 79 3 27 80
1 28 81 2 28 82 3 28 83
Links containing a T1/J1 or an E1 stream may be channelised. Data at each
time-slot may be independently assigned to a different channel. The RCAS672
performs a table lookup to associate the link and time-slot identity with a channel.
The position of T1/J1 and E1 framing bits/bytes is identified by frame pulse
signals generated by the SBI PISO blocks. Links containing a DS-3 stream are
unchannelised, i.e. all data on the link belongs to one channel. The RCAS672
performs a table lookup using only the link number to determine the associated
channel, as time-slots are non-existent in unchannelised links. Links may
additionally be configured to operate in an unframed “clear channel” mode, in
which all bit positions, including those normally reserved for framing information,
are assumed to be carrying HDLC data. Links so configured operate as
unchannelised regardless of link rate and the RCAS672 performs a table lookup
using only the link number to determine the associated channel.
8.4.1 Line Interface
There are 84 line interface blocks in the RCAS672. Each line interface block
contains a bit counter, an 8-bit shift register and a holding register that, together,
perform serial to parallel conversion. Whenever the holding register is updated,
a request for service is sent to the priority encoder block. When acknowledged
by the priority encoder, the line interface responds with the data residing in the
holding register.
To support channelised links, each line interface block contains a time-slot
counter. The time-slot counter is incremented each time the holding register is
updated and is reset on detection of a frame pulse from the SBI PISO blocks.
For unchannelised or unframed links, the time-slot counter is held reset.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 43
Page 53
DATA SHEET
PMC-1990114 ISSUE 6 84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER
PM7385 FREEDM-84A672
WITH ANY-PHY PACKET INTERFACE
8.4.2 Priority Encoder
The priority encoder monitors the line interfaces for requests and synchronises
them to the SYSCLK timing domain. Requests are serviced on a fixed priority
scheme where highest to lowest priority is assigned from the line interface
attached to link 0 to that attached to link 83. Thus, simultaneous requests from
link ‘m’ will be serviced ahead of link ‘n’, if m < n. When there are no pending
requests, the priority encoder generates an idle cycle. In addition, once every
fourth SYSCLK cycle, the priority encoder inserts a null cycle where no requests
are serviced. This cycle is used by the channel assigner downstream for host
microprocessor accesses to the provisioning RAMs.
8.4.3 Channel Assigner
The channel assigner block determines the channel number of the data byte
currently being processed. The block contains a 2688 word channel provision
RAM. The address of the RAM is constructed from concatenating the link
number and the time-slot number of the current data byte. The fields of each
RAM word include the channel number and a time-slot enable flag. The time-slot
enable flag labels the current time-slot as belonging to the channel indicated by
the channel number field.
8.4.4 Loopback Controller
The loopback controller block implements the channel based diagnostic loopback
function. Every valid data byte belonging to a channel with diagnostic loopback
enabled from the Transmit HDLC Processor / Partial Packet Buffer block
(THDL672) is written into a 256 word FIFO. The loopback controller monitors for
an idle time-slot or a time-slot carrying a channel with diagnostic loopback
enabled. If either conditions hold, the current data byte is replaced by data
retrieved from the loopback data FIFO.
The Receive HDLC Processor / Partial Packet Buffer block (RHDL672)
processes up to 672 synchronous transmission HDLC data streams. Each
channel can be individually configured to perform flag sequence detection, bit destuffing and CRC-CCITT or CRC-32 verification. The packet data is written into
the partial packet buffer. At the end of a frame, packet status including CRC
error, octet alignment error and maximum length violation are also loaded into the
partial packet buffer. Alternatively, a channel can be provisioned as transparent,
in which case, the HDLC data stream is passed to the partial packet buffer
processor verbatim.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 44
Page 54
DATA SHEET
PMC-1990114 ISSUE 6 84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER
PM7385 FREEDM-84A672
WITH ANY-PHY PACKET INTERFACE
There is a natural precedence in the alarms detectable on a receive packet.
Once a packet exceeds the programmable maximum packet length, no further
processing is performed on it. Thus, octet alignment detection, FCS verification
and abort recognition are squelched on packets with a maximum length violation.
An abort indication squelches octet alignment detection, minimum packet length
violations, and FCS verification. In addition, FCS verification is only performed
on packets that do not have octet alignment errors, in order to allow the
RHDL672 to perform CRC calculations on a byte-basis.
The partial packet buffer is a 32 Kbyte RAM that is divided into 16-byte blocks.
Each block has an associated pointer which points to another block. A logical
FIFO is created for each provisioned channel by programming the block pointers
to form a circular linked list. A channel FIFO can be assigned a minimum of 3
blocks (48 bytes) and a maximum of 2048 blocks (32 Kbytes). The depth of the
channel FIFOs are monitored in a round-robin fashion. Requests are made to
the Receive Any-PHY Interface block (RAPI672) to transfer, on the Rx APPI, data
in channel FIFOs with depths exceeding their associated threshold.
8.5.1 HDLC Processor
The HDLC processor is a time-slice state machine which can process up to 672
independent channels. The state vector and provisioning information for each
channel is stored in a RAM. Whenever new channel data arrives, the
appropriate state vector is read from the RAM, processed and written back to the
RAM. The HDLC state-machine can be configured to perform flag delineation, bit
de-stuffing, CRC verification and length monitoring. The resulting HDLC data
and status information is passed to the partial packet buffer processor to be
stored in the appropriate channel FIFO buffer.
The configuration of the HDLC processor is accessed using indirect channel read
and write operations. When an indirect operation is performed, the information is
accessed from RAM during a null clock cycle generated by the upstream Receive
Channel Assigner block (RCAS672). Writing new provisioning data to a channel
resets the channel’s entire state vector.
8.5.2 Partial Packet Buffer Processor
The partial packet buffer processor controls the 32 Kbyte partial packet RAM
which is divided into 16 byte blocks. A block pointer RAM is used to chain the
partial packet blocks into circular channel FIFO buffers. Thus, non-contiguous
sections of the RAM can be allocated in the partial packet buffer RAM to create a
channel FIFO. System software is responsible for the assignment of blocks to
individual channel FIFOs. Figure 3 shows an example of three blocks (blocks 1,
3, and 200) linked together to form a 48 byte channel FIFO.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 45
Page 55
DATA SHEET
PMC-1990114 ISSUE 6 84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER
PM7385 FREEDM-84A672
WITH ANY-PHY PACKET INTERFACE
Figure 3 – Partial Packet Buffer Structure
Block 0
Block 1
Block 2
Block 3
Partial Packet
Buffer RAM
16 bytes
16 bytes
16 bytes
16 bytes
Block 0
Block 1
Block 2
Block 3
Block
Pointer RAM
XX
0x03
XX
0xC8
0x01
XX
Block 2047
16 bytes
16 bytes
Block 200Block 200
Block 2047
The partial packet buffer processor is divided into three sections: writer, reader
and roamer. The writer is a time-sliced state machine which writes the HDLC
data and status information from the HDLC processor into a channel FIFO in the
packet buffer RAM. The reader transfers channel FIFO data from the packet
buffer RAM to the downstream Receive Any-PHY Interface block (RAPI672).
The roamer is a time-sliced state machine which tracks channel FIFO buffer
depths and signals the reader to service a particular channel. If a buffer over-run
occurs, the writer ends the current packet from the HDLC processor in the
channel FIFO with an overrun flag and ignores the rest of the packet.
The FIFO algorithm of the partial packet buffer processor is based on a
programmable per-channel transfer size. Instead of tracking the number of full
blocks in a channel FIFO, the processor tracks the number of transactions.
Whenever the partial packet writer fills a transfer-sized number of blocks or writes
an end-of-packet flag to the channel FIFO, a transaction is created. Whenever
the partial packet reader transmits a transfer-size number of blocks or an end-ofpacket flag to the RAPI672 block, a transaction is deleted. Thus, small packets
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 46
Page 56
DATA SHEET
PMC-1990114 ISSUE 6 84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER
PM7385 FREEDM-84A672
WITH ANY-PHY PACKET INTERFACE
less than the transfer size will be naturally transferred to the RAPI672 block
without having to precisely track the number of full blocks in the channel FIFO.
The partial packet roamer performs the transaction accounting for all channel
FIFOs. The roamer increments the transaction count when the writer signals a
new transaction and sets a per-channel flag to indicate a non-zero transaction
count. The roamer searches the flags in a round-robin fashion to decide for
which channel FIFO to request transfer by the RAPI672 block. The roamer
informs the partial packet reader of the channel to process. The reader transfers
the data to the RAPI672 until the channel transfer size is reached or an end of
packet is detected. The reader then informs the roamer that a transaction is
consumed. The roamer updates its transaction count and clears the non-zero
transaction count flag if required. The roamer then services the next channel
with its transaction flag set high.
The writer and reader determine empty and full FIFO conditions using flags.
Each block in the partial packet buffer has an associated flag. The writer sets the
flag after the block is written and the reader clears the flag after the block is read.
The flags are initialized (cleared) when the block pointers are written using
indirect block writes. The writer declares a channel FIFO overrun whenever the
writer tries to store data to a block with a set flag. In order to support optional
removal of the FCS from the packet data, the writer does not declare a block as
filled (set the block flag nor increment the transaction count) until the first double
word of the next block in channel FIFO is filled. If the end of a packet resides in
the first double word, the writer declares both blocks as full at the same time.
When the reader finishes processing a transaction, it examines the first double
word of the next block for the end-of-packet flag. If the first double word of the
next block contains only FCS bytes, the reader would, optionally, process next
transaction (end-of-packet) and consume the block, as it contains information not
transferred to the RAPI672 block.
8.6 Receive Any-PHY Interface
The Receive Any-PHY Interface (RAPI672) provides a low latency path for
transferring data out of the partial packet buffer in the RHDL672 and onto the
Receive Any-PHY Packet Interface (Rx APPI). The RAPI672 contains a FIFO
block for latency control as well as to segregate the APPI timing domain from the
SYSCLK timing domain. The RAPI672 contains the necessary logic to manage
and respond to device polling from an upper layer device. The RAPI672 also
provides the upper layer device with status information on a per packet basis.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 47
Page 57
DATA SHEET
PMC-1990114 ISSUE 6 84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER
PM7385 FREEDM-84A672
WITH ANY-PHY PACKET INTERFACE
8.6.1 FIFO Storage and Control
The FIFO block temporarily stores channel data during transfer across the Rx
APPI. RAPI672 burst data transfers are transaction based – a write burst data
transfer must be complete before any data will be read, and all data must be
completely read from the FIFO before any further data will be written into the
FIFO. To support full Rx APPI bus rate, a double buffer scheme is used. While
data is being read from one FIFO onto the Rx APPI, data can be written into the
other FIFO. Because the bandwidth on the writer side of the FIFOs is higher
than that on the reader side, the RAPI672 can maintain continuous full bandwidth
transfer over the Rx APPI.
A maximum of 256 bytes can be stored in each of the two FIFOs for any given
burst transfer. A separate storage element samples the 10 bit channel ID to
associate the data in that FIFO with a specific HDLC channel. This channel ID is
prepended in-band as the first word of every burst data transfer across the Rx
APPI. (The maximum length of a burst data transfer on the Rx APPI is therefore
129 words, including prepend.) The 3 most significant bits of the prepended
word of each burst data transfer across the Rx APPI identify the FREEDM84A672 device associated with the transfer and reflect the value of the base
address programmed in the RAPI672 Control register.
The writer controller provides a means for writing data into the FIFOs. The writer
controller indicates that it can accept data when there is at least one completely
empty FIFO. In response, a burst transfer of data, up to a maximum of 256
bytes, is written into that empty FIFO. (The transfer is sourced by the upstream
RHDL672 block which selects from those channels with data available using its
round-robin algorithm.) The writer controller then informs the reader controller
that data is available in that FIFO. The writer controller now switches to the other
FIFO and repeats the process. When both FIFOs are full, the writer throttles the
upstream RHDL672 block to prevent of any further data writes into the FIFOs.
The reader controller provides a means of reading data out of the FIFOs onto the
Rx APPI. When selected to do so, and the writer controller has indicated that at
least one FIFO is full, the reader controller will read the data out of the FIFOs in
the order in which they were filled. To prevent from overloading the Rx APPI with
several small bursts of data, the RAPI672 automatically deselects after every
burst transfer. This provides time for the upper layer device to detect an end of
packet indication and possibly reselect a different FREEDM-84A672 device
without having to store the extra word or two which may have been output onto
the Rx APPI during the time it took for deselection.
The RAPI672 provides packet status information on the Rx APPI at the end of
every packet transfer. The RAPI672 asserts RERR at the end of packet
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 48
Page 58
DATA SHEET
PMC-1990114 ISSUE 6 84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER
PM7385 FREEDM-84A672
WITH ANY-PHY PACKET INTERFACE
reception (REOP high) to indicate that the packet is in error. The RAPI672 may
optionally be programmed to overwrite RXDATA[7:0] of the final word of each
packet transfer (REOP is high) with the status of packet reception when that
packet is errored (RERR is high). Overwriting of status information is enabled by
setting the STATEN bit in the RAPI Control register.
8.6.2 Polling Control and Management
The RAPI672 only responds to device polls which match the base address
programmed in the RAPI672 Control register. A positive poll response indicates
that at least one of the two FIFOs has a complete XFER[3:0] plus one blocks of
data, or an end of packet, and is ready to be selected to transfer this data across
the Rx APPI.
8.7 Transmit Any-PHY Interface
The Transmit Any-PHY Interface (TAPI672) provides a low latency path for
transferring data from the Transmit Any-PHY Packet Interface (Tx APPI) into the
partial packet buffer in the THDL672. The TAPI672 contains a FIFO block for
latency control as well as to segregate the APPI timing domain from the SYSCLK
timing domain. The TAPI672 contains the necessary logic to manage and respond
to channel polling from an upper layer device.
8.7.1 FIFO Storage and Control
The FIFO block temporarily stores channel data during transfer across the Tx
APPI. TAPI672 burst data transfers are transaction based on the writer side of
the FIFO – all data must be completely read from the FIFO before any further
data will be written into the FIFO. To support as close as possible to full Tx APPI
bus rate, a double buffer is used. While data is being read from the one FIFO,
data can be written into the other FIFO. Because the bandwidth on the reader
side of the FIFOs is higher than that on the writer side, the TAPI672 will not incur
any bandwidth reduction to maximum burst data transfers through its FIFOs.
The upper layer device cannot interrupt data transfers on the Tx APPI. However,
the FREEDM-84A672 may throttle the upper layer device if both FIFOs in the
TAPI672 are full. When the FIFOs in the TAPI672 cannot accept data, the
TAPI672 deasserts the TRDY output to the upper layer device connected to the
Tx APPI. In this instance, the upper layer device must halt data transfer until the
TRDY output is returned high. The upper layer device connected to the Tx APPI
must sample the TRDY output high before continuing to burst data across the Tx
APPI.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 49
Page 59
DATA SHEET
PMC-1990114 ISSUE 6 84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER
PM7385 FREEDM-84A672
WITH ANY-PHY PACKET INTERFACE
A maximum of 256 bytes may be stored in each of the two FIFOs for any given
burst transfer. The first word of each burst transfer contains a prepended
address field. (The maximum length of a burst transfer on the Tx APPI is
therefore 129 words, including prepend.) A separate storage element samples
the 10 least significant bits of the prepended channel address to associate the
data with a specific channel. The 3 most significant bits must match the base
address programmed into the TAPI672 Control register for the TAPI672 to
respond to the data transaction on the Tx APPI.
The writer controller provides a means for writing data from the Tx APPI into the
FIFOs. The writer controller can accept data when there is at least one
completely empty FIFO. When a data transfer begins and there are no empty
FIFOs, the writer controller catches the data provided on the Tx APPI and
throttles the upper layer device. The writer controller will continue to throttle the
upper layer device until at least one FIFO is completely empty and can accept a
maximum burst transfer of data.
The whisper controller provides the channel address of the data being written
into the FIFO. As soon as the first word of data has been written into the FIFO,
the whisper controller provides the channel information for that data to the
downstream THDL672 block. The whisper controller will wait for
acknowledgement and the reader controller is then requested to read the data
from the FIFO. Once the reader controller has commenced the data transfer, the
whisper controller will provide the channel information for the other FIFO. The
whisper controller alternates between the two FIFOs in the order in which data is
written into them.
The reader controller provides a means of reading data out of the FIFOs. When
the writer controller indicates that data has been completely written into one of
the two FIFOs, the reader controller is permitted to read that data. The reader
controller will then wait for a request for data from the THDL672 block. When
requested to transfer data, the reader controller will completely read all the data
out of the FIFO before indicating to the writer controller that more data may be
written into that FIFO. Because the reader controller reads data out of the FIFOs
in the order in which they were filled, the THDL672 block will request data for
channels in the order in which they were whispered. The reader controller
manages the read and write FIFO pointers to allow simultaneous reading and
writing of data to/from the double buffer FIFO.
8.7.2 Polling Control and Management
The TAPI672 only responds to poll addresses which are in the range
programmed in the base address field in the TAPI672 Control register. The
TAPI672 uses the 3 most significant bits of the poll address for device recognition
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 50
Page 60
DATA SHEET
PMC-1990114 ISSUE 6 84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER
PM7385 FREEDM-84A672
WITH ANY-PHY PACKET INTERFACE
and the 10 least significant bits of the poll address for identification of a channel.
The TAPI672 provides three poll results for every poll address according to Table
9. The TPAn[0] bit indicates whether or not space exists in the channel FIFO for
data and the TPAn[1] bit indicates whether or not that polled channel FIFO is at
risk of underflowing and should be provided data soon. The TPAn[2] bit indicates
that an underflow event has occurred on that channel FIFO.
The TAPI672 maintains a mirror image of the status of each channel FIFO in the
partial packet buffer. The THDL672 continuously reports the status of the 672
channel FIFOs to the TAPI672 and the TAPI672 updates the mirror image
accordingly. The THDL672 also signals to the TAPI672 whenever an underflow
event has occurred on a channel FIFO. At the beginning of every data transfer
across the Tx APPI, the TAPI672 sets the mirror image status of the channel to
“full”. Only the TAPI672 can cause the status to be set to “full” and only the
THDL672 can cause the status to be set to “space” or “starving”. Only the
THDL672 can cause the status to be set to “underflow” and only the TAPI672 can
clear the “underflow” status when that channel FIFO is polled. In the event that
both the TAPI672 and the THDL672 try to change the mirror image status of a
particular channel simultaneously, the TAPI672 takes precedence, except for the
“underflow” status, where the THDL672 takes precedence.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 51
Page 61
DATA SHEET
PMC-1990114 ISSUE 6 84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER
The Transmit HDLC Controller / Partial Packet Buffer block (THDL672) contains
a partial packet buffer for Tx APPI latency control and a transmit HDLC controller.
The THDL672 also contains logic to monitor the full/empty status of each channel
FIFO and push this status onto the polling interface signals.
The THDL672 requests data from the TAPI672 in response to control information
from the TAPI672 indicating the channel for which data is available and ready to
be transferred. Packet data received from the TAPI672 is stored in channel
specific FIFOs residing in the partial packet buffer. When the amount of data in a
FIFO reaches a programmable threshold, the HDLC controller is enabled to
initiate transmission. The HDLC controller performs flag generation, bit stuffing
and, optionally, frame check sequence (FCS) insertion. The FCS is software
selectable to be CRC-CCITT or CRC-32. The minimum packet size, excluding
FCS, is two bytes. A single byte payload is illegal. The HDLC controller delivers
data to the Transmit Channel Assigner block (TCAS672) on demand. A packet in
progress is aborted if an under-run occurs. The THDL672 is programmable to
operate in transparent mode where packet data retrieved from the TAPI672 is
transmitted verbatim.
8.8.1 Transmit HDLC Processor
The HDLC processor is a time-slice state machine which can process up to 672
independent channels. The state vector and provisioning information for each
channel is stored in a RAM. Whenever the TCAS672 requests data, the
appropriate state vector is read from the RAM, processed and finally written back
to the RAM. The HDLC state-machine can be configured to perform flag
insertion, bit stuffing and CRC generation. The HDLC processor requests data
from the partial packet processor whenever a request for channel data arrives.
However, the HDLC processor does not start transmitting a packet until the entire
packet is stored in the channel FIFO or until the FIFO free space is less than the
software programmable limit. If a channel FIFO under-runs, the HDLC processor
aborts the packet, generates a microprocessor interrupt and signals the
underflow to the transmit Any-PHY interface.
The configuration of the HDLC processor is accessed using indirect channel read
and write operations. When an indirect operation is performed, the information is
accessed from RAM during a null clock cycle inserted by the TCAS672 block.
Writing new provisioning data to a channel resets the channel’s entire state
vector.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 52
Page 62
DATA SHEET
PMC-1990114 ISSUE 6 84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER
PM7385 FREEDM-84A672
WITH ANY-PHY PACKET INTERFACE
8.8.2 Transmit Partial Packet Buffer Processor
The partial packet buffer processor controls the 32 Kbyte partial packet RAM
which is divided into 16 byte blocks. A block pointer RAM is used to chain the
partial packet blocks into circular channel FIFO buffers. Thus, non-contiguous
sections of RAM can be allocated in the partial packet buffer RAM to create a
channel FIFO. Figure 4 shows an example of three blocks (blocks 1, 3, and 200)
linked together to form a 48 byte channel FIFO. The three pointer values would
be written sequentially using indirect block write accesses. When a channel is
provisioned within this FIFO, the state machine can be initialized to point to any
one of the three blocks.
Figure 4 – Partial Packet Buffer Structure
Partial Packet
Buffer RAM
Block
Pointer RAM
Block 0
Block 1
Block 2
Block 3
Block 2047
16 bytes
16 bytes
16 bytes
16 bytes
16 bytes
16 bytes
Block 0
Block 1
Block 2
Block 3
Block 200Block 200
Block 2047
XX
0x03
XX
0xC8
0x01
XX
The partial packet buffer processor is divided into three sections: reader, writer
and roamer. The roamer is a time-sliced state machine which tracks each
channel’s FIFO buffer free space and signals the writer to service a particular
channel. The writer requests data from the TAPI672 block and transfers packet
data from the TAPI672 to the associated channel FIFO. The reader is a time-
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 53
Page 63
DATA SHEET
PMC-1990114 ISSUE 6 84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER
PM7385 FREEDM-84A672
WITH ANY-PHY PACKET INTERFACE
sliced state machine which transfers the HDLC information from a channel FIFO
to the HDLC processor in response to a request from the HDLC processor. If a
buffer under-run occurs for a channel, the reader informs the HDLC processor
and purges the rest of the packet. If a buffer overflow occurs for a channel (this
can only happen if an external device disregards or mis-interprets poll results on
the Tx APPI and transfers data to a channel which does not have space in its
FIFO), the THDL672 overwrites the FIFO contents resulting in data corruption on
that particular channel. When either an underflow or an overflow occurs, an
interrupt is generated and the cause of the interrupt may be read via the interrupt
status register using the microprocessor interface.
The writer and reader determine empty and full FIFO conditions using flags.
Each block in the partial packet buffer has an associated flag. The writer sets the
flag after the block is written and the reader clears the flag after the block is read.
The flags are initialized (cleared) when the block pointers are written using
indirect block writes. The reader declares a channel FIFO under-run whenever it
tries to read data from a block without a set flag.
The FIFO algorithm of the partial packet buffer processor is based on perchannel software programmable transfer size and free space trigger level.
Instead of tracking the number of full blocks in a channel FIFO, the processor
tracks the number of empty blocks, called free space, as well as the number of
end of packets stored in the FIFO. Recording the number of empty blocks
instead of the number of full blocks reduces the amount of information the
roamer must store in its state RAM.
The partial packet roamer records the FIFO free space and end-of-packet count
for all channel FIFOs. When the reader signals that a block has been read, the
roamer increments the FIFO free space and sets a per-channel request flag if the
free space is greater than the limit set by XFER[3:0]. The roamer pushes this
status information to the TAPI672 to indicate that it can accept at least XFER[3:0]
blocks of data. The roamer also decrements the end-of-packet count when the
reader signals that it has passed an end of a packet to the HDLC processor. If
the HDLC processor is transmitting a packet and the FIFO free space is greater
than the starving trigger level and there are no complete packets within the FIFO
(end-of-packet count equal to zero), a per-channel starving flag is set. The
roamer searches the starving flags in a round-robin fashion to decide which
channel FIFOs are at risk of underflowing and pushes this status information to
the TAPI672. The roamer listens to control information from the TAPI672 to
decide which channel FIFO requests data from the TAPI672 block. The roamer
informs the partial packet writer of the channel FIFO to process and the FIFO
free space. The writer sends a request for data to the TAPI672 block, writes the
response data to the channel FIFO, and sets the block full flags. The writer
reports back to the roamer the number of blocks and end-of-packets transferred.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 54
Page 64
DATA SHEET
PMC-1990114 ISSUE 6 84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER
PM7385 FREEDM-84A672
WITH ANY-PHY PACKET INTERFACE
The maximum amount of data transferred during one request is limited by a
software programmable limit (XFER[3:0]).
The roamer round-robins between all channel FIFOs and pushes the status to
the TAPI672 block. The status consists of two pieces of information: (1) is there
space in the channel FIFO for at least one XFER[3:0] of data, and (2) is this
channel FIFO at risk of underflowing. Where a channel FIFO is at risk of
underflowing, the THDL672 pushes a starving status for that channel FIFO to the
TAPI672 at the earliest possible opportunity.
The configuration of the HDLC processor is accessed using indirect channel read
and write operations as well as indirect block read and write operations. When
an indirect operation is performed, the information is accessed from RAM during
a null clock cycle identified by the TCAS672 block. Writing new provisioning data
to a channel resets the entire state vector.
8.9 Transmit Channel Assigner
The Transmit Channel Assigner block (TCAS672) processes up to 672 channels.
Data for all channels is sourced from a single byte-serial stream from the
Transmit HDLC Controller / Partial Packet Buffer block (THDL672). The
TCAS672 demultiplexes the data and assigns each byte to any one of 84 links.
When sending data to the SBI SIPO blocks, each link may be configured to
support channelised T1/J1/E1 traffic, unchannelised DS-3 traffic or unframed
traffic at T1/J1, E1 or DS-3 rates. When sending data to the TD outputs, links 0,
1 and 2 support unchannelised data at arbitary rates up to 51.84 Mbps. Each link
is independent and has its own associated clock.
The 84 TCAS links have a fixed relationship to the SPE and tributary numbers on
the SBI ADD BUS as shown in the following table.
Table 10 – SBI SPE/Tributary to TCAS Link Mapping
SBI
SPE
No.
SBI
Trib.
No.
TCAS
Link
No.
SBI
SPE
No.
SBI
Trib.
No.
TCAS
Link
No.
SBI
SPE
No.
SBI
Trib.
No.
TCAS
Link
No.
1 1 0 2 1 1 3 1 2
1 2 3 2 2 4 3 2 5
1 3 6 2 3 7 3 3 8
1 4 9 2 4 10 3 4 11
1 5 12 2 5 13 3 5 14
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 55
Page 65
DATA SHEET
PMC-1990114 ISSUE 6 84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER
SBI
SPE
No.
SBI
Trib.
No.
TCAS
Link
No.
SBI
SPE
No.
SBI
Trib.
No.
TCAS
Link
No.
SBI
SPE
No.
PM7385 FREEDM-84A672
WITH ANY-PHY PACKET INTERFACE
SBI
Trib.
No.
TCAS
Link
No.
1 6 15 2 6 16 3 6 17
1 7 18 2 7 19 3 7 20
1 8 21 2 8 22 3 8 23
1 9 24 2 9 25 3 9 26
1 10 27 2 10 28 3 10 29
1 11 30 2 11 31 3 11 32
1 12 33 2 12 34 3 12 35
1 13 36 2 13 37 3 13 38
1 14 39 2 14 40 3 14 41
1 15 42 2 15 43 3 15 44
1 16 45 2 16 46 3 16 47
1 17 48 2 17 49 3 17 50
1 18 51 2 18 52 3 18 53
1 19 54 2 19 55 3 19 56
1 20 57 2 20 58 3 20 59
1 21 60 2 21 61 3 21 62
1 22 63 2 22 64 3 22 65
1 23 66 2 23 67 3 23 68
1 24 69 2 24 70 3 24 71
1 25 72 2 25 73 3 25 74
1 26 75 2 26 76 3 26 77
1 27 78 2 27 79 3 27 80
1 28 81 2 28 82 3 28 83
As shown in the table above, TCAS links 0, 1, and 2 are mapped to tributary 1 of
SPEs 1, 2 and 3 respectively. These links may be configured to operate at DS-3
rate. (They may also be configured to output data to the TD outputs at rates up
to 51.84 Mbps.) For each of these high-speed links, the TCAS672 provides a six
byte FIFO. For the remaining links (TCAS links 3 to 83, mapped to tributaries 2
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 56
Page 66
DATA SHEET
PMC-1990114 ISSUE 6 84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER
PM7385 FREEDM-84A672
WITH ANY-PHY PACKET INTERFACE
to 28 of each SPE), the TCAS672 provides a single byte holding register. The
TCAS672 performs parallel to serial conversion to form bit-serial streams which
are passed to the SBI SIPO blocks. In the event where multiple links are in need
of data, TCAS672 requests data from upstream blocks on a fixed priority basis
with link 0 having the highest priority and link 83 the lowest.
Links containing a T1/J1 or an E1 stream may be channelised. Data at each
time-slot may be independently assigned to be sourced from a different channel.
The position of T1/J1 and E1 framing bits/bytes is identified by frame pulse
signals generated by the SBI SIPO blocks. With knowledge of the transmit link
and time-slot identity, the TCAS672 performs a table look-up to identify the
channel from which a data byte is to be sourced.
Links containing a DS-3 stream are unchannelised, in which case, all data bytes
on the link belong to one channel. The TCAS672 performs a table look-up to
identify the channel to which a data byte belongs using only the outgoing link
identity, as no time-slots are associated with unchannelised links. Links may
additionally be configured to operate in an unframed “clear channel” mode, in
which case the FREEDM-84A672 will output HDLC data in all bit positions,
including those normally reserved for framing information. Links so configured
operate as unchannelised regardless of link rate and the TCAS672 performs a
table lookup using only the link number to determine the associated channel.
8.9.1 Line Interface
There are 84 line interface blocks in the TCAS672. Each line interface block
contains a bit counter, an 8-bit shift register and a holding register that, together,
perform parallel to serial conversion. Whenever the shift register is updated, a
request for service is sent to the priority encoder block. When acknowledged by
the priority encoder, the line interface responds by writing the data into the
holding register.
To support channelised links, each line interface block contains a time-slot
counter. The time-slot counter is incremented each time the shift register is
updated and is reset on detection of a frame pulse from the SBI SIPO blocks.
For unchannelised or unframed links, the time-slot counter is held reset.
8.9.2 Priority Encoder
The priority encoder monitors the line interfaces for requests and synchronises
them to the SYSCLK timing domain. Requests are serviced on a fixed priority
scheme where highest to lowest priority is assigned from the line interface
attached to link 0 to that attached to link 83. Thus, simultaneous requests from
link ‘m’ will be serviced ahead of link ‘n’, if m < n. The priority encoder selects the
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 57
Page 67
DATA SHEET
PMC-1990114 ISSUE 6 84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER
PM7385 FREEDM-84A672
WITH ANY-PHY PACKET INTERFACE
request from the link with the highest priority for service. When there are no
pending requests, the priority encoder generates an idle cycle. In addition, once
every fourth SYSCLK cycle, the priority encoder inserts a null cycle where no
requests are serviced. This cycle is used by the channel assigner upstream for
CBI accesses to the channel provision RAM.
8.9.3 Channel Assigner
The channel assigner block determines the channel number of the request
currently being processed. The block contains a 2688 word channel provision
RAM. The address of the RAM is constructed from concatenating the link
number and the time-slot number of the highest priority requester. The fields of
each RAM word include the channel number and a time-slot enable flag. The
time-slot enable flag labels the current time-slot as belonging to the channel
indicted by the channel number field. For time-slots that are enabled, the
channel assigner issues a request to the THDL672 block which responds with
packet data within one byte period of the transmit stream.
8.10 SBI Inserter and SIPO
The SBI transmit circuitry consists of an SBI Insert block and three SBI Serial to
Parallel Converter (SBI SIPO) blocks. Each SIPO block processes data for one
of the three Synchronous Payload Envelopes (SPEs) conveyed on the SBI ADD
BUS. It receives serial data on either 28 links running at T1/J1 rate, 21 links at
E1 rate or a single link at DS-3 rate and converts it to an internal parallel bus
format. The SBI Insert block receives data from the SIPO blocks in the internal
format and transmits it on the SBI ADD BUS.
The SIPO blocks generate the serial clocks for the TCAS672 and thus are able to
control the rate at which data is transmitted on to the SBI. The SBI Insert block
can command the SIPO blocks to speed up or slow down these clocks in
response to justfication requests received on the SBI interface. The SBI Insert
block also contains FIFO circuitry to compensate for short term variations in the
rate at which data is output by the TCAS672 and the rate at which it is
transmitted on the SBI ADD BUS.
The SBI Insert block may be configured to enable or disable transmission of
individual tributaries on to the SBI ADD bus. Individual tributaries may also be
configured to operate in framed or unframed mode.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 58
Page 68
DATA SHEET
PMC-1990114 ISSUE 6 84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER
PM7385 FREEDM-84A672
WITH ANY-PHY PACKET INTERFACE
8.11 Performance Monitor
The Performance Monitor block (PMON) contains four counters. The first two
accumulate receive partial packet buffer FIFO overrun events and transmit partial
packet buffer FIFO underflow events, respectively. The remaining two counters
are software programmable to accumulate a variety of events, such as receive
packet count, FCS error counts, etc. All counters saturate upon reaching
maximum value. The accumulation logic consists of a counter and holding
register pair. The counter is incremented when the associated event is detected.
Writing to the FREEDM-84A672 Master Clock / Frame Pulse Activity Monitor and
Accumulation Trigger register transfer the count to the corresponding holding
register and clear the counter. The contents of the holding register is accessible
via the microprocessor interface.
8.12 JTAG Test Access Port Interface
The JTAG Test Access Port block provides JTAG support for boundary scan. The
standard JTAG EXTEST, SAMPLE, BYPASS, IDCODE and STCTEST instructions
are supported. The FREEDM-84A672 identification code is 073850CD
hexadecimal.
8.13 Microprocessor Interface
The FREEDM-84A672 supports microprocessor access to an internal register
space for configuring and monitoring the device. All registers are 16 bits wide but
are DWORD aligned in the microprocessor memory map. The registers are
described below:
Table 11 – Normal Mode Microprocessor Accessible Registers
0x690 SBI INSERT Tributary RAM Indirect Access Control
0x694 SBI INSERT Reserved
0x698 SBI INSERT Tributary RAM Indirect Access Data
0x69C – 0x6FC SBI INSERT Reserved
0x700 – 0x7FC Reserved
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 63
Page 73
DATA SHEET
PMC-1990114 ISSUE 6 84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER
PM7385 FREEDM-84A672
WITH ANY-PHY PACKET INTERFACE
9 NORMAL MODE REGISTER DESCRIPTION
Normal mode registers are used to configure and monitor the operation of the
FREEDM-84A672.
Notes on Normal Mode Register Bits:
1. Writing values into unused register bits has no effect. However, to ensure software
compatibility with future, feature-enhanced versions of the product, unused register
bits must be written with logic zero. Reading back unused bits can produce either a
logic one or a logic zero; hence, unused register bits should be masked off by
software when read.
2. Except where noted, all configuration bits that can be written into can also be read
back. This allows the processor controlling the FREEDM-84A672 to determine the
programming state of the block.
3. Writable normal mode register bits are cleared to logic zero upon reset unless
otherwise noted.
4. Writing into read-only normal mode register bit locations does not affect FREEDM84A672 operation unless otherwise noted.
5. Certain register bits are reserved. These bits are associated with megacell functions
that are unused in this application. To ensure that the FREEDM-84A672 operates
as intended, reserved register bits must only be written with their default values.
Similarly, writing to reserved registers should be avoided.
9.1 Microprocessor Accessible Registers
Microprocessor accessible registers can be accessed by the external
microprocessor. For each register description below, the hexadecimal register
number indicates the address in the FREEDM-84A672 when accesses are made
using the external microprocessor.
Note
These registers are not byte addressable. Writing to any one of these registers
modifies all 16 bits in the register.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 64
Page 74
DATA SHEET
PMC-1990114 ISSUE 6 84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER
PM7385 FREEDM-84A672
WITH ANY-PHY PACKET INTERFACE
Register 0x000 : FREEDM-84A672 Master Reset
Bit Type Function Default
Bit 15 R/W Reset 0
Bit 14
Unused XH
to
Bit 12
Bit 11 R TYPE[3] 0
Bit 10 R TYPE[2] 1
Bit 9 R TYPE[1] 0
Bit 8 R TYPE[0] 1
Bit 7 R ID[7] 0
Bit 6 R ID[7] 0
Bit 5 R ID[5] 0
Bit 4 R ID[4] 0
Bit 3 R ID[3] 0
Bit 2 R ID[2] 0
Bit 1 R ID[1] 1
Bit 0 R ID[0] 0
This register provides software reset capability and device ID information.
RESET:
The RESET bit allows the FREEDM-84A672 to be reset under software
control. If the RESET bit is a logic one, the entire FREEDM-84A672, except
the microprocessor interface, is held in reset. In addition, all registers are
reset to their default values. This bit is not self-clearing. Therefore, a logic
zero must be written to bring the FREEDM-84A672 out of reset. Holding the
FREEDM-84A672 in a reset state places it into a low power, stand-by mode.
A hardware reset clears the RESET bit, thus negating the software reset.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 65
Page 75
DATA SHEET
PMC-1990114 ISSUE 6 84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER
PM7385 FREEDM-84A672
WITH ANY-PHY PACKET INTERFACE
Note
Unlike the hardware reset input (RSTB), RESET does not force the FREEDM84A672’s microprocessor interface pins tristate. RESET causes all registers to
be set to their default values and forces the APPI outputs tristate.
TYPE[3:0]:
The Device Type bits (TYPE[3:0]) allow software to identify the device as the
FREEDM-84A672 member of the FREEDM family of products.
ID[7:0]:
The Device ID bits (ID[7:0]) allow software to identify the version level of the
FREEDM-84A672.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 66
Page 76
DATA SHEET
PMC-1990114 ISSUE 6 84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER
This register provides interrupt enables for various events detected or initiated by
the FREEDM-84A672.
RFCSEE:
The receive frame check sequence error interrupt enable bit (RFCSEE)
enables receive FCS error interrupts to the microprocessor. When RFCSEE
is set high, a mismatch between the received FCS code and the computed
CRC residue will cause an interrupt to be generated on the INTB output.
Interrupts are masked when RFCSEE is set low. However, the RFCSEI bit
remains valid when interrupts are disabled and may be polled to detect
receive FCS error events.
RABRTE:
The receive abort interrupt enable bit (RABRTE) enables receive HDLC abort
interrupts to the microprocessor. When RABRTE is set high, receipt of an
abort code (at least 7 contiguous 1’s) will cause an interrupt to be generated
on the INTB output. Interrupts are masked when RABRTE is set low.
However, the RABRTI bit remains valid when interrupts are disabled and may
be polled to detect receive abort events.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 67
Page 77
DATA SHEET
PMC-1990114 ISSUE 6 84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER
PM7385 FREEDM-84A672
WITH ANY-PHY PACKET INTERFACE
RPFEE:
The receive packet format error interrupt enable bit (RPFEE) enables receive
packet format error interrupts to the microprocessor. When RPFEE is set
high, receipt of a packet that is longer than the maximum specified in the
RHDL Maximum Packet Length register, or a packet that is shorter than 32
bits (CRC-CCITT) or 48 bits (CRC-32), or a packet that is not octet aligned
will cause an interrupt to be generated on the INTB output. Interrupts are
masked when RPFEE is set low. However, the RPFEI bit remains valid when
interrupts are disabled and may be polled to detect receive packet format
error events.
RFOVRE:
The receive FIFO overrun error interrupt enable bit (RFOVRE) enables
receive FIFO overrun error interrupts to the microprocessor. When RFOVRE
is set high, attempts to write data into the logical FIFO of a channel when it is
already full will cause an interrupt to be generated on the INTB output.
Interrupts are masked when RFOVRE is set low. However, the RFOVRI bit
remains valid when interrupts are disabled and may be polled to detect
receive FIFO overrun events.
TPRTYE:
The transmit parity error interrupt enable bit (TPRTYE) enables parity errors
on the transmit APPI to generate interrupts to the microprocessor. When
TPRTYE is set high, detection of a parity error on the transmit APPI will cause
an interrupt to be generated on the INTB output. Interrupts are masked when
TPRTYE is set low. However, the TPRTYI bit remains valid when interrupts
are disabled and may be polled to detect parity error events.
TUNPVE:
The transmit unprovisioned error interrupt enable bit (TUNPVE) enables
attempted transmissions to unprovisioned channels to generate interrupts to
the microprocessor. When TUNPVE is set high, attempts to write data to an
unprovisioned channel will cause an interrupt to be generated on the INTB
output. Interrupts are masked when TUNPVE is set low. However, the
TUNPVI bit remains valid when interrupts are disabled and may be polled to
detect attempted transmissions to unprovisioned channel events.
TFOVRE:
The transmit FIFO overflow error interrupt enable bit (TFOVRE) enables
transmit FIFO overflow error interrupts to the microprocessor. When
TFOVRE is set high, attempts to write data to the logical FIFO when it is
already full will cause an interrupt to be generated on the INTB output.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 68
Page 78
DATA SHEET
PMC-1990114 ISSUE 6 84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER
PM7385 FREEDM-84A672
WITH ANY-PHY PACKET INTERFACE
Interrupts are masked when TFOVRE is set low. However, the TFOVRI bit
remains valid when interrupts are disabled and may be polled to detect
transmit FIFO overflow events.
TFUDRE:
The transmit FIFO underflow error interrupt enable bit (TFUDRE) enables
transmit FIFO underflow error interrupts to the microprocessor. When
TFUDRE is set high, attempts to read data from the logical FIFO when it is
already empty will cause an interrupt to be generated on the INTB output.
Interrupts are masked when TFUDRE is set low. However, the TFUDRI bit
remains valid when interrupts are disabled and may be polled to detect
transmit FIFO underflow events.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 69
Page 79
DATA SHEET
PMC-1990114 ISSUE 6 84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER
PM7385 FREEDM-84A672
WITH ANY-PHY PACKET INTERFACE
Register 0x008 : FREEDM-84A672 Master Interrupt Status
Bit Type Function Default
Bit 15 R TFUDRI X
Bit 14 R TFOVRI X
Bit 13 R TUNPVI X
Bit 12 R TPRTYI X
Bit 11
Unused XXH
to
Bit 6
Bit 5 R RFOVRI X
Bit 4 R RPFEI X
Bit 3 R RABRTI X
Bit 2 R RFCSEI X
Bit 1 Unused X
Bit 0 Unused X
This register reports the interrupt status for various events detected or initiated by
the FREEDM-84A672. Reading this registers acknowledges and clears the
interrupts.
RFCSEI:
The receive frame check sequence error interrupt status bit (RFCSEI) reports
receive FCS error interrupts to the microprocessor. RFCSEI is set high when
a mismatch between the received FCS code and the computed CRC residue
is detected. RFCSEI remains valid when interrupts are disabled and may be
polled to detect receive FCS error events.
RABRTI:
The receive abort interrupt status bit (RABRTI) reports receive HDLC abort
interrupts to the microprocessor. RABRTI is set high upon receipt of an abort
code (at least 7 contiguous 1’s). RABRTI remains valid when interrupts are
disabled and may be polled to detect receive abort events.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 70
Page 80
DATA SHEET
PMC-1990114 ISSUE 6 84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER
PM7385 FREEDM-84A672
WITH ANY-PHY PACKET INTERFACE
RPFEI:
The receive packet format error interrupt status bit (RPFEI) reports receive
packet format error interrupts to the microprocessor. RPFEI is set high upon
receipt of a packet that is longer than the maximum programmed length, of a
packet that is shorter than 32 bits (CRC-CCITT) or 48 bits (CRC-32), or of a
packet that is not octet aligned. RPFEI remains valid when interrupts are
disabled and may be polled to detect receive packet format error events.
RFOVRI:
The receive FIFO overrun error interrupt status bit (RFOVRI) reports receive
FIFO overrun error interrupts to the microprocessor. RFOVRI is set high on
attempts to write data into the logical FIFO of a channel when it is already full.
RFOVRI remains valid when interrupts are disabled and may be polled to
detect receive FIFO overrun events.
TPRTYI:
The transmit parity error interrupt status bit (TPRTYI) reports the detection of
a parity on the transmit APPI. TPRTYI is set high upon detection of a parity
error. TPRTYI remains valid when interrupts are disabled and may be polled
to detect parity errors.
TUNPVI:
The transmit unprovisioned error interrupt status bit (TUNPVI) reports an
attempted data transmission to an unprovisioned channel FIFO. TUNPVI is
set high upon attempts to write data to an unprovisioned channel FIFO.
TUNPVI remains valid when interrupts are disabled and may be polled to
detect an attempt to write data to an unprovisioned channel FIFO.
TFOVRI:
The transmit FIFO overflow error interrupt status bit (TFOVRI) reports
transmit FIFO overflow error interrupts to the microprocessor. TFOVRI is set
high upon attempts to write data to the logical FIFO when it is already full.
TFOVRI remains valid when interrupts are disabled and may be polled to
detect transmit FIFO overflow events. (Note – Transmit FIFO overflows will
not occur if channels are properly polled on the Transmit APPI before
transferring data.)
TFUDRI:
The transmit FIFO underflow error interrupt status bit (TFUDRI) reports
transmit FIFO underflow error interrupts to the microprocessor. TFUDRI is set
high upon attempts to read data from the logical FIFO when it is already
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 71
Page 81
DATA SHEET
PMC-1990114 ISSUE 6 84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER
PM7385 FREEDM-84A672
WITH ANY-PHY PACKET INTERFACE
empty. TFUDRI remains valid when interrupts are disabled and may be
polled to detect transmit FIFO underflow events.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 72
Page 82
DATA SHEET
PMC-1990114 ISSUE 6 84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER
This register provides activity monitoring on the FREEDM-84A672 clock and SBI
frame pulse inputs. When a monitored input makes a transition, the
corresponding register bit is set high. The bit will remain high until this register is
read, at which point, all the bits in this register are cleared. A lack of transitions is
indicated by the corresponding register bit reading low. This register should be
read periodically to detect for stuck at conditions.
Writing to this register delimits the accumulation intervals in the PMON
accumulation registers. Counts accumulated in those registers are transferred to
holding registers where they can be read. The counters themselves are then
cleared to begin accumulating events for a new accumulation interval. The bits in
this register are not affected by write accesses.
SYSCLKA:
The system clock active bit (SYSCLKA) monitors for low to high transitions on
the SYSCLK input. SYSCLKA is set high on a rising edge of SYSCLK, and is
set low when this register is read.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 73
Page 83
DATA SHEET
PMC-1990114 ISSUE 6 84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER
PM7385 FREEDM-84A672
WITH ANY-PHY PACKET INTERFACE
REFCLKA:
The SBI reference clock active bit (REFCLKA) monitors for low to high
transitions on the REFCLK input. REFCLKA is set high on a rising edge of
REFCLK, and is set low when this register is read.
FASTCLKA:
The SBI fast clock active bit (FASTCLKA) monitors for low to high transitions
on the FASTCLK input. FASTCLKA is set high on a rising edge of FASTCLK,
and is set low when this register is read.
C1FPA:
The SBI frame pulse active bit (C1FPA) monitors for low to high transitions on
the C1FP input. C1FPA is set high on a rising edge of C1FP, and is set low
when this register is read.
RXCLKA:
The Any-PHY receive clock active bit (RXCLKA) monitors for low to high
transitions on the RXCLK input. RXCLKA is set high on a rising edge of
RXCLK, and is set low when this register is read.
TXCLKA:
The Any-PHY transmit clock active bit (TXCLKA) monitors for low to high
transitions on the TXCLK input. TXCLKA is set high on a rising edge of
TXCLK, and is set low when this register is read.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 74
Page 84
DATA SHEET
PMC-1990114 ISSUE 6 84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER
PM7385 FREEDM-84A672
WITH ANY-PHY PACKET INTERFACE
Register 0x014 : FREEDM-84A672 Master Line Loopback
Bit Type Function Default
Bit 15
R/W Reserved 0000H
to
Bit 3
Bit 2 R/W LLBEN[2] 0
Bit 1 R/W LLBEN[1] 0
Bit 0 R/W LLBEN[0] 0
This register controls line loopback for the three serial data links (enabled when
SPEn_EN is low).
LLBEN[2:0]:
The line loopback enable bits (LLBEN[2:0]) control line loopback for links #2
to #0. When LLBEN[n] is set high, the data on RD[n] is passed verbatim to
TD[n] which is then updated on the falling edge of RCLK[n]. TCLK[n] is
ignored. When LLBEN[n] is set low, TD[n] is processed normally.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 75
Page 85
DATA SHEET
PMC-1990114 ISSUE 6 84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER
PM7385 FREEDM-84A672
WITH ANY-PHY PACKET INTERFACE
Register 0x024 : FREEDM-84A672 Master Performance Monitor Control
Bit Type Function Default
Bit 15 Unused X
Bit 14 R/W TP2EN 0
Bit 13 R/W TABRT2EN 0
Bit 12 R/W RP2EN 0
Bit 11 R/W RLENE2EN 0
Bit 10 R/W RABRT2EN 0
Bit 9 R/W RFCSE2EN 0
Bit 8 R/W RSPE2EN 0
Bit 7 Unused X
Bit 6 R/W TP1EN 0
Bit 5 R/W TABRT1EN 0
Bit 4 R/W RP1EN 0
Bit 3 R/W RLENE1EN 0
Bit 2 R/W RABRT1EN 0
Bit 1 R/W RFCSE1EN 0
Bit 0 R/W RSPE1EN 0
This register configures the events that are accumulated in the two configurable
performance monitor counters in the PMON block.
RSPE1EN:
The receive small packet error accumulate enable bit (RSPE1EN) enables
counting of minimum packet size violation events. When RSPE1EN is set
high, receipt of a packet that is shorter than 32 bits (CRC-CCITT, Unspecified
CRC or no CRC) or 48 bits (CRC-32) will cause the PMON Configurable
Accumulator #1 register to increment. Small packet errors are ignored when
RSPE1EN is set low.
RFCSE1EN:
The receive frame check sequence error accumulate enable bit (RFCSE1EN)
enables counting of receive FCS error events. When RFCSE1EN is set high,
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 76
Page 86
DATA SHEET
PMC-1990114 ISSUE 6 84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER
PM7385 FREEDM-84A672
WITH ANY-PHY PACKET INTERFACE
a mismatch between the received FCS code and the computed CRC residue
will cause the PMON Configurable Accumulator #1 register to increment.
Receive frame check sequence errors are ignored when RFCSE1EN is set
low.
RABRT1EN:
The receive abort accumulate enable bit (RABRT1EN) enables counting of
receive HDLC abort events. When RABRT1EN is set high, receipt of an abort
code (at least 7 contiguous 1’s) will cause the PMON Configurable
Accumulator #1 register to increment. Receive aborts are ignored when
RABRT1EN is set low.
RLENE1EN:
The receive packet length error accumulate enable bit (RLENE1EN) enables
counting of receive packet length error events. When RLENE1EN is set high,
receipt of a packet that is longer than the programmable maximum or of a
packet that in not octet aligned will cause the PMON Configurable
Accumulator #1 register to increment. (Receipt of a packet that is both too
long and not octet aligned results in only one increment.) Receive packet
length errors are ignored when RLENE1EN is set low.
RP1EN:
The receive packet enable bit (RP1EN) enables counting of receive error-free
packets. When RP1EN is set high, receipt of an error-free packet will cause
the PMON Configurable Accumulator #1 register to increment. Receive errorfree packets are ignored when RP1EN is set low.
TABRT1EN:
The transmit abort accumulate enable bit (TABRT1EN) enables counting of
transmit HDLC abort events. When TABRT1EN is set high, insertion of an
abort in the outgoing stream will cause the PMON Configurable Accumulator
#1 register to increment. Transmit aborts are ignored when TABRT1EN is set
low.
TP1EN:
The transmit packet enable bit (TP1EN) enables counting of transmit
error-free packets. When TP1EN is set high, transmission of an error-free
packet will cause the PMON Configurable Accumulator #1 register to
increment. Transmit error-free packets are ignored when TP1EN is set low.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 77
Page 87
DATA SHEET
PMC-1990114 ISSUE 6 84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER
PM7385 FREEDM-84A672
WITH ANY-PHY PACKET INTERFACE
RSPE2EN:
The receive small packet error accumulate enable bit (RSPE2EN) enables
counting of minimum packet size violation events. When RSPE2EN is set
high, receipt of a packet that is shorter than 32 bits (CRC-CCITT, Unspecified
CRC or no CRC) or 48 bits (CRC-32) will cause the PMON Configurable
Accumulator #2 register to increment. Small packet errors are ignored when
RSPE2EN is set low.
RFCSE2EN:
The receive frame check sequence error accumulate enable bit (RFCSE2EN)
enables counting of receive FCS error events. When RFCSE2EN is set high,
a mismatch between the received FCS code and the computed CRC residue
will cause the PMON Configurable Accumulator #2 register to increment.
Receive frame check sequence errors are ignored when RFCSE2EN is set
low.
RABRT2EN:
The receive abort accumulate enable bit (RABRT2EN) enables counting of
receive HDLC abort events. When RABRT2EN is set high, receipt of an abort
code (at least 7 contiguous 2’s) will cause the PMON Configurable
Accumulator #2 register to increment. Receive aborts are ignored when
RABRT2EN is set low.
RLENE2EN:
The receive packet length error accumulate enable bit (RLENE2EN) enables
counting of receive packet length error events. When RLENE2EN is set high,
receipt of a packet that is longer than the programmable maximum or of a
packet that in not octet aligned will cause the PMON Configurable
Accumulator #2 register to increment. (Receipt of a packet that is both too
long and not octet aligned results in only one increment.) Receive packet
length errors are ignored when RLENE2EN is set low.
RP2EN:
The receive packet enable bit (RP2EN) enables counting of receive error-free
packets. When RP2EN is set high, receipt of an error-free packet will cause
the PMON Configurable Accumulator #2 register to increment. Receive errorfree packets are ignored when RP2EN is set low.
TABRT2EN:
The transmit abort accumulate enable bit (TABRT2EN) enables counting of
transmit HDLC abort events. When TABRT2EN is set high, insertion of an
abort in the outgoing stream will cause the PMON Configurable Accumulator
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 78
Page 88
DATA SHEET
PMC-1990114 ISSUE 6 84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER
PM7385 FREEDM-84A672
WITH ANY-PHY PACKET INTERFACE
#2 register to increment. Transmit aborts are ignored when TABRT2EN is set
low.
TP2EN:
The transmit packet enable bit (TP2EN) enables counting of transmit
error-free packets. When TP2EN is set high, transmission of an error-free
packet will cause the PMON Configurable Accumulator #2 register to
increment. Transmit error-free packets are ignored when TP2EN is set low.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 79
Page 89
DATA SHEET
PMC-1990114 ISSUE 6 84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER
This register provides interrupt enables for various events detected or initiated by
the SBI circuitry within the FREEDM-84A672.
SBIEXTE:
The SBI Extracter interrupt enable bit (SBIEXTE) enables interrupts from the
SBI Extract block to the microprocessor. When SBIEXTE is set high, an
interrupt from the SBI Extract block will cause an interrupt to be generated on
the INTB output. Interrupts are masked when SBIEXTE is set low. However,
the SBIEXTI bit remains valid when interrupts are disabled and may be polled
to detect interrupts from the SBI Extract Block.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 80
Page 90
DATA SHEET
PMC-1990114 ISSUE 6 84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER
PM7385 FREEDM-84A672
WITH ANY-PHY PACKET INTERFACE
Register 0x02C : FREEDM-84A672 Master SBI Interrupt Status
Bit Type Function Default
Bit 15
Unused XXH
to
Bit 1
Bit 0 R SBIEXTI X
This register reports the interrupt status for various events detected or initiated by
the SBI circuitry within the FREEDM-84A672. Reading this register
acknowledges and clears the interrupts.
SBIEXTI:
The SBI Extracter interrupt status bit (SBIEXTI) reports an error condition
from the SBI Extract block to the microprocessor. SBIEXTI remains valid
when interrupts are disabled and may be polled to detect SBI Extract block
error conditions.
Note
The only error condition which the SBI Extract block reports is a parity error
on the SBI DROP BUS. If parity errors occur, the SBI EXTRACT Parity Error
Interrupt Reason register (0x5DC) may be read to obtain more detailed
information concerning the error.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 81
Page 91
DATA SHEET
PMC-1990114 ISSUE 6 84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER
This register controls line loopback for tributaries #1 to #16 of SPE #1.
SPE1_LBEN[16:1]:
The SPE #1 loopback enable bits (SPE1_LBEN[16:1]) control line loopback
for tributaries #16 to #1 of SPE #1 of the SBI Interface. When SPE1_LBEN[n]
is set high, the data on tributary #n output by the SBI PISO block is looped
back to the tributary #n input of the SBI SIPO block. When SPE1_LBEN[n] is
set low, transmit data for tributary #n is provided by the TCAS block (i.e.
processed normally).
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 82
Page 92
DATA SHEET
PMC-1990114 ISSUE 6 84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER
This register controls line loopback for tributaries #17 to #28 of SPE #1 and
tributaries #1 to #4 of SPE #2.
SPE1_LBEN[28:17]:
The SPE #1 loopback enable bits (SPE1_LBEN[28:17]) control line loopback
for tributaries #28 to #17 of SPE #1 of the SBI Interface. When
SPE1_LBEN[n] is set high, the data on tributary #n output by the SBI PISO
block is looped back to the tributary #n input of the SBI SIPO block. When
SPE1_LBEN[n] is set low, transmit data for tributary #n is provided by the
TCAS block (i.e. processed normally).
SPE2_LBEN[4:1]:
The SPE #2 loopback enable bits (SPE2_LBEN[4:1]) control line loopback for
tributaries #4 to #1 of SPE #2 of the SBI Interface. When SPE2_LBEN[n] is
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 83
Page 93
DATA SHEET
PMC-1990114 ISSUE 6 84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER
PM7385 FREEDM-84A672
WITH ANY-PHY PACKET INTERFACE
set high, the data on tributary #n output by the SBI PISO block is looped back
to the tributary #n input of the SBI SIPO block. When SPE2_LBEN[n] is set
low, transmit data for tributary #n is provided by the TCAS block (i.e.
processed normally).
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 84
Page 94
DATA SHEET
PMC-1990114 ISSUE 6 84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER
This register controls line loopback for tributaries #5 to #20 of SPE #2.
SPE2_LBEN[20:5]:
The SPE #2 loopback enable bits (SPE2_LBEN[20:5]) control line loopback
for tributaries #20 to #5 of SPE #2 of the SBI Interface. When SPE2_LBEN[n]
is set high, the data on tributary #n output by the SBI PISO block is looped
back to the tributary #n input of the SBI SIPO block. When SPE2_LBEN[n] is
set low, transmit data for tributary #n is provided by the TCAS block (i.e.
processed normally).
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 85
Page 95
DATA SHEET
PMC-1990114 ISSUE 6 84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER
This register controls line loopback for tributaries #21 to #28 of SPE #2 and
tributaries #1 to #8 of SPE #3.
SPE3_LBEN[28:21]:
The SPE #2 loopback enable bits (SPE2_LBEN[28:21]) control line loopback
for tributaries #28 to #21 of SPE #2 of the SBI Interface. When
SPE2_LBEN[n] is set high, the data on tributary #n output by the SBI PISO
block is looped back to the tributary #n input of the SBI SIPO block. When
SPE2_LBEN[n] is set low, transmit data for tributary #n is provided by the
TCAS block (i.e. processed normally).
SPE3_LBEN[8:1]:
The SPE #3 loopback enable bits (SPE3_LBEN[8:1]) control line loopback for
tributaries #8 to #1 of SPE #3 of the SBI Interface. When SPE3_LBEN[n] is
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 86
Page 96
DATA SHEET
PMC-1990114 ISSUE 6 84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER
PM7385 FREEDM-84A672
WITH ANY-PHY PACKET INTERFACE
set high, the data on tributary #n output by the SBI PISO block is looped back
to the tributary #n input of the SBI SIPO block. When SPE3_LBEN[n] is set
low, transmit data for tributary #n is provided by the TCAS block (i.e.
processed normally).
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 87
Page 97
DATA SHEET
PMC-1990114 ISSUE 6 84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER
This register controls line loopback for tributaries #9 to #24 of SPE #3.
SPE3_LBEN[24:9]:
The SPE #3 loopback enable bits (SPE3_LBEN[24:9]) control line loopback
for tributaries #24 to #9 of SPE #3 of the SBI Interface. When SPE3_LBEN[n]
is set high, the data on tributary #n output by the SBI PISO block is looped
back to the tributary #n input of the SBI SIPO block. When SPE3_LBEN[n] is
set low, transmit data for tributary #n is provided by the TCAS block (i.e.
processed normally).
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 88
Page 98
DATA SHEET
PMC-1990114 ISSUE 6 84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER
This register controls line loopback for tributaries #25 to #28 of SPE #3.
SPE3_LBEN[28:25]:
The SPE #3 loopback enable bits (SPE3_LBEN[28:25]) control line loopback
for tributaries #28 to #25 of SPE #3 of the SBI Interface. When
SPE3_LBEN[n] is set high, the data on tributary #n output by the SBI PISO
block is looped back to the tributary #n input of the SBI SIPO block. When
SPE3_LBEN[n] is set low, transmit data for tributary #n is provided by the
TCAS block (i.e. processed normally).
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 89
Page 99
DATA SHEET
PMC-1990114 ISSUE 6 84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER
PM7385 FREEDM-84A672
WITH ANY-PHY PACKET INTERFACE
Register 0x048 : FREEDM-84A672 SBI DROP BUS Master Configuration
Bit Type Function Default
Bit 15
Unused X
to
Bit 10
Bit 9 R/W Reserved 0
Bit 8 R/W Reserved 0
Bit 7 R/W FCLK_FREQ[1] 0
Bit 6 R/W FCLK_FREQ[0] 0
Bit 5 R/W SPE3_TYP[1] 0
Bit 4 R/W SPE3_TYP[0] 0
Bit 3 R/W SPE2_TYP[1] 0
Bit 2 R/W SPE2_TYP[0] 0
Bit 1 R/W SPE1_TYP[1] 0
Bit 0 R/W SPE1_TYP[0] 0
This register controls configures the operation of the SBI DROP BUS.
SPEn_TYP[1:0]:
The SPE type bits (SPEn_TYP[1:0]) determine the configuration of each of
the three Synchronous Payload Envelopes conveyed on the SBI DROP BUS,
according to the following table.
Table 12 – SPE Type Configuration
SPEn_TYP[1:0]Link Configuration
00 28 T1/J1 links
01 21 E1 links
10 Single DS-3 link
11 Reserved
FCLK_FREQ[1:0]:
The FASTCLK frequency selector bits (FCLK_FREQ[1:0]) must be set
according to the following table, depending on the frequency chosen for the
FASTCLK input.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 90
Page 100
DATA SHEET
PMC-1990114 ISSUE 6 84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER
PM7385 FREEDM-84A672
WITH ANY-PHY PACKET INTERFACE
Table 13 – FASTCLK Frequency Selection
FCLK_FREQ[1:0] FASTCLK Frequency
00 51.84 MHz
01 44.928 MHz
10 Reserved
11 66 MHz
Reserved:
The reserved bits must be set low for correct operation of the FREEDM84A672 device.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 91
Loading...
+ hidden pages
You need points to download manuals.
1 point = 1 manual.
You can buy points or you can get point for every manual you upload.