Datasheet PM7346 Datasheet (PMC)

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PM7346 S/UNI-QJET

DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3

PM7346

S/UNI

QJET

S/UNI-QJET

SATURN QUAD USER NETWORK

INTERFACE FOR J2/E3/T3

DATASHEET

PROPRIETARY AND CONFIDENTIAL

ISSUE 6: MAY 1999

PMC-SIERRA, INC. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND ITS CUSTOMERS’ INTERNAL USE

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PM7346 S/UNI-QJET

DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3

REVISION HISTORY

Issue No. Issue Date Details of Change

6 May 14, 1999

• The S/UNI-QJET requires a software

initialization sequence in order to guarantee proper device operation and long term reliability. Please refer to Section 12.1 of this document for the details on how to program this sequence.

• Updated the RFCLK and TFCLK pin

descriptions to reflect that these pins are not 5V tolerant. Both pins are 3.3V only input pins.

• Documentation clarifications.

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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3

CONTENTS

1 FEATURES...............................................................................................1

2 APPLICATIONS........................................................................................6

3 REFERENCES.........................................................................................7

4 APPLICATION EXAMPLES....................................................................10

5 BLOCK DIAGRAM..................................................................................13

6 DESCRIPTION.......................................................................................17

7 PIN DIAGRAM........................................................................................21

8 PIN DESCRIPTION................................................................................22

9 FUNCTIONAL DESCRIPTION...............................................................59

9.1 DS3 FRAMER..............................................................................59

9.2 E3 FRAMER ................................................................................61

9.3 J2 FRAMER.................................................................................63

9.3.1 J2 FRAME FIND ALGORITHMS.......................................65

9.4 PMON PERFORMANCE MONITOR ACCUMULATOR................68

9.5 RBOC BIT-ORIENTED CODE DETECTOR.................................68

9.6 RDLC FACILITY DATA LINK RECEIVER.....................................69

9.7 SPLR PLCP LAYER RECEIVER .................................................70

9.8 ATMF ATM CELL DELINEATOR ..................................................70

9.9 RXCP-50 RECEIVE CELL PROCESSOR...................................72

9.10 RXFF RECEIVE FIFO..................................................................74

9.11 CPPM CELL AND PLCP PERFORMANCE MONITOR...............75

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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3

9.12 PRGD PSEUDO-RANDOM SEQUENCE

GENERATOR/DETECTOR ..........................................................75

9.13 DS3 TRANSMITTER....................................................................76

9.14 E3 TRANSMITTER......................................................................77

9.15 J2 TRANSMITTER.......................................................................78

9.16 XBOC BIT ORIENTED CODE GENERATOR ..............................79

9.17 TDPR FACILITY DATA LINK TRANSMITTER..............................79

9.18 SPLT SMDS PLCP LAYER TRANSMITTER................................81

9.19 TXCP-50 TRANSMIT CELL PROCESSOR.................................82

9.20 TXFF TRANSMIT FIFO................................................................83

9.21 TTB TRAIL TRACE BUFFER.......................................................83

9.22 JTAG TEST ACCESS PORT........................................................84

9.23 MICROPROCESSOR INTERFACE.............................................84

10 NORMAL MODE REGISTER DESCRIPTION........................................91

11 TEST FEATURES DESCRIPTION .......................................................294

11.1 TEST MODE 0 DETAILS...........................................................300

11.2 JTAG TEST PORT......................................................................305

12 OPERATION.........................................................................................308

12.1 SOFTWARE INITIALIZATION SEQUENCE...............................308

12.2 REGISTER SETTINGS FOR BASIC CONFIGURATIONS ........310

12.3 PLCP FRAME FORMATS..........................................................311

12.3.1PLCP PATH OVERHEAD OCTET PROCESSING..........314

12.4 DS3 FRAME FORMAT..............................................................319

12.5 G.751 E3 FRAME FORMAT.......................................................321

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12.6 G.832 E3 FRAME FORMAT.......................................................323

12.7 J2 FRAME FORMAT..................................................................325

12.8 S/UNI-QJET CELL DATA STRUCTURE.....................................327

12.9 RESETTING THE RXFF AND TXFF FIFOS ..............................331

12.10 SERVICING INTERRUPTS........................................................331

12.11 USING THE PERFORMANCE MONITORING FEATURES.......332

12.12 USING THE INTERNAL FDL TRANSMITTER...........................333

12.13 USING THE INTERNAL DATA LINK RECEIVER.......................336

12.14 PRGD PATTERN GENERATION................................................341

12.14.1 GENERATING AND DETECTING REPETITIVE

PATTERNS......................................................................341

12.14.2 COMMON TEST PATTERNS...........................................

........................................................................................342

12.15 JTAG SUPPORT........................................................................344

13 FUNCTIONAL TIMING .........................................................................353

14 ABSOLUTE MAXIMUM RATINGS........................................................380

15 D.C. CHARACTERISTICS ....................................................................381

16 MICROPROCESSOR INTERFACE TIMING CHARACTERISTICS......384

17 A.C. TIMING CHARACTERISTICS.......................................................388

18 ORDERING AND THERMAL INFORMATION ......................................405

19 MECHANICAL INFORMATION.............................................................406

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LIST OF REGISTERS

CONFIGURATION..................................................................................97

CONFIGURATION................................................................................100

CONTROL............................................................................................103

REGISTER 005H, 105H, 205H, 305H: S/UNI-QJET INTERRUPT STATUS...107 REGISTER 006H: S/UNI-QJET IDENTIFICATION, MASTER RESET, AND

GLOBAL MONITOR UPDATE ...............................................................108

MONITOR AND INTERRUPT IDENTIFICATION..................................110

..............................................................................................................125

METERS...............................................................................................128

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..............................................................................................................130

COUNT LSB.........................................................................................131

COUNT MSB........................................................................................132

COUNT LSB.........................................................................................133

COUNT MSB........................................................................................134

..............................................................................................................135

..............................................................................................................136

LSB.......................................................................................................137

MSB......................................................................................................138

COUNT LSB.........................................................................................139

COUNT MSB........................................................................................140

LSB.......................................................................................................141

MSB......................................................................................................142

PERFORMANCE METERS..................................................................144

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COUNT LSB.........................................................................................147

COUNT MSB........................................................................................148

(ACE=0)................................................................................................153

CONFIGURATION REGISTER (ACE=1)..............................................155

..............................................................................................................168

ENABLE ...............................................................................................170

INDICATION AND STATUS...................................................................172

INTERRUPT ENABLE..........................................................................175

INTERRUPT INDICATION....................................................................177

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STATUS ................................................................................................179

OPTIONS .............................................................................................184

ADAPTATION OPTIONS.......................................................................187

..............................................................................................................192

..............................................................................................................194

ENABLE ...............................................................................................196

STATUS ................................................................................................198

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..............................................................................................................213

..............................................................................................................214

..............................................................................................................217

THRESHOLD .......................................................................................218

CLEAR..................................................................................................221

CONFIG................................................................................................229

COUNTER STATUS..............................................................................231

..............................................................................................................233

(MSB) ...................................................................................................235

(LSB) ....................................................................................................236

PATTERN..............................................................................................238

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..............................................................................................................239

COUNT.................................................................................................240

ERROR COUNT...................................................................................241

(LSB) ....................................................................................................242

..............................................................................................................243

(MSB) ...................................................................................................244

..............................................................................................................245

..............................................................................................................247

..............................................................................................................254

CONTROL............................................................................................256

CONTROL............................................................................................257

(LSB) ....................................................................................................258

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(MSB) ...................................................................................................260

..............................................................................................................263

REGISTER 094H, 194H, 294H, 394H: TTB EXPECTED PAYLOAD TYPE LABEL267 REGISTER 095H, 195H, 295H, 395H: TTB PAYLOAD TYPE LABEL

CONTROL/STATUS..............................................................................269

ENABLE ...............................................................................................271

..............................................................................................................281

..............................................................................................................285

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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3

REGISTER 0ACH, 1ACH, 2ACH, 3ACH: PRGD PATTERN DETECTOR #1..290 REGISTER 0ADH, 1ADH, 2ADH, 3ADH: PRGD PATTERN DETECTOR #2..291 REGISTER 0AEH, 1AEH, 2AEH, 3AEH: PRGD PATTERN DETECTOR #3..292 REGISTER 0AFH, 1AFH, 2AFH, 3AFH: PRGD PATTERN DETECTOR #4...293

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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3

LIST OF FIGURES

FIGURE 1 - S/UNI-QJET, AS AN ATM PHY, IN AN ATM SWITCH...................10

FIGURE 3 - S/UNI-QJET, AS A QUAD FRAMER DEVICE, IN FRAME RELAY

EQUIPMENT.....................................................................................................11

FIGURE 5 - S/UNI-QJET, AS A CELL PROCESSOR, IN DSLAM EQUIPMENT

FIGURE 7 - NORMAL OPERATING MODE.....................................................13

FIGURE 8 - DS3/E3/J2 FRAMERS BYPASSED..............................................14

FIGURE 9 - DS3/E3/J2 TRANSCEIVER MODE..............................................15

FIGURE 10- LOOPBACK MODES....................................................................16

FIGURE 11- FRAMING ALGORITHM (CRC_REFR = 0)..................................66

FIGURE 13- FRAMING ALGORITHM (CRC_REFR = 1)..................................67

FIGURE 15- CELL DELINEATION STATE DIAGRAM.......................................71

FIGURE 17- HCS VERIFICATION STATE DIAGRAM.......................................74

FIGURE 19- DS3 PLCP FRAME FORMAT.....................................................312

FIGURE 13- DS1 PLCP FRAME FORMAT.....................................................313

FIGURE 14- G.751 E3 PLCP FRAME FORMAT.............................................313

FIGURE 23- E1 PLCP FRAME FORMAT .......................................................314

FIGURE 16- DS3 FRAME STRUCTURE........................................................319

FIGURE 18- G.751 E3 FRAME STRUCTURE................................................321

FIGURE 20- G.832 E3 FRAME STRUCTURE................................................323

FIGURE 22- J2 FRAME STRUCTURE...........................................................325

FIGURE 24- 16-BIT WIDE, 26 WORD STRUCTURE......................................327

FIGURE 26- 16-BIT WIDE, 27 WORD STRUCTURE......................................328

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FIGURE 28- 8-BIT WIDE, 52 WORD STRUCTURE........................................329

FIGURE 30- 8-BIT WIDE, 53 WORD STRUCTURE........................................330

FIGURE 32- TYPICAL DATA FRAME..............................................................339

FIGURE 33- EXAMPLE MULTI-PACKET OPERATIONAL SEQUENCE.........340

FIGURE 34- PRGD PATTERN GENERATOR .................................................341

FIGURE 36- BOUNDARY SCAN ARCHITECTURE........................................345

FIGURE 37- TAP CONTROLLER FINITE STATE MACHINE ..........................347

FIGURE 38- INPUT OBSERVATION CELL (IN_CELL)...................................350

FIGURE 39- OUTPUT CELL (OUT_CELL).....................................................351

FIGURE 40- BI-DIRECTIONAL CELL (IO_CELL)...........................................351

FIGURE 41- LAYOUT OF OUTPUT ENABLE AND BI-DIRECTIONAL CELLS

.....................................................................................................352

FIGURE 42- RECEIVE DS1 STREAM............................................................353

FIGURE 43- RECEIVE E1 STREAM ..............................................................353

FIGURE 44- RECEIVE BIPOLAR DS3 STREAM...........................................354

FIGURE 45- RECEIVE UNIPOLAR DS3 STREAM ........................................354

FIGURE 46- RECEIVE BIPOLAR E3 STREAM..............................................355

FIGURE 47- RECEIVE UNIPOLAR E3 STREAM...........................................355

FIGURE 48- RECEIVE BIPOLAR J2 STREAM ..............................................356

FIGURE 49- RECEIVE UNIPOLAR J2 STREAM............................................356

FIGURE 50- GENERIC RECEIVE STREAM ..................................................357

FIGURE 51- RECEIVE DS3 OVERHEAD.......................................................357

FIGURE 52- RECEIVE G.832 E3 OVERHEAD...............................................358

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FIGURE 53- RECEIVE G.751 E3 OVERHEAD...............................................359

FIGURE 54- RECEIVE J2 OVERHEAD..........................................................359

FIGURE 55- RECEIVE PLCP OVERHEAD....................................................360

FIGURE 56- TRANSMIT DS1 STREAM.........................................................361

FIGURE 57- TRANSMIT E1 STREAM............................................................361

FIGURE 58- TRANSMIT BIPOLAR DS3 STREAM.........................................362

FIGURE 59- TRANSMIT UNIPOLAR DS3 STREAM......................................362

FIGURE 60- TRANSMIT BIPOLAR E3 STREAM...........................................363

FIGURE 61- TRANSMIT UNIPOLAR E3 STREAM.........................................363

FIGURE 62- TRANSMIT BIPOLAR J2 STREAM............................................364

FIGURE 63- TRANSMIT UNIPOLAR J2 STREAM.........................................364

FIGURE 64- GENERIC TRANSMIT STREAM................................................365

FIGURE 65- TRANSMIT DS3 OVERHEAD ....................................................366

FIGURE 66- TRANSMIT G.832 E3 OVERHEAD............................................367

FIGURE 67- TRANSMIT G.751 E3 OVERHEAD............................................368

FIGURE 68- TRANSMIT J2 OVERHEAD........................................................368

FIGURE 69- TRANSMIT PLCP OVERHEAD..................................................369

FIGURE 70- FRAMER MODE DS3 TRANSMIT INPUT STREAM..................370

FIGURE 71- FRAMER MODE DS3 TRANSMIT INPUT STREAM WITH

TGAPCLK .....................................................................................................370

FIGURE 72- FRAMER MODE DS3 RECEIVE OUTPUT STREAM ................371

FIGURE 73- FRAMER MODE DS3 RECEIVE OUTPUT STREAM WITH

RGAPCLK .....................................................................................................371

FIGURE 74- FRAMER MODE G.751 E3 TRANSMIT INPUT STREAM..........371

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FIGURE 75- FRAMER MODE G.751 E3 TRANSMIT INPUT STREAM WITH

TGAPCLK .....................................................................................................372

FIGURE 76- FRAMER MODE G.751 E3 RECEIVE OUTPUT STREAM........372

FIGURE 77- FRAMER MODE G.751 E3 RECEIVE OUTPUT STREAM WITH

RGAPCLK .....................................................................................................372

FIGURE 78- FRAMER MODE G.832 E3 TRANSMIT INPUT STREAM..........373

FIGURE 79- FRAMER MODE G.832 E3 TRANSMIT INPUT STREAM WITH

TGAPCLK .....................................................................................................373

FIGURE 80- FRAMER MODE G.832 E3 RECEIVE OUTPUT STREAM........374

FIGURE 81- FRAMER MODE G.832 E3 RECEIVE OUTPUT STREAM WITH

RGAPCLK .....................................................................................................374

FIGURE 82- FRAMER MODE J2 TRANSMIT INPUT STREAM.....................374

FIGURE 83- FRAMER MODE J2 TRANSMIT INPUT STREAM WITH TGAPCLK

.....................................................................................................375

FIGURE 84- FRAMER MODE J2 RECEIVE OUTPUT STREAM ...................375

FIGURE 85- FRAMER MODE J2 RECEIVE OUTPUT STREAM WITH

RGAPCLK .....................................................................................................375

FIGURE 86- MULTI-PHY POLLING AND ADDRESSING TRANSMIT CELL

INTERFACE ....................................................................................................376

FIGURE 87- MULTI-PHY POLLING AND ADDRESSING RECEIVE CELL

INTERFACE ....................................................................................................377

FIGURE 88- MICROPROCESSOR INTERFACE READ TIMING....................385

FIGURE 90- MICROPROCESSOR INTERFACE WRITE TIMING..................387

FIGURE 92- RSTB TIMING ............................................................................388

FIGURE 94- TRANSMIT ATM CELL INTERFACE TIMING.............................389

FIGURE 96- RECEIVE ATM CELL INTERFACE TIMING ...............................391

FIGURE 98- TRANSMIT INTERFACE TIMING ...............................................394

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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3

FIGURE 100......................................................- RECEIVE INTERFACE TIMING

.....................................................................................................399

FIGURE 102..................................................- JTAG PORT INTERFACE TIMING

.....................................................................................................403

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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3

LIST OF TABLES

TABLE 1 - SUPPORTED OPERATING FORMATS..........................................1

TABLE 2 - REGISTER MEMORY MAP .........................................................84

TABLE 3 - STATSEL[2:0] OPTIONS ..............................................................96

TABLE 4 - TFRM[1:0] TRANSMIT FRAME STRUCTURE CONFIGURATIONS

.......................................................................................................98

TABLE 5 - LOF[1:0] INTEGRATION PERIOD CONFIGURATION...............101

TABLE 6 - RFRM[1:0] RECEIVE FRAME STRUCTURE CONFIGURATIONS

.....................................................................................................101

TABLE 7 - SPLR FORM[1:0] CONFIGURATIONS.......................................113

TABLE 8 - PLCP LOF DECLARATION/REMOVAL TIMES..........................118

TABLE 9 - SPLT FORM[1:0] CONFIGURATIONS .......................................122

TABLE 10 - DS3 FRMR EXZS/LCV COUNT CONFIGURATIONS ................156

TABLE 11 - DS3 FRMR AIS CONFIGURATIONS .........................................157

TABLE 12 - E3 FRMR FORMAT[1:0] CONFIGURATIONS ............................167

TABLE 13 - E3 TRAN FORMAT[1:0] CONFIGURATIONS.............................181

TABLE 14 - J2 FRMR LOS THRESHOLD CONFIGURATIONS ....................190

TABLE 15 - RDLC PBS[2:0] DATA STATUS...................................................210

TABLE 16 - RXCP-50 HCS FILTERING CONFIGURATIONS........................226

TABLE 17 - RXCP-50 CELL DELINATION ALGORITHM BASE ...................227

TABLE 18 - RXCP-50 LCD INTEGRATION PERIODS..................................237

TABLE 19 - TXCP-50 FIFO DEPTH CONFIGURATIONS..............................252

TABLE 20 - TTB PAYLOAD TYPE MATCH CONFIGURATIONS....................267

TABLE 21 - PRGD PATTERN DETECTOR REGISTER CONFIGURATION..279

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TABLE 22 - PRGD GENERATED BIT ERROR RATE CONFIGURATIONS...285

TABLE 23 - TEST MODE REGISTER MEMORY MAP..................................294

TABLE 24 - TEST MODE 0 INPUT READ ADDRESS LOCATIONS..............300

TABLE 25 - TEST MODE 0 OUTPUT WRITE ADDRESS LOCATIONS ........302

TABLE 26 - INSTRUCTION REGISTER........................................................305

TABLE 27 - BOUNDARY SCAN REGISTER .................................................306

TABLE 28 - REGISTER SETTINGS FOR BASIC CONFIGURATIONS.........310

TABLE 29 - PLCP OVERHEAD PROCESSING............................................314

TABLE 30 - PLCP PATH OVERHEAD IDENTIFIER CODES.........................317

TABLE 32 - DS3 PLCP TRAILER LENGTH ..................................................318

TABLE 34 - E3 PLCP TRAILER LENGTH.....................................................318

TABLE 36 - DS3 FRAME OVERHEAD OPERATION ....................................320

TABLE 37 - G.751 E3 FRAME OVERHEAD OPERATION ............................322

TABLE 38 - G.832 E3 FRAME OVERHEAD OPERATION ............................323

TABLE 39 - J2 FRAME OVERHEAD OPERATION........................................326

TABLE 40 - PSEUDO RANDOM PATTERN GENERATION (PS BIT = 0)......342

TABLE 41 - REPETITIVE PATTERN GENERATION (PS BIT = 1).................343

TABLE 42 - DS3 RECEIVE OVERHEAD BITS..............................................358

TABLE 43 - DS3 TRANSMIT OVERHEAD BITS ...........................................366

TABLE 44 - ABSOLUTE MAXIMUM RATINGS..............................................380

TABLE 45 - DC CHARACTERISTICS............................................................381

TABLE 46 - MICROPROCESSOR INTERFACE READ ACCESS (FIGURE 88)

.....................................................................................................384

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TABLE 47 - MICROPROCESSOR INTERFACE WRITE ACCESS (FIGURE 90)

.....................................................................................................386

TABLE 48 - RSTB TIMING (FIGURE 92).......................................................388

TABLE 49 - TRANSMIT ATM CELL INTERFACE TIMING (FIGURE 94).......388

TABLE 50 - RECEIVE ATM CELL INTERFACE TIMING (FIGURE 96).........390

TABLE 51 - TRANSMIT INTERFACE TIMING (FIGURE 98).........................392

TABLE 52 - RECEIVE INTERFACE TIMING (FIGURE 100)..........................398

TABLE 53 - JTAG PORT INTERFACE (FIGURE 102)...................................402

TABLE 54 - PACKAGING INFORMATION .....................................................405

TABLE 55 - THERMAL INFORMATION.........................................................405

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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3

FEATURES

Single chip quad ATM User Network Interface operating at 44.736 Mbit/s,

•

34.368 Mbit/s, and 6.312 Mbit/s conforming to ATMF-95-1207R1, ATMF-940406R5, and AF-PHY-0029.000. Each line can be individually configured for the desired rate.

Implements ATM Direct Cell Mapping into DS1, DS3, E1, E3, and J2

•

transmission systems according to ITU-T Recommendation G.804. Provides a UTOPIA Level 2 compatible ATM-PHY Interface.

•

Implements the Physical Layer Convergence Protocol (PLCP) for DS1 and

•

DS3 transmission systems according to the ATM Forum User Network Interface Specification and ANSI TA-TSY-000773, TA-TSY-000772, and E1 and E3 transmission systems according to the ETSI 300-269 and ETSI 300-

270. Support is provided for SMDS and ATM mappings into various rate

•

transmission systems as follows:

Table 1 - Supported Operating Formats

Rate Format

T3 (44.736 Mbit/s)

E3 (34.368 Mbit/s)

J2 (6.312 Mbit/s)

E1 (2.048 Mbit/s)

T1 (1.544 Mbit/s)

Arbitrary Cell Rate (up to 52 Mbit/s)

C-bit Parity M23 G.751 G.832 G.704 & NTT

CRC-4 PCM30 ESF SF

Framer

Only

YES YES YES YES YES YES YES YES YES YES n/a YES YES n/a YES

external YES YES external YES YES external YES YES external YES YES

bypass n/a YES

SMDS PLCP

Mapping

ATM Direct

Mapping

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Implements the ATM physical layer for Broadband ISDN according to ITU-T

•

Recommendation I.432. Provides on-chip DS3, E3 (G.751 and G.832), and J2 framers.

•

Can be configured to be used solely as a DS3, E3, or J2 Framer.

•

When configured to operate as a DS3, E3, or J2 Framer, gapped transmit and

•

receive clocks can be optionally generated for interface to devices which only need access to payload data bits.

Provides support for an arbitrary rate external transmission system interface

•

up to a maximum rate of 52 Mbit/s which enables the S/UNI-QJET to be used as a quad ATM cell delineator.

Uses the PMC-Sierra PM4341 T1XC, PM4344 TQUAD, PM6341 E1XC, and

•

PM6344 EQUAD T1 and E1 framer/line interface chips for DS1 and E1 applications.

Provides programmable pseudo-random test pattern generation, detection,

•

and analysis features. Provides integral transmit and receive HDLC controllers with 128-byte FIFO

•

depths. Provides performance monitoring counters suitable for accumulation periods

•

of up to 1 second. Provides an 8-bit microprocessor interface for configuration, control and

•

status monitoring. Provides a standard 5 signal P1149.1 JTAG test port for boundary scan board

•

test purposes. Low power 3.3V CMOS technology with 5V tolerant inputs.

•

Available in a high density 256-pin SBGA package (27mm x 27mm).

•

The receiver section:

Provides frame synchronization for the M23 or C-bit parity DS3 applications,

•

alarm detection, and accumulates line code violations, framing errors, parity errors, path parity errors and FEBE events. In addition, far end alarm channel

PMC-SIERRA, INC. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND ITS CUSTOMERS’ INTERNAL USE

Page 24

PM7346 S/UNI-QJET

DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3

codes are detected, and an integral HDLC receiver is provided to terminate the path maintenance data link.

• Provides frame synchronization for the G.751 or G.832 E3 applications, alarm

detection, and accumulates line code violations, framing errors, parity errors, and FEBE events. In addition, in G.832, the Trail Trace is detected, and an integral HDLC receiver is provided to terminate either the Network Requirement or the General Purpose data link.

• Provides frame synchronization for G.704 and NTT 6.312 Mbit/s J2

applications, alarm detection, and accumulates line code violations, framing errors, and CRC parity errors. An integral HDLC receiver is provided to terminate the data link.

• Provides frame synchronization, cell delineation and extraction for DS3,

G.751 E3, G.832 E3, and G.704 and NTT J2 ATM direct-mapped formats.

• Provides PLCP frame synchronization, path overhead extraction, and cell

extraction for DS1 PLCP, DS3 PLCP, E1 PLCP, and G.751 E3 PLCP formatted streams.

• Provides a 50 MHz 8-bit wide or 16-bit wide Utopia FIFO buffer in the receive

path with parity support, and multi-PHY (Level 2) control signals.

• Provides ATM framing using cell delineation. ATM cell delineation may

optionally be disabled to allow passing of all cell bytes regardless of cell delineation status.

• Provides cell descrambling, header check sequence (HCS) error detection,

idle cell filtering, header descrambling (for use with PPP packets), and accumulates the number of received idle cells, the number of received cells written to the FIFO, and the number of HCS errors.

• Provides a four cell FIFO for rate decoupling between the line, and a higher

layer processing entity. FIFO latency may be reduced by changing the number of operational cell FIFOs.

• Provides a receive HDLC controller with a 128-byte FIFO to accumulate data

link information.

• Provides detection of yellow alarm and loss of frame (LOF), and accumulates

BIP-8 errors, framing errors and FEBE events.

PMC-SIERRA, INC. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND ITS CUSTOMERS’ INTERNAL USE

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PM7346 S/UNI-QJET

DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3

Provides programmable pseudo-random test-sequence detection (up to 232-

•

1 bit length patterns conforming to ITU-T O.151 standards) and analysis features.

The transmitter section:

Provides frame insertion for the M23 or C-bit parity DS3 applications, alarm

•

insertion, and diagnostic features. In addition, far end alarm channel codes may be inserted, and an integral HDLC transmitter is provided to insert the path maintenance data link.

Provides frame insertion for the G.751 or G.832 E3 applications, alarm

•

insertion, and diagnostic features. In addition, for G.832, the Trail Trace is inserted, and an integral HDLC transmitter is provided to insert either the Network Requirement or the General Purpose data link.

Provides frame insertion for G.704 6.312 Mbit/s J2 applications, alarm

•

insertion, and diagnostic features. An integral HDLC transmitter is provided to insert the path maintenance data link.

Provides frame insertion and path overhead insertion for DS1, DS3, E1 or E3

•

based PLCP formats. In addition, alarm insertion and diagnostic features are provided.

Provides a 50 MHz 8-bit wide or 16-bit wide Utopia FIFO buffer in the transmit

•

path with parity support and multi-PHY (Level 2) control signals. Provides optional ATM cell scrambling, header scrambling (for use with PPP

•

packets), HCS generation/insertion, programmable idle cell insertion, diagnostics features and accumulates transmitted cells read from the FIFO.

Provides a four cell FIFO for rate decoupling between the line and a higher

•

layer processing entity. FIFO latency may be reduced by changing the number of operational cell FIFOs.

Provides a transmit HDLC controller with a 128-byte FIFO.

•

Provides an 8 kHz reference input for locking the transmit PLCP frame rate to

•

an externally applied frame reference. Provides programmable pseudo-random test sequence generation (up to

•

232-1 bit length sequences conforming to ITU-T O.151 standards).

PMC-SIERRA, INC. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND ITS CUSTOMERS’ INTERNAL USE

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PM7346 S/UNI-QJET

DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3

Diagnostic abilities include single bit error insertion or error insertion at bit error rates ranging from 10-1 to 10-7.

Bypass and Loopback features:

• Allows bypassing of the DS3, E3, and J2 framers to enable transmission

system sublayer processing by an external device (for example, the PM4344 Quad DS1 Framer may be used for DS1-based services, and the PM6344 Quad E1 Framer may be used for E1-based services).

• Allows bypassing of the PLCP and ATM functions to enable use of the

S/UNI-QJET as a quad DS3, E3, or J2 framer.

• Provides for diagnostic loopbacks, line loopbacks, and payload loopbacks.

PMC-SIERRA, INC. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND ITS CUSTOMERS’ INTERNAL USE

Page 27

PM7346 S/UNI-QJET

DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3

APPLICATIONS

ATM or SMDS Switches, Multiplexers, and Routers

•

SONET/SDH Mux E3/DS3 Tributary Interfaces

•

PDH Mux J2/E3/DS3 Line Interfaces

•

DS3/E3/J2 Digital Cross Connect Interfaces

•

DS3/E3/J2 PPP Internet Access Interfaces

•

DS3/E3/J2 Frame Relay Interfaces

•

PMC-SIERRA, INC. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND ITS CUSTOMERS’ INTERNAL USE

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PM7346 S/UNI-QJET

DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3

REFERENCES

1. ANSI T1.627 - 1993, "Broadband ISDN - ATM Layer Functionality and Specification".

2. ANSI T1.107a - 1990, "Digital Hierarchy - Supplement to Formats Specifications (DS3 Format Applications)".

3. ANSI T1.107 - 1995, "Digital Hierarchy - Formats Specifications".

4. ANSI T1.646 - 1995, "Broadband ISDN - Physical Layer Specification for UserNetwork Interfaces Including DS1/ATM".

5. ATM Forum - ATM User-Network Interface Specification, V3.1, October, 1995.

6. ATM Forum - “UTOPIA, An ATM PHY Interface Specification, Level 2, Version 1”, June, 1995.

7. ATM Forum, 94-0406R5, "E3 (34,368 kbps) Physical Layer Interface", Dec. 21, 1994.

8. ATM Forum, 95-1207R1, "DS3 Physical Layer Interface Specification", December

1995.

9. ATM Forum, af-phy-0029.000, "6,312 Kbps UNI Specification, Version 1.0", June

1995.

10. Bell Communications Research, TA-TSY-000773 - “Local Access System Generic Requirements, Objectives, and Interface in Support of Switched Multi-megabit Data Service” Issue 2, March 1990 and Supplement 1, December 1990.

11. ETS 300 269 Draft Standard T/NA(91)17 - “Metropolitan Area Network Physical Layer Convergence Procedure for 2.048 Mbit/s”, April 1994.

12. ETS 300 270 Draft Standard T/NA(91)18 - “Metropolitan Area Network Physical Layer Convergence Procedure for 34.368 Mbit/s”, April 1994.

13. ITU-T Recommendation O.151 - "Error Performance Measuring Equipment Operating at the Primary Rate and Above", October, 1992.

14. ITU-T Recommendation I.432 - "B-ISDN User-Network Interface - Physical Layer Specification", 1993

15. ITU-T Recommendation G.703 - "Physical/Electrical Characteristics of Hierarchical Digital Interfaces", 1991.

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PM7346 S/UNI-QJET

DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3

16. ITU-T Recommendation G.704 - "General Aspects of Digital Transmission Systems; Terminal Equipments - Synchronous Frame Structures Used At 1544, 6312, 2048, 8488 and 44 736 kbit/s Hierarchical Levels", July, 1995.

17. ITU-T Recommendation G.751 - CCITT Blue Book Fa sc. III.4, "Digital Multiplex Equipments Operating at the Third Order Bit Rate of 34,368 kbit/s and the Fourth Order Bit Rate of 139,264 kbit/s and Using Positive Justification", 1988.

18. ITU-T Draft Recommendation G.775 - "Loss of Signal (LOS) and Alarm Indication Signal (AIS) Defect Detection and Clearance Criteria", October 1993.

19. ITU-T Recommendation G.804 - "ATM Cell Mapping into Plesiochronous Digital Hierarchy (PDH)", 1993.

20. ITU-T Recommendation G.832 - "Transpor t of SDH Elements on PDH Networks: Frame and Multiplexing Structures", 1993.

21. ITU-T Recommendation Q.921 - "ISDN User-Network Interface - Data Link Layer Specification", March, 1993.

22. NTT Technical Reference, "NTT Technical Reference for High-Speed Digital Leased Circuit Services", 1991.

PMC-SIERRA, INC. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND ITS CUSTOMERS’ INTERNAL USE

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PM7346 S/UNI-QJET

DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3

APPLICATION EXAMPLES

The S/UNI-QJET can be configured as an ATM physical layer device. On the line side, it connects to one or more J2/E3/T3 line interface units and on the system side, the S/UNI-QJET interfaces to the ATM layer device, such as PM7322 RCMP-800, over an 8 or 16 bit wide UTOPIA Level 2 interface (as shown in Figure 1).

Figure 1 - S/UNI-QJET, as an ATM PHY, in an ATM Switch

T1/E1 Line Card

PM4314

QDSX

PM7344

S/UNI-MPH

J2/E3/T3 Line Card

J2/E3/T3

LIU

J2/E3/T3

LIU

J2/E3/T3

LIU

J2/E3/T3

LIU

PM7346

PM5355

PM7346

S/UNI-QJET

S/UNI-622

S/UNI-QJET

UT O P IA Bus

ATM Switch Core

Switch

Fabric

PM7322

RCMP-800

Egress Device

UT O P IA Bus

OC-12 Line Card

PM5355

S/UNI-622

OC-3 Line Cards

PM5346

PM5355

S/UNI-LITE

S/UNI-622

PM7348

S/UNI-DUAL

PM5347

PM5355

S/UNI-PLUS

S/UNI-622

PMD

PMC-SIERRA, INC. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND ITS CUSTOMERS’ INTERNAL USE

Page 31

PM7346 S/UNI-QJET

(

)

DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3

S/UNI-QJET can be configured as a quad J2/E3/T3 framer for use in router, frame relay switch and multiplexer applications (as shown in Figure 2). In an unchannelized J2/E3/T3 line card, S/UNI-QJET interfaces directly to one or more PM7366 FREEDM-8 HDLC controllers. Each FREEDM-8 can process two highspeed links, such as T3 and E3, or it can process up to eight lower speed links such as J2. The S/UNI-QJET can gap all the overhead bits such that only the payload data is passed to and from FREEDM-8. On the line side, S/UNI-QJET is connected to one or more J2/E3/T3 line interface units. On the system side, S/UNI-QJET interfaces with a data link device over a serial bit interface.

In a PPP-Over-SONET application, the S/UNI-QJET interfaces to PM5342 SPECTRA-155 to map three T3 data streams onto three corresponding STS-1 services that are collectively carried over an OC-3 link.

Figure 2 - S/UNI-QJET, as a Quad Framer Device, in Frame Relay Equipment

8 Port Channelized T1 Card

PM4314

QDSX

4 Port Channelized E1 Card

PM4314

QDSX

28 Port Unchannelized T1 Card (M13

DS-3

LIU

PM4388

TOCTL

PM6344

PM4388

EQUAD

TOCTL

PM4388

TOCTL

PM8313

D3MX

PM7366

PM7345

PM7366

FREEDM-8

S/UNI-PDH

FREEDM-8

PM7366

PM7345

FREEDM-8

S/UNI-PDH

PM7364

PM7345

FREEDM-32

S/UNI-PDH

IP S wit ch /R o u te r C o re

Switch Fabric

PCI Bus

Processor

Packet

Memor

PCI Bus

Unchannelized

J2/E3/T3 Card

PM7366

FREEDM-8

PM7366

FREEDM-8

PM7366

FREEDM-8

S/UNI-QJET

Packet Over SONET Card

3 DS-3s Over OC-3

S/UNI-QJET

SPECTRA-155

PM7346

PM5355

S/UNI-622

PM7346

PM5342

UPLINK SIDEACCESS SIDE

J2/E3/T 3

LIU

J2/E3/T 3

LIU

J2/E3/T 3

LIU

J2/E3/T 3

LIU

Optics

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PM7346 S/UNI-QJET

DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3

The S/UNI-QJET can be configured as a cell processor to provide cell mapping functions for xDSL modems in an ATM based Digital Subscriber Loop Access Multiplexer (DSLAM) equipment. As shown in Figure 3, each S/UNI-QJET provides four cell processors. Two S/UNI-QJETs are required in an 8 port xDSL line card.

Figure 3 - S/UNI-QJET, as a Cell Processor, in DSLAM Equipment

ACCESS SIDE

8 Port xDSL C ard

xDSL M o dem

PM7346

PM5355

S/UNI-QJET

S/UNI-622

PM7346

PM5355

S/UNI-QJET

S/UNI-622

UTOP IA Bu s

ATM Switch Co re

Switch

Fabric

PM7322

RCMP-800

Egress Device

UPLINK SIDE

OC-3 Line Ca rds

PM5346

PM5355

S/UNI-LITE

S/UNI-622

PM7348

S/UNI-DUAL

UTOP IA Bu s

PM5347

S/UNI-PLUS

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PM7346 S/UNI-QJET

DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3

BLOCK DIAGRAM

Figure 4 - Normal Operating Mode

TPOS/TDATO[4:1]

TNEG/TOHM[4:1]`

TCLK[4:1]

RCLK[4:1]

RPOS/RDATI[4:1]

RNEG/RLCV/ROHM[4:1]

XBOC

FEAC

Line

Encode

Line

Decode

RBOC

FEAC

]

TOHINS[4:1

TDPR

Access

HDLC

TRAN

J2, E3 , o r DS3

Transmit

Framer

FRMR

J2, E3 , o r DS3

Receive

Framer

RDLC

PMON

HDLC

Monitor

O/H

Perf.

[4:1]

TCELL

APCLK/

FPO/TG

]

TMF PI[4:1]

]

TOH[4:1]

TOHFP[4:1]

TOHCLK[4:1

1/2 TTB

Tx Trail

Buffer

Transmit ATM

1/2 TTB

O/H

Rx Trail

Access

Buffer

TI[4:1

H/TDA

TPOHCLK[4:

TPOHINS[4:

TIOHM/TFPI/

TPO

TICLK[4:

SPLT

and PLCP

Framer

ATMF/SPLR

Receive

ATM and PLCP

Framer

PO/TM

HFP/TF TPO

REF8KI

BER Tester

PRGD

CPPM

PLCP/cell

Perf. M o n ito r

IEEE P1149.1

TXCP_50

Cell

Processor

RXCP_50

Cell

Processor

TDO

TDI

TCK

JTAG T est

Access Port

Microprocessor

TMS

I/F

TRSTB

TXFF

Tx 4 Cell FIFO

RXFF

4 Cell

FIFO

System

I/F

DTC A [4:1]

TDAT[15:0]

TPRTY TSOC TCA TADR[4:0] TENB TFCLK

PHY_ADR[2:0] ATM8

RFCLK RENB RADR[4:0] RCA RSOC RPRTY RDAT[15:0] DRCA[4:1]

ROH[4:1]

ROHFP[4:1]

ROHCLK[4:1]

]

:1]

PO[4 :1 ]

STAT[4

APC L K[4:1]

FRM

LCD/RDATO[4:1

RPOH/ROVRHD[4:1]]

RPOHCLK/RSCLK/RG

REF8KO/RPOHFP/RFPO/RMF

D[7:0]

A[10:0]

ALE

RDB

CSB

INTB

WRB

RSTB

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PM7346 S/UNI-QJET

DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3

Figure 5 - DS3/E3/J2 Framers Bypassed

TPOHINS[4:

]

HM [4 :1

TPOHCLK[4:

TIO

TPOH[4 :1

TPOHF P [4 :1

REF8KI

TICLK[4:

TDO

TCK

TDI

TRSTB

TMS

TDATO[4:1]

TOHM[4:1]`

TCLK[4 :1]

RCLK[4:1]

RDATI[4 :1]

ROHM[4:1]

XBOC

FEAC

Line

Encode

Line

Decode

RBOC

FEAC

TDPR

Access

HDLC

TRAN

J2, E 3 , o r DS 3

Transmit

Framer

FRMR

J2, E 3 , o r DS 3

Receive

Framer

RDLC

PMON

Perf.

HDLC

Monitor

O/H

1/2 TTB

Tx Trail

Buffer

SPLT

Transmit ATM

and PLCP

Framer

O/H

Access

1/2 TTB

Rx Trail

Buffer

ATMF/SPLR

Receive

ATM and PLCP

Framer

LCD[4:1]

RPOH[4:1]

RPOHF P [4 :1 ]

CPPM

PLCP/cell

Perf. M o n ito r

:1]

STAT[4

FRM

RPOHCLK[4:1]

BER Teste r

PRGD

IEEE P1 14 9 .1

TXCP_50

Cell

Processor

RXCP_50

Cell

Processor

JTAG Test

Access Port

Microprocessor

ALE

D[7:0]

A[10:0]

TXFF

Tx 4 Cell FIFO

RXFF

4 Cell

FIFO

I/F

CSB

WRB

System

I/F

RDB

INTB

RSTB

DTC A [4:1 ] TDAT[15:0] TPRTY TSOC TCA TADR[4:0] TENB TFCLK

PHY_ADR[2:0] ATM8

RFCLK RENB RADR[4:0] RCA

RSOC RPRTY RDAT[15:0] DRCA[4:1]

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PM7346 S/UNI-QJET

DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3

Figure 6 - DS3/E3/J2 Transceiver Mode

4:1]

CELL[

PCLK/T

]

TOH[4:1]

TOHFP[4:1]

TOHINS[4:1

TO H CL K [4 :1

:1]

TDATI[4

O/TGA

[4:1]

O/TMFP TFP

TFP I/T M F P I

TICLK[4:

TDO

TCK

TDI

TMS

TRSTB

TPOS/TDATO [4:1] TNEG/TOHM[4:1]`

TCLK[4:1]

RCLK[4:1]

RPOS/RDATI[4:1]

RNEG/RLCV[4:1]

XBOC

FEAC

Line

Encode

Line

Decode

RBOC

FEAC

TDPR

Access

HDLC

TRAN

J2, E3 , or D S3

Transmit

Framer

FRMR

J2, E3 , or D S3

Receive

Framer

RDLC

PMON

Perf.

HDLC

Monitor

O/H

1/2 TTB

Tx Trail

Buffer

O/H

Access

ROH[4:1]

RO HC L K [4 :1 ]

1/2 TTB

Rx Trail

Buffer

ROHFP[4:1]

SPLT

Transmit ATM

and PLCP

Framer

ATMF/SPLR

Receive

ATM and PLCP

Framer

[4:1]

RDATO[4:1]

RO VRHD [4:1 ]

O/RMFPO

KO/RFP

REF8

CPPM

PLCP/cell

Perf. M on itor

:1]

[4:1]

STAT[4 FRM

RSCLK/RGAPCLK

BER Tester

PRGD

IEEE P1149.1

TXCP_50

Cell

Processor

RXCP_50

Cell

Processor

JTAG T est

Access Port

Microprocessor

ALE

D[7:0]

A[10:0]

TXFF

4 Cell

FIFO

RXFF

4 Cell

FIFO

I/F

RDB

CSB

WRB

RSTB

System

I/F

INTB

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Page 36

PM7346 S/UNI-QJET

DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3

Figure 7 - Loopback Modes

[4:1]

TCELL

APCLK/

FPO/TG

]

TMF PI[4:1]

TI[4:1

H/TDA

TPOHCLK[4:

TPOHINS[4:

TIOHM/TFPI/

TPO

TICLK[4:

SPLT

Timing

and PLCP

Framer

ATMF/SPLR

Receive

ATM and PLCP

Framer

]

PO[4 :1 ]

APC L K[4:1]

LCD/RDATO[4:1

RPOH/ROVRHD[4:1]

PO/TM

HFP/TF TPO

REF8KI

BER Tester

PRGD

CPPM

PLCP/cell

Perf. M o n ito r

:1]

STAT[4 FRM

IEEE P1149.1

TXCP_50

Cell

Processor

RXCP_50

Cell

Processor

TDO

TDI

TCK

JTAG T est

Access Port

Microprocessor

ALE

D[7:0]

A[10:0]

TMS

I/F

CSB

TRSTB

TXFF

4 Cell

FIFO

RXFF

4 Cell

FIFO

WRB

RDB

DTC A [4:1]

TDAT[15:0]

TPRTY TSOC TCA TADR[4:0] TENB

System

I/F

INTB

RSTB

TFCLK PHY_ADR[2:0]

ATM8

RFCLK RENB RADR[4:0] RCA RSOC RPRTY RDAT[15:0] DRCA[4:1]

Line

TPOS/TDATO[4:1] TNEG/TOH M[4:1]`

TCLK[4:1 ]

RCLK[4:1]

RPOS/RDA TI[4:1]

RNEG/RLCV/ROHM[4:1]

Diagnostic

XBOC

FEAC

Line

Encode

Line

Decode

RBOC

FEAC

]

TOHINS[4:1

TDPR

Access

HDLC

TRAN

J2, E3 , o r DS3

Transmit

Framer

FRMR

J2, E3 , o r DS3

Receive

Framer

RDLC

PMON

HDLC

Monitor

O/H

Perf.

TOH[4:1]

]

TOHFP[4:1]

TOHCLK[4:1

Payload

Access

1/2 TTB

Tx Trail

Buffer

O/H

ROH[4:1]

ROHCLK[4:1]

1/2 TTB

Rx Trail

Buffer

ROHFP[4:1]

Transmit ATM

RPOHCLK/RSCLK/RG

REF8KO/RPOHFP/RFPO/RMF

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Page 37

PM7346 S/UNI-QJET

DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3

DESCRIPTION

The PM7346 S/UNI-QJET is a quad ATM physical layer processor with integrated DS3, E3, and J2 framers. PLCP sublayer DS1, DS3, E1, and E3 processing is supported as is ATM cell delineation.

The S/UNI-QJET contains integral DS3 framers, which provide DS3 framing and error accumulation in accordance with ANSI T1.107, and T1.107a, integral E3 framers, which provide E3 framing in accordance with ITU-T Recommendations G.832 and G.751, and integral J2 framers, which provide J2 framing in accordance with ITU-T Recommendation G.704 and I.432.

When configured for DS3 transmission system sublayer processing, the S/UNI-QJET accepts and outputs both digital B3ZS-encoded bipolar and unipolar signals compatible with M23 and C-bit parity applications.

When configured for E3 transmission system sublayer processing, the S/UNI-QJET accepts and outputs both HDB3-encoded bipolar and unipolar signals compatible with G.751 and G.832 applications.

When configured for J2 transmission system sublayer processing, the S/UNI-QJET accepts and outputs both B8ZS-encoded bipolar and unipolar signals compliant with G.704 and NTT 6.312 Mbit/s applications.

When configured for DS1, or E1 transmission system sublayer processing, the S/UNI-QJET accepts and outputs unipolar signals with appropriate clock and frame pulse signals for physical sublayer processing. When configured for other transmission systems, the S/UNI-QJET provides a generic interface for physical sublayer processing.

In the DS3 receive direction, the S/UNI-QJET frames to DS3 signals with a maximum average reframe time of 1.5 ms and detects line code violations, loss of signal, framing bit errors, parity errors, path parity errors, AIS, far end receive failure and idle code. The DS3 overhead bits are extracted and presented on serial outputs. When in C-bit parity mode, the Path Maintenance Data Link and the Far End Alarm and Control (FEAC) channels are extracted. HDLC receivers are provided for Path Maintenance Data Link support. In addition, valid bitoriented codes in the FEAC channels are detected and are available through the microprocessor port.

In the E3 receive direction, the S/UNI-QJET frames to G.751 and G.832 E3 signals with a maximum average reframe times of 135µs for G.751 frames and 250µs for G.832 frames. Line code violations, loss of signal, framing bit errors,

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AIS, and remote alarm indication are detected. Further, when processing G.832 formatted data, parity errors, far end receive failure, and far end block errors are also detected; and the Trail Trace message may be extracted and made available through the microprocessor port. HDLC receivers are provided for either the G.832 Network Requirement or the G.832 General Purpose Data Link support.

In the J2 receive direction, the S/UNI-QJET frames to G.704 6.312 MHz signals with a maximum average reframe time of 5.07ms. An alternate framing algorithm which uses the CRC-5 bits to rule out 99.9% of all static mimic framing patterns is available with a maximum average reframe time of 10.22ms when operating

with a 10-4 bit error rate. The alternate framing algorithm can be selected via the CRC_REFR bit in the J2-FRMR Configuration Register. Line code violations, loss of signal, loss of frame, framing bit errors, physical layer AIS, payload AIS, CRC-5 errors, Remote End Alarm, and Remote Alarm Indication are detected. HDLC receivers are provided for Data Link support.

Error event accumulation is also provided by the S/UNI-QJET. Framing bit errors, line code violations, parity errors, path parity errors and far end block errors are accumulated, when appropriate, in saturating counters for DS3, E3, and J2 frames. Loss of Frame detection for DS3, E3, and J2 is provided as recommended by ITU-T G.783 with integration times of 1ms, 2ms, and 3ms.

In the DS3 transmit direction, the S/UNI-QJET inserts DS3 framing, X and P bits. When enabled for C-bit parity operation, bit-oriented code transmitters and HDLC transmitters are provided for insertion of the FEAC channels and the Path Maintenance Data Links into the appropriate overhead bits. Alarm Indication Signals can be inserted by using internal register bits; other status signals such as the idle signal can be inserted when enabled by internal register bits. When M23 operation is selected, the C-bit Parity ID bit (the first C-bit of the first M subframe) is forced to toggle so that downstream equipment will not confuse an M23-formatted stream with stuck-at 1 C-bits for C-bit Parity application.

In the E3 transmit direction, the S/UNI-QJET inserts E3 framing in either G.832 or G.751 format. When enabled for G.832 operation, an HDLC transmitter is provided for insertion of either the Network Requirement or General Purpose Data Link into the appropriate overhead bits. The Alarm Indication Signal and other status signals can be inserted by internal register bits.

In the J2 transmit direction, the S/UNI-QJET inserts J2 6.312 Mbit/s G.704 framing. HDLC transmitter are provided for insertion of the Data Links. CRC-5 check bits are calculated and inserted into the J2 multiframe. External pins are provided to enable overwriting of any of the overhead bits within the J2 frame.

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The S/UNI-QJET also supports diagnostic options which allow it to insert, when appropriate for the transmit framing format, parity or path parity errors, F-bit framing errors, M-bit framing errors, invalid X or P-bits, line code violations, all-zeros, AIS, Remote Alarm Indications, and Remote End Alarms.

The S/UNI-QJET provides cell delineation for ATM cells using the PLCP framing format, or by using the header check sequence octet in the ATM cell header as specified by ITU-T Recommendation I.432. DS1, DS3, E1 and E3 based PLCP frame formats can be processed. Non-PLCP-based cell delineation is accomplished with either bit, nibble, or byte-wide search algorithms, depending on the line interface used. An interface consistent with the generic physical interface defined by ITU-T Recommendation I.432 is provided for arbitrary rates up to 52 Mbit/s. This interface is used to provide physical layer support for transmission systems that do not have an associated PLCP sublayer, or to provide an efficient means of directly mapping ATM cells to existing transmission system formats (such as DS3 and DS1).

In the PLCP receive direction, framing, path overhead extraction and cell extraction is provided. BIP-8 error events, frame octet error events and far end block error events are accumulated.

In the PLCP transmit direction, the S/UNI-QJET provides overhead insertion using inputs or internal registers, DS3 nibble and E3 byte stuffing, automatic BIP8 octet generation and insertion and automatic far end block error insertion. Diagnostic features for BIP-8 error, framing error and far end block error insertion are also supported.

In the cell receive path, idle cells may be dropped according to a programmable filter. By default, incoming cells with single bit HCS errors are corrected and written to the FIFO buffer. Optionally, cells can be dropped upon detection of a HCS error. Cell delineation may optionally be disabled to allow passing of all cells, regardless of cell delineation status. The ATM cell payloads are optionally descrambled. ATM cell headers may optionally be descrambled (for use with PPP packets). Assigned cells containing no detectable HCS errors are written to a FIFO buffer. Cells data is read from the FIFO using a synchronous 50 MHz 8-

bit wide or 16-bit wide SCI-PHYTM and Utopia Level 2 compatible interface. Cell data parity is also provided. Counts of error-free assigned cells, and cells containing HCS errors are accumulated independently for performance monitoring purposes.

In the cell transmit path, cell data is written to a FIFO buffer using a synchronous 50 MHz 8-bit wide or 16-bit wide SCI-PHYTM compatible interface. Cell d ata

parity is also examined for errors. Idle cells are automatically inserted when the FIFO contains less than one full cell. HCS generation, cell payload scrambling,

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and cell header scrambling (for use with PPP packets) are optionally provided. Counts of transmitted cells are accumulated for performance monitoring purposes.

Both receive and transmit cell FIFOs provide buffering for four cells. The FIFOs provide the rate matching interface between the higher layer ATM entity and the S/UNI-QJET.

The S/UNI-QJET is configured, controlled and monitored via a generic 8-bit microprocessor bus through which all internal registers are accessed. All sources of interrupts can be identified, acknowledged, or masked via this interface.

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PIN DIAGRAM

The S/UNI-QJET is packaged in a 256-pin SBGA package having a body size of 27mm by 27mm and a pin pitch of 1.27 mm.

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PIN DESCRIPTION

Pin Name Type Pin No. Function

TPOS[4] TPOS[3] TPOS[2] TPOS[1]

Output C6

B4 D3 F2

Transmit Digital Positive Pulse (TPOS[4:1]). TPOS[4:1] contains the positive pulses transmitted on the B3ZSencoded DS3, HDB3-encoded E3, or B8ZS-encoded J2 transmission system when the dual-rail output format is

selected. TDATO[4] TDATO[3] TDATO[2] TDATO[1]

Transmit Data (TDATO[4:1]). TDATO[4:1]

contains the transmit data stream when

the single-rail (unipolar) output format is

enabled or when a non-DS3/E3/J2 based

transmission system is selected.

The TPOS/TDATO[4:1] pin function

selection is controlled by the TFRM[1:0]

and the TUNI bits in the S/UNI-QJET

Transmit Configuration Registers. Output

signal polarity control is provided by the

TPOSINV bit in the S/UNI-QJET Transmit

Configuration Registers. Both TPOS[4:1]

and TDATO[4:1] are updated on the falling

edge of TCLK[4:1] by default, and may be

configured to be updated on the rising

edge of TCLK[4:1] through the TCLKINV

bit in the S/UNI-QJET Transmit

Configuration Registers. Finally, both

TPOS[4:1] and TDATO[4:1] can be

updated on the rising edge of TICLK[4:1],

enabled by the TICLK bit in the

S/UNI-QJET Transmit Configuration

Registers. TNEG[4] TNEG[3] TNEG[2] TNEG[1]

Output A5

D5 E4 F1

Transmit Digital Negative Pulse

(TNEG[4:1]). TNEG[4:1] contains the

negative pulses transmitted on the B3ZS-

encoded DS3, HDB3-encoded E3, or

B8ZS-encoded J2 transmission system

when the dual-rail NRZ output format is

selected.

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Pin Name Type Pin No. Function

TOHM[4] TOHM[3] TOHM[2] TOHM[1]

Output A5

D5 E4 F1

Transmit Overhead Mask (TOHM[4:1]).

TOHM[4:1] indicates the position of

overhead bits (non-payload bits) in the

transmission system stream aligned with

TDATO[4:1]. TOHM[4:1] indicates the

location of the M-frame boundary for DS3,

the position of the frame boundary for E3,

and the position of the multi-frame

boundary for J2 when the single-rail

(unipolar) NRZ input format is enabled.

When a PLCP formatted signal is

transmitted, TOHM[4:1] is set to logic 1

once per transmission frame, and

indicates the DS1 or E1 frame alignment.

When a non-PLCP, non-DS3, non-E3, non-

J2 based signal is transmitted, TOHM[4:1]

is a delayed version of the TIOHM[4:1]

input, and indicates the position of each

overhead bit in the transmission frame.

TOHM[4:1] is updated on the falling edge

of TCLK[4:1].

The TNEG/TOHM[4:1] pin function

selection is controlled by the TFRM[1:0]

and the TUNI bits in the S/UNI-QJET

Transmit Configuration Registers. Output

signal polarity control is provided by the

TNEGINV bit in the S/UNI-QJET Transmit

Configuration Registers. Both TNEG[4:1]

and TOHM[4:1] are updated on the falling

edge of TCLK[4:1] by default, and may be

enabled to be updated on the rising edge

of TCLK[4:1]. This sampling is controlled

by the TCLKINV bit in the S/UNI-QJET

Transmit Configuration Registers. Finally,

both TNEG[4:1] and TOHM[4:1] can be

updated on the rising edge of TICLK[4:1],

enabled by the TICLK bit in the

S/UNI-QJET Transmit Configuration

Registers.

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Pin Name Type Pin No. Function

TCLK[4] TCLK[3] TCLK[2] TCLK[1]

RPOS[4] RPOS[3] RPOS[2] RPOS[1]

RDATI[4] RDATI[3] RDATI[2] RDATI[1]

Output B5

C4 D2 G3

Input D6

D1 E2 H4

Transmit Output Clock (TCLK[4:1]).

TCLK[4:1] provides the transmit direction

timing. TCLK[4:1] is a buffered version of

TICLK[4:1] and can be enabled to update

the TPOS/TDATO[4:1] and

TNEG/TOHM[4:1] outputs on its rising or

falling edge.

Receive Digital Positive Pulse

(RPOS[4:1]). RPOS[4:1] contains the

positive pulses received on the B3ZS-

encoded DS3, the HDB3-encoded E3, or

the B8ZS-encoded J2 transmission

system when the dual-rail NRZ input

format is selected.

Receive Data (RDATI[4:1]). RDATI[4:1]

contains the data stream when the single-

rail (unipolar) NRZ input format is enabled

or when a non-DS3/E3/J2 based

transmission system is being processed

(for example RDATI may contain a DS1 or

E1 stream).

The RPOS/RDATI[4:1] pin function

selection is controlled by the RFRM[1:0]

bits in the S/UNI-QJET Configuration

Registers and by the UNI bits in the DS3

FRMR, the E3 FRMR, or the J2 FRMR

Configuration Registers. Both RPOS[4:1]

and RDATI[4:1] are sampled on the rising

edge of RCLK[4:1] by default, and may be

enabled to be sampled on the falling edge

of RCLK[4:1]. This sampling is controlled

by the RCLKINV bit in the S/UNI-QJET

Receive Configuration Registers. In

addition, signal polarity control is provided

by the RPOSINV bit in the S/UNI-QJET

Receive Configuration Registers.

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Pin Name Type Pin No. Function

RNEG[4] RNEG[3] RNEG[2] RNEG[1]

RLCV[4] RLCV[3] RLCV[2] RLCV[1]

Input C5

E3 E1 G2

Receive Digital Negative Pulse

(RNEG[4:1]). RNEG[4:1] contains the

negative pulses received on the B3ZS

encoded DS3, the HDB3-encoded E3, or

the B8ZS-encoded J2 transmission

system when the dual-rail NRZ input

format is selected.

Receive Line Code Violation (RLCV[4:1]).

RLCV[4:1] contains line code violation

indications when the single-rail (unipolar)

NRZ input format is enabled for DS3, E3,

or J2 applications. Each line code

violation is represented by an RCLK[4:1]

period-wide pulse.

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Pin Name Type Pin No. Function

ROHM[4] ROHM[3] ROHM[2] ROHM[1]

Input C5

E3 E1 G2

Receive Overhead Mask (ROHM[4:1]).

When a DS1 or E1 PLCP or ATM direct-

mapped signal is received, ROHM[4:1] is

pulsed once per transmission frame, and

indicates the DS1 or E1 frame alignment

relative to the RDATI[4:1] data stream.

When an alternate frame-based signal is

received, ROHM[4:1] indicates the position

of each overhead bit in the transmission

frame.

The RNEG/RLCV/ROHM[4:1] pin function

selection is controlled by the RFRM[1:0]

bits in the S/UNI-QJET Receive

Configuration Registers, the UNI bits in the

DS3 FRMR, E3 FRMR, or J2 FRMR

Configuration Registers, and the PLCPEN

and EXT bits in the SPLR Configuration

ROHM[4:1] are sampled on the rising

edge of RCLK[4:1] by default, and may be

enabled to be sampled on the falling edge

of RCLK[4:1]. This sampling is controlled

by the RCLKINV bit in the S/UNI-QJET

Receive Configuration Registers. In

addition, signal polarity control is provided

by the RNEGINV bit in the S/UNI-QJET

Receive Configuration Registers. RCLK[4] RCLK[3] RCLK[2] RCLK[1]

Input A4

F4 F3 G1

Receive Clock (RCLK[4:1]). RCLK[4:1]

provides the receive direction timing.

RCLK[4:1] is the externally recovered

transmission system baud rate clock that

samples the RPOS/RDATI[4:1] and

RNEG/RLCV/ROHM[4:1] inputs on its

rising or falling edge.

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Pin Name Type Pin No. Function

TOHINS[4] TOHINS[3] TOHINS[2] TOHINS[1]

Input J4

K2 M4 R1

Transmit DS3/E3/J2 Overhead Insertion

(TOHINS[4:1]). TOHINS[4:1] controls the

insertion of the DS3, E3, or J2 overhead

bits from the TOH[4:1] input. When

TOHINS[4:1] is high, the associated

overhead bit in the TOH[4:1] stream is

inserted in the transmitted DS3, E3, or J2

frame. When TOHINS[4:1] is low, the DS3,

E3, or J2 overhead bit is generated and

insert ed internally. TOHINS[4:1] is

sampled on the rising edge of

TOHCLK[4:1]. If TOHINS[4:1] is a logic 1,

the TOH[4:1] input has precedence over

the internal datalink transmitter, or any

internal register bit setting.

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Pin Name Type Pin No. Function

TOH[4] TOH[3] TOH[2] TOH[1]

Input H3

K3 N1 P3

Transmit DS3/E3/J2 Overhead Data

(TOH[4:1]). When configured for DS3

operation, TOH[4:1] contains the overhead

bits (C, F, X, P, and M) that may be

inserted in the transmit DS3 stream.

When configured for G.832 E3 operation,

TOH[4:1] contains the overhead bytes

(FA1, FA2, EM mask, TR, MA, NR, and

GC) that may be inserted in the transmit

G.832 E3 stream.

When configured for G.751 E3 operation,

TOH[4:1] contains the overhead bits (RAI,

National Use, Stuff Indication, and Stuff

Opportunity) that may be inserted in the

transmit G.751 E3 stream.

When configured for J2 operation,

TOH[4:1] contains the overhead bits

(TS97, TS98, Framing, X

, A, M, E

1-3

1-5

)

that may be inserted in the transmit J2

stream.

If TOHINS[4:1] is a logic 1, the TOH[4:1]

input has precedence over the internal

datalink transmitter, or any other internal

on the rising edge of TOHCLK[4:1].

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Pin Name Type Pin No. Function

TOHFP[4] TOHFP[3] TOHFP[2] TOHFP[1]

TOHCLK[4] TOHCLK[3] TOHCLK[2] TOHCLK[1]

Output J3

L3 N3 R3

Output H2

K1 N2 R2

Transmit DS3/E3/J2 Overhead Frame

Position (TOHFP[4:1]). TOHFP[4:1] is

used to align the individual overhead bits

in the transmit overhead data stream,

TOH[4:1], to the DS3 M-frame or the E3

frame. For DS3, TOHFP[4:1] is high

during the X1 overhead bit position in the

TOH[4:1] stream. For G.832 E3,

TOHFP[4:1] is high during the first bit of

the FA1 byte. For G.751 E3, TOHFP[4:1]

is high during the RAI overhead bit

position in the TOH[4:1] stream. For J2,

TOHFP[4:1] is high during the first bit of

timeslot 97 in the first frame of a 4-frame

multiframe). TOHFP[4:1] is updated on the

falling edge of TOHCLK[4:1].

Transmit DS3/E3/J2 Overhead Clock

(TOHCLK[4:1]). TOHCLK[4:1] is active

when a DS3, E3, or J2 stream is being

processed. TOHCLK[4:1] is nominally a

526 kHz clock for DS3, a 1.072 MHz clock

for G.832 E3, a 1.074 MHz clock for G.751

E3, and a gapped 6.312 MHz clock with

an average frequency of 168 kHz for J2.

TOHFP[4:1] is updated on the falling edge

of TOHCLK[4:1]. TOH[4:1], and

TOHINS[4:1] are sampled on the rising

edge of TOHCLK[4:1].

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Pin Name Type Pin No. Function

REF8KI Input T3 Reference 8 kHz Input (REF8KI). The

PLCP frame rate is locked to an external 8

kHz reference applied on this input . An

internal phase-frequency detector

compares the transmit PLCP frame rate

with the externally applied 8 kHz reference

and adjusts the PLCP frame rate.

The REF8KI input must transition high

once every 125 µs for correct operation.

The REF8KI input is treated as an

asynchronous signal and must be “glitch-

free”. If the LOOPT register bit is logic 1,

the PLCP frame rate is locked to the

RPOHFP[x] signal instead of the REF8KI

input. TPOHINS[4] TPOHINS[3] TPOHINS[2] TPOHINS[1]

Input V14

W11 U9 W5

Transmit Path Overhead Insertion

(TPOHINS[4:1]). TPOHINS[4:1] controls

the insertion of PLCP overhead octets on

the TPOH[4:1] input. When TPOHINS[4:1]

is logic 1, the associated overhead bit in

the TPOH[4:1] stream is inserted in the

transmit PLCP frame. When

TPOHINS[4:1] is logic 0, the PLCP path

overhead bit is generated and inserted

internally. TPOHINS[4:1] is sampled on

the rising edge of TPOHCLK[4:1].

Note, when operating in G.751 E3 PLCP

mode, bits 8, 7 and 6 of the C1 octet

should not be manipulated.

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Pin Name Type Pin No. Function

TPOH[4] TPOH[3] TPOH[2] TPOH[1]

TDATI[4] TDATI[3] TDATI[2] TDATI[1]

Input Y15

W12 W8 Y5

Transmit PLCP Overhead Data

(TPOH[4:1]). TPOH[4:1] is valid when the

FRMRONLY bit in the S/UNI-QJET

Configuration 1 registers is logic 0.

TPOH[4:1] contains the PLCP path

overhead octets (Zn, F1, B1, G1, M1, M2,

and C1) which may be inserted in the

transmit PLCP frame. The octet data on

TPOH[4:1] is shifted in order from the

most significant bit (bit 1) to the least

significant bit (bit 8). TPOH[4:1] is

sampled on the rising edge of

TPOHCLK[4:1].

Framer Transmit Data (TDATI[4:1]).

TDATI[4:1] contains the serial data to be

transmitted when the S/UNI-QJET is

configured as a DS3, E3, or J2 framer

device for non-ATM applications by setting

the FRMRONLY bit in the S/UNI-QJET

Configuration 1 Register. TDATI[4:1] is

sampled on the rising edge of TICLK[4:1] if

the TXGAPEN register bit in the

S/UNI-QJET Configuration 2 register is

logic 0. If TXGAPEN is logic 1, then

TDATI[4:1] is sampled on the falling edge

of TGAPCLK[4:1]. TPOHFP[4] TPOHFP[3] TPOHFP[2] TPOHFP[1]

Output W 14

Y10 Y7 V5

Transmit Path Overhead Frame Position

(TPOHFP[4:1]). TPOHFP[4:1] is valid

when the FRMRONLY bit in the

S/UNI-QJET Configuration 1 Registers is

logic 0. The TPOHFP[4:1] output locates

the individual PLCP path overhead bits in

the transmit overhead data stream,

TPOH[4:1]. TPOHFP[4:1] is logic 1 while

bit 1 (the most significant bit) of the path

user channel octet (F1) is present in the

TPOH[4:1] stream. TPOHFP[4:1] is

updated on the falling edge of

TPOHCLK[4:1].

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Pin Name Type Pin No. Function

TFPO[4] TFPO[3] TFPO[2] TFPO[1]

TMFPO[4] TMFPO[3] TMFPO[2] TMFPO[1]

Output W14

Y10 Y7 V5

Framer Transmit Frame Pulse/Multi-frame

Pulse Reference (TFPO/TMFPO[4:1]).

TFPO/TMFPO[4:1] is valid when the

S/UNI-QJET is configured as a DS3, E3,

or J2 framer for non-ATM applications by

setting the FRMRONLY bit in the

S/UNI-QJET Configuration 1 Registers to

logic 1 and the TXGAPEN bit in the

S/UNI-QJET Configuration Registers to

logic 0.

TFPO[4:1] pulses high for 1 out of every

85 clock cycles when configured for DS3,

giving a free-running mark for all overhead

bits in the frame. TFPO[4:1] pulses high

for 1 out of every 1536 clock cycles when

configured for G.751 E3, giving a free-

running reference G.751 indication.

TFPO[4:1] pulses high for 1 out of every

4296 clock cycles when configured for

G.832 E3, giving a free-running reference

G.832 frame indication. TFPO[4:1] pulses

high for 1 out of every 789 clock cycles

when configured for J2, giving a free-

running reference frame indication.

TMFPO[4:1] pulses high for 1 out of every

4760 clock cycles when configured for

DS3, giving a free-running reference M-

frame indication. TMFPO[4:1] pulses high

for 1 out of every 3156 clock cycles when

configured for J2, giving a free-running

reference multi-frame indication.

TMFPO[4:1] behaves the same as

TFPO[4:1] for E3 applications.

TFPO/TMFPO[4:1] is updated on the

rising edge of TICLK[4:1] or RCLK[4:1] if

loop-timed.

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PM7346 S/UNI-QJET

DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3

Pin Name Type Pin No. Function

TGAPCLK[4] TGAPCLK[3] TGAPCLK[2] TGAPCLK[1]

TCELL[4] TCELL[3] TCELL[2] TCELL[1]

Output W14

Y10 Y7 V5

Framer Gapped Transmit Clock

(TGAPCLK[4:1]). TGAPCLK[4:1] is valid

when the S/UNI-QJET is configured as a

DS3, E3, or J2 framer for non-ATM

applications by setting the FRMRONLY bit

in the S/UNI-QJET Configuration 1

Registers and the TXGAPEN bit in the

S/UNI-QJET Configuration 2 Registers.

TGAPCLK[4:1] is derived from the transmit

reference clock TICLK[4:1] or from the

receive clock if loop-timed. The overhead

bit (gapped) positions are generated

internal to the device. TGAPCLK[4:1] is

held high during the overhead bit

positions. This clock is useful for

interfacing to devices which source

payload data only. TGAPCLK[4:1] is used

to sample TDATI[4:1].

Transmit Cell Indication (TCELL[4:1]).

TCELL[x] is valid when the TCELL bit in

the S/UNI-QJET Misc. register (09BH,

19BH, 29BH, 39BH) is set. TCELL[x]

pulses once for every cell (idle or

assigned) transmitted. TCELL[x] is

updated using timing derived from the

transmit input clock (TICLK[x]), and is

active for a minimum of 8 TICLK[x] periods

(or 8 RCLK[x] periods if loop-timed).

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PM7346 S/UNI-QJET

DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3

Pin Name Type Pin No. Function

TPOHCLK[4] TPOHCLK[3] TPOHCLK[2] TPOHCLK[1]

TIOHM[4] TIOHM[3] TIOHM[2] TIOHM[1]

Output U13

V11 V8 U6

Input W15

V12 V9 V6

Transmit PLCP Overhead Clock

(TPOHCLK[4:1]). TPOHCLK[4:1] is active

when PLCP processing is enabled.

TPOHCLK[4:1] is nominally a 26.7 kHz

clock for a DS1 PLCP frame, a 768 kHz

clock for a DS3 PLCP frame, a 33.7 kHz

clock for an E1 based PLCP frame, and a

576 kHz clock for an G.751 E3 based

PLCP frame. TPOHFP[4:1] is updated on

the falling edge of TPOHCLK[4:1].

TPOH[4:1], and TPOHINS[4:1] are

sampled on the rising edge of

TPOHCLK[4:1].

Transmit Input Overhead Mask

(TIOHM[4:1]). TIOHM[4:1] is valid only if

the FRMRONLY bit in the S/UNI-QJET

Configuration 1 register is logic 0.

TIOHM[4:1] indicates the position of

overhead bits when not configured for

DS1, DS3, E1, E3, or J2 transmission

system streams. TIOHM[4:1] is delayed

internally to produce the TOHM[4:1]

output. When configured for operation

over a DS1, a DS3, an E1, an E3, or a J2

transmission system sublayer, TIOHM[4:1]

is not required, and should be set to logic

0. When configured for other transmission

systems, TIOHM[4:1] is set to logic 1 for

each overhead bit position. TIOHM[4:1] is

set to logic 0 if the transmission system

contains no overhead bits. TIOHM[4:1] is

sampled on the rising edge of TICLK[4:1].

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PM7346 S/UNI-QJET

DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3

Pin Name Type Pin No. Function

TFPI[4] TFPI[3] TFPI[2] TFPI[1]

TMFPI[4] TMFPI[3] TMFPI[2] TMFPI[1]

Input W15

V12 V9 V6

Framer Transmit Frame Pulse/Multiframe

Pulse (TFPI/TMFPI[4:1]). TFPI/TMFPI[4:1]

is valid when the S/UNI-QJET is

configured as a DS3, E3, or J2 framer for

non-ATM applications by setting the

FRMRONLY bit in the S/UNI-QJET

Configuration 1 Register to logic 1.

TFPI[4:1] indicates the position of all

overhead bits in each DS3 M-subframe,

the first bit in each G.751 E3 or G.832 E3

frame, or the first framing bit in each J2

frame. TFPI[4:1] is not required to pulse at

every frame boundary in E3 or J2 modes.

TMFPI[4:1] indicates the position of the

first bit in each DS3 M-frame, the first bit in

each E3 frame, or the first framing bit in

each J2 multiframe. TMFPI[4:1] is not

required to pulse at every multiframe

boundary.

TFPI/TMFPI[4:1] is sampled on the rising

edge of TICLK[4:1]. TICLK[4] TICLK[3] TICLK[2] TICLK[1]

Input V15

Y13 W9 W6

Transmit Input Clock (TICLK[4:1]).

TICLK[4:1] provides the transmit direction

timing. TICLK[4:1] is the externally

generated transmission system baud rate

clock. It is internally buffered to produce

the transmit clock output, TCLK[4:1], and

can be enabled to update the

TPOS/TDATO[4:1] and TNEG/TOHM[4:1]

outputs on the TICLK[4:1] rising edge. The

TICLK[4:1] maximum frequency is 52

MHz.

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PM7346 S/UNI-QJET

DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3

Pin Name Type Pin No. Function

ROHFP[4] ROHFP[3] ROHFP[2] ROHFP[1]

ROH[4] ROH[3] ROH[2] ROH[1]

Output J1

M2 P2 T2

Output J2

L2 P1 T1

Receive DS3/E3/J2 Overhead Frame

Position (ROHFP[4:1]). ROHFP[4:1]

locates the individual overhead bits in the

received overhead data stream, ROH[4:1].

ROHFP[4:1] is high during the X1

overhead bit position in the ROH[4:1]

stream when processing a DS3 stream.

ROHFP[4:1] is high during the first bit of

the FA1 byte when processing a G.832 E3

stream. ROHFP[4:1] is high during the

RAI overhead bit position when processing

a G.751 E3 stream. ROHFP[4:1] is high

during the first bit in Timeslot 97 in the first

frame of the 4-frame multiframe when

processing a J2 stream. ROHFP[4:1] is

updated on the falling edge of

ROHCLK[4:1].

Receive DS3/E3/J2 Overhead Data

(ROH[4:1]). ROH[4:1] contains the

overhead bits (C, F, X, P, and M) extracted

from the received DS3 stream; ROH[4:1]

contains the overhead bytes (FA1, FA2,

EM, TR, MA, NR, and GC) extracted from

the received G.832 E3 stream; ROH[4:1]

contains the overhead bits (RAI, National

Use, Stuff Indication, and Stuff

Opportunity) extracted from the received

G.751 E3 stream; ROH[4:1] contains the

overhead bits (Framing, X

, A, M, E

1-3

1-5

)

extracted from the received J2 stream.

ROH[4:1] is updated on the falling edge of

ROHCLK[4:1].

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PM7346 S/UNI-QJET

DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3

Pin Name Type Pin No. Function

ROHCLK[4] ROHCLK[3] ROHCLK[2] ROHCLK[1]

REF8KO[4] REF8KO[3] REF8KO[2] REF8KO[1]

Output K4

M3 N4 R4

Output U12

Y9 Y6 V4

Receive DS3/E3/J2 Overhead Clock

(ROHCLK[4:1]). ROHCLK[4:1] is active

when a DS3, E3, or J2 stream is being

processed. ROHCLK[4:1] is nominally a

526 kHz clock when processing DS3, a

1.072 MHz clock when processing G.832

E3, a 1.074 MHz clock when processing

G.751 E3, and a gapped 6.312 MHz clock

with an average frequency of 168 kHz for

J2. ROH[4:1], and ROHFP[4:1] are

updated on the falling edge of

ROHCLK[4:1].

Reference 8kHz Output (REF8KO[4:1]).

REF8KO[4:1] is an 8kHz reference derived

from the receive clocks on RCLK[4:1]. A

free-running divide-down counter is used

to generate REF8KO[4:1] so it will not

glitch on reframe actions. REF8KO[4:1]

will pulse high for approximately 1

RCLK[4:1] cycle every 125 µs.

REF8KO[4:1] should be treated as a

glitch-free asynchronous signal. RPOHFP[4] RPOHFP[3] RPOHFP[2] RPOHFP[1]

Receive PLCP Overhead Frame Position

(RPOHFP[4:1]). RPOHFP[4:1] locates the

individual PLCP path overhead bits in the

receive overhead data stream, RPOH[4:1].

RPOHFP[4:1] is logic 1 while bit 1 (the

most significant bit) of the path user

channel octet (F1) is present in the

RPOH[4:1] stream. RPOHFP[4:1] is

updated on the falling edge of

RPOHCLK[4:1]. RPOHFP[4:1] is available

when the PLCPEN register bit is logic 1 in

the SPLR Configuration Register.

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PM7346 S/UNI-QJET

DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3

Pin Name Type Pin No. Function

RFPO[4] RFPO[3] RFPO[2] RFPO[1]

RMFPO[4] RMFPO[3] RMFPO[2] RMFPO[1]

Output U12

Y9 Y6 V4

Framer Receive Frame Pulse/Multi-frame

Pulse (RFPO/RMFPO[4:1]).

RFPO/RMFPO[4:1] is valid when the

S/UNI-QJET is configured to be in framer

only mode. The 8KREFO bit must be set

to logic 0 S/UNI-QJET Configuration

RFPO[4:1] is aligned to RDATO[4:1] and

indicates the position of the first bit in each

DS3 M-subframe, the first bit in each

G.751 E3 or G.832 E3 frame, or the first

framing bit in each J2 frame

RMFPO[4:1] is aligned to RDATO[4:1] and

indicates the position of the first bit in each

DS3 M-frame, the first bit in each G.751 or

G.832 E3 multiframe, or the first framing

bit in each J2 multiframe.

RFPO/RMFPO[4:1] is updated on either

the falling or rising edge of RSCLK[4:1]

depending on the setting of the RSCLKR

bit in the S/UNI-QJET Receive

Configuration register. RPOH[4] RPOH[3] RPOH[2] RPOH[1]

Output V13

V10 U8 W4

Receive PLCP Overhead Data

(RPOH[4:1]). RPOH[4:1] contains the

PLCP path overhead octets (Zn, F1, B1,

G1, M1, M2, and C1) extracted from the

received PLCP frame when the PLCP

layer is in-frame. When the PLCP layer is

in the loss of frame state, RPOH[4:1] is

forced to all ones. The octet data on

RPOH[4:1] is shifted out in order from the

most significant bit (bit 1) to the least

significant bit (bit 8). RPOH[4:1] is

updated on the falling edge of

RPOHCLK[4:1].

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PM7346 S/UNI-QJET

DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3

Pin Name Type Pin No. Function

ROVRHD[4 ] ROVRHD[3 ] ROVRHD[2 ] ROVRHD[1 ]

RPOHCLK[4] RPOHCLK[3] RPOHCLK[2] RPOHCLK[1]

Output V13

V10 U8 W4

Output W13

U10 V7 U5

Framer Receive Overhead Indication

(ROVRHD[4:1]). ROVRHD[4:1] is valid

when the S/UNI-QJET is configured as a

DS3, E3, or J2 framer for non-ATM

applications by setting the FRMRONLY bit

in the S/UNI-QJET Configuration 1

Registers. ROVRHD[4:1] will be high

whenever the data on RDATO[4:1]

corresponds to an overhead bit position.

ROVRHD[4:1] is updated on the either the

falling or rising edge of RSCLK[4:1]

depending on the setting of the RSCLKR

bit in the S/UNI-QJET Receive

Configuration register.

Receive PLCP Overhead Clock

(RPOHCLK[4:1]). RPOHCLK[4:1] is active

when PLCP processing is enabled. The

frequency of this signal depends on the

selected PLCP format. RPOHCLK[4:1] is

nominally a 26.7 kHz clock for a DS1

PLCP frame, a 768 kHz clock for a DS3

PLCP frame, a 33.7 kHz clock for an E1

based PLCP frame, or a 576 kHz clock for

a G.751 E3 based PLCP frame.

RPOHFP[4:1] and RPOH[4:1] are updated

on the falling edge of RPOHCLK[4:1]. RSCLK[4] RSCLK[3] RSCLK[2] RSCLK[1]

Framer Recovered Clock (RSCLK[4:1]).

RSCLK[4:1] is valid when the S/UNI-QJET

is configured as a DS3, E3, or J2 framer

for non-ATM applications by setting the

FRMRONLY bit in the S/UNI-QJET

Configuration Register.

RSCLK[4:1] is the recovered clock and

timing reference for RDATO[4:1],

RFPO/RMFPO[4:1], and ROVRHD[4:1].

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PM7346 S/UNI-QJET

DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3

Pin Name Type Pin No. Function

RGAPCLK[4] RGAPCLK[3] RGAPCLK[2] RGAPCLK[1]

LCD[4] LCD[3] LCD[2] LCD[1]

RDATO[4] RDATO[3] RDATO[2] RDATO[1]

Output W13

U10 V7 U5

Output Y14

W10 W7 Y4

Framer Recovered Gapped Clock

(RGAPCLK[4:1]). RGAPCLK[4:1] is valid

when the S/UNI-QJET is configured as a

DS3, E3, or J2 framer for non-ATM

applications by setting the FRMRONLY bit

in the S/UNI-QJET Configuration 1

S/UNI-QJET Configuration 2 Register.

RGAPCLK[4:1] is the recovered clock and

timing reference for RDATO[4:1].

RGAPCLK[4:1] is held high for bit

positions which correspond to overhead.

Loss of Cell Delineation (LCD[4:1]).

LCD[4:1] is an active high signal which is

asserted while the ATM cell processor has

detected a Loss of Cell Delineation defect.

The FRMRONLY bit in the S/UNI-QJET

Configuration 1 Register must be set to

logic 0 for LCD[4:1] to be valid.

Framer Receive Data (RDATO[4:1]).

RDATO[4:1] is valid when the S/UNI-QJET

is configured as a DS3, E3, or J2 framer

for non-ATM applications by setting the

FRMRONLY bit in the S/UNI-QJET

Configuration 1 Register.

RDATO[4:1] is the received data aligned to

RFPO/RMFPO[4:1] and ROVRHD[4:1].

RDATO[4:1] is updated on the active edge

(as set by the RSCLKR register bit) of

RSCLK[4:1] or RGAPCLK[4:1].

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PM7346 S/UNI-QJET

DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3

Pin Name Type Pin No. Function

FRMSTAT[4] FRMSTAT[3] FRMSTAT[2] FRMSTAT[1]

Output U1

U2 T4 U3

Framer Status (FRMSTAT[4:1]).

FRMSTAT[4:1] is an active high signal

which can be configured to show when

one of the J2, E3, DS3, or PLCP framers

have detected certain conditions. The

FRMSTAT[4:1] outputs can be

programmed via the STATSEL[2:0] bits in

the S/UNI-QJET Configuration 2 Register

to indicate: E3/DS3 Loss of Frame or J2

extended Loss of Frame, E3/DS3 Out of

Frame or J2 Loss of Frame, PLCP Loss of

Frame, PLCP Out of Frame, AIS, Loss of

Signal, and DS3 Idle. FRMSTAT[4:1]

should be treated as a glitch free

asynchronous signal. ATM8 Input L18 ATM Interface Bus Width Selection

(ATM8). The ATM8 input pin determines

whether the S/UNI-QJET works with a 8-

bit wide interface (RDAT[7:0] and

TDAT[7:0]) or a 16-bit wide interface

(RDAT[15:0] and TDAT[15:0]). If ATM8 is

set to logic 1, then the 8-bit wide interface

is chosen. If ATM8 is set to logic 0, then

the 16-bit wide interface is chosen.

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PM7346 S/UNI-QJET

DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3

Pin Name Type Pin No. Function

TDAT[15] TDAT[14] TDAT[13] TDAT[12] TDAT[11] TDAT[10] TDAT[9] TDAT[8] TDAT[7] TDAT[6] TDAT[5] TDAT[4] TDAT[3] TDAT[2] TDAT[1]

Input C15

A16 B16 D15 C16 A17 B17 D16 C17 D18 E17 D19 D20 E18 F17

Transmit Cell Data Bus (TDAT[15:0]). This

bus carries the ATM cell octets that are

written to the selected transmit FIFO.

TDAT[15:0] is sampled on the rising edge

of TFCLK and is considered valid only

when TENB is simultaneously asserted

and the S/UNI-QJET has been selected

via the TADR[4:2] and PHY_ADR[2:0]

inputs.

The S/UNI-QJET can be configured to

operate with an 8-bit wide or 16-bit wide

ATM data interface via the ATM8 input pin.

When configured for the 8-bit wide

interface, TDAT[15:8] are not used and

should be tied to ground.

TDAT[0]

E19

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PM7346 S/UNI-QJET

DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3

Pin Name Type Pin No. Function

TPRTY Input G19 Transmit bus parity (TPRTY). The transmit

parity (TPRTY) signal indicates the parity

of the TDAT[15:0] or TDAT[7:0] bus. If

configured for the 8-bit bus (via the ATM8

input pin), then parity is calculated over

TDAT[7:0]. If configured for the 16-bit bus,

then parity is calculated over TDAT[15:0].

A parity error is indicated by a status bit

and a maskable interrupt. Cells with parity

errors are inserted in the transmit stream,

so the TPRTY input may be unused.

Odd or even parity selection is made using

the TPTYP register bit. TPRTY is sampled

on the rising edge of TFCLK and is

considered valid only when TENB is

simultaneously asserted and the

S/UNI-QJET has been selected via the

TADR[4:0] and PHY_ADR[2:0] inputs. TSOC Input G20 Transmit Start of Cell (TSOC). The

transmit start of cell (TSOC) signal marks

the start of cell on the TDAT bus. When

TSOC is high, the first word of the cell

structure is present on the TDAT bus. It is

not necessary for TSOC to be present for

each cell. An interrupt may be generated

if TSOC is high during any word other than

the first word of the cell structure. TSOC is

sampled on the rising edge of TFCLK and

is considered valid only when TENB is

simultaneously asserted and the

S/UNI-QJET has been selected via the

TADR[4:2] and PHY_ADR[2:0] inputs.

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PM7346 S/UNI-QJET

DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3

Pin Name Type Pin No. Function

TENB Input H18 Transmit Multi-Phy Write Enable (TENB).

The TENB signal is an active low input

which is used along with the TADR[4:0]

inputs to initiate writes to the transmit

FIFOs. When sampled low using the rising

edge of TFCLK, the word on the TDAT bus

is written into the transmit FIFO selected

by the TADR[4:0] address bus. When

sampled high using the rising edge of

TFCLK, no write is performed, but the

TADR[4:0] address is latched to identify

the transmit FIFO to be accessed. A

complete 53 octet cell must be written to

the transmit FIFO before it is inserted into

the transmit stream. Idle cells are inserted

when a complete cell is not available.

TADR[4] TADR[3] TADR[2] TADR[1] TADR[0]

Input F18

F19 F20 G18 H17

Transmit Address (TADR[4:0]). The

TADR[4:0] bus is used to select the FIFO

(and hence port) that is written to using

the TENB signal and the FIFO whose cell-

available signal is visible on the TCA

output. TADR[4:0] is sampled on the rising

edge of TFCLK together with TENB.

Note that the null-PHY address 1FH is an

invalid address and will not be identified to

any port on the S/UNI-QJET.

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PM7346 S/UNI-QJET

DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3

Pin Name Type Pin No. Function

TCA Output H19 Transmit Multi-Phy Cell Available (TCA).

The TCA signal indicates when a cell is

available in the transmit FIFO for the port

selected by TADR[4:0]. When high, TCA

indicates that the corresponding transmit

FIFO is not full and a complete cell may be

written. When TCA goes low, it can be

configured to indicate either that the

corresponding transmit FIFO is near full or

that the corresponding transmit FIFO is

full. TCA will transition low on the rising

edge of TFCLK which samples Payload

byte 43 (TCALEVEL0=0) or 47

(TCALEVEL0=1) for the 8-bit interface

(ATM8=1), or the rising edge of TFCLK

which samples Payload word 19

(TCALEVEL0=0) or 23 (TCALEVEL0=1)

for the 16-bit interface (ATM8=0) if the

PHY being polled is the same as the PHY

in use. To reduce FIFO latency, the FIFO

depth at which TCA indicates "full" can be

set to one, two, three or four cells. Note

that regardless of what fill level TCA is set

to indicate "full" at, the transmit cell

processor can store 4 complete cells.

TCA is tri-stated when either the null-PHY

address (1FH) or an address not matching

the address space set by PHY_ADR[2:0]

is latched (by TFCLK) from the TADR[4:2]

inputs.

The polarity of TCA (with respect the the

description above) is inverted when the

TCAINV register bit is set to logic 1.

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PM7346 S/UNI-QJET

DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3

Pin Name Type Pin No. Function

TFCLK Input E20 Transmit FIFO Wr ite Clock (TFCLK). This

signal is used to write ATM cells to the four

cell transmit FIFOs. TFCLK cycles at a 52

MHz or lower instantaneous rate.

Please note that the TFCLK input is not 5

V tolerant, it is a 3.3 V only input pin. DTCA[4] DTCA[3] DTCA[2] DTCA[1]

Output J17

J18 J19 K19

Direct Access Transmit Cell Available

(DTCA[4:1]). These output signals

indicate when a cell is available in the

transmit FIFO for the corresponding port.

When high, DTCA[x] indicates that the

corresponding transmit FIFO is not full and

a complete cell may be written. DTCA[x]

can be configured to indicate either that

the corresponding transmit FIFO is near

full and can accept no more than four

writes or that the corresponding transmit

FIFO is full. DTCA[x] will thus transition

low on the rising edge of TFLCK which

samples Payload byte 43 (TCALEVEL0=0)

or 47 (TCALEVEL0=1) for the 8-bit

interface (ATM8=1), or the rising edge of

TFCLK which samples Payload word 19

(TCALEVEL0=0) or 23 (TCALEVEL0=1)

for the 16-bit interface (ATM8=0). To

reduce FIFO latency, the FIFO depth at

which DTCA[x] indicates "full" can be set

to one, two, three or four cells. Note that

regardless of what fill level DTCA[x] is set

to indicate "full" at, the transmit cell

processor can store 4 complete cells.

The polarity of DTCA[x] (with respect the

the description above) is inverted when

the TCAINV register bit is set to logic 1.

The DTCA[4:1] outputs can be used to

support Utopia Direct Access mode.

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Pin Name Type Pin No. Function

RDAT[15] RDAT[14] RDAT[13] RDAT[12] RDAT[11] RDAT[10] RDAT[9] RDAT[8] RDAT[7] RDAT[6] RDAT[5] RDAT[4] RDAT[3] RDAT[2] RDAT[1]

Output T20

T19 R17 T18 U20 U19 T17 U18 V17 U16 W17 Y17 V16 U15 W16

Receive Cell Data Bus (RDAT[15:0]). This

bus carries the ATM cell octets that are

read from the receive ATM FIFO selected

by RADR[4:0]. RDAT[15:0] is tri-stated

when RENB is high. RDAT[15:0] is

updated on the rising edge of RFCLK.

The S/UNI-QJET can be configured to

operate with an 8-bit wide or 16-bit wide

ATM data interface via the ATM8 input pin.

RDAT[15:8] will remain tri-stated if ATM8 is

set to logic 1.

RDAT[15:0] is tri-stated when either the

null-PHY address (1FH) or an address not

matching the address space set by

PHY_ADR[2:0] is latched from the

RADR[4:2] inputs when RENB is high.

RDAT[0]

Y16

RPRTY Output R18 Receive Parity (RPRTY). The receive

parity (RPRTY) signal indicates the parity

of the RDAT bus.

The S/UNI-QJET can be configured to

operate with an 8-bit wide or 16-bit wide

ATM data interface via the ATM8 input pin.

In the 8-bit mode, RPRTY reflects the

parity of RDAT[7:0]. In the 16-bit mode,

RPRTY reflects the parity of RDAT[15:0].

Odd or even parity selection is made using

the RXPTYP register bit.

RPRTY is tri-stated when either the null-

PHY address (1FH) or an address not

matching the address space set by

PHY_ADR[2:0] is latched from the

RADR[4:2] inputs when RENB is high.

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Pin Name Type Pin No. Function

RSOC Output M17 Receive Start of Cell (RSOC). This signal

marks the start of cell on the RDAT bus.

RSOC marks the start of the cell on the

RDAT bus.

RSOC is tri-stated when either the null-

PHY address (1FH) or an address not

matching the address space set by

PHY_ADR[2:0] is latched from the

RADR[4:0] inputs when RENB is high. RENB Input N18 Receive Multi-Phy Read Enable (RENB).

The RENB signal is used to initiate reads

from the receive FIFOs. When sampled

low using the rising edge of RFCLK, a byte

is read (if one is available) from the receive

FIFO selected by the RADR[4:0] address

bus and output on the RDAT bus. When

sampled high using the rising edge of

RFCLK, no read is performed and

RDAT[15:0], RPRTY, and RSOC are tri-

stated, and the address on RADR[4:0] is

latched to select the device or port for the

next ATM FIFO access. RENB must

operate in conjunction with RFCLK to

access the FIFOs at a high enough rate to

prevent FIFO overflows. The ATM layer

device may de-assert RENB at anytime it

is unable to accept another byte.

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Pin Name Type Pin No. Function

RADR[4] RADR[3] RADR[2] RADR[1]

Input P19

N17 P18 R20

Receive Address (RADR[4:0]). The

RADR[4:1] signal is used to select the

FIFO (and hence port) that is read from

using the RENB signal and the FIFO

whose cell-available signal is visible on the

RCA output. RADR[4:0] is sampled on the RADR[0]

R19

rising edge of RFCLK together with RENB.

Note that the null-PHY address 1FH is an

invalid address and will not be identified to

any port on the S/UNI-QJET.

RCA Output N19 Receive Multi-Phy Cell Available (RCA).

The RCA signal indicates when a cell is

available in the receive FIFO for the port

selected by RADR[4:0]. RCA can be

configured to be de-asserted when either

zero or four bytes remain in the

selected/addressed FIFO. RCA will thus

transition low on the rising edge of RFCLK

after Payload byte 48 (RCALEVEL0=1) or

43 (RCALEVEL0=0) is output for the 8-bit

interface (ATM8=1), or after Payload word

24 (RCALEVEL0=1) or 19

(RCALEVEL0=0) is output for the 16-bit

interface (ATM8=0) if the PHY being polled

is the same as the PHY in use.

RCA is tri-stated when either the null-PHY

address (1FH) or an address not matching

the address space set by PHY_ADR[2:0]

is latched (by RFCLK) from the RADR[4:2]

inputs.

The polarity of RCA (with respect to the

description above) is inverted when the

RCAINV register bit is set to logic 1.

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Pin Name Type Pin No. Function

RFCLK Input P20 Receive FIFO Read Clock (RFCLK). This

signal is used to read ATM cells from the

receive FIFOs. RFCLK must cycle at a 52

MHz or lower instantaneous rate, but at a

high enough rate to avoid FIFO overflows.

Please note that the RFCLK input is not 5

V tolerant, it is a 3.3 V only input pin. DRCA[4] DRCA[3] DRCA[2] DRCA[1]

PHY_ADR[2] PHY_ADR[1] PHY_ADR[0]

Output L17

M20 M19 M18

Input K18

L20 L19

Direct Access Receive Cell Available

(DRCA[4:1]). These output signals

indicate when a cell is available in the

receive FIFO for the corresponding port.

DRCA[4:1] can be configured to be de-

asserted when either zero or four bytes

remain in the FIFO. DRCA[4:1] will thu s

transition low on the rising edge of RFCLK

after Payload byte 48 (RCALEVEL0=1) or

43 (RCALEVEL0=0) is output for the 8-bit

interface (ATM8=1), or after Payload word

24 (RCALEVEL0=1) or 19

(RCALEVEL0=0) is output for the 16-bit

interface (ATM8=0).

The DRCA[4:1] outputs can be used to

support Utopia Direct Access mode.

Device Identification Address

(PHY_ADR[2:0]). The PHY_ADR[2:0]

inputs are the most-significant bits of the

address space which this S/UNI-QJET

occupies. When the PHY_ADR[2:0] inputs

match the TADR[4:2] or RADR[4:2] inputs,

then one of the four quadrants (as

determined by the TADR[1:0] or RADR[1:0]

inputs) in this S/UNI-QJET is selected for

transmit or receive ATM access.

Note that the null-PHY address 1FH is an

invalid address and will not be identified to

any port on the S/UNI-QJET.

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Pin Name Type Pin No. Function

CSB Input C9 Active low Chip Select (CSB). This signal

must be low to enable S/UNI-QJET

(RDB and WRB determine register reads

and writes) then it should be tied to an

inverted version of RSTB. WRB Input B8 Active low Write Strobe (WRB). This signal

is pulsed low to enable a S/UNI-QJET

clocked into the addressed register on the

rising edge of WRB while CSB is low. RDB Input D9 Active low Read Enable (RDB). This signal

is pulsed low to enable a S/UNI-QJET

drives the D[7:0] bus with the contents of

the addressed register while RDB and

CSB are both low. D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]

I/O D12

C13 A14 B14 D13 C14 A15 B15

Bi-directional Data Bus (D[7:0]). The bi-

directional data bus D[7:0] is used during

S/UNI-QJET register read and write

accesses.

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Pin Name Type Pin No. Function

A[10] A[9] A[8] A[7] A[6] A[5] A[4] A[3] A[2] A[1] A[0]

Input B9

B10 C10 A11 B11 C11 D11 A12 B12 C12 B13

Address Bus (A[10:0]). The address bus

A[10:0] selects specific registers during

S/UNI-QJET register accesses.

RSTB Input C8 Active low Reset (RSTB). This signal is set

low to asynchronously reset the

S/UNI-QJET. RSTB is a Schmitt-trigger

input with an integral pull-up resistor. ALE Input A8 Address Latch Enable (ALE). The address

latch enable (ALE) is active-high and

latches the address bus A[10:0] when low.

When ALE is high, the internal address

latches are transparent. It allows the

S/UNI-QJET to interface to a multiplexed

address/data bus. ALE has an integral

pull-up resistor. INTB Output A7 Active low Open-Drain Interrupt (INTB).

This signal goes low when an unmasked

interrupt event is detected on any of the

internal interrupt sources. Note that INTB

will remain low until all active, unmasked

interrupt sources are acknowledged at

their source. TCK Input B6 Test Clock (TCK). This signal provides

timing for test operations that can be

carried out using the IEEE P1149.1 test

access port.

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Pin Name Type Pin No. Function

TMS Input C7 Test Mode Select (TMS). This signal

controls the test operations that can be

carried out using the IEEE P1149.1 test

access port. TMS is sampled on the rising

edge of TCK. TMS has an integral pull up

resistor. TDI Input D8 Test Data Input (TDI). This signal carries

test data into the S/UNI-QJET via the

IEEE P1149.1 test access port. TDI is

sampled on the rising edge of TCK. TDI

has an integral pull up resistor. TDO Output B7 Test Data Output (TDO). This signal

carries test data out of the S/UNI-QJET via

the IEEE P1149.1 test access port. TDO

is updated on the falling edge of TCK.

TDO is a tri-state output which is inactive

except when scanning of data is in

progress. TRSTB Input A6 Active low Test Reset (TRSTB). This signal

provides an asynchronous S/UNI-QJET

test access port reset via the IEEE

P1149.1 test access port. TRSTB is a

Schmitt triggered input with an integral pull

up resistor. TRSTB must be asserted

during the power up sequence.

Note that if not used, TRSTB must be

connected to the RSTB input. BIAS Input H20

U17 D4 U4

+5V Bias (BIAS). When tied to +5V, the

BIAS input is used to bias the wells in the

input and I/O pads so that the pads can

tolerate 5V on their inputs without fo rward

biasing internal ESD protection devices.

When tied to VDD, the inputs and bi-

directional inputs will only tolerate input

levels up to VDD.

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Pin Name Type Pin No. Function

VDD[1] VDD[2] VDD[3] VDD[4] VDD[5] VDD[6] VDD[7] VDD[8] VDD[9] VDD[10] VDD[11] VDD[12] VDD[13] VDD[14] VDD[15]

Power B2

B3 B18 B19 C2 C3 C18 C19 D7 D10 D14 G4 G17 K17 L4

DC Power. The DC Power pins should be

connected to a well-decoupled +3.3V DC

supply.

VDD[16] VDD[17] VDD[18] VDD[19] VDD[20] VDD[21] VDD[22] VDD[23] VDD[24] VDD[25] VDD[26] VDD[27] VDD[28]

P4 P17 U7 U11 U14 V2 V3 V18 V19 W2 W3 W18 W19

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Pin Name Type Pin No. Function

VSS[1] VSS[2] VSS[3] VSS[4] VSS[5] VSS[6] VSS[7] VSS[8] VSS[9] VSS[10] VSS[11] VSS[12] VSS[13] VSS[14] VSS[15]

Ground A1

A2 A3 A9 A10 A13 A18 A19 A20 B1 B20 C1 C20 H1 J20

DC Ground. The DC Ground pins should

be connected to GND.

VSS[16] VSS[17] VSS[18] VSS[19] VSS[20] VSS[21] VSS[22] VSS[23] VSS[24] VSS[25] VSS[26] VSS[27] VSS[28] VSS[29]

K20 L1 M1 N20 V1 V20 W1 W20 Y1 Y2 Y3 Y8 Y11 Y12

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Pin Name Type Pin No. Function

VSS[30] VSS[31] VSS[32]

Ground Y18

Y19 Y20

DC Ground. The DC Ground pins should

be connected to GND.

Notes on Pin Description:

1. All S/UNI-QJET inputs and bi-directionals present minimum capacitive loading and operate at TTL logic levels.

2. All S/UNI-QJET outputs and bi-directionals have at least 3 mA drive capability. The data bus outputs, D[7:0], have 3 mA drive capability. The FIFO interface outputs, RDAT[15:0 ], RPRTY, RCA, DRCA[4:1], RSOC, TCA, and DTCA[4:1], have 12 mA drive capability. The outputs TCLK[4:1], TPOS/TDATO[4:1], TNEG/T OHM[4:1], TPOHFP/TFPO/TMFPO/TGAPCLK[4:1], LCD/RDATO[4:1], RPOH/ROVRHD[4: 1 ], RPOHCLK/RSCLK/RGAPCLK[4:1], and REF8KO/RPOHFP/RFPO/RMFPO[4:1] have 6 mA drive capability. All other outputs have 3 mA drive capability.

3. Inputs RSTB, ALE, TMS, TDI and TRSTB have internal pull-up resistors.

4. RSTB, TRSTB, TMS, TDI, TCK, REF8KI, TFCLK, RFCLK, TICLK[4:1], and RCLK[4:1] are schmitt trigger input pads.

5. RFCLK and TFCLK are 3.3 V only input pins – they are not 5 V tolerant. Connecting a 5 V signal to these inputs may result in damage to the part.

6. The VSS [32:1] ground pins are not internally connected together. Failure to connect these pins externally may cause malfunction or damage the S/UNI-QJET.

7. The VDD[28:1] power pins are not internally connected together. Failure to connect these pins externally may cause malfunction or damage the device. These power supply connections must all be utilized and must all connect to a common +3.3 V or ground rail, as appropriate.

8. During power-up and power-down, the voltage on the BIAS pin must be kept equal to or greater than the voltage on the VDD [28:1] pins, to avoid damage to the device.

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FUNCTIONAL DESCRIPTION

9.1 DS3 Framer

The DS3 Framer (T3-FRMR) Block integrates circuitry required for decoding a B3ZS-encoded signal and framing to the resulting DS3 bit stream. The T3-FRMR is directly compatible with the M23 and C-bit parity DS3 applications.

The T3-FRMR decodes a B3ZS-encoded signal and provides indications of line code violations. The B3ZS decoding algorithm and the LCV definition can be independently chosen through software. A loss of signal (LOS) defect is also detected for B3ZS encoded streams. LOS is declared when inputs RPOS and RNEG contain zeros for 175 consecutive RCLK cycles. LOS is removed when the ones density on RPOS and/or RNEG is greater than 33% for 175 ±1 RCLK cycles.

The framing algorithm examines five F-bit candidates simultaneously. When at least one discrepancy has occurred in each candidate, the algorithm examines the next set of five candidates. When a single F-bit candidate remains in a set, the first bit in the supposed M-subframe is examined for the M-frame alignment signal (i.e., the M-bits, M1, M2, and M3 are following the 010 pattern). Framing is declared, and out-of-frame is removed, if the M-bits are correct for three consecutive M-frames while no discrepancies have occurred in the F-bits. During the examination of the M-bits, the X-bits and P-bits are ignored. The algorithm gives a maximum average reframe time of 1.5 ms.

While the T3-FRMR is synchronized to the DS3 M-frame, the F-bit and M-bit positions in the DS3 stream are examined. An out-of-frame defect is detected when 3 F-bit errors out of 8 or 16 consecutive F-bits are observed (as selected by the M3O8 bit in the DS3 FRMR Configuration Register), or when one or more M-bit errors are detected in 3 out of 4 consecutive M-frames. The M-bit error criteria for OOF can be disabled by the MBDIS bit in the DS3 Framer Configuration register. The 3 out of 8 consecutive F-bits out-of-frame ratio provides more robust operation, in the presence of a high bit error rate, than the 3 out of 16 consecutive F-bits ratio. Either out-of-frame criteria allows an out-offrame defect to be detected quickly when the M-subframe alignment patterns or, optionally, when the M-frame alignment pattern is lost.

Also while in-frame, line code violations, M-bit or F-bit framing bit errors, and Pbit parity errors are indicated. When C-bit parity mode is enabled, both C-bit parity errors and far end block errors are indicated. These error indications, as well as the line code violation and excessive zeros indication, are accumulated

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over 1 second intervals with the Performance Monitor (PMON). Note that the framer is an off-line framer, indicating both OOF and COFA events. Even if an OOF is indicated, the framer will continue indicating p erformance monitoring information based on the previous frame alignment.

Three DS3 maintenance signals (a RED alarm condition, the alarm indication signal, and the idle signal) are detected by the T3-FRMR. The maintenance detection algorithm employs a simple integrator with a 1:1 slope that is based on the occurrence of "valid" M-frame intervals. For the RED alarm, an M-frame is said to be a "valid" interval if it contains a RED defect, defined as an occurrence of an OOF or LOS event during that M-frame. For AIS and IDLE, an M-frame interval is "valid" if it contains AIS or IDLE, defined as the occurrence of less than 15 discrepancies in the expected signal pattern (1010... for AIS, 1100... for IDLE) while valid frame alignment is maintained. This discrepancy threshold ensures

the detection algorithms operate in the presence of a 10-3 bit error rate. For AIS, the expected pattern may be selected to be: the framed "1010" signal; the framed arbitrary DS3 signal and the C-bits all zero; the framed "1010" signal and the Cbits all zero; the framed all-ones signal (with overhead bits ignored); or the unframed all-ones signal (with overhead bits equal to ones). Each "valid" Mframe causes an associated integration counter to increment; "invalid" M-frames cause a decrement. With the "slow" detection option, RED, AIS, or IDLE are declared when the respective counter saturates at 127, which results in a detection time of 13.5 ms. With the "fast" detection option, RED, AIS, or IDLE are declared when the respective counter saturates at 21, which results in a detection time of 2.23 ms (i.e., 1.5 times the maximum average reframe time). RED, AIS, or IDLE are removed when the respective counter decrements to 0. DS3 Loss of Frame detection is provided as recommended by ITU-T G.783 with programmable integration periods of 1ms, 2ms, or 3ms. While integrating up to assert LOF, the counter will integrate up when the framer asserts an Out of Frame condition and integrates down when the framer de-asserts the Out of Frame condition. Once an LOF is asserted, the framer must not assert OOF for the entire integration period before LOF is de-asserted.

Valid X-bits are extracted by the T3-FRMR to provide indication of far end receive failure (FERF). A FERF defect is detected if the extracted X-bits are equal and are logic 0 (X1=X2=0); the defect is removed if the extracted X-bits are equal and are logic 1 (X1=X2=1). If the X-bits are not equal, the FERF status remains in its previous state. The extracted FERF status is buffered for 2 M-frames before being reported within the DS3 FRMR Status register. This buffer ensures a better than 99.99% chance of freezing the FERF status on a correct value during the occurrence of an out of frame.

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When the C-bit parity application is enabled, both the far end alarm and control (FEAC) channel and the path maintenance data link are extracted. Codes in the FEAC channel are detected by the Bit Oriented Code Detector (RBOC). HDLC messages in the Path Maintenance Data Link are received by the Data Link Receiver (RDLC).

The T3-FRMR can be enabled to automatically assert the RAI indication in the outgoing transmit stream upon detection of any combination of LOS, OOF or RED, or AIS. The T3-FRMR can also be enabled to automatically insert C-bit Parity FEBE upon detection of receive C-bit parity error.

The T3-FRMR extracts the entire DS3 overhead (56 bits per M-frame) using the ROH output, along with the ROHCLK, and ROHFP outputs.

The T3-FRMR may be configured to generate interrupts on error events or status changes. All sources of interrupts can be masked or acknowledged via internal registers. Internal registers are also used to configure the T3-FRMR. Access to these registers is via a generic microprocessor bus.

9.2 E3 Framer

The E3 Framer (E3-FRMR) Block integrates circuitry required for decoding an HDB3-encoded signal and framing to the resulting E3 bit stream. The E3-FRMR is directly compatible with the G.751 and G.832 E3 applications.

The E3-FRMR searches for frame alignment in the incoming serial stream based on either the G.751 or G.832 formats. For the G.751 format, the E3-FRMR expects to see the selected framing pattern error-free for three consecutive frames before declaring INFRAME. For the G.832 format, the E3-FRMR expects to see the selected framing pattern error-free for two consecutive frames before declaring INFRAME. Once the frame alignment is established, the incoming data is continuously monitored for framing bit errors and byte interleaved parity errors (in G.832 format).

While in-frame, the E3-FRMR also extracts various overhead bytes and processes them according to the framing format selected:

In G.832 E3 format, the E3-FRMR extracts:

• the Trail Trace bytes and outputs them as a serial stream for further

processing by the Trail Trace Buffer (TTB) block;

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the FERF bit and indicates an alarm when the FERF bit is a logic 1 for 3 or 5

• consecutive frames. The FERF indication is removed when the FERF bit is a logic 0 for 3 or 5 consecutive frames;

the FEBE bit and outputs it for accumulation in PMON;

• the Payload Type bits and buffers them so that they can be read by the

• microprocessor;

the Timing Marker bit and asserts the Timing Marker indication when the

• value of the extracted bit has been in the same state for 3 or 5 consecutive frames;

the Network Operator byte and presents it as a serial stream for further

• processing by the RDLC block when the RNETOP bit in the S/UNI-QJET Data Link and FERF Control register is logic 1. The byte is also brought out on the ROH[x] output with an associated clock on ROHCLK[x]. All 8 bits of the Network Operator byte are extracted and presented on the overhead output and, optionally, presented to the RDLC.

the General Purpose Communication Channel byte and presents it to the

• RDLC when the RNETOP bit in the S/UNI-QJET Data Link and FERF Control register is logic 0 The byte is also brought out on the ROH[x] output with an associated clock on ROHCLK[x].

In G.751 E3 mode, the E3-FRMR extracts:

the Remote Alarm Indication bit (bit 11 of the frame) and indicates a Remote

• Alarm when the RAI bit is a logic 1 for 3 or 5 consecutive frames. Similarly, the Remote Alarm is removed when the RAI bit is logic 0 for 3 or 5 consecutive frames;

the National Use reserved bit (bit 12 of the frame) and presents it as a serial

• stream for further processing in the RDLC when the RNETOP bit in the S/UNI-QJET Data Link and FERF Control register is logic 0. The bit is also brought out on the ROH[x] output with an associated clock on ROHCLK[x]. Optionally, an interrupt can be generated when the National Use bit changes state.

Further, while in-frame, the E3-FRMR indicates the position of all the overhead bits in the incoming digital stream to the ATMF/SPLR block. For G.751 mode, the tributary justification bits can optionally be identified as either overhead or payload for payload mappings that take advantage of the full bandwidth.

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The E3-FRMR declares out of frame alignment if the framing pattern is in error for four consecutive frames. The E3-FRMR is an "off-line" framer, where all frame alignment indications, all overhead bit indications, and all overhead bit processing continue based on the previous alignment. Once the framer has determined the new frame alignment, the out-of-frame indication is removed and a COFA indication is declared if the new alignment differs from the previous alignment.

The E3-FRMR detects the presence of AIS in the incoming data stream when less than 8 zeros in a frame are detected while the framer is OOF in G.832 mode, or when less than 5 zeros in a frame are detected while OOF in G.751 mode. This algorithm provides a probability of detecting AIS in the presence of a 10-3 BER as 92.9% in G.832 and 98.0% in G.751.

Loss of signal is LOS is declared when no marks have been received for 32 consecutive bit periods. Loss of signal is de-asserted after 32 bit periods during which there is no sequence of four consecutive zeros.

E3 Loss of Frame detection is provided as recommended by ITU-T G.783 with programmable integration periods of 1ms, 2ms, or 3ms. While integrating up to assert LOF, the counter will integrate up when the framer asserts an Out of Frame condition and integrates down when the framer de-asserts the Out of Frame condition. Once an LOF is asserted, the framer must not assert OOF for the entire integration period before LOF is de-asserted.

The E3-FRMR can also be enabled to automatically assert the RAI/FERF indication in the outgoing transmit stream upon detection of any combination of LOS, OOF or AIS. The E3-FRMR can also be enabled to automatically insert G.832 FEBE upon detection of receive BIP-8 errors.

9.3 J2 Framer

The J2-FRMR integrates circuitry to decode a unipolar or B8ZS encoded signal and frame to the resulting 6312 kbps J2 bit stream. Having found frame, the J2FRMR extracts a variety of overhead and datalink information from the J2 bit stream.

The J2 format consists of 789-bit frames, each 125µs long, consisting of 96 bytes of payload, 2 reserved bytes, and 5 F-bits. The frames are grouped into 4frame multiframes. The multiframe format is as follows:

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Bit # 1-8 ... 761-768 769-776 777-784 785 786 787 788 789 Frm. 1 Frm. 2 Frm. 3 Frm. 4

TS1[1:8] ... TS96[1:8] TS97[1:8] TS98[1:8] 1 1 0 0 m TS1[1:8] ... TS96[1:8] TS97[1:8] TS98[1:8] 1 0 1 0 0 TS1[1:8] ... TS96[1:8] TS97[1:8] TS98[1:8] x1 x2 x3 a m TS1[1:8] ... TS96[1:8] TS97[1:8] TS98[1:8] e1 e2 e3 e4 e5

TS1 .. TS96 : Byte interleaved payload TS97, TS98: Reserved channels for signaling Frame Alignment Signal: represented as binary ones and zeroes m : 4-kHz datalink x1, x2, x3: Spare bits, usually logic 1 a : Remote Loss of Frame alarm bit, active high e1..e5: CRC-5 check sequence. The entire 3156-bit multiframe,

including the CRC-5 check sequence, should have a remainder of 0

when divided by x5 + x4 + x2 + 1

The J2-FRMR frames to a J2 signal with an average reframe time of 5.07 ms. An alternate framing algorithm that uses the CRC-5 check to detect static mimic patterns is available. Once in frame, the J2-FRMR provides indications of frame and multiframe boundaries, and marks overhead bits, x-bits, m-bits, and reserved channels (TS97 and TS98). Indications of loss of signal, bipolar violations, excessive zeroes, change of frame alignment, framing errors, and CRC errors are provided, and may be accumulated by the PMON (with the exception of change of frame alignment); maskable interrupts are available to alert the microprocessor to the occurrence of any of these events. In addition to marking x-bit values, J2-FRMR provides microprocessor access to the x-bits, and will optionally generate an interrupt when any of the x-bits changes state. The m-bits and the associated clock are can either be extracted through the RDLC or through the ROH[x] and ROHCLK[x] output pins of the S/UNI-QJET. The m-bits are also presented to the RBOC for detection of any generic bit-oriented codes.

Status signals such as Physical AIS, Payload AIS, Remote Alarm Indication in

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m-bits, and Remote Loss of Frame (a-bit) are detected by the J2-FRMR. In addition to providing indication signals of these states, the J2-FRMR will optionally generate an interrupt when any of these status signals changes.

J2 LOS is declared when no marks have been received for one of 15, 31, 63, or 255 consecutive bit periods. J2 LOS is cleared when either 15, 31, 63, or 255 consecutive bit periods have passed without an excessive zeros (8 or more consecutive zeros) detection as required by ITU-T G.775.

J2 LOF is declared when 7 or more consecutive multiframes with errored framing patterns are received. The J2 LOF is cleared when 3 or more consecutive multiframes with correct framing patterns are received. A framing algorithm which takes into account the CRC calculation is also available. The framing algorithms are described in the following text.

J2 Physical Layer AIS is declared when 2 or less zeros are detected in a sequence of 3156 bits. It is cleared when 3 or more zeros is detected in a sequence of 3156 bits as required by ITU-T G.775.

J2 Payload AIS is detected when the incoming J2 payload has 2 or less zeros in a sequence of 3072 bits. It is cleared when 3 or more zeros are detected in a sequence of 3072 bits.

The J2-FRMR may be forced to re-frame by microprocessor control. Similarly, the microprocessor may disable the J2-FRMR from reframing due to framing bit errors.

The J2-FRMR may be configured, and all sources of interrupts may be masked or acknowledged, via internal registers. These internal registers are accessed via a generic microprocessor bus.

9.3.1 J2 Frame Find Algorithms

The J2-FRMR searches for frame alignment using one of two algorithms, as selected by the CRC_REFR bit in the J2-FRMR Configuration Register.

When the CRC_REFR bit is set to logic 0, the J2-FRMR uses only the frame alignment sequence to find frame, searching for three consecutive correct frame alignment sequences. The frame find block searches for the entire 9-bit sequence (spread over two multiframes) at the same time, greatly reducing the time required to find frame alignment. The framing process with CRC-REFR cleared is illustrated in Figure 8.

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Figure 8 - Framing algorithm (CRC_REFR = 0)

Reset

Out of Frame

Fail

Slip 1 bit

Framing Pattern Matched

Mark multiframe alignment

Confirm Framing Pattern

in next multifram e

Pass

Confirm Fram ing Pattern

in next multiframe

Pass

Declare in-frame

Else

Using this algorithm, the J2-FRMR will on average find frame in 5.07ms when starting the search in the worst possible position, given a 10-4 error rate and no static mimic patterns.

When the CRC_REFR bit is set to logic 1, in addition to requiring three consecutive correct framing patterns, the J2-FRMR requires that the first two CRC-5 checks be correct, or a reframe is initiated. To speed the process, the CRC-5 and frame alignment checks are run concurrently, as illustrated in Figure

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Figure 9 - Framing Algorithm (CRC_REFR = 1)

Reset

Out of Frame

Fail

S lip 1 b it

Framing Pattern Matc hed

Mark multiframe alignment

Confirm Framing Pattern

in ne xt m ul t if r ame

Pass

Check CRC-5 Sequence

Pass

Confirm Framing Pattern

in ne xt m ul t if r ame

Pass

Check CRC-5 Sequence

Else

Pass

Declare in-frame

Using this algorithm, the J2-FRMR will find frame in 10.22ms, on average when starting the search in the worst possible position, given a 10-4 error rate and no static mimic patterns. The algorithm will reject 99.90% of mimic patterns. Further protection against mimic patterns is available by monitoring the rate of CRC-5 errors.

Once frame alignment is found, the block sets the LOF indication low, indicates a change of frame alignment (if it occurred). The block declares loss of frame alignment if 7 consecutive FASs have been received in error. In the presence of a random 10-3 bit error rate the frame loss criteria provides a mean time to falsely lose frame alignment of 1.65 years. The Frame Find Block can be forced to initiate a frame search at any time when the REFRAME bit in the J2-FRMR Configuration. Conversely, when the FLOCK bit is set to logic 1, the J2-FRMR

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will never declare Loss of Frame or search for a new frame alignment due to excess framing bit errors.

J2 extended Loss of Frame detection is provided as recommended by ITU-T G.783 with programmable integration periods of 1ms, 2ms, or 3ms. While integrating up to assert LOF, the counter will integrate up when the framer asserts an Out of Frame condition and integrates down when the framer deasserts the Out of Frame condition. Once an LOF is asserted, the framer must not assert OOF for the entire integration period before LOF is de-asserted.

9.4 PMON Performance Monitor Accumulator

The Performance Monitor (PMON) Block interfaces directly with either the DS3 Framer (T3-FRMR) to accumulate line code violation (LCV) events, parity error (PERR) events, path parity error (CPERR) events, far end block error (FEBE) events, excess zeros (EXZS), and framing bit error (FERR) events using saturating counters; the E3 Framer (E3-FRMR) to accumulate LCV, PERR (in G.832 mode), FEBE and FERR events; or the J2 Framer (J2-FRMR) to accumulate LCVs, CRC errors (in the PERR counter), Framing bit errors (FERR), and excess zeros (EXZS). The PMON stops accumulating error signal from the E3, DS3, or J2 Framers once frame synchronization is lost.

When an accumulation interval is signaled by a write to the PMON register address space or a write to the S/UNI-QJET Identification, Master Reset, and Global Monitor Update register, the PMON transfers the current counter values into microprocessor accessible holding registers and resets the counters to begin accumulating error events fo r the next interval. The counters are reset in such a manner that error events occurring during the reset period are not missed.

When counter data is transferred into the holding registers, an interrupt is generated, providing the interrupt is enabled. If the holding registers have not been read since the last interrupt, an overrun status bit is set. In addition, a register is provided to indicate changes in the PMON counters since the last accumulation interval.

9.5 RBOC Bit-Oriented Code Detector

The Bit-Oriented Code Detector is only used in DS3 C-bit Parity or J2 mode. The Bit-Oriented Code Detector (RBOC) Block detects the presence of 63 of the

64 possible bit-oriented codes (BOCs) contained in the DS3 C-bit parity far-end alarm and control (FEAC) channel or in the J2 datalink signal stream. The 64 code ("111111") is similar to the HDLC flag sequence and is ignored.

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Bit-oriented codes (BOCs) are received on the FEAC channel as 16-bit sequences each consisting of 8 ones, a zero, 6 code bits, and a trailing zero ("111111110xxxxxx0"). BOCs are validated when repeated at least 10 times. The RBOC can be enabled to declare a code valid if it has been observed for 8 out of 10 times or for 4 out of 5 times, as specified by the AVC bit in the RBOC Configuration/Interrupt Enable Register. The RBOC declares that the code is removed if two code sequences containing code values different from the detected code are received in a moving window of ten code periods.

Valid BOCs are indicated through the RBOC Interrupt Status Register. The BOC bits are set to all ones ("111111") when no valid code is detected. The RBOC can be programmed to generate an interrupt when a detected code has been validated and when the code is removed.

9.6 RDLC Facility Data Link Receiver

The RDLC is a microprocessor peripheral used to receive LAPD/HDLC frames on any serial HDLC bit stream that provides data and clock information such as the DS3 C-bit parity Path Maintenance Data Link, the E3 G.832 Network Requirement byte or the General Purpose data link (selectable using the RNETOP bit in the S/UNI-QJET Data Link and FERF/RAI Control register), the E3 G.751 Network Use bit, or the J2 m-bit Data Link.

The RDLC detects the change from flag characters to the first byte of data, removes stuffed zeros on the incoming data stream, receives packet data, and calculates the CRC-CCITT frame check sequence (FCS).

In the address matching mode, only those packets whose first data byte matches one of two programmable bytes or the universal address (all ones) are stored in the FIFO. The two least significant bits of the address comparison can be masked for LAPD SAPI matching.

Received data is placed into a 128-level FIFO buffer. An interrupt is generated when a programmable number of bytes are stored in the FIFO buffer. Other sources of interrupt are detection of the terminating flag sequence, abort sequence, or FIFO buffer overrun.

The Status Register contains bits which indicate the overrun or empty FIFO status, the interrupt status, and the occurrence of first flag or end of message bytes written into the FIFO. The Status Register also indicates the abort, flag, and end of message status of the data just read from the FIFO. On end of message, the Status Register indicates the FCS status and if the packet contained a non-integer number of bytes.

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9.7 SPLR PLCP Layer Receiver

The PLCP Layer Receiver (SPLR) Block integrates circuitry to support DS1, DS3, E1, and G.751 E3 PLCP frame processing. The SPLR provides framing for PLCP based transmission formats.

The SPLR frames to DS1, DS3, E1, and G.751 E3 based PLCP frames with maximum average reframe times of 635 µs, 22 µs, 483 µs, and 32 µs respectively. Framing is declared (out of frame is removed) upon finding 2 valid, consecutive sets of framing (A1 and A2) octets and 2 valid and sequential path overhead identifier (POHID) octets. While framed, the A1, A2, and POHID octets are examined. OOF is declared when an error is detected in both the A1 and A2 octets or when 2 consecutive POHID octets are found in error. LOF is declared when an OOF state persists for more than 25 ms, 1 ms, 20 ms, or 1 ms for DS1, DS3, E1, or G.751 E3 PLCP formats respectively. If the OOF events are intermittent, the LOF counter is decremented at a rate 1/12 (DS3 PLCP), 1/10 (E1, DS1 PLCP) or 1/9(G.751 E3 PLCP) of the incrementing rate. LOF is thus removed when an in-frame state persists for more than 250 ms for a DS1 signal, 12 ms for a DS3 signal, 200 ms for an E1 signal, or 9 ms for a G.751 E3 signal. When LOF is declared, PLCP reframe is initiated.

When in frame, the SPLR extracts the path overhead octets and outputs them bit serially on output RPOH, along with the RPOHCLK and RPOHFP outputs. Framing octet errors and path overhead identifier octet errors are indicated as frame errors. Bit interleaved parity errors and far end block errors are indicated. The yellow signal bit is extracted and accumulated to indicate yellow alarms. Yellow alarm is declared when 10 consecutive yellow signal bits are set to logical 1; it is removed when 10 consecutive received yellow signal bits are set to logical

0. The C1 octet is examined to maintain nibble alignment with the incoming

transmission system sublayer bit stream.

9.8 ATMF ATM Cell Delineator

The ATM Cell Delineator (ATMF) Block integrates circuitry to support HCS-based cell delineation for non-PLCP based transmission formats. The ATMF block accepts a bit serial cell stream from an upstream transmission system sublayer entity (such as the T3-FRMR, E3-FRMR, or J2-FRMR Block) and performs cell delineation to locate the cell boundaries. For PLCP applications, ATM cell positions are fixed relative to the PLCP frame, but the ATMF still performs cell delineation to locate the cell boundaries.

Cell delineation is the process of framing to ATM cell boundaries using the header check sequence (HCS) field found in the ATM cell header. The HCS is a

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(

)

(

)

(

)

(

)

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CRC-8 calculation over the first 4 octets of the ATM cell header. When performing delineation, correct HCS calculations are assumed to indicate cell boundaries.

The ATMF performs a sequential bit-by-bit, a nibble-by-nibble (DS-3 direct mapped), or a byte-by-byte (J2 and E3 direct-mapped) hunt for a correct HCS sequence. This state is referred to as the HUNT state. When receiving a bit serial cell stream from an upstream transmission system sublayer entity, the bit, nibble, or byte boundaries are determined from the location of the overhead.

When a correct HCS is found, the ATMF locks on the particular cell boundary and assumes the PRESYNC state. This state verifies that the previously detected HCS pattern was not a false indication. If the HCS pattern was a false indication then an incorrect HCS should be received within the next DELTA cells. At that point a transition back to the HUNT state is executed. If an incorrect HCS is not found in this PRESYNC period then a transition to the SYNC state is made. In this state synchronization is not relinquished until ALPHA consecutive incorrect HCS patterns are found. In such an event a transition is made back to the HUNT state. The state diagram of the cell delineation process is shown in Figure 10.

Figure 10 - Cell delineation State Diagram

Correct HCS

bit by bit

HUNT

Inc o r r e c t HCS

ce ll by cell

ALPHA co nsecutive inc o r r ec t HCS's

ce ll by cell

SYNC

PRESYNC

DELTA consecutive correct H CS 's

ce ll by cell

The values of ALPHA and DELTA determine the robustness of the delineation method. ALPHA determines the robustness against false misalignments due to bit errors. DELTA determines the robustness against false delineation in the

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synchronization process. ALPHA is chosen to be 7 and DELTA is chosen to be 6 as recommended in ITU-T Recommendation I.432. These values result in a maximum average time to frame of 127 µs for a DS3 stream carrying ATM cells directly mapped into the DS3 information payload.

Loss of cell delineation (LCD) is detected by counting the number of incorrect cells while in the HUNT state. The counter value is stored in the RXCP-50 LCD Count Threshold register. The threshold has a default value of 360 which results in a DS3 application detection time of 3.5 ms, an E3 G.832 application detection time of 4.5 ms, and E3 G.751 application detection time of 5.0 ms, a J2 application time of 24.8ms, an E1 application detection time of 77 ms, and a DS1 application detection time of 100 ms. If the counter value is set to zero, the LCD output signal is asserted for every incorrect cell.

9.9 RXCP-50 Receive Cell Processor

The Receive Cell Processor (RXCP-50) Block integrates circuitry to support scrambled or unscrambled cell payloads, scrambled or unscrambled cell headers, header check sequence (HCS) verification, idle cell filtering, and performance monitoring.

The RXCP-50 operates upon a delineated cell stream. For PLCP based transmissions systems, cell delineation is performed by the SPLR. For nonPLCP based transmission systems, cell delineation is performed by the ATMF. Framing status indications from these blocks ensure that cells are not written to the RXFF while the SPLR is in the loss of frame state, or cells are not written to the RXFF while the ATMF is in the HUNT or PRESYNC states.

The RXCP-50 descrambles the cell payload field using the self synchronizing descrambler with a polynomial of x43 + 1. The header portion of the cells can optionally be descrambled also. Note that cell payload scrambling is enabled by default in the S/UNI-QJET as required by ITU-T Recommendation I.432, but may be disabled to ensure backwards compatibility with older equipment.

The HCS is a CRC-8 calculation over the first 4 octets of the ATM cell header. The RXCP-50 verifies the received HCS using the accumulation polynomial, x8 + x2 + x + 1. The coset polynomial x6 + x4 + x2 + 1 is added (modulo 2) to the received HCS octet before comparison with the calculated result as required by the ATM Forum UNI specification, and ITU-T Recommendation I.432.

The RXCP-50 can be programmed to drop all cells containing an HCS error or to filter cells based on the HCS and the cell header. Filtering according to a particular HCS and the GFC, PTI, and CLP bits of the ATM cell header (the VCI and VPI bits must be all logic 0) is programmable through the RXCP-50 registers.

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More precisely, filtering is performed when filtering is enabled or when HCS errors are found when HCS checking is enabled. Otherwise, all cells are passed on regardless of any error conditions. Cells can be blocked if the HCS pattern is invalid or if the filtering 'Match Pattern' and 'Match Mask' registers are programmed with a certain blocking pattern. ATM Idle cells are filtered by default. For ATM cells, Null cells (Idle cells) are identified by the standardized header pattern of 'H00, 'H00, 'H00 and 'H01 in the first 4 octets followed by the valid HCS octet.

While the cell delineation state machine is in the SYNC state, the HCS verification circuit implements the state machine shown in Figure 11.

In normal operation, the HCS verification state machine remains in the 'Correction' state. Incoming cells containing no HCS errors are passed to the receive FIFO. Incoming single-bit errors are corrected, and the resulting cell is passed to the FIFO. Upon detection of a single-bit error or a multi-bit error, the state machine transitions to the 'Detection' state.

A programmable hysteresis is provided when dropping cells based on HCS errors. When a cell with an HCS error is detected, the RXCP-50 can be programmed to continue to discard cells until m (where m = 1, 2, 4, 8) cells are received with a correct HCS. The mth cell is not discarded (see Figure 11). Note that the dropping of cells due to HCS errors only occurs while the ATMF is in the SYNC state.

Cell delineation can optionally be disabled, allowing the RXCP-50 to pass all data bytes it receives.

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Figure 11 - HCS Verification State Diagram

ATM DELINEATION

No Erro rs

Detected

(Pa ss C e ll)

SYNC STATE

CORRECTIO N

MODE

Ap p a rent M ulti-Bit E rror

(Dro p C e ll)

Single Bit Error

(Co rre c t error and pass cell)

DETECTIO N

MODE

Drop Cell

ALPHA cons e c utive incorrect HCS's (To HUNT state)

DELTA consecutive correct HCS's (From P R E S Y N C state)

(M = 1, 2, 4, or 8) consecutiv e cells

9.10 RXFF Receive FIFO

The Receive FIFO (RXFF) provides FIFO management and the S/UNI-QJET receive cell interface. The receive FIFO contains four cells. The FIFO provides the cell rate decoupling function between the transmission system physical layer and the ATM layer.

In general, the management functions include filling the receive FIFO, indicating when the receive FIFO contains cells, maintaining the receive FIFO read and write pointers, and detecting FIFO overrun and underrun conditions.

The FIFO interface is “UTOPIA Level 2" compliant and accepts a read clock (RFCLK) and read enable signal (RENB). The receive FIFO output bus (RDAT[15:0]) is tri-stated when RENB is logic 1 or if the PHY device address (RADR[4:0]) selected does not match this device's address. The interface indicates the start of a cell (RSOC) and the receive cell available status (RCA and DRCA[4:1]) when data is read from the receive FIFO (using the rising edges

No Erro rs De te c te d in M

(Pass Last Cell)

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of RFCLK). The RCA (and DRCA[x]) status changes from available to unavailable when the FIFO is either empty (RCALEVEL0=1) or near empty (RCALEVEL0 is logic 0). This interface also indicates FIFO overruns via a maskable interrupt and register bits. Read accesses while RCA (or DRCA[x]) is a logic 0 will output invalid data.

9.11 CPPM Cell and PLCP Performance Monitor

The Cell and PLCP Performance Monitor (CPPM) Block interfaces directly to the SPLR to accumulate bit interleaved parity error events, framing octet error events, and far end block error events in saturating counters. When the PLCP framer (SPLR) declares loss of frame, bit interleaved parity error events, framing octet error events, far end block error events, header check sequence error events are not counted.

When an accumulation interval is signaled by a write to the CPPM register address space or to the S/UNI-QJET Identification, Master Reset, and Global Monitor Update register, the CPPM transfers the current counter values into holding registers and resets the counters to begin accumulating error events for the next interval. The counters are reset in such a manner that error events occurring during the reset period are not missed.

9.12 PRGD Pseudo-Random Sequence Generator/Detector

The Pseudo-Random Sequence Generator/Detector (PRGD) block is a software programmable test pattern generator, receiver, and analyzer. Two types of test patterns (pseudo-random and repetitive) conform to ITU-T O.151.

The PRGD can be programmed to generate any pseudo-random pattern with length up to 232-1 bits or any user programmable bit pattern from 1 to 32 bits in length. In addition, the PRGD can insert single bit errors or a bit error rate

between 10-1 to 10-7. The PRGD can be programmed to check for the presence of the generated

pseudo-random pattern. The PRGD can perform an auto-synchronization to the expected pattern, and generate interrupts on detection and loss of the specified pattern. The PRGD can accumulate the total number of bits received and the total number of bit errors in two saturating 32-bit counters. The counters accumulate over an interval defined by writes to the S/UNI-QJET Identification/Master Reset, and Global Monitor Update register (register 006H) or by writes to any PRGD accumulation register. When an accumulation is forced by either method, then the holding registers are updated, and the counters reset to begin accumulating for the next interval. The counters are reset in such a way

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that no events are missed. The data is then available in the holding registers until the next accumulation. In addition to the two counters, a record of the 32 bits received immediately prior to the accumulation is available.

The PRGD may also be programmed to check for repetitive sequences. When configured to detect a pattern of length N bits, the PRGD will load N bits from the detected stream, and determine whether the received pattern repeats itself every N subsequent bits. Should it fail to find such a pattern, it will continue loading and checking until it finds a repetitive pattern. All the features (error counting, auto-synchronization, etc.) available for pseudo-random sequences are also available for repetitive sequences. Whenever a PRGD accumulation is forced, the PRGD stores a snapshot of the 32 bits received immediately prior to the accumulation. This snapshot may be examined in order to determine the exact nature of the repetitive pattern received by PRGD.

The pseudo-random or repetitive pattern can be inserted/extracted in the PLCP payload (if PLCP framing is enabled) or in the DS3, E3, J2, or Arbitrary framing format payload (if PLCP framing is disabled). It cannot be inserted into the ATM cell payload.

9.13 DS3 T ransmitter

The DS3 Transmitter (T3-TRAN) Block integrates circuitry required to insert the overhead bits into a DS3 bit stream and produce a B3ZS-encoded signal. The T3-TRAN is directly compatible with the M23 and C-bit parity DS3 formats.

Status signals such as far end receive failure (FERF), the alarm indication signal, and the idle signal can be inserted when their transmission is enabled by internal register bits. FERF can also be automatically inserted on detection of any combination of LOS, OOF or RED, or AIS by the T3-FRMR.

A valid pair of P-bits is automatically calculated and inserted by the T3-TRAN. When C-bit parity mode is selected, the path parity bits, and far end block error (FEBE) indications are automatically inserted.

When enabled for C-bit parity operation, the FEAC channel is sourced by the XBOC bit-oriented code transmitter. The path maintenance data link messages are sourced by the TDPR data link transmitter. These overhead signals can also be overwritten by using the TOH[x] and TOHINS[x] inputs.

When enabled for M23 operation, the C-bits are forced to logic 1 with the exception of the C-bit Parity ID bit (first C-bit of the first M-subframe), which is forced to toggle every M-frame.

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The T3-TRAN supports diagnostic modes in which it inserts parity or path parity errors, F-bit framing errors, M-bit framing errors, invalid X or P-bits, line code violations, or all-zeros.

User control of each of the overhead bits in the DS3 frame is provided. Overhead bits may be inserted on a bit-by-bit basis from a user supplied data stream. An overhead clock (at 526 kHz) and a DS3 overhead alignment output are provided to allow for control of the user provided stream.

9.14 E3 T ransmitter

The E3 Transmitter (E3-TRAN) Block integrates circuitry required to insert the overhead bits into an E3 bit stream and produce an HDB3-encoded signal. The E3-TRAN is directly compatible with the G.751 and G.832 framing formats.

The E3-TRAN generates the frame alignment signal and inserts it into the incoming serial stream based on either the G.751 or G.832 formats and an alignment pulse applied to it by the SPLT block. All overhead and status bits in each frame format can be individually controlled by register bits or by the transmit overhead stream. While in certain framing format modes, the E3-TRAN generates various overhead bytes according to the following:

In G.832 E3 format, the E3-TRAN:

• inserts the BIP-8 byte calculated over the preceding frame;

• inserts the Trail Trace bytes through the Trail Trace Buffer (TTB) block;

• inserts the FERF bit via a register bit or, optionally, when the E3-FRMR

declares OOF, or when the loss of cell delineation (LCD) defect is declared;

• inserts the FEBE bit, which is set to logic 1 when one or more BIP-8 errors

are detected by the receive framer. If there are no BIP-8 errors indicated by the E3-FRMR, the E3-TRAN sets the FEBE bit to logic 0;

• inserts the Payload Type bits based on the register value set by the

microprocessor;

• inserts the Tributary Unit multiframe indicator bits either via the TOH overhead

stream or by register bit values set by the microprocessor;

• inserts the Timing Marker bit via a register bit;

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inserts the Network Operator (NR) byte from the TDPR block when the

• TNETOP bit in the S/UNI-QJET Data Link and FERF Control register is logic 1; otherwise, the NR byte is set to all ones. The NR byte can be overwritten by using the TOH[x] and TOHINS[x] input pins. All 8 bits of the Network Operator byte are available for use as a datalink;

inserts the General Purpose Communication Channel (GC) byte from the

• TDPR block when the TNETOP bit in the S/UNI-QJET Data Link and FERF Control register is logic 0; otherwise, the byte is set to all ones. The GC byte can be overwritten by using the TOH[x] and TOHINS[x] input pins.

In G.751 E3 mode, the E3-TRAN :

inserts the Remote Alarm Indication bit (bit 11 of the frame) either via a

• register bit or, optionally, when the E3-FRMR declares OOF;

inserts the National Use reserved bit (bit 12 of the frame) either as a fixed

• value through a register bit or from the TDPR block as configured by the TNETOP bit in the S/UNI-QJET Data Link and FERF Control register and the NATUSE bit in the E3 TRAN Configuration register;

optionally identifies the tributary justification bits and stuff opportunity bits as

• either overhead or payload to SPLT for payload mappings that take advantage of the full bandwidth.

Further, the E3-TRAN can provide insertion of bit errors in the framing pattern or in the parity bits, and insertion of single line code violations for diagnostic purposes. Most of the overhead bits can be overwritten by using the TOH[x] and TOHINS[x] input pins.

9.15 J2 T ransmitter

The J2 Transmitter (J2-TRAN) Block integrates circuitry required to insert the overhead bits into an J2 bit stream and produce a B8ZS-encoded signal. The J2-TRAN is directly compatible with the framing format specified in G.704 and NTT Technical Reference for High-Speed Digital Leased Circuit Services.

The J2-TRAN generates the frame alignment signal and inserts it into the incoming serial stream. All overhead and status bits in each frame format can be individually controlled by either register bits or by the transmit overhead stream.

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The J2-TRAN:

insert s the CRC-5 bits calculated over the preceding multiframe;

• inserts the x-bits through microprocessor programmable register bits;

• inserts the a-bit through a microprocessor programmable register bit;

• inserts the m-bit data link through the TDPR block;

• inserts payload AIS or physical layer AIS through microprocessor

• programmable register bits;

inserts RAI over the m-bits, overwriting HDLC frames, by using the XBOC

• block or through automatic activation upon detection of certain remote alarm conditions.

The J2-TRAN allows overwriting of any of the overhead bits by using the TOH[x], TOHINS[x], TOHFP[x], and TOHCLK[x] overhead signals. Further, the J2-TRAN can provide inser t ion of single bit errors in the framing pattern or in the CRC-5 bits, and insertion of single line code violations for diagnostic purposes.

9.16 XBOC Bit Oriented Code Generator

The Bit Oriented Code Generator (XBOC) Block transmits 63 of the possible 64 bit oriented codes (BOC) in the C-bit parity Far End Alar m and Control (FEAC) channel. A BOC is a 16-bit sequence consisting of 8 ones, a zero, 6 code bits, and a trailing zero (111111110xxxxxx0) which is repeated as long as the code is not 111111. The code to be transmitted is programmed by writing the XBOC

Code Register. The 64th code (111111) is similar to the HDLC idle sequence and is used to disable the transmission of any bit oriented codes. When transmission is disabled, the FEAC channel is set to all ones.

9.17 TDPR Facility Data Link Transmitter

The Facility Data Link Transmitter (TDPR) provides a serial data link for the C-bit parity path maintenance data link in DS3, the serial Network Operator byte or the General Purpose datalink in G.832 E3, the National Use bit datalink in G.751 E3, or the m-bit datalink in J2. The TDPR is used under microprocessor control to transmit HDLC data frames. It performs all of the data serialization, CRC generation, zero-bit stuffing, as well as flag, and abort sequence insertion. Upon completion of the message, a CRC-CCITT frame check sequence (FCS) can be

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appended, followed by flags. If the TDPR transmit data FIFO underflows, an abort sequence is automatically transmitted.

When enabled, the TDPR continuously transmits flags (01111110) until data is ready to be transmitted. Data bytes to be transmitted are written into the TDPR Transmit Data Register. The TDPR automatically begins transmission of data once at least one complete packet is written into its FIFO. All complete packets of data will be transmitted if no error condition occurs. After the last data byte of a packet, the CRC FCS (if CRC insertion has been enabled) and a flag, or just a flag (if CRC insertion has not been enabled) is transmitted. The TDPR then returns to the transmission of flag characters until the next packet is available for transmission. The TDPR will also force transmission of the FIFO data once the FIFO depth has surpassed the programmable upper limit threshold. Transmission commences regardless of whether or not a packet has been completely written into the FIFO. The user must be careful to avoid overfilling the FIFO. Underruns can only occur if the packet length is greater than the programmed upper limit threshold because, in such a case, transmission will begin before a complete packet is stored in the FIFO.

An interrupt can be generated once the FIFO depth has fallen below a user configured lower threshold as an indicator for the user to write more data. Interrupts can also be generated if the FIFO underflows while transmitting a packet, when the FIFO is full, or if the FIFO is overr un.

If there are more than five consecutive ones in the raw transmit data or in the CRC data, a zero is stuffed into the serial data output. This prevents the unintentional transmission of flag or abort sequences.

Abort sequences (01111111 sequence where the 0 is transmitted first) can be continuously transmitted at any time by setting a control bit. During packet transmission, an underrun situation can occur if data is not written to the TDPR Transmit Data register before the previous byte has been depleted. In this case, an abort sequence is transmitted, and the controlling processor is notified via the UDR register bit. An abort sequence will also be transmitted if the user overflows the FIFO with a packet of length greater than 128 bytes. Overflows where other complete packets are still stored in the FIFO will not generate an abort. Only the packet which caused the overflow is corrupted and an interrupt is generated to the user via the OVR register bit. The other packets remain unaffected.

When the TDPR is disabled, a logical 1 (Idle) is inserted in the path maintenance data link.

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9.18 SPLT SMDS PLCP Layer Transmitter

The SMDS PLCP Layer Transmitter (SPLT ) Block integrates circuitry to support DS1, DS3, E1, and G.751 E3 based PLCP frame insertion.

The SPLT automatically inserts the framing (A1, A2) and path overhead identification (POHID) octets and provides registers or automatic generation of the F1, B1, G1, M2, M1 and C1 octets.

Registers are provided for the path user channel octet (F1) and the path status octet (G1). The bit interleaved parity octet (B1) and the FEBE subfield are automatically inserted.

The DQDB management information octets, M1 and M2 are generated. The type 0 and type 1 patterns described in TA-TSY-000772 are automatically inserted. The type 1 page counter may be reset using a register bit in the SPLT Configuration register. Note that this feature is not required for the ATM Forum compliant DS3 UNI. For this application, the M1 and M2 octets must be set to all zeros.

The PLCP transmit frame C1 cycle/stuff counter octet and the transmit stuffing pattern can be referenced to the REF8KI input pin. Alternately, a fixed stuffing pattern may be inserted into the C1 cycle/stuff counter octet. A looped timing operating mode is provided where the transmit PLCP timing is derived from the received timing. In this mode, the C1 stuffing is generated based on the received stuffing pattern as determined by the SPLR block. When DS1 or E1 PLCP format is enabled, the pattern 00H is inserted.

When DS3 PLCP format is enabled, the C1 octet indicates the phase of the 375 µs nibble stuffing opportunity cycle. During frame one of the three frame cycle, the pattern FFH is inserted in the C1 octet, indicating a 13 nibble trailer length. During frame two, the pattern 00H is inserted, indicating a 14 nibble trailer length. During frame three, the pattern 66H or 99H is inserted, indicating a 13 or 14 nibble trailer length respectively.

When configured for G.751 E3 PLCP frame format, the C1 octet is used to indicate the number of octets stuffed in the trailer. The following table shows the C1 octet pattern for each of the possible octet stuff lengths:

Stuff Length C1(Hex)

17 3B

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Stuff Length C1(Hex)

18 4F 19 75 20 9D 21 A7

The SPLT block generates a stuff length pattern of 18, 19 or 20 octets determined by the phase alignment of the start of the G.751 E3 frame and the start of the E3 PLCP frame. The REF8KI input is provisioned to loop time the PLCP transmit frame to an externally applied 8 kHz reference.

The Zn, growth octets are set to 00H. The Zn octets may be inserted from an external device via the path overhead stream input, TPOH.

9.19 TXCP-50 Transmit Cell Processor

The Transmit Cell Processor (TXCP-50) Block integrates circuitry to support ATM cell payload scrambling, header check sequence (HCS) generation, and idle/unassigned cell generation.

The TXCP-50 scrambles the cell payload field using the self synchronizing scrambler with polynomial x43 + 1. The header portion of the cells may optionally also be scrambled. Note that cell payload scrambling may be disabled in the S/UNI-QJET, though it is required by ITU-T Recommendation I.432. The ATM Forum DS3 UNI specification requires that cell payloads are scrambled for the DS3 physical layer interface. However, to ensure backwards compatibility with older equipment, the payload scrambling may be disabled.

The HCS is generated using the polynomial, x8 + x2 + x + 1. The coset polynomial x6 + x4 + x2 + 1 is added (modulo 2) to the calculated HCS octet as required by the ATM Forum UNI specification, and ITU-T Recommendation I.432. The resultant octet optionally overwrites the HCS octet in the transmit cell. When the transmit FIFO is empty, the TXCP-50 inserts idle/unassigned cells. The idle/unassigned cell header is fully programmable using five internal registers. Similarly, the 48 octet information field is programmed with an 8 bit repeating pattern using an internal register.

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Datasheet PM7346 Datasheet (PMC)

Specifications and Main Features

Frequently Asked Questions

User Manual