Datasheet PM7341 Datasheet (PMC)

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PRELIMINARY

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DATASHEET

PMC-2000223 ISSUE 4 INVERSE MULTIPLEXING OVER ATM

PM7341 S/UNI-IMA-84

PM7341

S/UNI-IMA-84

S/UNI INVERSE MULTIPLEXING FOR

ATM, 84 LINKS

DATASHEET

PROPRIETARY AND CONFIDENTIAL

PRELIMINARY

ISSUE 4: JULY 2001

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE iii

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PM7341 S/UNI-IMA-84

REVISION HISTORY

Issue

Issue Date Details of Change

No.

1 February,

2000

2 March, 2000

3 February,

2001

4 July, 2001

Creation of Document.

Added details in Register Section, Functional Description, Operations and D.C. characteristics. Added details in interrupt reporting structure, SBI async/sync support clarified. Increased number of TADR pins to 11 for glueless interconnect to the S/UNIAPEX. Rearranged IMA context and configuration tables. Added capability to add/delete delay from active groups. Additional detailed added.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE iv

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1 DEFINITIONS ........................................................................................ 23

2 FEATURES ............................................................................................ 25

3 APPLICATIONS ..................................................................................... 31

4 REFERENCES....................................................................................... 32

5 APPLICATION EXAMPLES ................................................................... 33

5.1 ATM MULTISERVICE SWITCH IMA / UNI PORT CARD............. 33

5.2 ATM MULTISERVICE SWITCH, ANY SERVICE ANY PORT CARD

.................................................................................................... 33

6 BLOCK DIAGRAM ................................................................................. 35

7 DESCRIPTION....................................................................................... 36

8 PIN DIAGRAM ....................................................................................... 39

9 PIN DESCRIPTION................................................................................ 41

9.1 RECEIVE SLAVE ATM INTERFACE (ANY-PHY MODE) (28

SIGNALS).................................................................................... 41

9.2 RECEIVE SLAVE ATM INTERFACE (UTOPIA L2 MODE) (26

SIGNALS).................................................................................... 44

9.3 TRANSMIT SLAVE INTERFACE (ANY-PHY MODE) (34 SIGNALS)46

9.4 TRANSMIT SLAVE INTERFACE (UTOPIA L2 MODE) (26

SIGNALS).................................................................................... 49

9.5 MICROPROCESSOR INTERFACE (31 SIGNALS)..................... 51

9.6 SDRAM I/F (35 SIGNALS) .......................................................... 53

9.7 CLK/DATA (129 SIGNALS).......................................................... 56

9.8 SBI INTERFACE SIGNALS (27).................................................. 60

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9.9 GENERAL (5 SIGNALS) ............................................................. 65

9.10 JTAG & SCAN INTERFACE (7 SIGNALS) .................................. 67

9.11 POWER (120 SIGNALS)............................................................. 68

10 FUNCTIONAL DESCRIPTION............................................................... 71

10.1 ANY-PHY/UTOPIA INTERFACES ............................................... 71

10.1.1 TRANSMIT ANY-PHY/UTOPIA SLAVE (TXAPS).............. 72

10.1.2 RECEIVE ANY-PHY/UTOPIA SLAVE (RXAPS)................ 75

10.1.3 SUMMARY OF ANY-PHY/UTOPIA MODES..................... 79

10.1.4 ANY-PHY/UTOPIA LOOPBACK ....................................... 81

10.2 IMA SUB-LAYER ......................................................................... 81

10.2.1 OVERVIEW ...................................................................... 81

10.2.2 IDCC SCHEDULER.......................................................... 82

10.2.3 TRANSMIT IMA PROCESSOR (TIMA) ............................ 83

10.2.4 RECEIVE IMA DATA PROCESSOR (RDAT) .................... 87

10.2.5 RECEIVE IMA PROTOCOL PROCESSOR (RIPP) ........ 100

10.2.6 SUPPORT OF IMA TEST PATTERN PROCEDURE ....... 111

10.2.7 SUPPORT OF SYMMETRIC/ASYMMETRIC OPERATION

MODES ...........................................................................111

10.2.8 SUPPORT OF DIFFERENT IMA VERSIONS ..................111

10.2.9 SDRAM INTERFACE.......................................................112

10.3 LINK FIFOS................................................................................115

10.4 TC LAYER ..................................................................................115

10.4.1 TX TC LAYER (TTTC) .....................................................115

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10.4.2 RX TC LAYER (RTTC).....................................................116

10.5 LINE SIDE PHYSICAL LAYER ...................................................118

10.5.1 TX CLOCK/DATA (TCAS)................................................118

10.5.2 TX NULL FRAMER (SDFR84).........................................119

10.5.3 INSERT SCALEABLE BANDWIDTH INTERCONNECT

(INSBI).............................................................................119

10.5.4 EXTRACT SCALEABLE BANDWIDTH INTERCONNECT

(EXSBI)............................................................................119

10.5.5 RX DEFRAMER (SDDF84) ............................................ 120

10.5.6 RX CLOCK/DATA (RCAS) .............................................. 120

10.6 MICROPROCESSOR INTERFACE .......................................... 121

10.6.1 MAPPING AND LINK IDENTIFICATION......................... 121

10.6.2 INTERRUPT DRIVEN ERROR/STATUS REPORTING .. 123

10.6.3 REGISTERS................................................................... 124

11 NORMAL MODE REGISTER DESCRIPTION ..................................... 131

11.1 GLOBAL REGISTERS .............................................................. 132

11.2 MASTER INTERRUPT REGISTERS ........................................ 137

11.3 UTOPIA INTERFACE REGISTERS .......................................... 147

11.4 SDRAM REGISTERS................................................................ 156

11.5 TC LAYER REGISTERS ........................................................... 166

11.6 SBI REGISTERS....................................................................... 177

11.7 LINE CLOCK/DATA INTERFACE .............................................. 203

11.8 RIPP REGISTERS .................................................................... 217

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11.9 RDAT REGISTERS ................................................................... 292

11.10 TIMA REGISTERS .................................................................... 325

11.11 TX IDCC REGISTERS .............................................................. 341

11.12 RX IDCC REGISTERS.............................................................. 347

12 OPERATION ........................................................................................ 351

12.1 HARDWARE CONFIGURATION............................................... 351

12.2 START-UP................................................................................. 351

12.3 CONFIGURING THE S/UNI-IMA-84.......................................... 352

12.3.1 CONFIGURING SBI INTERFACE .................................. 352

12.3.2 CONFIGURING CLOCK/DATA INTERFACE.................. 354

12.3.3 CONFIGURING TC LAYER OPTIONS........................... 356

12.3.4 UTOPIA INTERFACE CONFIGURATION....................... 357

12.4 IMA_LAYER CONFIGURATION................................................ 358

12.4.1 INDIRECT ACCESS TO INTERNAL MEMORY TABLES 358

12.4.2 CONFIGURING LINKS FOR TRANSMISSION

CONVERGENCE OPERATIONS ................................... 359

12.4.3 CONFIGURING FOR IMA OPERATIONS ...................... 361

12.5 IMA OPERATIONS.................................................................... 365

12.5.1 ISSUING A RIPP COMMAND......................................... 365

12.5.2 SUMMARY OF RIPP COMMANDS ................................ 366

12.5.3 ADDING A GROUP......................................................... 371

12.5.4 DELETING A GROUP..................................................... 372

12.5.5 RESTART GROUP ......................................................... 372

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12.5.6 INHIBIT GROUP/NOT INHIBIT GROUP......................... 373

12.5.7 ADDING A LINK OR LINKS TO AN EXISTING GROUP

(START LASR) ............................................................... 373

12.5.8 REPORTING LINK DEFECTS IN THE ICP CELL .......... 374

12.5.9 FAULTING/INHIBITING LINKS ...................................... 374

12.5.10 CHANGE TRL............................................................ 374

12.5.11 DELETING A LINK FROM A GROUP......................... 375

12.5.12 TEST PATTERN PROCEDURES .............................. 375

12.5.13 IMA EVENTS ............................................................. 375

12.5.14 END-TO-END CHANNEL COMMUNICATION........... 376

12.6 DIAGNOSTIC FEATURES ........................................................ 376

12.6.1 ICP CELL TRACE........................................................... 376

12.6.2 SDRAM DIAGNOSTIC ACCESS.................................... 377

12.7 IMA PERFORMANCE PARAMETERS AND FAILURE ALARMS

SUPPORT................................................................................. 378

13 FUNCTIONAL TIMING......................................................................... 382

13.1 SBI DROP BUS INTERFACE TIMING ...................................... 382

13.2 SBI ADD BUS INTERFACE TIMING ......................................... 383

13.3 RECEIVE LINK INPUT TIMING................................................. 384

13.4 TRANSMIT LINK OUTPUT TIMING .......................................... 385

13.5 ANY-PHY/UTOPIA L2 INTERFACES ........................................ 388

13.5.1 UTOPIA L2 TRANSMIT SLAVE INTERFACE................. 388

13.5.2 ANY-PHY TRANSMIT SLAVE INTERFACE.................... 389

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13.5.3 UTOPIA L2 MULTI-PHY RECEIVE SLAVE INTERFACE 390

13.5.4 UTOPIA L2 SINGLE-PHY RECEIVE SLAVE INTERFACE

391

13.5.5 ANY-PHY RECEIVE SLAVE INTERFACE ...................... 392

13.6 SDRAM INTERFACE ................................................................ 392

14 ABSOLUTE MAXIMUM RATINGS ....................................................... 397

15 D. C. CHARACTERISTICS .................................................................. 398

16 A.C. TIMING CHARACTERISTICS...................................................... 401

16.1 MICROPROCESSOR INTERFACE TIMING CHARACTERISTICS

.................................................................................................. 401

16.2 SYNCHRONOUS I/O TIMING................................................... 405

16.3 SBI TIMING ............................................................................... 409

16.4 JTAG TIMING............................................................................ 412

17 ORDERING AND THERMAL INFORMATION...................................... 414

18 MECHANICAL INFORMATION ............................................................ 415

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LIST OF FIGURES

FIGURE 1 - ATM EDGE SWITCH IMA AND UNI PORT CARD EXAMPLE ..... 33

FIGURE 2 - ATM MULTISERVICE SWITCH, ANY SERVICE ANY PORT CARD EXAMPLE 34

FIGURE 3 - S/UNI-IMA-84 BLOCK DIAGRAM................................................ 35

FIGURE 4 - S/UNI-IMA PINOUT (BOTTOM VIEW)......................................... 40

FIGURE 5 - 16-BIT TRANSMIT CELL TRANSFER FORMAT ......................... 74

FIGURE 6 - 8-BIT TRANSMIT CELL TRANSFER FORMAT ........................... 74

FIGURE 7 - 16-BIT RECEIVE CELL TRANSFER FORMAT............................ 78

FIGURE 8 - 8-BIT RECEIVE CELL TRANSFER FORMAT.............................. 78

FIGURE 9 - INVERSE MULTIPLEXING .......................................................... 82

FIGURE 10- MAX DIFFERENTIAL DELAY TOLERANCE VS. SDRAM SIZE .. 88

FIGURE 11 - IFSM STATE MACHINE............................................................... 89

FIGURE 12- STUFF EVENT WITH ERRORED ICP (ADVANCED INDICATION)

FIGURE 13- INVALID STUFF SEQUENCE (ADVANCED INDICATION) ......... 91

FIGURE 14- ERRORED/INVALID ICP CELLS IN PROXIMITY TO A STUFF EVENT 92

FIGURE 15- SNAPSHOT OF DCB BUFFERS................................................. 93

FIGURE 16- SNAPSHOT OF DCB BUFFERS AFTER ADDITION OF LINK WITH

SMALLER TRANSPORT DELAY...................................................................... 94

FIGURE 17- SNAPSHOT OF DCB BUFFERS WHEN TRYING TO ADD LINK

WITH LARGER TRANSPORT DELAY.............................................................. 95

FIGURE 18- SNAPSHOT OF DCB BUFFERS AFTER DELAY ADJUSTMENT 96

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FIGURE 19- SNAPSHOT OF DCB BUFFERS AFTER DELETION OF LINKS FROM GROUP 97

FIGURE 20- IMA ERROR/MAINTENANCE STATE DIAGRAM ........................ 98

FIGURE 21- CELL STORAGE MAP................................................................112

FIGURE 22- 2 MBYTE ....................................................................................113

FIGURE 23- 8 MBYTE ....................................................................................114

FIGURE 24- CELL DELINEATION STATE DIAGRAM.....................................117

FIGURE 25-BURST RAM FORMAT............................................................... 161

FIGURE 26- SBI DROP BUS T1/E1 FUNCTIONAL TIMING.......................... 382

FIGURE 27- SBI DROP BUS DS3 FUNCTIONAL TIMING ............................ 382

FIGURE 28- SBI ADD BUS ADJUSTMENT REQUEST FUNCTIONAL TIMING

383

FIGURE 29- UNCHANNELIZED RECEIVE LINK TIMING ............................. 384

FIGURE 30- CHANNELIZED T1 RECEIVE LINK TIMING ............................. 385

FIGURE 31- CHANNELIZED E1 RECEIVE LINK TIMING ............................. 385

FIGURE 32- UNCHANNELIZED TRANSMIT LINK TIMING........................... 386

FIGURE 33- CHANNELIZED T1 TRANSMIT LINK TIMING W/ CLOCK GAPPED LOW 386

FIGURE 34- CHANNELIZED T1 TRANSMIT LINK TIMING W/ CLOCK GAPPED HIGH 387

FIGURE 35- CHANNELIZED E1 TRANSMIT LINK TIMING W/ CLOCK GAPPED LOW 387

FIGURE 36- CHANNELIZED E1 TRANSMIT LINK TIMING W/ CLOCK GAPPED HIGH 387

FIGURE 37- UTOPIA L2 TRANSMIT SLAVE ................................................. 389

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FIGURE 38- ANY-PHY TRANSMIT SLAVE .................................................... 390

FIGURE 39- UTOPIA L2 MULTI-PHY RECEIVE SLAVE................................ 391

FIGURE 40- UTOPIA L2 SINGLE-PHY RECEIVE SLAVE ............................. 391

FIGURE 41- ANY-PHY RECEIVE SLAVE ...................................................... 392

FIGURE 42- SDRAM READ TIMING ............................................................. 393

FIGURE 43- SDRAM WRITE TIMING............................................................ 394

FIGURE 44- SDRAM REFRESH.................................................................... 395

FIGURE 45- POWER UP AND INITIALIZATION SEQUENCE ....................... 396

FIGURE 46- MICROPROCESSOR INTERFACE READ TIMING................... 402

FIGURE 47- MICROPROCESSOR INTERFACE WRITE TIMING ................. 404

FIGURE 48- RSTB TIMING............................................................................ 405

FIGURE 49- SYNCHRONOUS I/O TIMING ................................................... 405

FIGURE 50- SBI FRAME PULSE TIMING ..................................................... 409

FIGURE 51- SBI DROP BUS TIMING............................................................ 410

FIGURE 52- SBI ADD BUS TIMING................................................................411

FIGURE 53- SBI ADD BUS COLLISION AVOIDANCE TIMING ......................411

FIGURE 54- JTAG PORT INTERFACE TIMING............................................. 413

FIGURE 55- 416 PIN PBGA –27X27 MM BODY – (P SUFFIX) ..................... 415

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LIST OF TABLES

TABLE 1 TERMINOLOGY............................................................................. 23

TABLE 2 UTOPIA L2 AND ANY-PHY COMPARISON ................................... 76

TABLE 3 PM COMMAND DESCRIPTION .................................................. 101

TABLE 4 REGISTER MEMORY MAP......................................................... 125

TABLE 5 CONFIGURATION MEMORY ADDRESS SPACE ....................... 218

TABLE 6 CONTEXT MEMORY ADDRESS SPACE .................................... 219

TABLE 7 RIPP GROUP CONFIGURATION RECORD STRUCTURE ........ 221

TABLE 8 RX PHYSICAL LINK TABLE ........................................................ 229

TABLE 9 RIPP TX LINK CONFIGURATION RECORD STRUCTURE ........ 230

TABLE 10 RIPP RX LINK CONFIGURATION RECORD STRUCTURE........ 232

TABLE 11 RIPP GROUP CONTEXT RECORD STRUCTURE ..................... 234

TABLE 12 RIPP TX LINK CONTEXT RECORD STRUCTURE..................... 249

TABLE 13 RIPP RX LINK CONTEXT RECORD STRUCTURE .................... 253

TABLE 14 COMMAND REGISTER ENCODING........................................... 271

TABLE 15 COMMAND DATA REGISTER ARRAY FORMAT ........................ 282

TABLE 16 GROUP ERROR/STATUS BIT MAPPING ................................... 284

TABLE 17 LINK EVENT INTERRUPT BIT MAPPING................................... 286

TABLE 18 LINK STATUS BIT MAPPING ...................................................... 288

TABLE 19 RECEIVE ICP CELL BUFFER STRUCTURE .............................. 290

TABLE 20 RDAT LINK STATISTICS RECORD (IMA) ................................... 297

TABLE 21 RDAT LINK STATISTICS RECORD (TC)..................................... 298

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TABLE 22 RDAT IMA GROUP STATISTICS RECORD................................. 299

TABLE 23 RDAT TC LINK STATISTICS RECORD ....................................... 300

TABLE 24 RDAT VALIDATION RECORD ..................................................... 301

TABLE 25 RDAT LINK CONTEXT RECORD................................................ 304

TABLE 26 RDAT LINK MESSAGE STATUS RECORD................................. 309

TABLE 27 RECEIVE ICP CELL BUFFER STRUCTURE .............................. 310

TABLE 28 RDAT IMA GROUP CONTEXT RECORD.................................... 312

TABLE 29 RDAT TC LINK CONTEXT RECORD .......................................... 314

TABLE 30 RECEIVE ATM CONGESTION COUNT REGISTER ................... 315

TABLE 31 TRANSMIT IMA GROUP CONTEXT RECORD ........................... 330

TABLE 32 TRANSMIT IMA GROUP CONFIGURATION TABLE RECORD .... 333

TABLE 33 TRANSMIT LID TO PHYSICAL LINK MAPPING TABLE ............. 335

TABLE 34 TIMA PHYSICAL LINK CONTEXT RECORD............................... 336

TABLE 35 REFCLK/SYSCLK FREQUENCY REQUIREMENT..................... 356

TABLE 36 IMA PERFORMANCE PARAMETER SUPPORT......................... 378

TABLE 37 IMA FAILURE ALARM SUPPORT................................................ 379

TABLE 38 ABSOLUTE MAXIMUM RATINGS ............................................... 397

TABLE 39 D.C. CHARACTERISTICS ........................................................... 398

TABLE 40 MICROPROCESSOR INTERFACE READ ACCESS................... 401

TABLE 41 MICROPROCESSOR INTERFACE WRITE ACCESS ................. 403

TABLE 42 RTSB TIMING.............................................................................. 404

TABLE 43 SYSCLK AND REFCLK TIMING.................................................. 405

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TABLE 44 CELL BUFFER SDRAM INTERFACE .......................................... 406

TABLE 45 ANY-PHY/UTOPIA TRANSMIT INTERFACE ............................... 406

TABLE 46 ANY-PHY/UTOPIA RECEIVE INTERFACE.................................. 407

TABLE 47 SERIAL LINK INPUT.................................................................... 407

TABLE 48 SERIAL LINK OUTPUT................................................................ 408

TABLE 49 SBI FRAME PULSE TIMING ....................................................... 409

TABLE 50 SBI DROP BUS TIMING .............................................................. 409

TABLE 51 SBI ADD BUS .............................................................................. 410

TABLE 52 JTAG PORT INTERFACE ............................................................ 412

TABLE 53 ORDERING AND THERMAL INFORMATION.............................. 414

TABLE 54 THERMAL INFORMATION - THETA JA VS. AIRFLOW ............... 414

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LIST OF REGISTERS

147

149

(TXAPS_ADD_CFG) ...................................................................................... 153

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175

(SBI_BUS_CFG_REG)................................................................................... 177

183

184

ACCESS ADDRESS REGISTER.................................................................... 185

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ACCESS CONTROL REGISTER ................................................................... 186

ACCESS DATA REGISTER............................................................................ 187

188

189

194

ACCESS ADDRESS REGISTER.................................................................... 196

ACCESS CONTROL REGISTER ................................................................... 197

ACCESS DATA REGISTER............................................................................ 198

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216

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322

323

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1 DEFINITIONS

Table 1 Terminology

Term Definition

Any-PHY Interoperable version of UTOPIA and UTOPIA L2, with

inband addressing.

ATM Asynchronous Transfer Mode

CDV Cell Delay Variation

CTC Common Transmit Clock

DLL Delay Locked Loop

ECBI Enhanced Common Bus Interface (asynchronous

EXSBI Extract Scalable Bandwidth Interconnect

FIFO First-In-First-Out

Framed Framing information available – may be channelized or

unchannelized.

HEC Header Error Check

HCS Header Check Sequence

ICP IMA Control Protocol Cell

IDCC IMA Data Cell Clock

IDCR IMA Data Cell Rate

IFSN IMA Frame Sequence Number

IMA Inverse Multiplexing for ATM

INSBI Insert Scalable Bandwidth Interconnect

ITC Independent Transmit Clock

LCD Loss of Cell Delineation

LID Link ID

LSI Link Stuff Indication

MIB Management Information Base

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MCFD Multi-Channel Cell Based FIFO

OAM Operation, Administration and Maintenance

OCD Out of Cell Delineation

PISO Parallel in Serial Out

PM Plane Management (Microprocessor)

RCAS Receive Channel Assigner

RDAT RX IMA Data Processor

RIPP RX IMA Protocol Processor

RMTS RX Master TX Slave

SBI Scalable Bandwidth Interconnect

SIPO Serial in Parallel Out

SPE Synchronous Payload Envelope

TC Transmission Convergence

TCAS Transmit Channel Assigner

TDM Time Division Multiplexing

TRL Timing Reference Link

TRLCR TRL Cell Rate

TSB Telecom Systems Block

TC Transmission Convergence

TIMA TX IMA Processor

Unframed No framing information available

UTOPIA Universal Test & Operations PHY Interface for ATM

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2 FEATURES

The PM7341 S/UNI-IMA-84 is a monolithic integrated circuit that implements the ATM Forum Inverse Multiplexing for ATM (IMA 1.1) protocol with backward compatibility to IMA 1.0 and the Transmission Convergence (TC) layer function. The S/UNI-IMA-84 has two line side interface modes that determine the total number of physical links supported: the Scalable Bandwidth Interconnect (SBI) bus interface mode and the Clock and Data interface mode.

In SBI mode, the S/UNI-IMA-84 supports up to 84 T1, 63 E1 or 3 DS3 (TC only) physical links where each link is dynamically configurable to support either IMA

1.1, backward compatible IMA 1.0, ATM over T1/E1 or up to three ATM over DS3 streams (using HEC delineation).

In Clock and Data mode, the S/UNI-IMA-84 supports 32 independent T1, E1 or unchannelized physical links. Each link is dynamically configurable to support either IMA 1.1, backward compatible IMA 1.0, or ATM HEC cell delineation. ATM over fractional T1/E1 is also supported. Unchannelized links may be used to support applications such as G.SHDSL.

Standards Supported

• ATM Forum Inverse Multiplexing for ATM Specification Version 1.1, March

1999

• ATM Forum Inverse Multiplexing for ATM Specification Version 1.0 – supports

the method of reporting Rx cell information as in Appendix C.8 of the ATM Forum Inverse Multiplexing for ATM Specification Version 1.1 for symmetrical configurations with M=128.

• I.432-1 B-ISDN user network interface – Physical Layer specification: General

characteristics

• I.432-3 B-ISDN user network interface – Physical Layer specification: 1544

kbps and 2048 kbps operation

• DS3 Physical Layer Interface Specification, af-phy-0054.000 January, 1996

• ATM on Fractional E1/T1, af-phy-0130.00 October, 1999.

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IMA Features

• IMA 1.1 protocol including group and link state machines implemented by on-

chip hardware.

• All ICP cell processing is performed internally by the S/UNI-IMA device with

no requirement for microprocessor intervention; however, ICP cells are made available for diagnostic purposes.

• Supports up to 42 simultaneous IMA groups.

• Each IMA group can support 1 to 32 links chosen from any of the supported

links.

• Each link can be programmed for either IMA processing or cell delineation.

• Supports all IMA Group Symmetry modes:

• Symmetrical configuration with symmetrical operation

• Symmetrical configuration with asymmetrical operation.

• Asymmetrical configuration with asymmetrical operation.

• Performs IMA differential delay calculation and synchronization.

• Provides programmable limit on allowable differential delay and minimum

number of links per group.

• Supports up to 279 ms (for T1 links) and 226 ms (for E1 links) link-differential

delay among links in an IMA group.

• Performs ICP and stuff-cell insertion and removal.

• Supports both Common Transmit Clock (CTC) and Independent Transmit

Clock (ITC) transmit ICP stuffing modes.

• Supports IMA frame lengths (M) equal to 32, 64, 128, or 256.

• Optionally supports the IMA 1.0 method of reporting Rx cell information as

defined in appendix C.8 of the ATM Forum Inverse Multiplexing for ATM Specification Version 1.1 for symmetrical configurations with M=128.

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• Provides IMA layer statistic counts and alarms for support of IMA

Performance and Failure Alarm Monitoring and MIB support.

• Provides per link counters for statistics and performance monitoring:

• ICP Violations

• OIF anomalies

• Rx Link stuff events

• Tx Link stuff events

• User cells

• Filler cells

• Provides per group counters for statistics and performance monitoring:

• User cells received

• Filler cells received

• User cells transmitted

• Filler cells transmitted

TC Features

• Performs cell delineation on all links.

• Performs receive cell Header Error Check (HEC) checking and transmit cell

HEC generation.

• Optionally supports receive cell payload unscrambling and transmit cell

payload scrambling.

• Provides TC layer statistics counts and alarms for MIB support.

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Interface Support

• Two line side interface modes: Scalable Bandwidth Interconnect (SBI) bus

and Clock and Data.

SBI Interface:

• Supports a byte serial 19.44 MHz Scalable Bandwidth Interconnect (SBI)

bus interface for high-density line-side device interconnection of up to 84 T1, 63 E1, or three DS3 streams.

• The SBI interface bus uses three Synchronous Payload Envelopes (SPE)

where each SPE can carry up to 28 framed T1, 21 framed E1, or one framed DS3 stream.

• For SPEs configured to support DS3, TC layer processing is supported

only. IMA is not supported over DS3.

• Always acts as a clock slave receiving clock rate information from the SBI

based framer.

• Supports Common Transmit Clock (CTC) and Independent Transmit Clock

(ITC) modes across the SBI bus.

• Seamlessly interconnects to PMC-Sierra’s PM8315 TEMUX and PM8316

TEMUX-84 highly integrated T1/ E1 framers, M13 MUXs and SONET/SDH VT/TU mapper devices

Clock/Data Interface:

• Supports 32 individual serial (T1 or E1 or unchannelized rates up to 2.304

Mbps) links or 8 individual serial 8Mbps unchannelized links via a 2-pin clock and data interface.

• Supports ATM over fractional T1/E1 by providing the capability to select

any DS0 timeslots that are active in a link.

• Serial link interface supports both independent transmit clock (ITC) and

common transmit clock (CTC) options.

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• Interfaces to a 1M x 16 ( for at least 69 msec of T1, 56 msec of E1 differential

delay tolerance)or 4M x 16 SDRAM ( for 279 msec of T1, 226 msec of E1 differential delay tolerance) through a 16-bit SDRAM interface.

• Provides a 16-bit microprocessor bus interface for configuration and Link and

Unit Management.

• ATM receive interface supports 8- and 16-bit UTOPIA L2 or Any-PHY cell

interfaces at clock rates up to 52 MHz.

• Any-PHY receive slave appears as single device. The PHY-ID of each cell

is identified in the in-band address.

• UTOPIA L2 receive slave appears as a 31 port multi-PHY.

• UTOPIA L2 receive slave can also appear as a single port with the logical

port provided as a prepend or in the HEC/UDF field.

• ATM transmit interface supports 8- and 16-bit UTOPIA L2 and Any-PHY cell

interfaces at clock rates up to 52 MHz.

• Each link configured for cell delineation or each IMA group appears as a

PHY port on the Any-PHY and UTOPIA L2 bus.

• Any-PHY transmit slave appears as an 84-port multi-PHY. The PHY-ID of

each cell is identified in the in-band address.

• UTOPIA L2 transmit slave appears as a 31-port multi-PHY.

• Seamlessly interconnects to PMC-Sierra’s PM7326 S/UNI-APEX ATM/Packet

Traffic Manager and Switch and PM7324 S/UNI-ATLAS ATM layer devices.

Loopback and Diagnostic Features

• Supports UTOPIA L2 / Any-PHY Loopback (global loopback– where all cells

received on the UTOPIA L2 / Any-PHY interface are looped back out)

• Supports Line Side Loopback (global loopback– where all data received on

the line side is looped back out)

• Supports the capability to trace ICP cells for any group

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Software

• The S/UNI-IMA device driver, written in ANSI C, provides a well-defined

Application Programming Interface (API) for use by application software. Low level utility functions are also provided for diagnostics and debugging purposes. Software wrappers are used for RTOS-related functions making the S/UNI-IMA device driver portable to any Real Time Operating System (RTOS) and hardware environment. The S/UNI-IMA device driver is compatible across the S/UNI-IMA family of devices.

Packaging

• Implemented in low power, 0.18 micron, 1.8V CMOS technology with TTL

compatible inputs and outputs.

• Provides a standard 5-pin P1149 JTAG port.

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3 APPLICATIONS

The S/UNI-IMA-84 is ideal for the following applications:

• ATM Multiservice Switches - IMA/UNI and Any Service Any Port linecards

• Wireless Base Station Controllers

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4 REFERENCES

• AF-PHY-0086.001 “Inverse Multiplexing for ATM (IMA) Specification Version

1.1”, March 1999

• I.432-1 B-ISDN User Network Interface – Physical Layer specification:

General characteristics

• I.432-3 B-ISDN User Network Interface – Physical Layer specification: 1544

kbps and 2048 kbps operation

• G.804 “ATM Cell Mapping into Plesiochronous Digital Hierarchy (PDH)”

• AF-PHY-0016.000 “ATM Forum DS1 Physical Layer Specification”

• AF-PHY-0064.000 “ATM Forum E1 Physical Interface”

• ATM Forum, UTOPIA, an ATM-PHY Layer Specification, Level 2, V. 1.0,

Foster City, CA USA, June 1995.

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5 APPLICATION EXAMPLES

5.1 ATM Multiservice Switch IMA / UNI Port Card

An optimized solution comprising the S/UNI-IMA-84, PM8316 TEMUX-84, PM5342 SPECTRA-155, PM7326 S/UNI-APEX, PM7324 S/UNI-ATLAS devices enables a new generation of high density port cards for terminating n x DS3, n x OC-3’s worth of IMA and/or ATM UNI circuits. See Figure 1.

Figure 1 - ATM Edge Switch IMA and UNI Port Card Example

SBITelecom Bus

PM5342

SPECTRA-155

PM7341

S/UNI-IMA-84

PM5342

SPECTRA-155

DS3 LIUs

PM8316

TEMUX-84

With a PM5313 SPECTRA-622, four TEMUX-84s, four S/UNI-IMA-84s, PM7326 S/UNI-APEX, and PM7324 S/UNI-ATLAS devices, an OC-12’s worth of IMA/UNI circuits can be terminated on a single linecard.

5.2 ATM Multiservice Switch, Any Service Any Port Card

With the S/UNI-IMA-84 and its support for the SBITM bus, high density Any Service Any Port linecards for ATM Switches can be designed with PMC-Sierra’s SPECTRATM, TEMUXTM, AAL1gatorTM, S/UNI -IMA, FREEDMTM, S/UNI -

APEX

and S/UNI -ATLASTM products for supporting a broad spectrum of existing and emerging services including Frame Relay (FR), multi-link Frame Relay, multi-link PPP, Internet Protocol (IP), Dedicated Private Line, Integrated Voice and Data, Voice-over- IP and Voice-over-ATM as shown in Figure 2.

UTOPIA L2 /

Any-PHY

PM7326

S/UNI-APEX

PM7324

S/UNI-ATLAS

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Figure 2 - ATM Multiservice Switch, Any Service Any Port Card Example

UTOPIA L2 /

Any-PHY

UTOPIA

Traffic

Manager

PM7326

S/UNI-APEX

PM7324

S/UNI-ATLAS

OC-12

STS-12

SONET/SDH

Framer

PM5313

SPECTRA-

622

Telecom

T1/J1/E1 Framer

TU/VT Mapper

M13 Mux

PM8316

TEMUX-84

PM8316

TEMUX-84

PM8316

TEMUX-84

SBI

Packet

Processor

PM7389

FREEDM-84

S/UNI-IMA-84

Emulation Service

AAL1gator-32

Any-PHY

IMA / UNI

PM7341

AAL1 Circuit

PM73122

Packet/Cell

Internetworking

APPI

Function

ML-PPP and

ML-Frame Relay

IMA / UNI

Circuit

Emulation Service

OAM and

Policing

RM7000

MIPS

Processor

PM8316

TEMUX-84

H-MVIP

Voice Processor

DSP

VoATM

Voice Processing

The S/UNI-IMA-84 implements the IMA 1.1 protocol (with backward compatibility to IMA 1.0) including link and group state machines, HEC cell delineation (UNI), cell scheduling and provides internal cell FIFOs. The S/UNI-IMA-84 interfaces seamlessly over a standard UTOPIA Level 2 or Any-PHY bus to an ATM Traffic Management device such as the PM7326 S/UNI-APEX. Depending on the S/UNI-IMA-84’s register configuration, ATM traffic is sent over the network as part of an IMA 1.1 or IMA 1.0 group or over a standard ATM over T1/E1 or DS3 UNI. Through register programming, for example, the number of links, groups, minimum and maximum number of links/group, frame sizes (M=32, 64, 128,

256), differential delay tolerance, transmit clock mode (independent and common) and symmetrical/asymmetrical configuration and operation are dynamically configurable. An external low-cost standard 4Mx16 SDRAM is required to buffer data for tolerating up to a maximum of 279 msec (T1) / 226 msec (E1) of differential delay across the links.

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6 BLOCK DIAGRAM

Figure 3 - S/UNI-IMA-84 Block Diagram

TCK

TMS

TDI

TRSTB

JTAG

TDO

Any-PHY/

UTOPIA Tx Slave

(TXAPS)

Tx Slave

ATM I/F

TCLK TPA TENB TADR[10:0] TCSB TSOP TSX TDAT[15:0] TPRTY

SBI Add

Bus I/F

AC1FP

ADATA[7:0]

ADP

APL AV5

AJUST_REQ

AACTIVE

ADETECT

32 Clk/Data

TSCLK[31:0]

TSDATA[31:0]

CTSCLK

INSBI

TCAS

Null

Framer

(SDFR84)

TC Layer

(TTTC84)

DLL

84-chan

x 7 cell

FIFO

(MCFD)

SYSCLK

IDCC

D[15:0]

A[10:1]

ALE

Microprocessor I/F

Tx IMA Proce ssor

(TIMA)

WRB

RDB

CSB

INTB

84-chan

x 3 cell FIFO

REFCLK

RSTB

32 Clk/Data

RSCLK[31:0]

RSDATA[31:0]

SBI Drop

Bus I/F

DC1FP

DDATA[7:0]

DDP

DPL DV5

EXSBI

VL.DLB.EN

RCAS

De-

Framer

(SDDF84)

Tc Layer

(RTTC84)

LINE_LOOP

84-chan

x 2 cell

FIFO

Internal Bus

IDCC

Processor

Rx IMA

Data Processor

(RDAT)

Cell Writer Cell Reader

Memory Interfac e

(MEMI)

CBCSB

CBWEB

CBRASB

CBCASB

Rx IMA

Protocol

(RIPP)

CBA[11:0]

CBBS[1:0]

U2U_LOOP

Rx Slave

ATM I/F

RCLK

31 chan 4 cell FIFO

Any-PHY/

UTOPIA Rx Slave (RXAPS)

RPA RENB RADR[4:0] RCSB RSOP RSX RDAT[15:0] RPRTY

CBDQM

CBDQ[15:0]

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7 DESCRIPTION

The PM7341 S/UNI-IMA-84 is a monolithic integrated circuit that implements the Inverse Multiplexing for ATM (IMA 1.1) protocol with backward compatibility to IMA 1.0 and the Transmission Convergence (TC) layer function. The S/UNIIMA-84 has two line side interface modes that determine the total number of links supported: the Scalable Bandwidth Interconnect (SBI) bus interface mode and the Clock and Data interface mode. In SBI mode, the S/UNI-IMA-84 supports up to 84 T1, 63 E1 and 3 DS3 (TC only) links where each link is dynamically configurable to support either IMA 1.1, backward compatible IMA 1.0, ATM over T1/E1 and up to three ATM over DS3 streams (using HEC delineation).

In the Clock and Data interface mode, the S/UNI-IMA-84 supports 32 independent T1, E1 or unchannelized links. Each link is dynamically configurable to support either IMA 1.1, backward compatible IMA 1.0, or ATM HEC cell delineation. ATM over Fractional T1/E1 is also supported. Unchannelized links may be used to support applications such as G.SHDSL.

All links within an IMA group must be the same nominal rate, however the link rates within a group can be different across groups.

The Scaleable Bandwidth Interconnect (SBI) high-density byte serial system interface provides higher levels of integration and dense interconnect. The SBI bus interconnects up to 84 T1s or 63 E1s asynchronously. The SBI allows transmit timing to be mastered by the PHY layer device connected to the SBI bus with the S/UNI-IMA-84 always behaving as a clock slave. In addition to framed T1s and E1s, the S/UNI-IMA-84 can transport framed DS3 links over the SBI bus.

The S/UNI-IMA-84 also supports a clock and data interface mode where 32 2-pin serial clock and data interfaces are provided. Each clock and data interface can be configured to support either a T1 link, E1 link, or an unchannelized link. For IMA, all links within a group must be the same nominal rate, but IMA groups consisting of either E1 or T1 links may coexist within the S/UNI-IMA-84. Additionally, for cell delineation only, ATM over fractional T1/E1 is supported by allowing individual DS0 timeslots to be configured as active or inactive.

IMA is a protocol designed to combine the transport bandwidth of multiple links into a single logical link. The logical link is called a group. The S/UNI-IMA-84 can support up to 42 independent groups with each group capable of supporting 1 to 32 links. Any link that is not participating in an IMA group can utilize the cell

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delineation features of the S/UNI IMA-84 for implementing either ATM over E1 or ATM over T1.

In the transmit direction, the S/UNI-IMA-84 accepts cells from the AnyPHY/UTOPIA Interface. The S/UNI-IMA-84 performs the IMA function which consists of taking a cell stream destined for a group and distributing the cells in a round-robin fashion to the links within a group, adding IMA Control Protocol (ICP) cells, filler cells, and stuff cells as needed. The ICP cells convey state information to the far end and are used to format an IMA frame. The IMA Frame is used as a mechanism to synchronize the links at the far end. Cell rate decoupling is performed at the IMA sub-layer via filler cells. Filler cells are used instead of physical layer cells for cell rate decoupling, thus a continuous stream of cells is sent to the TC layer. The stuff cells are used to maintain synchronization between the links in a group by absorbing the rate differential when links are running on different clocks.

The data from the IMA sub-layer is passed on to the TC layer. In the TC layer, the HEC is calculated and inserted into the cell headers and optional scrambling of the payload is performed. The cell stream is then mapped into the T1 or E1 payload with zeros inserted for the framing and overhead bits or bytes. The links are then transmitted via either the high density SBI interface or the clock and data interface. The S/UNI-IMA-84 acts as a clock slave – i.e., the clock is provided from logic external to the S/UNI-IMA-84. An optional common-clock mode is provided to enable all links to run from the same clock.

If using an unchannelized clock and data interface, the data is not mapped into the T1/E1 payload but is transmitted one bit for each provided clock pulse.

On the receive side, the framed data is received from either the SBI or the clock/data interface, and the ATM cell data is extracted from the T1, E1 or DS3 frame structure.

If using an unchannelized clock and data interface, the data is received one bit for each provided clock pulse.

The TC layer searches for cell delineation as per the procedures outlined in ITUT Recommendation I.432.1. Once cell delineation is obtained, the payload is optionally descrambled and the cells are passed to the IMA sub-layer. The TC layer provides counts of errored headers as well as OCD and LCD error interrupts.

The receive IMA sublayer performs IMA-frame delineation and stuff-cell removal. Based upon the ICP cell information, the S/UNI-IMA-84 determines the

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differential delay between the links within a group and applies the link and group state machine logic to coordinate the activation and deactivation of groups and links with the far end. As cells are received, they are stored in an external FIFO structure; this structure is based upon the IMA frame boundaries and the IMA frame sequence number. When links or groups are determined to be active by the link and group state machines, the data is played out to the AnyPHY/UTOPIA Interface at a constant rate to mimic the existence of a single higher bandwidth physical link.

Once a group of links is established, links can be added or deleted from the group. Under software control, the S/UNI-IMA-84 will perform all necessary steps to add or delete links from previously established groups.

In order to aid diagnostics, a line side loopback and a UTOPIA side loopback are provided. Also, an ICP cell trace feature is provided. When the ICP cell trace has been enabled for a group, the S/UNI-IMA-84 will place those ICP cells where a SCCI field change is detected into a buffer that is accessible to the microprocessor.

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8 PIN DIAGRAM

The S/UNI-IMA-84 is packaged in a 416-pin PBGA package that has a body size of 27mm by 27mm and a ball pitch of 1mm.

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Figure 4 - S/UNI-IMA Pinout (Bottom View)

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9 PIN DESCRIPTION

9.1 Receive Slave ATM Interface (Any-PHY mode) (28 Signals)

Pin Name Type Pin

Function

No.

RCLK Input W24 The Receive Clock (RCLK) signal is used to

transfer data blocks from the S/UNI-IMA-84 across the receive Any-PHY interface.

The RPA, RSOP, RSX, RDAT[15:0], and RPRTY outputs are updated on the rising edge of RCLK. The RENB, RADR[4:0], and RCSB inputs are sampled on the rising edge of RCLK.

The RCLK input must cycle at a 52 MHz or lower instantaneous rate.

RPA Tristate

Output

AB24 The Receive Packet Available (RPA) is an active

high signal that indicates whether at least one cell is queued for transfer.

The S/UNI-IMA-84 device drives the RPA with the cell availability status two RCLK cycles after RADR[4:0] matches the S/UNI IMA’s device address. The RPA output is high-impedance at all other times.

The RPA output is updated on the rising edge of RCLK.

RENB Input AB26 The Receive Enable Bar (RENB) is an active low

signal used to initiate the transfer of cells from the S/UNI-IMA-84 to an ATM layer component, such as a traffic management device.

The RENB input is sampled on the rising edge of RCLK.

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Pin Name Type Pin

Function

No.

RADR[4] RADR[3] RADR[2] RADR[1] RADR[0]

Input AA25

AA23 AA24 AA26

Y25

The Receive Address (RADR[4:0]) signals are used to address the S/UNI-IMA-84 device for the purposes of polling and selection for cell transfer. The RADR[4:0] signals are valid only when the RCSB signal is sampled active in the following RCLK cycle.

The RADR[4:0] input bus is sampled on the rising edge of RCLK.

RCSB Input Y24 The Receive Chip Select (RCSB) is an active low

signal that is used to select the S/UNI-IMA-84 receive interface. When the RCSB is sampled low, it indicates that the RADR[4:0] sampled at the previous clock is a valid address. If the RCSB is sampled high, the device is not selected and the RADR[4:0] sampled on the previous cycle is not a valid address and is ignored. When sufficient address space is provided by RADR[4:0] for all devices on the bus, this signal may be tied low.

RSOP Tristate

Output

RSX Tristate

Output

The RCSB input is sampled on the rising edge of RCLK.

W25 The Receive Start of Packet (RSOP) is an active

high signal that marks the start of the cell on the RDAT[15:0] bus. When RSOP is active, the first word of the cell is present on the RDAT[15:0] bus.

The RSOP output is updated on the rising edge of RCLK.

W23 The Receive Start of Transfer (RSX) signal is an

active high signal that marks the first cycle of a data block transfer on the RDAT[15:0] bus. When the RSX signal is active, the coinciding data on the RDAT[15:0] bus represents the in-band PHY address.

The RSX output is updated on the rising edge of RCLK.

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Pin Name Type Pin

No.

RDAT[15] RDAT[14] RDAT[13] RDAT[12] RDAT[11] RDAT[10] RDAT[9] RDAT[8] RDAT[7] RDAT[6] RDAT[5] RDAT[4] RDAT[3] RDAT[2] RDAT[1] RDAT[0]

RPRTY Tristate

Tristate

Output

W26

V25 V26 U25 V24 U26 U23

T25

U24

T26 R25 R26

T24 P25 R23 P26

N25 The Receive Parity (RPRTY) signal provides the

Output

Function

The Receive Cell Data (RDAT[15:0]) signals carry the ATM cell words that have been read from the S/UNI-IMA-84 internal cell buffers. When this interface is operating in 8-bit mode, the data is carried on RDAT[7:0].

The RDAT[15:0] output bus is updated on the rising edge of RCLK.

parity (programmable for odd or even parity) of the RDAT[15:0] bus. When the interface is operating in 8-bit mode, the parity is calculated over RDAT[7:0]

The RPRTY output is updated on the rising edge of RCLK.

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9.2 Receive Slave ATM Interface (UTOPIA L2 mode) (26 Signals)

Pin Name Type Pin

Function

No.

RCLK Input W24 The Receive Clock (RCLK) signal is used to

transfer data blocks from the S/UNI-IMA-84 across the receive UTOPIA L2 interface.

The RCA, RSOC, RDAT[15:0], and RPRTY outputs are updated on the rising edge of RCLK. The RENB and RADR[4:0] inputs are sampled on the rising edge of RCLK.

The RCLK input must cycle at a 52 MHz or lower instantaneous rate.

RCA Tristate

Output

AB24 The Receive Cell Available (RCA) is an active high

signal that, when polled using the RADR[4:0] signals, indicates if at least one cell is queued for transfer on the selected logical channel FIFO .

The S/UNI-IMA-84 device drives RCA with the cell availability status for the polled port one RCLK cycle after a valid RADR[4:0] address is sampled. The RCA output is high-impedance at all other times.

The RCA output is updated on the rising edge of RCLK.

RENB Input AB26 The Receive Enable Bar (RENB) is an active low

signal used to initiate the transfer of cells from the S/UNI-IMA-84 to an ATM-layer component, such as a traffic management device.

The RENB input is sampled on the rising edge of RCLK.

RADR[4] RADR[3] RADR[2] RADR[1] RADR[0]

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 44

Input AA25

AA23 AA24 AA26

Y25

The Receive Address (RADR[4:0]) signals are used to address the S/UNI-IMA-84 device for the purposes of polling and selecting for cell transfer.

The RADR[4:0] input bus is sampled on the rising edge of RCLK.

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Pin Name Type Pin

No.

RSOC Tristate

W25 The Receive Start of Cell (RSOC) is an active high

Output

RDAT[15] RDAT[14] RDAT[13] RDAT[12] RDAT[11] RDAT[10] RDAT[9] RDAT[8] RDAT[7] RDAT[6] RDAT[5] RDAT[4] RDAT[3] RDAT[2] RDAT[1] RDAT[0]

Tristate

Output

W26

V25 V26 U25 V24 U26 U23

T25 U24

T26 R25 R26

T24 P25 R23 P26

Function

signal that marks the first word of the cell on the RDAT[15:0] bus.

The RSOC output is updated on the rising edge of RCLK.

The RDAT[15:0] output bus is updated on the rising edge of RCLK.

RPRTY Tristate

Output

N25 The Receive Parity (RPRTY) signal provides the

parity (programmable for odd or even parity) of the RDAT[15:0] bus. When the interface is operating in 8-bit mode, the parity is calculated over RDAT[7:0]

The RPRTY output is updated on the rising edge of RCLK.

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9.3 Transmit Slave Interface (ANY-PHY mode) (34 Signals)

Pin Name Type Pin

Function

No.

TCLK Input F25 The Transmit Clock (TCLK) signal is used to

transfer cells across the ANY-PHY interface to the internal downstream cell buffers.

The TPA output is updated on the rising edge of TCLK.

The TENB. TSX, TSOP, TDAT[15:0], TPRTY, TADR[10:0], and TCSB inputs are sampled on the rising edge of TCLK.

The TCLK input must cycle at a 52 MHz or lower instantaneous rate.

TPA Tristate

Output

N26 The Transmit Packet Available (TPA) is an active

high signal that indicates the availability of space in the selected logical channel FIFO when polled using the TADR[10:0] signals.

The S/UNI-IMA-84 device drives TPA with the cell availability status of the polled port two TCLK cycles after TADR[10:0] matches the S/UNI IMA’s device address. The TPA output is high-impedance at all other times.

The TPA output is updated on the rising edge of TCLK.

TENB Input P24 The Transmit enable bar (TENB) is an active low

signal that is used to indicate cell transfers to the internal cell buffers.

The TENB input is sampled on the rising edge of TCLK.

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Pin Name Type Pin

Function

No.

TADR[10] TADR[9] TADR[8] TADR[7] TADR[6] TADR[5] TADR[4] TADR[3] TADR[2] TADR[1] TADR[0]

Input M25

N24

M26

L25

M24

L26

M23

K25

L24 K26 K23

The Transmit Address (TADR[10:0]) signals are used to address logical channels for the purpose of polling and device selection. The TADR[10:0] signals are valid only when the TCSB signal is sampled active in the following TCLK cycle.

The TADR[10:0] input bus is sampled on the rising edge of TCLK.

TCSB Input J25 The Transmit Chip Select (TCSB) is an active low

signal that is used to select the S/UNI-IMA-84 transmit interface. When the TCSB is sampled low, it indicates that the TADR[10:0] sampled at the previous clock is a valid address. If the TCSB is sampled high, the device is not selected and the TADR[10:0] sampled on the previous cycle is not a valid address and is ignored. When sufficient address space is provided by TADR[10:0] for all devices on the bus, this signal may be tied low.

The TCSB is asserted low one cycle after a valid address is present on the TADR[10:0] signals.

The TCSB input is sampled on the rising edge of TCLK.

TSOP Input K24 The Transmit Start of Packet (TSOP) is an active

high signal that marks the start of the cell on the TDAT[15:0] bus. When TSOP is active, the first word of the cell is present on the TDAT[15:0] bus.

The TSOP output is sampled on the rising edge of TCLK.

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Pin Name Type Pin

Function

No.

TSX Input J26 The Transmit Start of Transfer (TSX) signal is an

active high signal that marks the first cycle of a datablock transfer on the TDAT[15:0] bus. When the TSX signal is active, the coinciding data on the TDAT[15:0] bus represents the in-band PHY address.

The TSX output is sampled on the rising edge of RCLK.

TDAT[15] TDAT[14] TDAT[13] TDAT[12] TDAT[11] TDAT[10] TDAT[9] TDAT[8] TDAT[7] TDAT[6] TDAT[5] TDAT[4] TDAT[3] TDAT[2] TDAT[1] TDAT[0]

Input H25

H26

J24 G25 H23 G26 H24

F23

F26 G24 E25 E26

F24 D25 E23 D26

The Transmit Cell Data (TDAT[15:0]) signals carry the ATM cell octets that are transferred to the internal cell buffer. When this interface is operating in 8-bit mode, only TDAT[7:0] is used.

The TDAT[15:0] input bus is sampled on the rising edge of TCLK.

TPRTY Input E24 The Transmit Parity (TPRTY) signal provides the

parity (programmable for odd or even parity) of the TDAT[15:0] bus. The TPRTY signal is considered valid only when valid data and inband address are transferring as indicated by the TENB signal asserted low. When this interface is operating in 8bit mode, this signal provides the parity of TDAT[7:0].

A parity error is indicated by a status bit and a maskable interrupt.

The TPRTY input signal is sampled on the rising edge of TCLK.

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9.4 Transmit Slave Interface (UTOPIA L2 mode) (26 Signals)

Pin Name Type Pin

Function

No.

TCLK Input F25 The Transmit Clock (TCLK) signal is used to

transfer cells across the ANY-PHY interface to the internal downstream cell buffers.

The TCA output is updated on the rising edge of TCLK.

The TENB, TSOC, TDAT[15:0], TPRTY, TADR[4:0] inputs are sampled on the rising edge of TCLK.

The TCLK input must cycle at a 52 MHz or lower instantaneous rate.

TCA Tristate

Output

N26 The Transmit Cell Available (TCA) is an active high

signal that indicates the availability of space in the selected logical channel FIFO when polled using the TADR[4:0] signals.

The S/UNI-IMA-84 drives TCA with the cell space availability status for the polled port on TCLK cycles after a valid TADR[4:0} address is sampled.

The TCA output is high-impedance when not polled.

The TCA output is updated on the rising edge of TCLK.

TENB Input P24 The Transmit enable bar (TENB) is an active low

signal that is used to indicate cell transfers to the internal cell buffers.

The TENB input is sampled on the rising edge of TCLK.

TADR[4] TADR[3] TADR[2] TADR[1] TADR[0]

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 49

Input M23

K25

L24 K26 K23

The Transmit Address (TADR[4:0]) signals are used to address logical channels for the purposes of polling and device selection.

The TADR[4:0] input bus is sampled on the rising edge of TCLK.

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Pin Name Type Pin

Function

No.

TSOC Input K24 The Transmit Start of Cell (TSOC) is an active high

signal that marks the first word of the cell on the TDAT[15:0] bus.

The TSOC input is sampled on the rising edge of TCLK.

TDAT[15] TDAT[14] TDAT[13] TDAT[12] TDAT[11] TDAT[10] TDAT[9] TDAT[8] TDAT[7] TDAT[6] TDAT[5] TDAT[4] TDAT[3] TDAT[2] TDAT[1] TDAT[0]

Input H25

H26

J24 G25 H23 G26 H24

F23

F26 G24 E25 E26

F24 D25 E23 D26

The Transmit Cell Data (TDAT[15:0]) signals carry the ATM cell octets that are transferred to the internal cell buffer. The TDAT[15:0] signals are considered valid only when the TENB signal is asserted low. When this interface is operating in 8bit mode, only TDAT[7:0] is used.

The TDAT[15:0] input bus is sampled on the rising edge of TCLK.

TPRTY Input E24 The Transmit Parity (TPRTY) signal provides the

parity (programmable for odd or even parity) of the TDAT[15:0] bus. The TPRTY signal is considered valid only when valid data is transferring as indicated by the TENB signal asserted low. When this interface is operating in 8-bit mode, this signal provides the parity of TDAT[7:0].

A parity error is indicated by a status bit and a maskable interrupt.

The TPRTY input signal is sampled on the rising edge of TCLK.

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9.5 Microprocessor Interface (31 Signals)

Pin Name Type Pin

No.

D[15] D[14] D[13] D[12] D[11] D[10] D[9] D[8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]

A[10]

A[9]

A[8]

A[7]

A[6]

A[5]

A[4]

A[3]

A[2]

A[1]

I/O B19

D19 A19 C19 B18 A18 B17 C18 A17 D17 B16 A16 B15 A15 C16 B14

Input D15

A14 C15 B13 A13 C14 B12 C13 A12 B11

Function

The Micro Data (D[15:0]) signals provide a data bus to allow the S/UNI-IMA-84 device to interface to an external microprocessor. Both read and write transactions are supported. The microprocessor interface is used to configure and monitor the S/UNIIMA-84 device.

The Micro Address (A[10:1]) signals provide an address bus to allow the S/UNI-IMA-84 device to interface to an external microprocessor.

The A[10:1] indicate a word address. The S/UNIIMA-84 microprocessor interface is not byte addressable.

The A[10:1] input signals are sampled while the ALE is asserted high.

ALE Input C12 The Address Latch Enable (ALE) is an active high

signal that latches the A[10:1] signals during the address phase of a bus transaction. When ALE is set high, the address latches are transparent. When ALE is set low, the address latches hold the address provided on A[10:1].

The ALE input has an internal pull-up resistor.

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Pin Name Type Pin

Function

No.

WRB Input A11 The Write Strobe Bar (WRB) is an active low signal

that qualifies write accesses to the S/UNI-IMA-84 device. When the CSB is set low, the D[15:0] bus contents are clocked into the addressed register on the rising edge of WRB.

RDB Input D12 The Read Strobe Bar (RDB) is an active low signal

that qualifies read accesses to the S/UNI-IMA-84 device. When the CSB is set low, the S/UNI-IMA-84 device drives the D[15:0] bus with the contents of the addressed register on the falling edge of RDB.

CSB Input B10 The Chip Select Bar (CSB) is an active low signal

that qualifies read/write accesses to the S/UNI-IMA84 device. The CSB signal must be set low during read and write accesses. When the CSB is set high, the microprocessor-interface signals are ignored by the S/UNI-IMA-84 device.

If the CSB is not required (register accesses are controlled only by WRB and RDB), then it should be connected to an inverted version of the RSTB signal.

INTB Open-

Drain Output

C11 The Interrupt Bar (INTB) is an active low signal

indicating that an enabled bit in the Master Interrupt Register was set. When INTB is set low, the interrupt is active and enabled. When INTB is tristate, there is no interrupt pending or it is disabled.

INTB is an open drain output and should be pulled high externally with a fast resistor.

Maximum output current (IMAX) = TBD mA

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9.6 SDRAM I/F (35 Signals)

Pin Name Type Pin

Function

No.

CBCSB Output AD9 The Cell Buffer SDRAM Chip Select Bar (CBCSB)

is an active low signal used to control the SDRAM.

CBCSB, CBRASB, CBCASB, and CBWEB define the command being sent to the SDRAM.

The CBCSB output is updated on the rising edge of SYSCLK.

CBRASB Output AF10 The Cell Buffer SDRAM Row Address Strobe Bar

(CBRASB) is an active low signal used to control the SDRAM.

CBCSB, CBRASB, CBCASB, and CBWEB define the command being sent to the SDRAM.

The CBRASB output is updated on the rising edge of SYSCLK.

CBCASB Output AC10 The Cell Buffer SDRAM Column Address Strobe

Bar (CBCASB) is an active low signal used to control the SDRAM.

CBCSB, CBRASB, CBCASB, and CBWEB define the command being sent to the SDRAM.

The CBCASB output is updated on the rising edge of SYSCLK.

CBWEB Output AE11 The Cell Buffer SDRAM Write Enable Bar

(CBWEB) is an active low signal used to control the SDRAM.

CBCSB, CBRASB, CBCASB, and CBWEB define the command being sent to the SDRAM.

The CBWEB output is updated on the rising edge of SYSCLK.

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Pin Name Type Pin

No.

CBA[11] CBA[10] CBA[9] CBA[8] CBA[7] CBA[6] CBA[5] CBA[4] CBA[3] CBA[2] CBA[1] CBA[0]

CBBS[1] CBBS[0]

Output AD10

AF11 AE12 AF12 AD11 AE13 AC12 AF13 AD12 AE14 AD13 AE15

Output AD14

AF15

Function

The Cell Buffer SDRAM Address (CBA[11:0]) signals identify the row address (CBA[11:0]) and column address (CBA[7:0]) for the locations accessed.

The CBA[11:0] output is updated on the rising edge of SYSCLK.

The Cell Buffer SDRAM Bank Select (CBBS[1:0]) signals determine which bank of a dual/quad bank Cell Buffer SDRAM chip is active. CBBS is generated along with the row address when CBRASB is asserted low.

The CBBS[1:0] outputs are updated on the rising edge of SYSCLK.

CBDQM Output AE16 The Cell Buffer SDRAM Input/Output Data Mask

(CBDQM) signal is held high until the SDRAM initialization is complete and then set low for normal operation.

The CBDQM output is updated on the rising edge of SYSCLK.

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Pin Name Type Pin

No.

CBDQ[15] CBDQ[14] CBDQ[13] CBDQ[12] CBDQ[11] CBDQ[10] CBDQ[9] CBDQ[8] CBDQ[7] CBDQ[6] CBDQ[5] CBDQ[4] CBDQ[3] CBDQ[2] CBDQ[1] CBDQ[0]

I/O AD15

AF16 AC15 AE17 AD16 AF17 AC17 AE18 AD17 AF18 AF19 AD18 AE20 AC19 AF20 AD19

Function

The Cell Buffer SDRAM Data (CBDQ[15:0]) signals interface directly with the Cell Buffer SDRAM data ports.

The CBDQ[15:0] bi-directional signals are sampled and updated/tristated on the rising edge of SYSCLK.

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9.7 Clk/Data (129 signals)

Pin Name Type Pin No. Function

TSCLK[31] TSCLK[30] TSCLK[29] TSCLK[28] TSCLK[27] TSCLK[26] TSCLK[25] TSCLK[24] TSCLK[23] TSCLK[22] TSCLK[21] TSCLK[20] TSCLK[19] TSCLK[18] TSCLK[17] TSCLK[16] TSCLK[15] TSCLK[14] TSCLK[13] TSCLK[12] TSCLK[11] TSCLK[10] TSCLK[9] TSCLK[8] TSCLK[7] TSCLK[6] TSCLK[5] TSCLK[4] TSCLK[3] TSCLK[2] TSCLK[1] TSCLK[0]

Input A23

B22 D22 C22 A21 B20 A20 C20

C10

A9 B8 C9 B7 D8 A7 C8 B6 D6 A6 B3 C4 A3 A2 E3 F2 F4 F3

F1 G2 G1 G3

The Transmit Serial Clock (TSCLK[31:0]) signals contain the transmit clocks for the 32 independently timed links. The TSDATA[31:0] signals are updated on the falling edge of the corresponding TSCLK[31:0] clock.

For channelized T1 or E1 links, TSCLK[n] must be gapped during the framing bit (for T1 interfaces) or during time-slot 0 (for E1 interfaces) of the TSDATA[n] stream. The S/UNIIMA-84 uses the gapping information to determine the time-slot alignment in the transmit stream.

For unchannelized links, TSCLK[n] must be externally gapped during the bits or time-slots that are not part of the transmission format payload (i.e., not part of the ATM Cell).

The TSCLK[31:0] input signal is nominally a 50% duty cycle clock of 1.544 MHz for T1 links and

2.048 MHz for E1 links.

The TSCLK[31:0] may operate at higher rates in the unchannelized mode. At higher rates, the amount of lines available is limited. See 12.3.2.2 for more details.

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Pin Name Type Pin No. Function

TSDATA[31] TSDATA[30] TSDATA[29] TSDATA[28] TSDATA[27] TSDATA[26] TSDATA[25] TSDATA[24] TSDATA[23] TSDATA[22] TSDATA[21] TSDATA[20] TSDATA[19] TSDATA[18] TSDATA[17] TSDATA[16] TSDATA[15] TSDATA[14] TSDATA[13] TSDATA[12] TSDATA[11] TSDATA[10] TSDATA[9] TSDATA[8] TSDATA[7] TSDATA[6] TSDATA[5] TSDATA[4] TSDATA[3] TSDATA[2] TSDATA[1] TSDATA[0]

Output C25

D24 C26 B26 A22 B21 D21 C21

A5C6

B4 D5

A4 C5 D3 D1

B1 C2 C1 D2 H4 H1 H3

J2 J1

The Transmit Serial Data (TSDATA[31:0]) signals contain the transmit data for the 32 independently timed links. For channelized links, TSDATA[n] contains the 24 (T1) or 31 (E1) timeslots that comprise the channelized link. TSCLK[n] must be gapped during the T1 framing bit position or the E1 frame alignment signal (time-slot 0). The S/UNI-IMA-84 uses the location of the gap to determine the channel alignment on TSDATA[n].

For unchannelized links, TSDATA[n] contains the ATM cell data. For certain transmission formats, TSDATA[n] may contain place holder bits or timeslots. TSCLK[n] must be externally gapped during the place holder positions in the TSDATA[n] stream.

The TSDATA[31:0] output signals are updated on the falling edge of the corresponding TSCLK[31:0] clock

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Pin Name Type Pin No. Function

RSCLK[31] RSCLK[30] RSCLK[29] RSCLK[28] RSCLK[27] RSCLK[26] RSCLK[25] RSCLK[24] RSCLK[23] RSCLK[22] RSCLK[21] RSCLK[20] RSCLK[19] RSCLK[18] RSCLK[17] RSCLK[16] RSCLK[15] RSCLK[14] RSCLK[13] RSCLK[12] RSCLK[11] RSCLK[10] RSCLK[9] RSCLK[8] RSCLK[7] RSCLK[6] RSCLK[5] RSCLK[4] RSCLK[3] RSCLK[2] RSCLK[1] RSCLK[0]

Input AC25

AD26 AD25 AE26 AC22

AF23 AE23 AD21 AC21 AE21

AD8 AF8 AD6 AC6 AD1 AC3 AE7 AF6 AD5 AC5 AD4 AE4 AD2 AB3 AB1 AB2

AA1

V3 W1 W2

The Receive Serial Clock (RSCLK[31:0]) signals contain the recovered line clock for the 32 independently timed links. The RSDATA[31:0] signals are sampled on the rising edge of the corresponding RSCLK[31:0] clock.

For channelized T1 or E1 links, RSCLK[n] must be gapped during the framing bit (for T1 interfaces) or during time-slot 0 (for E1 interfaces) of the RSDATA[n] stream. The S/UNIIMA-84 uses the gapping information to determine the time-slot alignment in the receive stream. RSCLK[31:0] is nominally a 50% duty cycle clock of 1.544 MHz for T1 links and 2.048 MHz for E1 links.

For unchannelized links, RSCLK[n] must be externally gapped during the bits or time-slots that are not part of the transmission format payload (i.e., not part of the ATM cell).

The RSCLK[31:0] input signal is nominally a 50% duty cycle clock of 1.544 MHz for T1 links and

2.048 MHz for E1 links.

The RSCLK[31:0] may operate at higher rates in the unchannelized mode. At higher rates, the amount of lines available is limited See 12.3.2.2 for more details.

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Pin Name Type Pin No. Function

RSDATA[31] RSDATA[30] RSDATA[29] RSDATA[28] RSDATA[27] RSDATA[26] RSDATA[25] RSDATA[24] RSDATA[23] RSDATA[22] RSDATA[21] RSDATA[20] RSDATA[19] RSDATA[18] RSDATA[17] RSDATA[16] RSDATA[15] RSDATA[14] RSDATA[13] RSDATA[12] RSDATA[11] RSDATA[10] RSDATA[9] RSDATA[8] RSDATA[7] RSDATA[6] RSDATA[5] RSDATA[4] RSDATA[3] RSDATA[2] RSDATA[1] RSDATA[0]

Input AB23

AB25 AC26 AC24

AF25

AF24 AD23 AE24 AD20

AF21

AF9 AE9 AD7 AF7 AF3 AE3 AC8 AE8 AE6 AF5 AE5 AF4 AF2 AE1 AC1 AB4 AC2 AA3 AA4 AA2

The Receive Serial Data (RSDATA[31:0]) signals contain the recovered line data for the 32 independently timed links.

For channelized links, RSDATA[n] contains the 24 (T1) or 31 (E1) time-slots that comprise the channelized link. RSCLK[n] must be gapped during the T1 framing bit position or the E1 frame alignment signal (time-slot 0). The S/UNI-IMA-84 uses the location of the gap to determine the channel alignment on RSDATA[n].

For unchannelized links, RSDATA[n] contains the ATM cell data. For certain transmission formats, RSDATA[n] may contain place-holder bits or timeslots. RSCLK[n] must be externally gapped during the place-holder positions in the RSDATA[n] stream.

The RSDATA[31:0] input signals are sampled on the rising edge of the corresponding RSCLK[31:0] clock.

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Pin Name Type Pin No. Function

CTSCLK Input H2 The Common Transmit Serial Clock (CTSCLK)

signal is a common transmit line clock that can optionally be used by all 32 serial links instead of each link’s transmit serial line clock (TSCLK[n]). Ground if not used.

The CTSCLK input signal is nominally a 50% duty cycle clock of 1.544 MHz for T1 links and

2.048 MHz for E1 links.

9.8 SBI Interface Signals (27)

Pin Name Type Pin

Function

No.

DC1FP Input P3 The Active High Drop Bus C1 Frame Pulse

(C1FP) signal is externally generated to indicate the

first C1 octet of each four-frame SBI multiframe on the Drop bus.

This frame pulse is a single REFCLK cycle long and is sampled on the rising edge of REFCLK.

This signal should be pulsed once every fourth C1 octet to produce a 2 KHz multiframe signal. The frame pulse does not need to be repeated every fourth SBI frame. The S/UNI-IMA-84 will synchronize to this signal and flywheel in its absence.

DDATA[7] DDATA[6] DDATA[5] DDATA[4] DDATA[3] DDATA[2] DDATA[1] DDATA[0]

Input R4

U2 T3 U1 U4 V2 U3 V1

The Drop Bus Data (DDATA[7:0]) signals are a time division multiplexed bus which transports tributaries by assigning them to fixed octets within the SBI BUS structure.

Multiple PHY devices can drive this bus at uniquely assigned tributary columns within the SBI BUS structure.

The DDATA[7:0] input signals are sampled on the rising edge of REFCLK.

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Pin Name Type Pin

Function

No.

DDP Input R1 The Drop Bus Data Parity (DDP) signal carries the

even or odd parity for the drop bus signals. The parity calculation encompasses DDATA[7:0], DPL, and DV5 signals.

The selection of even or odd parity is made via the SBI_PAR_CTL bit of SBI Extract Control Register.

Multiple PHY-devices can drive this signal at uniquely assigned tributary columns within the SBI BUS structure. This parity signal is intended to detect multiple sources in the column assignment.

The DDP input signal is sampled on the rising edge of REFCLK.

DPL Input T2 The Active High Drop Bus Payload (DPL) is an

active high signal that indicates valid data within the SBI BUS structure. This signal is asserted during all octets making up a tributary. This signal goes high during the V3 octet within a tributary to accommodate negative timing adjustments between the tributary rate and the fixed SBI BUS structure. This signal goes low during the octet after the V3 octet within a tributary to accommodate positive timing adjustments between the tributary rate and the fixed SBI BUS structure.

Multiple PHY-devices can drive this signal at uniquely assigned tributary columns within the SBI BUS structure.

The DPL input signal is sampled on the rising edge of REFCLK.

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Pin Name Type Pin

Function

No.

DV5 Input T1 The Active High Drop Bus Payload Indicator

(DV5) is an active high signal that locates the

position of the floating payloads for each tributary within the SBI BUS structure. Timing differences between the port timing and the SBI BUS timing are indicated by adjustments of this payload pointer relative to the fixed SBI BUS structure.

Multiple PHY-devices can drive this signal at uniquely assigned tributary columns within the SBI BUS structure. All movements indicated by this signal must be accompanied by appropriate adjustments in the DPL signal.

The DV5 input signal is sampled on the rising edge of REFCLK.

AC1FP Input R2 The Active High Add Bus C1 Frame Pulse (C1FP)

signal is externally generated to indicate the first C1 octet of each four-frame SBI multiframe on the Add bus.

ADATA[7] ADATA[6] ADATA[5] ADATA[4] ADATA[3] ADATA[2] ADATA[1] ADATA[0]

Tristate OutputM2M1

L3 N2 M4 N1 M3 P2

This frame pulse is a single REFCLK cycle long and is sampled on the rising edge of REFCLK.

The Add Data (ADATA[7:0]) signals are a time division multiplexed bus which transports tributaries by assigning them to fixed octets within the SBI BUS structure.

The S/UNI-IMA-84 drives ADATA[7:0] only at uniquely assigned tributary columns within the SBI BUS structure.

The ADATA[7:0] output signals are updated on the rising edge of REFCLK.

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Pin Name Type Pin

No.

ADP Tristate

L1 The Add Bus Data Parity (ADP) signal carries the

Output

APL Tristate

K3 The Active High Add Bus Payload (APL) is an

Output

Function

even or odd parity for the add bus signals. The parity calculation encompasses ADATA[7:0], APL and AV5 signals.

The selection of even or odd parity is made via SBI_PAR_CTL bit of SBI Insert Control Register.

The S/UNI-IMA-84 drives ADP only at uniquely assigned tributary columns within the SBI BUS structure.

The ADP output signal is updated on the rising edge of REFCLK.

active high signal that indicates valid data within the SBI BUS structure. This active high signal is asserted during all octets making up a tributary. This signal goes high during the V3 or H3 octet within a tributary to accommodate negative timing adjustments between the tributary rate and the fixed SBI BUS structure. This signal goes low during the octet after the V3 or H3 octet within a tributary to accommodate positive timing adjustments between the tributary rate and the fixed SBI BUS structure.

The S/UNI-IMA-84 drives the APL only at uniquely assigned tributary columns within the SBI BUS structure.

The APL output signal is updated on the rising edge of REFCLK.

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Pin Name Type Pin

Function

No.

AV5 Tristate

Output

L2 The Active High Add Bus Payload Indicator (AV5)

is an active high signal that locates the position of the floating payload for each tributary within the add bus structure.

The S/UNI-IMA-84 drives AV5 only at uniquely assigned tributary columns within the SBI BUS structure. All movements indicated by this signal are accompanied by appropriate adjustments in the APL signal.

The AV5 output signal is updated on the rising edge of REFCLK.

AJUST_REQInput P1 The Active High Add Bus Justification Request

(AJUST_REQ) signal is used to speed up or slow down the S/UNI-IMA-84 which is sending data to the PHY (e.g., TEMUX).

This active high signal indicates negative timing adjustments when asserted high during the V3 or H3 octet, depending on the tributary type. In response to this, the S/UNI-IMA-84 will send an extra byte in the V3 or H3 octet of the next frame.

This signal indicates positive timing adjustments when asserted high during the octet following the V3 or H3 octet, depending on the tributary type. The S/UNI-IMA-84 will respond to this by not sending an octet during the V3 or H3 octet of the next frame.

All timing adjustments from the S/UNI-IMA-84 in response to the justification request will still set the payload and payload indicators appropriately for timing adjustments.

The AJUST_REQ input signal is sampled on the rising edge of REFCLK.

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Pin Name Type Pin

Function

No.

AACTIVE Output K4 The Add Bus Active Indicator (AACTIVE) is an

active high signal that is asserted during all octets when driving data and control signals - ADATA[7:0], ADP, APL and AV5 – onto the Add bus.

All other SBI Link Layer devices (e.g., other S/UNIIMA-84s on the SBI bus) driving the Add bus listen to this signal to detect multiple sources driving the Add bus, which can occur due to configuration problems

The AACTIVE output is asserted on the rising edge of REFCLK.

ADETECT Input N3 The Add Bus Active Detector (ADETECT) signal

indicates when another device is driving the Add bus. Other Link Layer device AACTIVE outputs can be externally OR’ed together and connected to ADETECT.

When the S/UNI-IMA-84 is driving AACTIVE high and simultaneously detects ADETECT is high, it tristates its Add bus outputs to minimize or eliminate contention.

ADETECT is an asynchronous signal which is used to disable the tristate drivers on the ADD bus. The AND of AACTIVE and ADETECT is used. to indicate that a collision has occurred.

This input must be tied low when not used.

9.9 General (5 signals)

Pin Name Type Pin

Function

No.

RSTB Input AE22 The Reset Bar (RSTB) is an active low signal that

provides an asynchronous S/UNI-IMA-84 reset. RSTB is a Schmitt-triggered input with an internal pull-up resistor.

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Pin Name Type Pin

Function

No.

OE Input AF22 The Output Enable (OE) is an active high signal

that allows all of the outputs of the device to operate in their functional state. When this signal is low, all outputs of the S/UNI-IMA-84 go to the high impedance state, with the exception of TDO.

SYSCLK Input AE10 The System Clock (SYSCLK) signal is the master

clock for the S/UNI-IMA-84 device. The core S/UNIIMA-84 logic (including the SDRAM interface) is timed to this signal.

External SDRAM devices share this clock and must have clocks aligned within 0.2ns skew of the clock seen by the S/UNI-IMA-84 device.

This clock must be stable prior to deasserting RSTB 0->1.

SYSCLK must cycle at a 50-55 MHz instantaneous rate to support the maximum number of links (84 T1, 63 E1 or 3 DS3).

REFCLK Input R3 SBI_MODE:The Reference Clock (REFCLK) signal

is an externally generated 19.44MHz +/-50ppm clock with a nominal 50% duty cycle. REFCLK is common to both the add and drop sides of the SBI BUS.

In CLK/Data mode, REFCLK is required and may be operated at frequencies up to 52 MHz. In general, for T1 and E1 links, 33 MHz is sufficient. See

12.3.2.3 for details on selecting the proper frequency.

NC AD22 No Connect. This signal ball is not connected to the

die.

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9.10 JTAG & Scan Interface (7 Signals)

Pin Name Type Pin

Function

No.

TCK Input A25 The Test Clock (TCK) signal provides timing for test

operations that are carried out using the IEEE P1149.1 test access port.

TMS Input B24 The Test Mode Select (TMS) is an active high signal

that controls the test operations carried out using the IEEE P1149.1 test access port.

The TMS signal has an integral pull-up resistor.

The TMS input is sampled on the rising edge of TCK.

TDI Input A24 The Test Data Input (TDI) signal carries test data

into the S/UNI-IMA-84 via the IEEE P1149.1 test access port.

The TDI signal has an integral pull-up resistor.

The TDI input is sampled on the rising edge of TCK.

TDO Tristate B23 The Test Data Output (TDO) signal carries test data

out of the S/UNI-IMA-84 via the IEEE P1149.1 test access port. TDO is a tristate output that is inactive except when the scanning of data is in progress.

The TDO output is updated/tristated on the falling edge of TCK.

TRSTB Input C23 The Active low Test Reset (TRSTB) is an active low

signal that provides an asynchronous S/UNI-IMA-84 test access port reset via the IEEE P1149.1 test access port. TRSTB is a Schmitt-triggered input with an integral pull-up resistor.

Note that when not being used, TRSTB must be connected to the RSTB input.

SCAN_MODEBInput A10 The Active low Scan Mode (SCAN_MODEB) is an

active low signal that places the S/UNI-IMA-84 into a manufacturing test mode. Must be tied high to disable the scan logic.

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Pin Name Type Pin

Function

No.

SCANENB Input D10 The Active low Scan Enable (SCANENB) is an

active low signal that enables the internal scan logic for production testing. Must be tied high to disable the scan logic.

9.11 Power (120 Signals)

Pin Name Type Pin No. Function

VDDI (1.8 V) Power E1

W3 AF14

The core power pins (VDDI[7:0]) should be connected to a well-decoupled +1.8 V DC

supply. AE19 Y26 R24 C17 A8

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VSS (VSSI, VSSO, VSSQ)

Ground A1,A26

B2,B25 C3,C24 D4,D9 D13,D14

VSS The VSS pins should be connected to

GND. VSSO pins are ground pins for ports.

VSSQ pins are “quiet” ground pins for ports.

VSSI pins are core ground pins. All grounds

should be connected together. D18,D23 J4,J23 N4,N23 P4,P23 V4,V23 AC4,AC9 AC13 AC14 AC18 AC23 AD3,AD24 AE2,AE25 AF1,AF26 K10,K11 K12,K13 K14,K15 K16,K17 L10,L11 L12,L13 L14,L15 L16,L17 M10,M11 M12,M13 M14,M15 M16,M17 N10,N11 N12,N13 N14,N15 N16,N17 P10,P11 P12,P13 P14,P15 P16,P17 R10,R11 R12,R13 R14,R15 R16,R17 T10,T11 T12,T13

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T14,T15 T16,T17 U10,U11

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VDD (3.3V) Power D7

D11 D16 D20 G4

VDD (3.3V) The I/O power pins (VDD) should

be connected to a well-decoupled +3.3 V DC

supply. These pins include the VDDO pins for

the switching, as well as the VDDQ for the

quiet power pins. G23 L4 L23 T4 T23 Y4 Y23 AC7 AC11 AC16 AC20

Notes on Pin Description:

• All S/UNI-IMA-84 I/O present minimum capacitive loading and operate at TTL

logic levels and can tolerate 5.0V levels.

• Inputs RSTB, ALE, TCK, TMS, TDI and TRSTB, TSCLK, CTSCLK, RSCLK,

RSDATA, an OE have internal pull-up resistors.

• Power to the VDD (3.3V) pins should be applied before power to the VDDI

(1.8V) pins is applied. Similarly, power to the VDDI (1.8V) pins should be removed before power to the VDD (3.3V) pins is removed.

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10 FUNCTIONAL DESCRIPTION

This section describes the function of each entity in the S/UNI-IMA-84 block diagram. Throughout this document the use of the term “transmit” implies data read in from the cell interface and sent out the lineside interface. Conversely, “receive” is used to describe the data path from the lineside interface to the cell interface.

The term “virtual PHY” refers to a single flow on the Any-PHY/UTOPIA bus. Each IMA group or a single TC connection is mapped to a virtual PHY. For simplicity, both an IMA group and a TC connection will be referenced as a group.

Each IMA group can map data to/from multiple links. Each TC group is mapped to a single link.

The term “link” refers to either: (1) a T1, E1, or DS3 link that is multiplexed onto the SBI bus or (2) a single T1/E1 link or unchannelized link on the clock/data interface. When supporting fractional T1/E1 via the Clock/Data interface, the timeslots that are chosen to be part of the fractional connection are also referred to as a link.

Within the clock/data interface, the external links are mapped to a contiguous space identified as Virtual Links. To support multiple fractional TC flows on a single external signal, a mapping is used to split a single channelized external signal into multiple Virtual Links. At the per-link FIFOs, the clock/data Virtual Link naming convention is used synonymously with the Physical Link naming convention.

10.1 Any-PHY/UTOPIA Interfaces

The ATM cell interfaces are Any-PHY compliant 8/16 bit slave interfaces which are compatible with the following options:

• Any-PHY Slave

• UTOPIA Level 2, 31-port slave (multi-PHY-mode)

• UTOPIA Level 2, single port slave (single address mode) for receive side only.

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10.1.1 Transmit Any-PHY/UTOPIA Slave (TXAPS)

In the transmit direction, each S/UNI-IMA-84 receives cells on the AnyPHY/UTOPIA L2 compatible interface operating at clock rates up to 52 MHz and supporting 16-bit and 8-bit wide cells. The S/UNI-IMA-84 operates as a bus slave only.

Cell transfers are cell-based, that is, an entire cell is transferred from one PHY device before another is selected. Polling occurs concurrently with cell transfers to ensure maximum throughput. Data pausing is not supported in Any-PHY mode. If the TENB is deasserted prior to a complete cell being transferred, the cell transfer error interrupt will be triggered.

10.1.1.1 UTOPIA Level 2 Multi-Address Slave Mode

In the UTOPIA Level 2 Multi-address Slave mode, the transmit interface of the S/UNI-IMA-84 appears as a 31 port multi-PHY. An 11-bit configuration register TCAEN (only 4 bits are used in UL2 mode) controls the response to polling the individual channels within this group of 31 ports. Setting high on TCAEN[0] enables addresses 0 through 7, and TCAEN[3] enables addresses 24 through

30. This is typically used to allow more than one slave device to share the Transmit Any-PHY/UTOPIA master bus.

For UTOPIA L2 Mode, only 31 ports are available, using 31 independent FIFOs. UTOPIA L2 Mode limits the S/UNI-IMA-84 to 31 IMA groups or TC links. Only TADR[4:0] are used for polling and selection. Each FIFO will only assert TCA when polled if it is not in the process of transferring a cell and if there is room in the FIFO for a complete cell. Unlike Any-PHY, in UTOPIA Mode the virtual PHY port must first be selected prior to the start of the data transfer. This selection is done using the same address lines that are used for polling in combination with the TENB pin.

10.1.1.2 Any-PHY Slave Mode

In the Any-PHY slave mode, the transmit interface of the S/UNI-IMA-84 appears as a multi-PHY device with 84 ports used for the data path where all ports are identified in the in-band address. The configuration register TCAEN controls the response to polling the individual channels within this group of 84 ports. Setting high on TCAEN[0] enables addresses 0 through 7, and TCAEN[3] enables addresses 24 through 31. This is typically used to allow more than one slave device to share the Transmit Any-PHY/UTOPIA master bus.

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Conceptually, the Any-PHY protocol can be divided into two processes: polling and cell transfer.

Polling in the transmit direction is used by the bus master – typically a traffic buffering and management device – to determine when a buffered data cell can be safely sent to a PHY. The S/UNI-IMA-84 provides an independent 3-deep cell buffer FIFO for each virtual PHY. In total, there are 84 FIFOs. This arrangement ensures that there is no head-of-line blocking, while providing latitude to the master for servicing high data rate ports as well as low data rate ports.

The traffic manager need only poll those virtual PHYs for which it has cells queued. A cell transfer can be initiated after a polled virtual PHY asserts the TPA output. Each virtual PHY’s cell buffer availability status (i.e., the status that will be driven onto the TPA output when the virtual PHY is polled) is deasserted when the first byte of the last cell is written into the buffer. It is re-asserted only when the FIFO can accept another complete cell.

In Any-PHY mode, polling is performed using the TADR[10:0] bus in conjunction with the TCSB. Each S/UNI-IMA-84 uses the TADR[6:0] bits to indicate the 84 logical virtual PHYs. The upper bits from the TADR bus, TADR[10:7], are compared to the configured address to select the device. The remaining address bits from the traffic manager are decoded externally and are used to drive the TCSB. The address prepend field in the cell transfer contains the entire 16-bit address. In 8-bit mode, the prepend address is reduced to 8-bits.

In Any-PHY mode, the cell transfer is initiated after a successful poll. The virtual PHY address is prepended to the cell, thus performing an inband selection. The S/UNI-IMA-84 monitors the address prepend on the cell transfer to detect its cells.

10.1.1.3 Transmit Cell Transfer Format

The Transmit Cell Transfer Format is shown in Figure 5 and Figure 6. Word/byte 0 is required for cell transfers to an Any-PHY slave. The address prepend is the S/UNI-IMA-84 virtual PHY ID. The virtual PHY ID can be mapped to a TC link or to an IMA group. Optional prepends are supported, but are ignored by the S/UNIIMA-84.

Inclusion of optional words is statically configurable for the interface. The optional words are always ignored.

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Figure 5 - 16-bit Transmit Cell Transfer Format

Bits 15-8 Bits 7-0

Word 0

Address Prepend

(Any-PHY only)

Word 1

Optional Prepend

(Optional)

Word 2

Word 3

Word 4

Word 5

Word 6

••

•••••

Word 28

H1 H2

H3 H4

HEC/UDF

PAYLO AD1 PAYLO AD2

PAYLO AD3 PAYLO AD4

•

••

•

••

PAYLO AD47 PAYLO AD48

Figure 6 - 8-bit Transmit Cell Transfer Format

Bits 7-0

Byte 0

Address Prepend

(Any-PHY only)

Byte 1

Optional Prepend[15:8]

(Optional)

Byte 2

Optional Prepend[7:0]

(Optional)

Byte 3

Byte 4

Byte 5

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Byte 6

Byte 7*

Byte 8

•

••••

Byte 55

HEC

PAYLO AD1

PAYLO AD48

10.1.2 Receive Any-PHY/UTOPIA Slave (RXAPS)

In the receive direction, each S/UNI-IMA-84 transmits cells on an AnyPHY/UTOPIA L2 compatible interface operating at clock rates up to 52 MHz and supporting 16-bit and 8-bit wide cells. The S/UNI-IMA-84 operates as a bus slave.

In all modes, an optional prepend is allowed on the bus. This prepend will always be set to zero and has no significance to the S/UNI IMA-84 but is provided for interoperability.

10.1.2.1 UTOPIA Level 2 Multi-Address Slave Mode

In UTOPIA Level 2 Multi-Address Slave mode, the S/UNI-IMA-84 operates as a 31 port multi-PHY with each virtual PHY stored in its own FIFO. UTOPIA L2 Mode limits the S/UNI-IMA-84 to 31 IMA groups or TC links. A 4-bit configuration register, RCAEN, controls the response to polling the individual channels within this group of 31 ports. Setting RCAEN[0] enables addresses 0 through 7, and RCAEN[3] enables addresses 24 through 30. This is typically used to allow more than one slave device to share the Receive UTOPIA master bus. When polled, the Receive Packet Available (RPA) output indicates whether there is at least one cell available for transfer from the polled link. Upon selection, the interface handles data pausing anywhere in the middle of a cell transfer.

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10.1.2.2 UTOPIA Level 2 Single-Address Slave Mode

In UTOPIA Level 2 Single Address Slave mode, the S/UNI-IMA-84 operates as a single device with a single large 124 cell FIFO, with all cells being identified by their virtual PHY ID (VPHY ID) in an address prepend. Each IMA or TC connection is limited to a maximum of 16 cells in the FIFO. The address prepend may be optionally mapped to the HEC/UDF field in order to maintain the standard cell length. When the address presented on the Any-PHY/UTOPIA Interface RADR pins matches a programmable 5-bit configuration register (DEVID), the RXAPS will respond to polls. In all other cases, the output signals are tristated which allows other slave devices to respond. When polled, the RPA output indicates whether there is at least one cell available for transfer from any link.

10.1.2.3 Any-PHY Slave Mode

In Any-PHY Slave mode, the S/UNI-IMA-84 operates as a single device with a single large 124 cell FIFO, with all cells being identified by their virtual PHY ID (VPHY ID) in a address prepend. Each IMA or TC connection is limited to a maximum of 16 cells in the FIFO. When the address presented on the AnyPHY/UTOPIA Interface RADR pins matches a programmable 5-bit configuration register (DEVID), the RXAPS will respond to polls. In all other cases, the output signals are tristated which allows other slave devices to respond. When polled, the RPA output indicates whether there is at least one cell available for transfer from any link. In Any-PHY mode, data pausing is not supported.

To support current and future ATM Layer devices, the cell interface is configurable as either an Any-PHY or UTOPIA L2 interface. Table 2 summarizes the distinctions between the two protocols.

Table 2 UTOPIA L2 and Any-PHY Comparison

Attribute UTOPIA L2 Any-PHY

Latency RDAT[15:0], RPRTY, and

RSOP are driven or become high impedance immediately upon sampling RENB low or high, respectively. The RPA is driven with the cell availability status one CLK cycle after the RADR[4:0]

RDAT[15:0], RPRTY, RSOP and RSX are driven or become high impedance on the RCLK rising edge following the one that samples RENB low or high, respectively. The RPA is driven with the cell

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pins match the S/UNI-IMA84’s address. A match is defined as either matching the programmed value in single PHY mode or being within the correct range for multi-PHY mode.

RSX Undefined. It is low when not

high impedance.

RSOP High coincident with the first

word of the cell data structure.

Paused transfers

Permitted by deasserting RENB high, but the S/UNIIMA’s address must be presented on RADR[4:0] the last cycle RENB is high to reselect the same PHY.

Autonomous deselection

Not supported. A subsequent cell is output (provided one is available) if RENB is held low beyond the end of a cell.

availability status two CLK cycles after RADR[4:0] pins match the S/UNI-IMA-84’s address.

High coincident with the first word of the cell data structure.

High coincident with the first byte of the cell header.

Not Permitted.

The outputs become high impedance after the last word of a cell is transferred and until the S/UNI-IMA-84 is reselected.

10.1.2.4 Receive Cell Transfer Format

The cell format for the receive direction is the same as the transmit interface; see Figure 7 and Figure 8 for the formats.

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Figure 7 - 16-bit Receive Cell Transfer Format

Bits 15-8 Bits 7-0

Word 0

(Any-PHY and single channel UL2 only*)

Word 1

(Optional)

Word 2

Word 3

Word 4*

Word 5

Word 6

Word 28

Address Prepend

Optional Prepend

H1 H2

H3 H4

HEC/UDF

PAYLO AD1 PAYLO AD2

PAYLO AD3 PAYLO AD4

••

•••••

•

••

•

••

PAYLO AD47 PAYLO AD48

Note: Address prepend for Single Channel UL2 may be inserted in HEC/UDF field

instead of prior to the cell.

Figure 8 - 8-bit Receive Cell Transfer Format

Bits 7-0

Byte 0

Address Prepend

(Any-PHY and single channel UL2 only*)

Byte 1

Optional Prepend[15:8]

(Optional)

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Byte 2

Optional Prepend[7:0]

(Optional)

Byte 3

Byte 4

Byte 5

Byte 6

Byte 7*

Byte 8

•

••••

Byte 55

HEC

PAYLO AD1

PAYLO AD48

Note: Address prepend for Single Channel UL2 may be inserted in HEC/UDF field

instead of prior to the cell

For Any-PHY mode or single-PHY mode, the address prepend field encoding indicates the virtual PHY ID. The virtual PHY ID contains 2 sections, the lower 7 bits indicates the virtual PHY ID with valid values for 0 to 83, while the upper bits are user programmable and not used by the device but may be required in a user’s system for unique device identification when multiple devices exist on a bus.

For UTOPIA multi-PHY mode, the address prepend is not used.

10.1.3 Summary of Any-PHY/UTOPIA Modes

The following table summarizes the available modes of the Any-PHY/UTOPIA Interfaces

Mode Dir &

Protocol

TX Poll

UL2 Single PHY UL2 Multi-PHY Any-PHY

Not supported PHY Channels: 31 PHY Channels: 84

Channel Enable Register: Channel Enable Register:

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TCAEN(3:0) TCAEN(10:0)

Channel Address Pins: TADR(4:0) Device ID Register:

CFG_ADDR(10:7)

Status Pin: TCA Channel Address Pins: TADR(6:0)

Device Address Pins: TADR(10:7)

Address Qualifier Pin: TCSB

Status Pin: TCA

TX Select

Not supported PHY Channels: 31 PHY Channels: 84

Channel Enable Register:

TCAEN(3:0)

Channel Enable Register:

TCAEN(10:0)

Channel Address Pins: TADR(4:0) Device ID Register:

CFG_ADDR(15:7) or (7)

Select Pin: TENB Channel Address: Prepend bits

(6:0)

Device Address: Prepend bits (bit

15:7, for 16 bit mode) or (bit 7 for

8-bit mode)

Select Pin: TENB

TX Transfer

Not supported Cell Size: 8 bit X 53 or 55 bytes Cell Size: 8 bit X 54 or 56 bytes

Cell Size: 16 bit X 27 or 28 words Cell Size: 16 bit X 28 or 29 words

Enable Pin: TENB Enable Pin: TENB, TSX to indicate

first byte of transfer.

Pause in Cell: w/ TENB

RX Poll

PHY Channels: 1 PHY Channels: 31 PHY Channels: 1 (in-band

addressing is used to identify

virtual PHYs)

Device ID Register: DEVID(4:0) Channel Enable Register:

Device ID Register: DEVID(4:0)

RCAEN(3:0)

Device Address Pins: RADR(4:0) Channel Address Pins: RADR(4:0) Device Address Pins: RADR(4:0)

Status Pin: RCA Status Pin: RCA Status Pin: RCA

RX Select

PHY Channels: 1 PHY Channels: 31 PHY Channels: 1

Device ID Register: DEVID(4:0) Channel Enable Register:

Device ID Register: DEVID(4:0)

RCAEN(3:0)

Device Address Pins: RADR(4:0) Channel Address Pins: RADR(4:0) Device Address Pins: RADR(4:0)

Select Pin: RENB Select Pin: RENB Select Pin: RENB

RX Transfer

Cell Size: 8 bit X 53, 54, 55 or 56

Cell Size: 8 bit X 53 or 55 bytes Cell Size: 8 bit X 54 or 56 bytes

bytes

Cell Size: 16 bit X 27, 28 or 29

Cell Size: 16 bit X 27 or 28 words Cell Size: 16 bit X 28 or 29 words

words

Enable Pin: RENB Enable Pin: RENB Enable Pin: RENB

Channel Address: Prepend or UDF Pause in Cell: w/ RENB Channel Address: Prepend

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10.1.4 ANY-PHY/UTOPIA Loopback

For diagnostic purposes, the capability to loopback all Any-PHY/UTOPIA traffic back to the Any-PHY/UTOPIA bus is provided. Cells are taken from the Transmit group FIFOs and placed into the respective Receive Group FIFOs, or to a single FIFO on a space available basis. If the receive interface is in Any-PHY or single address UTOPIA L2 mode, all tx ports are looped back to the respective rx port. If the receive Interface is in multiple port UTOPIA L2 mode and the transmit AnyPHY is configured in 84-port Any-PHY mode, the 84 transmit ports will be aliased onto the 31 receive ports. Transmit port numbers 31 and 63 will be blocked and are not functional for loopback operations.

10.2 IMA Sub-layer

10.2.1 Overview

The IMA protocol provides inverse multiplexing of a single ATM stream over multiple physical links and reassembles the original cell stream at the far-end. The inverse multiplexing is performed on a cell basis; hence, the IMA protocol is described as a cell-based protocol. See Figure 9 below.

The protocol is based upon the concept of an IMA frame. An IMA frame is programmable in size and is delineated by an IMA Control Protocol (ICP) Cell. It is recommended that the ICP cells of each link in the IMA group be offset from each other to reduce the notification time of link/group status changes.

The transmitter is responsible for aligning the IMA frames on all links within a group, and for ensuring that cells are transmitted continuously by adding filler cells as necessary. To maintain frame alignment in the presence of independently timed line clocks, a cell based stuffing algorithm is utilized.

Since the IMA frames are aligned on transmission, this allows the receive end to recover the IMA frames and align them to remove any differential delay between the physical links.

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Figure 9 - Inverse Multiplexing

Single ATM Cell Stream from ATM Layer

Tx direction cells distributed across links in round robin sequence Rx direction cells recombined into single ATM stream

10.2.2 IDCC scheduler

The IMA Data Cell Clock (IDCC) scheduler calculates the IMA Data Cell Rate (IDCR) for each group that is used by both the Receive and the Transmit IMA processors. There is one scheduler for each direction (TXIDCC and RXIDCC), and each scheduler can monitor the rate of up to 84 reference clocks; each scheduler can also generate up to 84 IDCC clocks based upon IDCR. For each group, the reference link can be selected to be one of the 84 monitored links. Each of the monitored links can only be the reference link for one group. IDCR is calculated using the following equation, with N each IDCR generator. N frame, and TRL Cell Rate (TRLCR) is the cell rate of the reference link.

IMA Group

Physical Link #0

PHY

Physical Link #1

PHY

Physical Link #2

PHY

IMA Virtual LInk

is the number of active links, M is the size of the IMA

IMA Group

PHY

Original Cell stream passed to ATM Layer

PHY

and M set independently for

IDCR = N

X TRLCR X (M-1/M) X (2048/2049)

TRLCR is generated from the byte rate. The byte rate is obtained by monitoring the data transfers on the internal bus in the TC layer.

For each IDCR clock tick, a service request is generated and placed into a rate based FIFO. Since there may be many requests generated in a short amount of time and the rate at which each request is generated may be different, a method is required to arbitrate between the requests to prevent blocking of high rate requests by large numbers of low rate requests. To achieve this, each request is placed into a priority FIFO. The priority of the request is based upon its rate.

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There are a total of 5 rate-based FIFOs. When a service request is accepted by the Transmit IMA processor (TIMA) or the Receive IMA Data Processor (RDAT), the next request to be presented is taken from the highest priority FIFO that has an entry. In this manner, the higher rate requests get higher priority than the lower rate requests. Since the S/UNI-IMA-84 can always service all of the requests, this algorithm limits the CDV experienced by any service request to approximately one inter-arrival time of the service request for each group.

Rate changes are restricted to IMA frame boundaries. An IMA frame boundary occurs once every (M-1)*N service requests. When a request is received to change the rate(Non), the request is saved until the next IMA frame boundary, at which point it takes effect. By restricting rate changes to frame boundaries, the rate accuracy is preserved preventing FIFO underflows/overflows. Since rate changes are not instantaneous, a vector that represents the active Link IDs (LIDs) in the group is passed with the service request. In this manner, the entity receiving the service requests is informed of the change in rate and of which links should currently be in the round robin for servicing.

All IMA-based rate changes are internally managed by the S/UNI-IMA-84; no user interaction is necessary for correct scheduling.

The IDCC is also used for scheduling the TC data flow. In this case, the rate generated is simply the cell rate of the TC link and is not modified for IMA ICP cells or stuff cells according to the following equation:

IDCR = TRLCR

For all TC connections, the IDCC must be configured in TC mode for the physical link.

10.2.3 Transmit IMA Processor (TIMA)

The TIMA is responsible for the transmit IMA functions. This consists of distributing the cells arriving from the ATM layer to links in a group and for inserting ICP cells, filler cells, and stuff cells as required by the IMA protocol. Additionally, the TIMA can support cell transmission on connections using only the Transmission Convergence (TC) sublayer without the use of the IMA protocol sublayer.

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10.2.3.1 IMA Frame

The Transmit IMA processor creates the IMA frame by inserting an ICP cell after every (M-1) cells per link. Values of M supported are 32, 64, 128, and 256. The ICP cell is offset within the IMA frame. This offset is programmable on a per-link basis, and the offsets should spread throughout the frame. To avoid interaction between groups, the offsets within a group may not be aligned at the same offset. If offsets are aligned at the same offset within a group, the CDV experienced by other groups will be increased. Each frame is identified with an IMA frame sequence number (IFSN); this number is the same for every link in the group that is within the same frame and increments with each frame. The TIMA is responsible for aligning the transmission of the IMA frame on all links within a group.

10.2.3.2 Stuffing Procedure

The TIMA can support both Independent Transmit Clock (ITC) and Common Transmit Clock (CTC) modes. The difference between these modes is the stuffing protocol. The method of stuffing is set independently from the clocking mode present in the ICP cell.

In CTC mode, a stuff cell is added after 2048 cells on each link. The stuff cell is identical to the ICP cell and is inserted immediately following the ICP cell. The stuff cell events will occur on the same frame on all links; however, the programmed ICP offsets determine at which cell in the frame the stuff event will occur.

In ITC mode, a stuff cell is added to the reference link after 2048 cells on the reference link. On all other links in the group, stuff cells are added as necessary to compensate for data rate differences between the link and the reference link of the group. The added stuff cells (or lack of stuff cells) keep the data rate between links equalized.

The stuff cell is generated immediately after the ICP cell and both the ICP cell and the stuff cell are identified as stuff cells via the Link Stuff Indication (LSI) field of the ICP cell.

In CTC mode, the stuff event is always advertised in the ICP cell of the preceding frame. The stuff event may also be advertised in the 4 preceding frames. It is programmable per group whether the ICP cell is advertised starting 1 frame or 4 frames prior to the occurrence of the stuff event.

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In ITC mode, the stuff event may be advertised in the ICP cell of the preceding frame or in the four preceding frames. If the stuff event needs to be advertised for four preceding frames, a DS1/E1 clock tolerance of +/- 50 ppm, or better, is required. If a frequency tolerance of +/- 50 ppm cannot be met among the independent transmit clocks, the TIMA can provide the single frame advertisement of stuff events.

To determine when a stuff cell is needed on ITC mode links (not the TRL), a link stuff detection unit with rate counters is used to track the relative rate of data being read from the link FIFOs within a group to the rate of data being read from the TRL FIFO for the same group. When the relative rate counter indicates that the rate differences have accounted for a slip of a cell, a stuff cell is inserted.

10.2.3.3 Data Flow

The TIMA can support up to 84 groups (IMA group or TC link). Each FIFO on the ATM-layer interface side represents either an IMA group or a TC group. Each group’s behavior is controlled by the internal memory tables and records.

For IMA groups, the following internal memory structures are used:

1) the Transmit IMA Group Configuration Record for configuring group options and mapping to a port on the ATM interface (VPHY ID)

2) Transmit IMA Group Context Record contains statistics and the current ICP cell image.

3) Transmit LID to the PHYsical Link Mapping Table is used to map individual physical links into a group and assign the LIDs..

4) TIMA Physical Link Context Record contains per-link statistics, and state information.

For TC links, only one record is used, the Transmit Physical Link Record, to maintain statistics and to map the physical link to a port on the ATM interface (VPHY ID).

The TIMA performs cell transfers from the group FIFOs to the link FIFOs in response to service requests from the TxIDCC. The TxIDCC schedules both IMA groups, as well as low and high rate (DS3) TC-only connections. Groups are scheduled according to their rates. Higher-rate groups are prioritized above the lower-rate groups. The TIMA operates at a rate sufficient to ensure the TxIDCC will not suffer request congestion provided the ICP cells are spread throughout

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the frame on IMA groups. If there is no service request pending, the TIMA remains idle. If a group is unused, no cells will be pulled from the respective group FIFO. Therefore, when de-activating groups, ATM cell flow to the S/UNIIMA-84 should be terminated prior to de-activating the group in order to prevent stale data from being stored in the group FIFO.

10.2.3.3.1 IMA Service

For each IMA group-service request, a cell is transferred from the group FIFO to one of the link FIFOs. If no cell is available from the group FIFO, an IMA filler cell is generated and placed in the link FIFO. The link FIFOs within a group are serviced in a round-robin fashion, with the round-robin order determined by the LID. If the next link in the round robin is due to receive an ICP cell, the ICP cell is generated using the link and group state information from the Transmit IMA Group Context Record, and the LID and LSI from the link. If a stuff event is scheduled, the stuff ICP cell is also inserted. Whenever an ICP cell is inserted, the IMA group servicing proceeds to the next link in the round robin without waiting for another service request. The IMA group service is complete when either: (1) a cell is transferred from the group FIFO or (2) an ATM filler cell is generated. When links are in the process of being added, but are not yet available for carrying data traffic, IMA frames consisting of filler cells and ICP cells are generated. Such links are not scheduled by the TxIDCC scheduler, but will be processed with the currently active links.

During group start-up, even with all of the transmit links in the unusable state, the TxIDCC scheduler is started and IMA frames are generated. During group start-up (i.e. links are not yet in the active state), a group can be configured such that cells received via the UTOPIA L2 / Any-PHY bus can be dropped to avoid the accumulation of stale data or to drop stale data in the group FIFO left over from a previous use of the VPHY ID. . During link additions, IMA frames are generated on new links when they are added to the group.

10.2.3.3.2 TC Only Service

For TC-only mode groups, servicing is also initiated by group service requests from the TxIDCC. However, servicing a group FIFO simply entails transferring a cell from the group FIFO to the proper link FIFO. If a cell is not present in the group FIFO, no cells are transferred and the servicing of the request is complete. In TC mode, no other cells are inserted into the data stream by the IMA sub-layer (physical layer idle cells are generated by the physical layer).

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10.2.3.4 Timing Reference Link Maintenance

It is possible to have the timing reference link for an IMA group change from one link to another while the IMA connection is in operation. If an IMA group is operating in CTC mode, the reference link used for the scheduling is simply switched. The next stuff cell insertion still occurs 2049 cells after the previous stuff. If the IMA group is operating in ITC mode and the reference link is switched, the first stuff insertion on the new TRL occurs at approximately the same frame a stuff would have been inserted had it not become the TRL. At the time of the TRL change, the existing accrued rate differential on the new TRL is used to prorate the number of cells out of 2048 until the next TRL stuff. Although the first stuff will occur at approximately the proper number of cells to maintain the correct differential delay, the actual time of the stuff will be dependent on the new TRL rate.

Similarly, the first stuff cell insertion on the previous TRL occurs in approximately the same frame a stuff cell would have been inserted had it still been the TRL although the actual frame for stuff insertion will also be dependent on the rate difference with the new TRL. This minimizes any effects on the differential delay for the group as well as reducing any FIFO level changes. All subsequent stuff cell insertions on the TRL then happen after every 2048 cells and all subsequent stuff cell insertions on the former TRL are dependent only on the link’s rate difference from the new TRL.

10.2.4 Receive IMA Data Processor (RDAT)

The Receive IMA Data Processor (RDAT) performs the IMA data-flow functions in the receive direction including the IMA Frame Synchronization Mechanism (IFSM), storage of data for accommodating differential delay, defect detection, and playout of data in a round robin fashion.

The number of links and the differential delay tolerance required determine the SDRAM size used for the Delay Compensation Buffers (DCB). Two configurations of SDRAM are supported: 16 Mbit (1 Mbit x 16) and 64 Mbit (4 Mbit x 16), both are available as single chip devices. Differential-delay tolerance may be configured through registers on a per-group basis to any value up to the maximum listed in Figure 10. Buffering is allocated on a per link basis. Each link is allocated the same number of cell buffers. Either 256 or 1024 cell buffers may be allocated per link. See Figure 10 for the required memory sizes.

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Figure 10 - Max Differential Delay Tolerance vs. SDRAM Size

# of T1/E1 Links

32 T1/ 32 E 84 T1/ 63 E 84 T1 / 63 E 1024 279 ms 226 ms 4Mbit x16

Cells of Buffering

Delay (T1) in ms

1024 279 ms 226 ms 1Mbit x16

256 69 ms 56 ms 1Mbit x16

Delay (E1) in msSDRAM

size

10.2.4.1 Writing data to the Delay Compensation Buffers (DCB)

When there is a full cell of data in the RX Link FIFOs, the link requests service. In order to support DS3 rates, the Synchronous Payload Envelope (SPE) concept is carried over from the SBI Interface. The link FIFOs are divided into 3 groups where each group is given 1/3 of the bandwidth. The RDAT arbitrates between links requiring service within each group. If a group does not use its priority bandwidth, it is made available to the next group. This arbitration also works with the Clock/Data interface since all links should be close in rate.

When a link is chosen for service, if it is not an IMA link, the cells are stored in external memory in a per link FIFO.

For IMA links, the IFSM is performed to locate the IMA Frame. Once the IMA frame is located, the RDAT calculates the location to store the cells. The cells are stored in a time-based FIFO structure. The buffer address for a cell is created from the cell number in the IMA frame concatenated with the lower x (depends upon M) bits of the IMA frame sequence number. Each link has its own reserved FIFO. The cells are stored in this manner such that they are aligned in time in the external memory and the differential-delay removal is simplified.

During periods in which the link is in a defect state, incoming cells will be replaced with filler cells prior to being written to the DCB.

10.2.4.2 IMA Frame Synchronization Mechanism (IFSM)

For IMA links, the RDAT performs the IFSM. The IFSM is based upon the cell delineation mechanism in I.432. The details of the IFSM can be found in AF-PHY-

0086.001 “Inverse Multiplexing for ATM (IMA) Specification Version 1.1”, March

1999. The state Machine is shown in Figure 11.

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(

)

γγγγ

(

)

(

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Figure 11 - IFSM State Machine

alid ICP at unexpected position (with cell by cell huntin

Missing ICP Cell

Starting

State

αααα=

consecutive

invalid ICP cells

β=

consecutive

IMA SYNC

frame by frame

====

consecutive

valid ICP cells

errored ICP cells

IMA HUNT cell by cell

One invalid or

errored/missing

ICP cell

One valid

ICP cells

IMA PRESYNC

frame by frame

Valid ICP at unexpected position

(with cell by cell hunting)

During group start-up, the fields in the ICP cells are validated by the RX IMA Protocol Processor (RIPP) block and the validated information is used to determine whether the ICP cells are valid or not. Validation by the RIPP checks the group fields of the ICP cell to ensure that they match the rest of the group and checks the LID to ensure that it is unique in the group. An ICP cell is invalid if either the IMA OAM Label, the LID, the IMA_ID, M, IFSN or the offset is not the same as the validated values. If the ICP cell cannot be validated by the RIPP (i.e. the IMA_ID is different from the rest of the group or the LID is a duplicate), the IFSM will remain in the starting state.

Once the ICP cells are validated by the RIPP, the IFSM will enter the IMA Hunt state. In this state, each cell will be examined to see if it is a valid ICP cell. When a single valid ICP cell has been received, the IFSM will enter the IMA Presync state.

While in the Presync state, at each expected ICP location (determined by the ICP offset and the IMA Frame Length), the cell will be examined (frame by frame).

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Once gamma (γ=)=valid ICP cells have been received, the IFSM will enter the IMA Sync state. If either: (1) an invalid (or errored) ICP cell is received or (2) a valid ICP cell is received in an unexpected location, the IFSM will re-enter the IMA Hunt state. While in the IMA Hunt state, the stuff indicators will be ignored.

While in the IMA Sync state, ICP cells are continually examined for each frame. If beta (β=)=consecutive ICP cells with HEC, OCD, or CRC-10 errors (errored ICP cells) are received, then the IFSM will reenter the IMA Hunt state. Also, if alpha (α=)=consecutive invalid ICP cells are received, the IFSM will reenter the IMA Hunt state. If a cell is received at the expected ICP position without an HEC error or OCD and without the IMA OAM cell header, or is a filler cell, it is considered a missing ICP cell, and the IFSM will reenter the IMA Hunt state immediately. Finally, if a valid ICP cell is received at an unexpected position, the IFSM will reenter the IMA Hunt state.

Alpha, Beta, and Gamma are globally programmable for the device. The RDAT keeps working-counts for these parameters for each link. It should be noted that alpha (the count of consecutive invalid ICP cells) will not be reset upon receipt of an errored cell; although beta (the count of consecutive errored ICP cells) will be reset upon receipt of an invalid ICP cell.

10.2.4.3 Stuff Events

At this point, the RDAT detects and removes the stuff cells. Stuff cells are identified by the LSI field with the ICP cells. Stuff events consist of two back-toback ICP cells on the same link. One of the ICP cells is considered a stuff cell. Since stuff cells are inserted for the purpose of equalizing the data rate on links with independent clocks, stuff cells are removed.

To improve robustness in the presence of errors, the transmitter is required to advertise that a stuff event is going to occur in the ICP cell in the frame preceding the stuff event. The transmitter may also advertise the stuff event for the 4 frames preceding the stuff event.

Once a valid non-errored ICP cell has been received with a LSI of 001, 010, 011, or 100, the RDAT will maintain an internal stuff count in link-context memory. This count will be decremented every frame, until the stuff event occurs. The count will be decremented even if an incoming ICP cell is errored or invalid (as shown in Figure 12). An ICP cell received with an invalid stuff sequence (i.e., LSI of 001, when a LSI of 010 was expected) will be declared invalid, and the internal stuff count will be decremented from the previous value (as shown in Figure 13. The internal count is reset to the maximum when the stuff event occurs. A stuff

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sequence of 111 followed by 000 is not considered an invalid stuff sequence (i.e., the RDAT will always accept immediate notification of a stuff event, to support the case when the 001 stuff cell was errored).

Figure 12 - Stuff Event with Errored ICP (Advanced Indication)

Time

Stuff event

ICP Cell

IFSN # i+4

LSI = 111

IFSN: IMA Frame Sequence Number LSI: Link Stuffing Indication

ICP Cell

IFSN # i+3

LSI = 000

ICP Cell

IFSN # i+3

LSI = 000

ICP Cell

IFSN # i+2

LSI = 001

ICP Cell

Errored

Figure 13 - Invalid Stuff Sequence (Advanced Indication)

Time

Stuff event

ICP Cell

IFSN # i+4

LSI = 111

IFSN: IMA Frame Sequence Number LSI: Link Stuffing Indication

ICP Cell

IFSN # i+3

LSI = 000

ICP Cell

IFSN # i+3

LSI = 000

ICP Cell

IFSN # i+2

LSI = 001

ICP Cell

IFSN #i+1

LSI=001

M-1 Filler or

ATM Layer Cells

M-1 Filler or

ATM Layer Cells

ICP Cell IFSN # i

LSI = 011

stuff_cnt =3stuff_cnt =0 stuff_cnt =1 stuff_cnt =2stuff_cnt =7

ICP Cell IFSN # i

LSI = 011

stuff_cnt =3stuff_cnt =0 stuff_cnt =1 stuff_cnt =2stuff_cnt =7

10.2.4.4 IMA Frame Synchronization with Stuff Events

The RDAT will maintain synchronization while receiving stuff events subjected to HEC or CRC errors, as shown in Figure 14. When one of the ICP cells comprising a stuff event is errored or invalid, the other will be used. If both are errored or invalid, then the internally maintained stuff count will be used to identify the stuff event (given that the advanced indicators were correct).

All of the cases assume that the IFSM is in the IMA Sync state prior to the window shown, and that the current errored/invalid counts are zero. Cases (1) through (6) require that alpha or beta be programmed to a value greater than one for synchronization to be maintained. Case (7) requires that alpha or beta be

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programmed to a value greater than two for synchronization to be maintained. Case (7) also requires that advance link stuff indication be given prior to the window shown in order to detect the stuff event.

Figure 14 - Errored/Invalid ICP Cells in Proximity to a Stuff Event

Time

ICP n+1

ICP

ICPICP

ICP

…

ICP n

ICP

…

M-1 Filler or

TM Layer Cells

HEC/CRC Errored or Invalid ICP Cell

ICP

vent

ICP

Stuf

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10.2.4.5 Delay Compensation Buffers

Since IMA must re-create the original cell stream in the proper order, delay compensation buffers (DCBs) are used to remove the differential delay between the links in a group. As cells arrive from each link, they are placed in that link’s DCB. Links with the least transport delay will have the largest amount of data in the DCB, while links with the largest amount of transport delay will have the least amount of data in the DCB.

At group start-up, all the links are compared to determine the link with the largest transport delay and the link with the least transport delay. The difference between these is the differential delay. Data is queued for all links until the corresponding data arrives for the link with the largest transport delay. Figure 15, shows a group with 3 links with a differential delay of 5 cells. Link 0 has the shortest transport delay and link 2 has the longest transport delay. Once the data has arrived for all of the links, it is played out to the ATM layer at the IDCC rate, thus keeping the depths of each DCB at a nominally constant level. (Depths are instantaneously effected by the presence of stuff cells and ICP cells, but these effects are transitory).

Figure 15 - Snapshot of DCB Buffers

Write Pointer 0

Group Read Pointer

DCB Link 0

Write Pointer 1

DCB Link 1

DCB Link 2

Write

Pointer 2

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When a group is already started, IMA supports the addition of links to the group. As illustrated by Figure 15, adding a link with a transport delay that is within the range of the existing links does not present any problems. The DCB for the new link must be aligned with the existing links and added to the round-robin for playout.

Adding a link with a smaller transport delay increases the differential delay of the group. This requires that the depth of the DCB buffer be larger than any of the existing links. As long as the differential delay is within acceptable bounds, the new link can be accepted. The DCB for the new link is aligned with the existing links and added to the round-robin for playout.

Figure 16 - Snapshot of DCB Buffers after addition of Link with smaller transport delay

Write Pointer 0

Group Read Pointer

DCB Link 0

Write Pointer 1

DCB Link 1

Write Pointer 2

DCB Link 2

DCB Link3

Write Pointer 3

Adding a link with a larger transport delay requires the DCB buffer depth to be smaller than the DCB for the link with the largest delay. If the desired DCB depth for the new link is less than 0, this means that the data for the other links has been played out prior to the arrival of data for the new link. This is shown in Figure 17. For the new link to be accepted, delay must be added to all other links in the group. When delay is added to the other links in the group, the playout of ATM cells is halted until enough delay is built up. This causes CDV for the group.

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Once the delay has been added, the DCB for the new link can be aligned with the existing links and added to the round-robin for playout. Figure 18 shows the case after delay was added to the existing links within the group. The adding of delay to a group may be disabled. In this case, the new link would be rejected due to a LODS defect meaning that the DCB could not be aligned with the group.

Figure 17 - Snapshot of DCB Buffers when trying to add Link with larger transport delay

Write Pointer 0

Group Read Pointer

DCB Link 0

Write Pointer 1

DCB Link 1

Write Pointer 2

DCB Link 2

Write Pointer 3

DCB Link3

-5

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Figure 18 - Snapshot of DCB Buffers after delay adjustment

Write Pointer 0

Group Read Pointer

DCB Link 0

Write Pointer 1

DCB Link 1

Write Pointer 2

DCB Link 2

DCB Link3

Write Pointer 3

When links are deleted from a group, the DCB buffer depths of the remaining links are not effected. As shown in Figure 19, links 2 and 3 have been deleted from the group and the depth of the delay compensation buffers remain unchanged.

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Figure 19 - Snapshot of DCB Buffers after deletion of links from group

Write Pointer 0

Group Read Pointer

DCB Link 0

Write Pointer 1

DCB Link 1

10.2.4.6 IMA Link Error Handling

Removed from group

DCB Link 2

DCB Link3

Removed from group

For IMA operation, the RDAT is responsible for detecting Loss of IMA Frame defects (LIF), Idle Cells on IMA Links, Loss of Cell Delineation defects (LCD), and DCB overruns/underruns that contribute to Loss of Delay Synchronization (LODS). This information is forwarded to the RIPP with the ICP messages for processing and reporting.

10.2.4.6.1 IMA Error/Maintenance State Machine (IESM)

A state machine is maintained for the LIF defect detection. This state machine is called the IMA Error/Maintenance State machine [IESM]. The state diagram for the IESM is shown in Figure 20. The RDAT maintains an IESM for each link. The LIF Defect state is the initial state for this process, thus all links will initially come up in the LIF condition.

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Figure 20 - IMA Error/Maintenance State Diagram

Persistence of non-IMA Sync (γ+2) IMA frames

LIF

Defect

IMA

Working State

Leaving IMA Sync state

Entering IMA Sync state

Persistence of IMA SYNC for at least 2 IMA frames

Out of IMA

Frame (OIF)

Anomaly

State

The IMA Working state enables the RDAT to write user cells to the DCB. If the IFSM leaves the IMA Sync state, the IESM state machine will transition to the OIF Anomaly state, and the OIF anomaly counter will be incremented.

In the OIF Anomaly state, incoming user cells are written as filler cells to the DCB, and write pointers are incremented. If the IFSM does not return to the IMA Sync state within gamma + 2 frames, the IESM state will transition to the LIF Defect state. (Gamma is programmable, and is the same gamma used in the IFSM). If the IMA Sync state is entered prior to gamma + 2 frames, the IESM state will transition back to the IMA Working State. This is considered a “fast recovery” from the OIF Anomaly.

In the LIF Defect state, incoming user cells are written as filler cells to the DCB, and write pointers are incremented. The LIF-latched status bit will be set in the link-context memory. The IESM state machine will transition to the IMA Working state when IMA Sync has been detected for two consecutive IMA frames. If the IMA Sync state is entered and then exited during LIF, then the OIF anomaly counter will be incremented. When the IESM enters the working state, user cells may be forwarded once again if an overrun (with respect to the configured depth for the link) is not detected. The overrun detection provides the necessary differential-delay checking required after a defect.

10.2.4.6.2 Loss of Cell Delineation Status (LCD)

LCD is detected by the TC layer and the information is passed to the RDAT. When a link is in LCD, a LCD-latched status bit is set in link context memory,

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which is cleared by the ICP cell processing procedure. Cells received while the LCD latched status bit is set will be written to the DCB as filler cells, and the write pointers will be incremented. After an LCD condition is exited, the delay synchronization of the link must be rechecked and resynchronized. An LCD defect will cause the IFSM state machine to go into the hunt state to ensure the delay synchronization is rechecked. The transition of the IFSM into the hunt state will also cause an OIF anomaly.

10.2.4.6.3 DCB Overrun Status

When cells are written into the DCB, overruns will be checked by comparing the group read pointer against the link write pointer. If the difference between the pointers exceeds the maximum allowed DCB depth, then an overrun has been detected. For IMA, this will cause the overrun latched status-in-link context to be set.

An overrun condition will not cause the IFSM to exit the sync state.

All user cells will be dropped while the overrun condition persists. The overrun condition is reset at the reception of an ICP cell with an acceptable delay as long as the link is clear of LIF or OIF. For TC, an interrupt to the processor will be generated and normal operation will resume once the overrun condition has ended.

10.2.4.6.4 DCB Underrun Status

When cells are read from the DCB, underruns will be checked by comparing the group read pointer against the link write pointer. When an underrun is detected, all user cells will be dropped until the underrun condition is cleared. The underrun condition will only be cleared at the reception of an ICP cell, such that the differential delay may be re-checked. An underrun condition will not cause the IFSM to exit the sync state.

10.2.4.6.5 Idle Cells on IMA Links

When Idle cells are detected on an IMA link, they will be reported. Idle cells on IMA links may be present for two reasons. They may have been inserted at the ATM layer of the transmitter as a rudimentary method for traffic management; in which case the IMA layer should treat them as user cells. Otherwise, they may have been inserted at the TC layer to assist with rate matching; this is illegal for

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IMA links. Idle cells will be treated as user cells by the RDAT for IMA processing and will not be dropped at the IMA sub-layer.

10.2.4.7 DCB Playout

The IDCC scheduler provides the rate for data to be played out to the ATM layer for an IMA group. For each cell to be played out, the IDCC generates a service request. Upon the IDCC service request, the RDAT plays out data from the FIFOs in a round-robin fashion. For each service request, the RDAT runs the round robin servicing until it processes either a filler cell or user cell. If ICP cells are encountered, the ICP cell is dropped and the servicing continues until a user or filler cell is found. If a user cell is found, it is transferred from the external memory to the appropriate group FIFO. If a filler cell is found, it is dropped.

The RDAT is not sensitive to the alignment of ICP cells within a group. There is no performance degradation even if all of the ICP cells in a group have the same offset.

If the device is in Any-PHY mode or UTOPIA L2 Single Port mode, there is only a single FIFO shared among all of the groups. The RDAT ensures that no more than 16 cells are stored in the shared FIFO for a single group. If the S/UNI-IMA84 is in UTOPIA L2 Multi-port mode, each group has its own FIFO.

If the group FIFO is not emptied in a timely fashion, data is dropped; this is similar to the procedure used by any other PHY level device. The IDCC service request FIFO will always be serviced regardless of the state of the Group FIFO. For multi-port mode, if the respective Group FIFO is full, the cell will be dropped. In Any-PHY mode and UTOPIA L2 Single Port mode, if either the shared FIFO is full or there are already 16 cells for the current group in the FIFO, the cell will be dropped.

10.2.5 Receive IMA Protocol Processor (RIPP)

The Receive IMA Protocol Processor (RIPP) block is responsible for maintaining and controlling the link and group state machines. The RIPP can accept commands from the management plane to initiate group and link state machine actions. The RIPP then controls the contents of ICP cells generated for the transmit data path, as well as analyzes the link and group states received within the ICP cells. The receive link and group states are utilized to maintain and update the link and group states. The RIPP coordinates group wide state transactions and performs the group wide procedures such as the Synchronized Link activation during Group Start-up Procedure and the Link Addition and Slow

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Recovery (LASR) procedure. When the links change state, the RIPP also coordinates the rate change between the round-robin procedures located in the receive and transmit data paths and their respective rate schedulers.

Since failures are based upon the persistence of defects, the defects are detected and passed as interrupts/status to the management plane. PM is responsible for the integration of defects into failure conditions and to set the failure conditions in the S/UNI-IMA-84.

Table 3 PM command description

Command Description

Add_group Starts up a group state machine and the link

state machines for the links configured in the group. Group and links need to be configured prior to issuing this command. As a result of this command, the transmitter will start to send out IMA frames on the links specified as part of the group, and the receiver will start to look for and analyze ICP cells received on the links within the group. If a sufficient number of links are detected to be active, the group will transition to the operational state and start to transmit and receive ATM traffic.

Delete_group Remove an existing group and all its links

immediately. This command will take the group state machine to the “not configured” state and all of the links in the group to the “not in group” state. The transmit links will cease to transmit IMA frames and will commence to transmit physical-layer idle cells until the links are reused. For group deletion without any loss of data, the links may be deleted or inhibited to stop traffic on the group or the group may be inhibited prior to deleting the group.

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Restart_group Restart the specified group. When executed,

the GSM goes back to “start-up” state and all tx links return to the “unusable” state and the Rx links return to the “unusable” state but report “Not in Group” since the LID is not yet validated. This command is intended to enable the change of parameters during the group start-up phase and to provide a local group reset for other conditions.

Inhibit_group Set the internal group inhibiting status flag.

Once a group is considered inhibited, it will go to BLOCKED state instead of the OPERATIONAL state when sufficient links exist in the group.

If the group is already in OPERATIONAL state when the command is issued, the GSM will go to BLOCKED state, and thus block the TX data path. However, the RX data path remains on.

Not_inhibit_group Clear the internal group inhibiting status. If the

group is currently in BLOCKED state, the GSM will go to OPERATIONAL state.

Start_LASR Start LASR procedure on one or more links.

The links involved may either be new links or existing links with a failure/fault/inhibiting condition. If the group configuration is symmetric, links should be added in both the TX and RX direction.

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Datasheet PM7341 Datasheet (PMC)

Specifications and Main Features

Frequently Asked Questions

User Manual

REVISION HISTORY

CONTENTS

LIST OF FIGURES

LIST OF TABLES

LIST OF REGISTERS