Datasheet PM5381-BI Datasheet (PMC)

PRELIMINARY

/

DATASHEET PMC-2000489 ISSUE 1 SATURN USER NETWORK INTERFACE FOR 2488 MBIT/S

PMC-Sierra, Inc.

PM5381 S/UNI-2488

PM5381

ââââ

S

UNI-

2488

S/UNI-2488

SATURN

USER NETWORK INTERFACE

FOR 2488 MBIT/S

DATASHEET

PROPRIET A RY AND CONFIDENTIAL

PRELIMINARY

ISSUE 1: MARCH 2000

PMC-Sierra, Inc. 105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 .415.6000

PRELIMINARY

DATASHEET PMC-2000489 ISSUE 1 SATURN USER NETWORK INTERFACE FOR 2488 MBIT/S

PMC-Sierra, Inc.

PM5381 S/UNI-2488

LIST OF REGISTERS

REGISTER 0000H: S/UNI-2488 IDENTITY, AND GLOBAL PERFORMANCE MONITOR UPDATE......98

REGISTER 0001H: S/UNI-2488 MASTER RESET, CONFIGURATION, AND LOOPBACK....................99

REGISTER 0003H: S/UNI-2488 CLOCK MONITORS............................................................................102

REGISTER 0004H: S/UNI-2488 MASTER INTERRUPT STATUS #1 ....................................................104

REGISTER 0005H: S/UNI-2488 MASTER INTERRUPT STATUS #2 ....................................................105

REGISTER 0006H: S/UNI-2488 MASTER INTERRUPT STATUS #3 ....................................................106

REGISTER 0007H: S/UNI-2488 MASTER INTERRUPT STATUS #4 ....................................................107

REGISTER 0008H: S/UNI-2488 MASTER INTERRUPT STATUS #5 ....................................................108

REGISTER 0009H: S/UNI-2488 MASTER INTERRUPT STATUS #6 ....................................................110

REGISTER 000AH: S/UNI-2488 MASTER INTERRUPT STATUS #7....................................................112

REGISTER 000BH: UNUSED...................................................................................................................113

REGISTER 000CH: APS INPUT TELECOMBUS SYNCHRONIZATION DELAY...................................114

REGISTER 000DH: APS OUTPUT TELECOMBUS SYNCHRONIZATION DELAY ...............................115

REGISTER 000EH: S/UNI-2488 DIAGNOST ICS....................................................................................116

REGISTER 000FH: S/UNI-2488 FREE REGISTER.................................................................................118

REGISTER 0010H: RX2488 ANALOG INTERRUPT CONTROL/STATUS.............................................119

REGISTER 0011H: RX2488 ANALOG CRU CONTROL .........................................................................122

REGISTER 0012H: RX2488 ANALOG CRU CLOCK TRAINING CONFIGURATION AND STATUS ....125

REGISTER 0013H: RX2488 ANALOG PRBS CONTROL.......................................................................127

REGISTER 0014H: RX2488 ANALOG PAT T ERN REGISTER................................................................ 129

REGISTER 0030H: SRLI CLOCK CONFIGURATION.............................................................................130

REGISTER 0031H: SRLI PGM CLOCK CONFIGURATION....................................................................132

Proprietary and Confidentail to PMC-Sierra Inc., and for its Customer’s Internal Use iv

PRELIMINARY

DATASHEET PMC-2000489 ISSUE 1 SATURN USER NETWORK INTERFACE FOR 2488 MBIT/S

PMC-Sierra, Inc.

PM5381 S/UNI-2488

REGISTER 0038H: STLI CLOCK CONFIGURATION .............................................................................134

REGISTER 0039H: STLI PGM CLOCK CONFIGURATION....................................................................135

THE PROGRAMMABLE TRANSMIT CLOCK FREQUENCY SELECTION (PGMTCLKSEL) BIT SELECTS THE FREQUENCY OF THE PGMTCLK OUTPUT CLOCK. WHEN PGMTCLKSEL IS SET HIGH, PGMTCLK IS A NOMINAL 8 KHZ CLOCK. WHEN PGMTCLKSEL IS SET TO LOGIC ZERO,

PGMTCLK IS A NOMINAL REGISTER 0040H: RRMP CONFIGURATION............................................136

REGISTER 0041H: RRMP STATUS.........................................................................................................138

REGISTER 0042H: RRMP INTERRUPT ENABLE..................................................................................140

REGISTER 0043H: RRMP INTERRUPT STATUS...................................................................................141

REGISTER 0044H: RRMP RECEIVE APS...............................................................................................143

REGISTER 0045H: RRMP RECEIVE SSM..............................................................................................144

REGISTER 0046H: RRMP AIS ENABLE.................................................................................................145

REGISTER 0047H: RRMP SECTION BIP ERROR COUNTER...............................................................147

REGISTER 0048H: RRMP LINE BIP ERROR COUNTER (LSB)............................................................148

REGISTER 0049H: RRMP LINE BIP ERROR COUNTER (MSB)...........................................................148

REGISTER 004AH: RRMP LINE REI ERROR COUNTER (LSB) ...........................................................149

REGISTER 004BH: RRMP LINE REI ERROR COUNTER (MSB) ..........................................................149

REGISTER 0080H: TRMP CONFIGURATION.........................................................................................150

REGISTER 0081H: TRMP REGISTER INSERTION................................................................................153

REGISTER 0082H: TRMP ERROR INSERTION .....................................................................................156

REGISTER 0083H: TRMP TRANSMIT J0 AND Z0 .................................................................................158

REGISTER 0084H: TRMP TRANSMIT E1 AND F1.................................................................................159

REGISTER 0085H: TRMP TRANSMIT D1D3 AND D4D12.....................................................................160

REGISTER 0086H: TRMP TRANSMIT K1 AND K2 ................................................................................161

REGISTER 0087H: TRMP TRANSMIT S1 AND Z1.................................................................................162

Proprietary and Confidentail to PMC-Sierra Inc., and for its Customer’s Internal Use v

PRELIMINARY

DATASHEET PMC-2000489 ISSUE 1 SATURN USER NETWORK INTERFACE FOR 2488 MBIT/S

PMC-Sierra, Inc.

PM5381 S/UNI-2488

REGISTER 0088H: TRMP TRANSMIT Z2 AND E2.................................................................................163

REGISTER 0089H: TRMP TRANSMIT H1 AND H2 MASK.....................................................................164

REGISTER 008A: TRMP TRANSMIT B1 AND B2 MASK.......................................................................165

REGISTER 00A0H: TRMP AUX2 CONFIGURATION..............................................................................166

REGISTER 00C0H: TRMP AUX3 CONFIGURATION..............................................................................166

REGISTER 00E0H: TRMP AUX4 CONFIGURATION..............................................................................166

REGISTER 00A2H: TRMP AUX2 ERROR INSERTION ..........................................................................167

REGISTER 00C2H: TRMP AUX3 ERROR INSERTION ..........................................................................167

REGISTER 00E2H: TRMP AUX4 ERROR INSERTION ..........................................................................167

REGISTER 0110H: SBER CONFIGURATION .........................................................................................168

REGISTER 0111H: SBER STATUS..........................................................................................................170

REGISTER 0112H: SBER INTERRUPT ENABLE...................................................................................171

REGISTER 0113H: SBER INTERRUPT STATUS....................................................................................172

REGISTER 0114H: SBER SF BERM ACCUMULAT ION P ERIOD (LSB) ...............................................173

REGISTER 0115H: SBER SF BERM ACCUMULATION PERIOD (MSB)...............................................173

REGISTER 0116H: SBER SF BERM SATURATION THRESHOLD (LSB).............................................174

REGISTER 0117H: SBER SF BERM SATURATION THRESHOLD (MSB)............................................174

REGISTER 0118H: SBER SF BERM DECLARING THRESHOLD (LSB) ..............................................175

REGISTER 0119H: SBER SF BERM DECLARING THRESHOLD (MSB)..............................................175

REGISTER 011AH: SBER SF BERM CLEARING THRESHOLD (LSB) ................................................176

REGISTER 011BH: SBER SF BERM CLEARING THRESHOLD (MSB)................................................176

REGISTER 011CH: SBER SD BERM ACCUMULATION PERIOD (LSB) ..............................................177

REGISTER 011DH: SBER SD BERM ACCUMULATION PERIOD (MSB)..............................................177

REGISTER 011EH: SBER SD BERM SATURATION THRESHOLD (LSB)............................................178

Proprietary and Confidentail to PMC-Sierra Inc., and for its Customer’s Internal Use vi

PRELIMINARY

DATASHEET PMC-2000489 ISSUE 1 SATURN USER NETWORK INTERFACE FOR 2488 MBIT/S

PMC-Sierra, Inc.

PM5381 S/UNI-2488

REGISTER 011FH: SBER SD BERM SATURATION THRESHOLD (MSB) ...........................................178

REGISTER 0120H: SBER SD BERM DECLARATION THRESHOLD (LSB) .........................................179

REGISTER 0121H: SBER SD BERM DECLARATION THRESHOLD (MSB) ........................................179

REGISTER 0122H: SBER SD BERM CLEARING THRESHOLD (LSB) ................................................180

REGISTER 0123H: SBER SD BERM CLEARING THRESHOLD (MSB)................................................180

REGISTER 0130H: RTTP SECTION INDIRECT ADDRESS...................................................................181

REGISTER 0131H: RTTP SECTION INDIRECT DATA...........................................................................183

REGISTER 0132H: RTTP SECTION TRACE UNSTABLE STATUS.......................................................184

REGISTER 0133H: RTTP SECTION TRACE UNSTABLE INTERRUPT ENABLE ................................185

REGISTER 0134H: RTTP SECTION TRACE UNSTABLE INTERRUPT STATUS .................................186

REGISTER 0135H: RTTP SECTION TRACE MISMATCH STATUS.......................................................187

REGISTER 0136H: RTTP SECTION TRACE MISMATCH INTERRUPT ENABLE.................................188

REGISTER 0137H: RTTP SECTION TRACE MISMATCH INTERRUPT STATUS .................................189

INDIRECT REGISTER 00H: RTTP SECTION TRACE CONFIGURATION.............................................190

INDIRECT REGISTER 40H TO 7FH: RTTP SECTION CAPTURED TRACE .........................................192

INDIRECT REGISTER 80H TO BFH: RTTP SECTION ACCEPTED TRACE .........................................193

INDIRECT REGISTER C0H TO FFH: RTTP SECTION EXPECTED TRACE.........................................194

REGISTER 0138H: TTTP SECTION INDIRECT ADDRESS....................................................................195

REGISTER 0139H: TTTP SECTION INDIRECT DATA............................................................................197

INDIRECT REGISTER 0138H: TTTP SECTION TRACE CONFIGURATION .........................................198

INDIRECT REGISTER 40H TO 7FH: TTTP SECTION TRACE...............................................................199

REGISTER 0200H: RHPP STS-1/STM-0 #1 THROUGH #12 INDIRECT ADDRESS REGISTER 0280H: RHPP STS-1/STM-0 #13 THROUGH #24 INDIRECT ADDRESS REGISTER 0300H: RHPP STS-1/STM0 #25 THROUGH #36 INDIRECT ADDRESS REGISTER 0380H: RHPP STS-1/STM-0 #37 THROUGH

#48 INDIRECT ADDRESS........................................................................................................................200

Proprietary and Confidentail to PMC-Sierra Inc., and for its Customer’s Internal Use vii

PRELIMINARY

DATASHEET PMC-2000489 ISSUE 1 SATURN USER NETWORK INTERFACE FOR 2488 MBIT/S

PMC-Sierra, Inc.

PM5381 S/UNI-2488

REGISTER 0201H: RHPP STS-1/STM-0 #1 THROUGH #12 INDIRECT DATA REGISTER 0281H: RHPP STS-1/STM-0 #13 THROUGH #24 INDIRECT DATA REGISTER 0301H: RHPP STS-1/STM-0 #25 THROUGH #36 INDIRECT DATA REGISTER 0381H: RHPP STS-1/STM-0 #37 THROUGH #48

INDIRECT DATA.......................................................................................................................................202

REGISTER 0208H, 0210H, 0218H, 0220H, 0228H, 0230H, 0238H, 0240H, 0248H, 0250H, 0258H, 0260H REGISTER 0288H, 0290H, 0298H, 02A0H, 02A8H, 02B0H, 02B8H, 02C0H, 02C8H, 02D0H, 02D8H, 02E0H REGISTER 0308H, 0310H, 0318H, 0320H, 0328H, 0330H, 0338H, 0340H, 0348H, 0350H, 0358H, 0360H REGISTER 0388H, 0390H, 0398H, 03A0H, 03A8H, 03B0H, 03B8H, 03C0H, 03C8H, 03D0H, 03D8H, 03E0H: RHPP STS-1/STM-0 #N (WHERE N=1 TO 48) POINTER INTERPRETER STATUS 203

REGISTER 0209H, 0211H, 0219H, 0221H, 0229H, 0231H, 0239H, 0241H, 0249H, 0251H, 0259H, 0261H REGISTER 0289H, 0291H, 0299H, 02A1H, 02A9H, 02B1H, 02B9H, 02C1H, 02C9H, 02D1H, 02D9H, 02E1H REGISTER 0309H, 0311H, 0319H, 0321H, 0329H, 0331H, 0339H, 0341H, 0349H, 0351H, 0359H, 0361H REGISTER 0389H, 0391H, 0399H, 03A1H, 03A9H, 03B1H, 03B9H, 03C1H, 03C9H, 03D1H, 03D9H, 03E1H: RHPP STS-1/STM-0 #N (WHERE N=1 TO 48) POINTER INTERPRETER INTERRUPT ENABLE 205

REGISTER 020AH, 0212H, 021AH, 0222H, 022AH, 0232H, 023AH, 0242H, 024AH, 0252H, 025AH, 0262H REGISTER 028AH, 0292H, 029AH, 02A2H, 02AAH, 02B2H, 02BAH, 02C2H, 02CAH, 02D2H, 02DAH, 02E2H REGISTER 030AH, 0312H, 031AH, 0322H, 032AH, 0332H, 033AH, 0342H, 034AH, 0352H, 035AH, 0362H REGISTER 038AH, 0392H, 039AH, 03A2H, 03AAH, 03B2H, 03BAH, 03C2H, 03CAH, 03D2H, 03DAH, 03E2H:

RHP

P STS-1/STM-0 #N (WHERE N=1 TO 48) POINTER INTERPRETER INTERRUPT STATUS 207

REGISTER 020B: RHPP STS-1/STM-0 #1 ERROR MONITOR STATUS ...............................................209

REGISTER 020C: RHPP STS-1/STM-0 #1 ERROR MONITOR INTERRUPT ENABLE ........................211

REGISTER 020D: RHPP STS-1/STM-0 #1 ERROR MONITOR INTERRUPT STATUS .........................213

REGISTER 020E: RHPP STS-1/STM-0 #1 PATH BIP ERROR COUNTER ............................................215

REGISTER 020F: RHPP STS-1/STM-0 #1 PATH REI ERROR COUNTER............................................216

INDIRECT REGISTER 00H: RHPP POINTER INTERPRETER CONFIGURATION ...............................217

INDIRECT REGISTER 01H: RHPP ERROR MONITOR CONFIGURATION...........................................219

INDIRECT REGISTER 02H: RHPP POINTER VALUE AND ERDI..........................................................222

INDIRECT REGISTER 03H: RHPP CAPTURED AND ACCEPTED PSL................................................223

INDIRECT REGISTER 04H: RHPP EXPECTED PSL AND PDI..............................................................224

Proprietary and Confidentail to PMC-Sierra Inc., and for its Customer’s Internal Use viii

PRELIMINARY

DATASHEET PMC-2000489 ISSUE 1 SATURN USER NETWORK INTERFACE FOR 2488 MBIT/S

PMC-Sierra, Inc.

PM5381 S/UNI-2488

INDIRECT REGISTER 05H: RHPP GPO AND OTHER STATUS............................................................225

REGISTER 0400H: THPP STS-1/STM-0 #1 THROUGH #12 INDIRECT ADDRESS REGISTER 0480H: THPP STS-1/STM-0 #13 THROUGH #24 INDIRECT ADDRESS REGI STER 0500H: THPP STS-1/STM-0 #25 THROUGH #36 INDIRECT ADDRESS REGISTER 0580H: THPP STS-1/STM-0 #37 THROUGH #48

INDIRECT ADDRESS...............................................................................................................................227

REGISTER 0401H: THPP STS-1/STM-0 #1 THROUGH #12 INDIRECT DATA REGISTER 0481H: THPP STS-1/STM-0 #13 THROUGH #24 INDIRECT DATA REGISTER 0501H: THPP STS-1/STM-0 #25 THROUGH #36 INDIRECT DATA REGISTER 0581H: THPP STS-1/STM-0 #37 THROUGH #48

INDIRECT DATA.......................................................................................................................................229

REGISTER 0402: THPP PAYLO AD CONFIGUR ATION.......................................................................... 230

INDIRECT REGISTER 00H: THPP CONTROL REGISTER ....................................................................231

INDIRECT REGISTER 01H: THPP SOURCE AND POINTER CONTROL REGISTER..........................233

INDIRECT REGISTER 02H: THPP CURRENT POINTER REGISTER ...................................................235

INDIRECT REGISTER 03H: THPP ARBITRARY POINTER REGISTER................................................236

INDIRECT REGISTER 05H: THPP B3 MASK AND FIXED STUFF BYTE..............................................238

INDIRECT REGISTER 06H: THPP TRANSMIT C2 AND J1....................................................................239

INDIRECT REGISTER 07H: THPP TRANSMIT H4 MASK AND G1.......................................................240

INDIRECT REGISTER 08H: THPP TRANSMIT F2 AND Z3....................................................................241

INDIRECT REGISTER 09H: THPP TRANSMIT Z4 AND Z5....................................................................242

REGISTER 0600H: RSVCA INDIRECT ADDRESS.................................................................................243

REGISTER 0601H: RSVCA INDIRECT DATA.........................................................................................245

REGISTER 0603H: RSVCA POSITIVE JUSTIFICATION INTERRUPT STATUS ...................................248

REGISTER 0604H: RSVCA NEGATIVE JUSTIFICATION INTERRUPT STATUS.................................. 249

REGISTER 0605H: RSVCA FIFO OVERFLOW INTERRUPT STATUS..................................................250

REGISTER 0606H: RSVCA FIFO UNDERFLOW INTERRUPT STATUS ...............................................251

INDIRECT REGISTER 00H: RSVCA POINTER JUSTIFICATION INTERRUPT ENABLE.....................252

INDIRECT REGISTER 01H: RSVCA FIFO INTERRUPT ENABLE.........................................................253

Proprietary and Confidentail to PMC-Sierra Inc., and for its Customer’s Internal Use ix

PRELIMINARY

DATASHEET PMC-2000489 ISSUE 1 SATURN USER NETWORK INTERFACE FOR 2488 MBIT/S

PMC-Sierra, Inc.

PM5381 S/UNI-2488

INDIRECT REGISTER 02H: RSVCA POSITIVE JUSTIFICATIONS PERFORMANCE MONITOR........254

INDIRECT REGISTER 03H: RSVCA NEGATIVE JUSTIFICATIONS PERFORMANCE MONITOR ......255

INDIRECT REGISTER 04H: RSVCA DIAGNOSTIC/CONFIGURATION.................................................256

REGISTER 0680H: TSVCA INDIRECT ADDRESS..................................................................................258

REGISTER 0601H: TSVCA INDIRECT DATA..........................................................................................260

REGISTER 0603H: TSVCA POSITIVE JUSTIFICATION INTERRUPT STATUS....................................261

REGISTER 0604H: TSVCA NEGATIVE JUST IFICATION INTERRUPT STATUS ..................................262

REGISTER 0605H: TSVCA FIFO OVERFLOW INTERRUPT STATUS ..................................................263

REGISTER 0606H: TSVCA FIFO UNDERFLOW INTERRUPT STATUS................................................264

INDIRECT REGISTER 00H: TSVCA POINTER JUSTIFICATION INTERRUPT ENABLE .....................265

INDIRECT REGISTER 01H: TSVCA FIFO INTERRUPT ENABLE .........................................................266

INDIRECT REGISTER 02H: TSVCA POSITIVE JUSTIFICATIONS PERFORMANCE MONITOR ........267

INDIRECT REGISTER 03H: TSVCA NEGATIVE JUSTIFICATIONS PERFORMANCE MONITOR.......268

INDIRECT REGISTER 04H: TSVCA DIAGNOSTIC/CONFIGURATION.................................................269

REGISTER 0700H: RTTP PATH INDIRECT ADDRESS..........................................................................271

REGISTER 0701H: RTTP PATH INDIRECT DATA..................................................................................273

REGISTER 0702H: RTTP PATH TRACE UNSTABLE STATUS..............................................................274

REGISTER 0703H: RTTP PATH TRACE UNSTABLE INTERRUPT ENABLE.......................................275

REGISTER 0704H: RTTP PATH TRACE UNSTABLE INTERRUPT STATUS........................................276

REGISTER 0705H: RTTP PATH TRACE MISMATCH STATUS..............................................................277

REGISTER 0706H: RTTP PATH TRACE MISMATCH INTERRUPT ENABLE .......................................278

REGISTER 0707H: RTTP PATH TRACE MISMATCH INTERRUPT STATUS ........................................279

INDIRECT REGISTER 00H: RTTP PATH TRACE CONFIGURATION....................................................280

INDIRECT REGISTER 40H TO 7FH: RTTP PATH CAPTURED TRACE ................................................282

Proprietary and Confidentail to PMC-Sierra Inc., and for its Customer’s Internal Use x

PRELIMINARY

DATASHEET PMC-2000489 ISSUE 1 SATURN USER NETWORK INTERFACE FOR 2488 MBIT/S

PMC-Sierra, Inc.

PM5381 S/UNI-2488

INDIRECT REGISTER 80H TO BFH: RTTP PATH ACCEPTED TRACE................................................283

INDIRECT REGISTER C0H TO FFH: RTTP PATH EXPECTED TRACE................................................284

REGISTER 0708H: TTTP PATH INDIRECT ADDRESS ..........................................................................285

REGISTER 0709H: TTTP PATH INDIRECT DATA ..................................................................................287

INDIRECT REGISTER 00H: TTTP PATH TRACE CONFIGURATION....................................................288

INDIRECT REGISTER 40H TO 7FH: TTTP PATH TRACE......................................................................289

REGISTER 0720H: SARC INDIRECT ADDRESS ...................................................................................290

REGISTER 0722H: SARC SECTION CONFIGURATION........................................................................291

REGISTER 0723H: SARC SECTION SALM ENABLE............................................................................292

REGISTER 0724H: SARC SECTION RLAISINS ENABLE .....................................................................295

REGISTER 0725H: SARC SECTION TLRDIINS ENABLE .....................................................................296

REGISTER 0728H: SARC PATH CONFIGURATION ..............................................................................297

REGISTER 0729H: SARC PATH RALM ENABLE ..................................................................................299

REGISTER 072A: SARC PATH RPAISINS ENABLE..............................................................................300

REGISTER 0730H: SARC LOP POINTER STATUS................................................................................301

REGISTER 0731H: SARC LOP POINTER INTERRUPT ENABLE.........................................................302

REGISTER 0732H: SARC LOP POINTER INTERRUPT STATUS..........................................................303

REGISTER 0733H: SARC AIS POINTER STATU S .................................................................................304

REGISTER 0734H: SARC AIS POINTER INTERRUPT ENABLE ..........................................................305

REGISTER 0735H: SARC AIS POINTER INTERRUPT STATUS ...........................................................306

REGISTER 0740H: RCFP CONFIGURATION .........................................................................................307

REGISTER 0741H: RCFP INTERRUPT ENABLE...................................................................................310

REGISTER 0742H: RCFP INTERRUPT INDICATION AND STATUS .....................................................312

REGISTER 0743H: RCFP MINIMUM PACKET LENGTH........................................................................314

Proprietary and Confidentail to PMC-Sierra Inc., and for its Customer’s Internal Use xi

PRELIMINARY

DATASHEET PMC-2000489 ISSUE 1 SATURN USER NETWORK INTERFACE FOR 2488 MBIT/S

PMC-Sierra, Inc.

PM5381 S/UNI-2488

REGISTER 0744H: RCFP MAXIMUM PACKET LENGTH ......................................................................315

REGISTER 0745H: RCFP LCD COUNT THRESHOLD...........................................................................316

REGISTER 0746H: RCFP IDLE CELL HEADER AND MASK................................................................317

REGISTER 0747H: RCFP RECEIVE BYTE/IDLE CELL COUNTER (LSB)............................................319

REGISTER 0748H: RCFP RECEIVE BYTE/IDLE CELL COUNTER ......................................................319

REGISTER 0749H: RCFP RECEIVE BYTE/IDLE CELL COUNTER (MSB)...........................................319

REGISTER 074AH: RCFP PACKET/CELL COUNTER (LSB) ................................................................320

REGISTER 074BH: RCFP RECEIVE PACKET/ATM CELL COUNTER (MSB) ......................................320

REGISTER 074CH: RCFP RECEIVE ERRED FCS/HCS COUNTER......................................................321

REGISTER 074DH: RCFP RECEIVE ABORTED PACKET COUNTER..................................................322

REGISTER 074EH: RCFP RECEIVE MINIMUM LENGTH PACKET ERROR COUNTER .....................323

REGISTER 074FH: RCFP RECEIVE MAXIMUM LENGTH PACKET ERROR COUNTER ....................324

REGISTER 0750H: TCFP CONFIGURATION..........................................................................................325

REGISTER 0751H: TCFP INTERRUPT INDICATION .............................................................................328

REGISTER 0752H: TCFP IDLE/UNASSIGNED ATM CELL HEADER ...................................................329

REGISTER 0753H: TCFP DIAGNOSTICS...............................................................................................331

REGISTER 0754H: TCFP TRANSMIT CELL/PACKET COUNTER (LSB)..............................................333

REGISTER 0755H: TCFP TRANSMIT CELL/PACKET COUNTER (MSB).............................................333

REGISTER 0756H: TCFP TRANSMIT BYTE COUNTER (LSB).............................................................334

REGISTER 0757H: TCFP TRANSMIT BYTE COUNTER........................................................................334

REGISTER 0758H: TCFP TRANSMIT BYTE COUNTER (MSB)............................................................334

REGISTER 0759H: TCFP ABORTED PACKET COUNTER....................................................................335

REGISTER 0760H: RXSDQ FIFO RESET...............................................................................................336

REGISTER 0761H: RXSDQ FIFO INTERRUPT ENABLE......................................................................337

Proprietary and Confidentail to PMC-Sierra Inc., and for its Customer’s Internal Use xii

PRELIMINARY

DATASHEET PMC-2000489 ISSUE 1 SATURN USER NETWORK INTERFACE FOR 2488 MBIT/S

PMC-Sierra, Inc.

PM5381 S/UNI-2488

REGISTER 0763H: RXSDQ FIFO OVERFLOW PORT AND INTERRUPT INDICATION......................338

REGISTER 0764H: RXSDQ FIFO SOP ERROR PORT AND INTERRUPT INDICATION .....................339

REGISTER 0765H: RXSDQ FIFO EOP ERROR PORT AND INTERRUPT INDICATION .....................340

REGISTER 0768H: RXSDQ FIFO INDIRECT ADDRESS.......................................................................341

REGISTER 0769H: RXSDQ FIFO INDIRECT CONFIGURATION..........................................................343

REGISTER 076AH: RXSDQ FIFO INDIRECT DATA AVAILABLE THRESHOLD..................................345

REGISTER 076BH: RXSDQ FIFO INDIRECT CELLS AND PACKETS COUNT....................................346

REGISTER 076CH: RXSDQ FIFO CELLS AND PACKETS ACCEPTED AGGREGATE COUNT (LSB)

...................................................................................................................................................................347

REGISTER 076DH: RXSDQ FIFO CELLS AND PACKETS ACCEPTED AGGREGATE COUNT (MSB)

...................................................................................................................................................................347

REGISTER 076EH: RXSDQ FIFO CELLS AND PACKETS DROPPED AGGREGATE COUNT ...........348

REGISTER 0770H: TXSDQ FIFO RESET................................................................................................349

REGISTER 0771H: TXSDQ FIFO INTERRUPT ENABLE......................................................................350

REGISTER 0773H: TXSDQ FIFO OVERFLOW PORT AND INTERRUPT INDICATION ......................351

REGISTER 0774H: TXSDQ FIFO SOP ERROR PORT AND INTERRUPT INDICATION......................352

REGISTER 0775H: TXSDQ FIFO EOP ERROR PORT AND INTERRUPT INDICATION......................353

REGISTER 0778H: TXSDQ FIFO INDIRECT ADDRESS.......................................................................354

REGISTER 0779H: TXSDQ FIFO INDIRECT CONFIGURATION..........................................................356

REGISTER 077AH: TXSDQ FIFO INDIRECT DATA AND BUFFER AVAILABLE THRESHOLDS .......358

REGISTER 077BH: TXSDQ FIFO INDIRECT CELLS AND PACKETS COUNT ....................................360

REGISTER 077CH: TXSDQ FIFO CELLS AND PACKETS ACCEPTED AGGREGATE COUNT (LSB)

...................................................................................................................................................................361

REGISTER 077DH: TXSDQ FIFO CELLS AND PACKETS ACCEPTED AGGREGATE COUNT (MSB)

...................................................................................................................................................................361

REGISTER 077EH: TXSDQ FIFO CELLS AND PACKETS DROPPED AGGREGATE COUNT............362

Proprietary and Confidentail to PMC-Sierra Inc., and for its Customer’s Internal Use xiii

PRELIMINARY

DATASHEET PMC-2000489 ISSUE 1 SATURN USER NETWORK INTERFACE FOR 2488 MBIT/S

PMC-Sierra, Inc.

PM5381 S/UNI-2488

REGISTER 0780H: RXPHY CONFIGURATION.......................................................................................363

REGISTER 0781H: RXPHY INTERRUPT STATUS .................................................................................364

REGISTER 0782H: RXPHY INTERRUPT ENABLE ................................................................................365

REGISTER 0783H: RXPHY INDIRECT BURST SIZE .............................................................................366

REGISTER 0784H: RXPHY CALENDAR LENGTH................................................................................. 368

REGISTER 0785H: RXPHY CALENDAR INDIRECT ADDRESS DATA.................................................369

REGISTER 0786H: RXPHY DATA TYPE FIELD......................................................................................371

REGISTER 0788H: TXPHY CONFIGURATION.......................................................................................372

REGISTER 0789H: TXPHY INTERRUPT STATUS..................................................................................374

REGISTER 078AH: TXPHY INTERRUPT ENABLE ................................................................................375

REGISTER 078BH: TXPHY DATA TYPE FIELD .....................................................................................376

REGISTER 0790H: SIRP CONFIGURATION TIMESLOT .......................................................................377

REGISTER 079CH: SIRP CONFIGURATION ..........................................................................................380

REGISTER 0800H: PRGM INDIRECT ADDRESS...................................................................................382

REGISTER 0810H: PRGM AUX 2 INDIRECT ADDRESS.......................................................................382

REGISTER 0820H: PRGM AUX 3 INDIRECT ADDRESS.......................................................................382

REGISTER 0830H: PRGM AUX 4 INDIRECT ADDRESS.......................................................................382

REGISTER 0801H: PRGM INDIRECT DATA...........................................................................................384

REGISTER 0811H: PRGM AUX 2 INDIRECT D ATA................................................................................384

REGISTER 0821H: PRGM AUX 3 INDIRECT DATA...............................................................................384

REGISTER 0831H: PRGM AUX 4 INDIRECT DATA...............................................................................384

REGISTER 0802H: PRGM GENERATOR PAYLOAD CONFIGURATION..............................................385

REGISTER 0812H: PRGM AUX 2 GENERATOR PAYLOAD CONFIGURATION...................................385

REGISTER 0822H: PRGM AUX 3 GENERATOR PAYLOAD CONFIGURATION...................................385

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PM5381 S/UNI-2488

REGISTER 0832H: PRGM AUX 4 GENERATOR PAYLOAD CONFIGURATION...................................385

REGISTER 0803H: PRGM MONITOR PAYLOAD CONFIGURATION REGISTER ................................386

REGISTER 0813H: PRGM AUX 2 MONITOR PAYLOAD CONFIGURATION ........................................386

REGISTER 0823H: PRGM AUX 3 MONITOR PAYLOAD CONFIGURATION ........................................386

REGISTER 0833H: PRGM AUX 4 MONITOR PAYLOAD CONFIGURATION ........................................386

REGISTER 0804H: PRGM MONITOR BYTE ERROR INTERRUPT STATUS........................................387

REGISTER 0814H: PRGM AUX 2 MONITOR BYTE ERROR INTERRUPT STATUS ............................387

REGISTER 0824H: PRGM AUX 3 MONITOR BYTE ERROR INTERRUPT STATUS ............................387

REGISTER 0834H: PRGM AUX 4 MONITOR BYTE ERROR INTERRUPT STATUS.............................387

REGISTER 0805H: PRGM MONITOR BYTE ERROR INTERRUPT ENABLE.......................................388

REGISTER 0815H: PRGM AUX 2 MONITOR BYTE ERROR INTERRUPT ENABLE............................388

REGISTER 0825H: PRGM AUX 3 MONITOR BYTE ERROR INTERRUPT ENABLE............................388

REGISTER 0835H: PRGM AUX 4 MONITOR BYTE ERROR INTERRUPT ENABLE............................388

REGISTER 0806H: MONITOR B1/E1 BYTES INTERRUPT STATUS ....................................................389

REGISTER 0807H: MONITOR B1/E1 BYTES INTERRUPT ENABLE....................................................390

REGISTER 0808H: MONITOR B1/E1 BYTES STATUS ..........................................................................391

REGISTER 0809H: PRGM MONITOR SYNCHRONIZATION INTERRUPT STATUS.............................392

REGISTER 0819H: PRGM AUX 2 MONITOR SYNCHRONIZATION INTERRUPT STATUS .................392

REGISTER 0829H: PRGM AUX 3 MONITOR SYNCHRONIZATION INTERRUPT STATUS .................392

REGISTER 0839H: PRGM AUX 4 MONITOR SYNCHRONIZATION INTERRUPT STATUS .................392

REGISTER 080AH: PRGM MONITOR SYNCHRONIZATION INTERRUPT ENABLE...........................393

REGISTER 081AH: PRGM AUX 2 MONITOR SYNCHRONIZATION INTERRUPT ENABLE................393

REGISTER 082AH: PRGM AUX 3 MONITOR SYNCHRONIZATION INTERRUPT ENABLE................393

REGISTER 083AH: PRGM AUX 4 MONITOR SYNCHRONIZATION INTERRUPT ENABLE................393

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REGISTER 080BH: PRGM MONITOR SYNCHRONIZATION STATUS..................................................394

REGISTER 081BH: PRGM AUX 2 MONITOR SYNCHRONIZATION STATUS ......................................394

REGISTER 082BH: PRGM AUX 3 MONITOR SYNCHRONIZATION STATUS ......................................394

REGISTER 083BH: PRGM AUX 4 MONITOR SYNCHRONIZATION STATUS ......................................394

INDIRECT REGISTER 0800H: PRGM MONITOR TIMESLOT CONFIGURATION PAGE......................395

INDIRECT REGISTER 0801H: PRGM MONITOR PRBS[22:7] ACCUMULATOR PAGE.......................397

INDIRECT REGISTER 0802H: PRGM MONITOR PRBS[6:0] ACCUMULATOR PAGE.........................397

INDIRECT REGISTER 0803H: PRGM MONITOR B1/E1 VALUE PAGE ................................................398

INDIRECT REGISTER 0804H: PRGM MONITOR ERROR COUNT PAGE ............................................399

INDIRECT REGISTER 0805H: PRGM MONITOR RECEIVED B1/E1 BYTES PAGE.............................400

INDIRECT REGISTER 0808H: PRGM GENERATOR TIMESLOT CONFIGURATION PAGE................401

INDIRECT REGISTER 0809H : PRGM GENERATOR PRBS[22:7] ACCUMULATOR PAGE................403

INDIRECT REGISTER 080AH: PRGM GENERATOR PRBS[6:0] ACCUMULATOR PAGE ..................403

INDIRECT REGISTER 080BH: PRGM GENERATOR B1/E1 VALUE PAGE..........................................404

REGISTER 0840H: R8TD APS1 CONTROL AND STATUS....................................................................405

REGISTER 0848H: R8TD APS2 CONTROL AND STATUS....................................................................405

REGISTER 0850H: R8TD APS3 CONTROL AND STATUS....................................................................405

REGISTER 0858H: R8TD APS4 CONTROL AND STATUS....................................................................405

REGISTER 0841H: R8TD APS1 INTERRUPT STATUS..........................................................................408

REGISTER 0849H: R8TD APS2 INTERRUPT STATUS..........................................................................408

REGISTER 0851H: R8TD APS3 INTERRUPT STATUS..........................................................................408

REGISTER 0859H: R8TD APS4 INTERRUPT STATUS..........................................................................408

REGISTER 0842H: R8TD APS1 LINE CODE VIOLATION COUNT .......................................................410

REGISTER 084AH: R8TD APS2 LINE CODE VIOLATION COUNT.......................................................410

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REGISTER 0852H: R8TD APS3 LINE CODE VIOLATION COUNT .......................................................410

REGISTER 085AH: R8TD APS4 LINE CODE VIOLATION COUNT.......................................................410

REGISTER 0843H: R8TD APS1 ANALOG CONTROL 1........................................................................411

REGISTER 084BH: R8TD APS2 ANALOG CONTROL 1........................................................................411

REGISTER 0853H: R8TD APS3 ANALOG CONTROL 1........................................................................411

REGISTER 085BH: R8TD APS4 ANALOG CONTROL 1........................................................................411

REGISTER 0844H: R8TD APS1 ANALOG CONTROL 2........................................................................412

REGISTER 084CH: R8TD APS2 ANALOG CONTROL 2........................................................................412

REGISTER 0854H: R8TD APS3 ANALOG CONTROL 2........................................................................412

REGISTER 085CH: R8TD APS4 ANALOG CONTROL 2........................................................................412

REGISTER 0860H: T8TE APS1 CONTROL AND STATUS .....................................................................413

REGISTER 0868H: T8TE APS2 CONTROL AND STATUS .....................................................................413

REGISTER 0870H: T8TE APS3 CONTROL AND STATUS .....................................................................413

REGISTER 0878H: T8TE APS4 CONTROL AND STATUS .....................................................................413

REGISTER 0861H: T8TE APS1 INTERRUPT STATUS...........................................................................415

REGISTER 0869H: T8TE APS2 INTERRUPT STATUS...........................................................................415

REGISTER 0871H: T8TE APS3 INTERRUPT STATUS...........................................................................415

REGISTER 0879H: T8TE APS4 INTERRUPT STATUS...........................................................................415

REGISTER 0862H: T8TE APS1 TELECOMBUS MODE #1....................................................................416

REGISTER 086AH: T8TE APS2 TELECOMBUS MODE #1 ...................................................................416

REGISTER 0872H: T8TE APS3 TELECOMBUS MODE #1....................................................................416

REGISTER 087AH: T8TE APS4 TELECOMBUS MODE #1 ...................................................................416

REGISTER 0863H: T8TE APS1 TELECOMBUS MODE #2....................................................................417

REGISTER 086BH: T8TE APS2 TELECOMBUS MODE #2 ...................................................................417

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REGISTER 0873H: T8TE APS3 TELECOMBUS MODE #2....................................................................417

REGISTER 087BH: T8TE APS4 TELECOMBUS MODE #2 ...................................................................417

REGISTER 0864H: T8TE APS1 TEST PATTERN ...................................................................................418

REGISTER 086CH: T8TE APS2 TEST PATTERN...................................................................................418

REGISTER 0874H: T8TE APS3 TEST PATTERN ...................................................................................418

REGISTER 087CH: T8TE APS4 TEST PATTERN...................................................................................418

REGISTER 0865H: T8TE APS1 ANALOG CONTROL............................................................................419

REGISTER 086DH: T8TE APS2 ANALOG CONTROL...........................................................................419

REGISTER 0875H: T8TE APS3 ANALOG CONTROL............................................................................419

REGISTER 087DH: T8TE APS4 ANALOG CONTROL...........................................................................419

REGISTER 0866H: T8TE APS1 DTB BUS..............................................................................................421

REGISTER 086EH: T8TE APS2 DTB BUS..............................................................................................421

REGISTER 0876H: T8TE APS3 DTB BUS..............................................................................................421

REGISTER 087EH: T8TE APS4 DTB BUS..............................................................................................421

REGISTER 0880H-0883H: RFCLK DLL RESERVED .............................................................................422

REGISTER 0884H-0887H: TFCLK DLL RESERVED..............................................................................423

REGISTER 0888H: CSTR CONTROL......................................................................................................424

REGISTER 0889H: CSTR INTERRUPT ENABLE AND CSU LOCK STATUS .......................................425

REGISTER 088AH: CSTR CSU LOCK INTERRUPT INDICATION ........................................................426

REGISTER 088BH: CSTR CSU LOCK INTERRUPT INDICATION ........................................................427

REGISTER 0890H-0897: S/UNI-2 488 RX STSI RESERVED ..................................................................428

REGISTER 0898H-089F: S/UNI-2488 TX STSI RESERVED ..................................................................429

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LIST OF TABLES

TABLE 1: PLM-P, UNEQ-P AND PDI-P DEFECTS DECLARATION ..........................................................60

TABLE 2: EXPECTED PDI DEFECT BASED ON PDI AND PDI RANGE VALUES ...................................61

TABLE 3: BYTE DESTUFFING..................................................................................................................69

TABLE 4: TOH INSERTION PRIORITY ......................................................................................................73

TABLE 5: Z0/NATIONAL GROWTH BYTES DEFINITION FOR ROW #1..................................................75

TABLE 6: BYTE STUFFING.......................................................................................................................78

TABLE 7: REGISTER MEMORY MAP........................................................................................................83

TABLE 8 CRU MODE CONTRO L .............................................................................................................123

TABLE 9: FUNCTIONALITY OF THE CRC_SEL[1:0] REGISTER BITS ..................................................308

TABLE 10: AVERAGE STS-X CELL PERIOD VERSUS LCD INTEGRATION PERIOD ..........................316

TABLE 11: SELECTION OF THE NUMBER OF FLAG BYTES...............................................................325

TABLE 12: CRC MODE SELECTION ......................................................................................................326

TABLE 13: SIRP RDI AND REI REPORTING MODES............................................................................378

TABLE 14: SIRP RDI SETTINGS.............................................................................................................378

TABLE 15: SIRP RDI MAINTENANCE.....................................................................................................379

TABLE 16: SIRP RDI PRIORITY SCHEMES...........................................................................................381

TABLE 17: ABSOLUTE MAXIMUM RATINGS.........................................................................................449

TABLE 18: D.C CHARACTERISTICS......................................................................................................450

TABLE 19: MICROPROCESSOR INTERFACE READ ACCESS (FIGURE 26)......................................453

TABLE 20: MICROPROCESSOR INTERFACE WRITE ACCESS (FIGURE 27) ....................................455

TABLE 21: RECEIVE SYSTEM INTERFACE TIMING (FIGURE 28).......................................................457

TABLE 22: TRANSMIT SYSTEM INTERFACE TIMING (FIGURE 29)....................................................459

TABLE 23: JTAG PORT INTERFACE (FIGURE 30)................................................................................461

TABLE 24: ORDERING INFORMATION..................................................................................................463

TABLE 25: THERMAL INFORMATION .....................................................................................................463

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LIST OF FIGURES

FIGURE 1: STS-48 (STM-16-16C) ATM (UTOPIA LEVEL 3) SWITCH PORT APPLICATION 11 FIGURE 2: STS-48 (STM-16-16C) PACKET OVER SONET (POS-PHY LEVEL 3) ROUTER

APPLICATION 12 FIGURE 3:NORMAL OPERATION 13 FIGURE 4:LOOPBACK MODES 14 FIGURE 5: APS WORKING 15 FIGURE 6: APS PROTECT 16 FIGURE 7: TYPICAL STS-48C (STM-16C) JITTER TOLERANCE 50 FIGURE 8: STS-48C (STM-16-16C) ON RTOH 53 FIGURE 9: POINTER INTERPRETATION STATE DIAGRAM 55 FIGURE 10: CONCATENATION POINTER INTERPRETATION STATE DIAGRAM 58 FIGURE 11: POINTER GENERATION STATE DIAGRAM 64 FIGURE 12: CELL DELINEATION STATE DIAGRAM 66 FIGURE 13: PPP/HDLC OVER SONET FRAME FORMAT 68 FIGURE 14: CRC DECODER 69 FIGURE 15: STS-48C (STM-16-16C) ON TTOH 73 FIGURE 16: CRC GENERATOR 78 FIGURE 17: GENERIC LVDS LINK BLOCK DIAGRAM 430 FIGURE 18 ATM MAPPING 433 FIGURE 19 PACKET OVER SONET MAPPING 434 FIGURE 20: A 52 BYTE ATM DATA STRUCTURE 438 FIGURE 21: A 63 BYTE PACKET DATA STRUCTURE 438 FIGURE 22 SINGLE-PHY UTOPIA LEVEL 3 RECEIVE FUNCTIONAL TIMING 441 FIGURE 23 SINGLE-PHY UTOPIA LEVEL 3 TRANSMIT FUNCTIONAL TIMING 442 FIGURE 24 SINGLE PHY POS-PHY LEVEL 3 RECEIVE FUNCTIONAL TIMING 444 FIGURE 25 SINGLE PHY POS-PHY LEVEL 3 TRANSMIT FUNCTIONAL TIMING 445 FIGURE 26: INTEL MICROPROCESSOR INTERFACE READ TIMING 454 FIGURE 27: INTEL MICROPROCESSOR INTERFACE WRITE TIMING 455 FIGURE 28: RECEIVE SYSTEM INTERFACE TIMING DIAGRAM 458 FIGURE 29: TRANSMIT SYSTEM INTERFACE TIMING 460 FIGURE 30: JTAG PORT INTERFACE TIMING 462

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1 FEATURES

1.1 General

• Single chip ATM and POS User-Network Interface operating at 2488.32 Mbit/s.

• Implements the ATM Forum User Network Interface Specification and the ATM physical layer for

Broadband ISDN according to CCITT Recommendation I.432.

• Implements the Point-to-Point Protocol (PPP) over SONET/SDH specification according to RFC

2615(1619)/1662 of the PPP Working Group of the Internet Engineering Task Force (IETF).

• Processes bit-serial 2488.32 Mbit/s STS-48 (STM-16-16c) data streams with on-chip clock and data

recovery and clock synthesis.

• Complies with Bellcore GR-253-CORE jitter tolerance, jitter transfer and intrinsic jitter criteria.

• Provides termination for SONET Section, Line and Path overhead or SDH Regenerator Section,

Multiplexer Section and High Order Pat h over h ead.

• Provides UTOPIA Level 3 32-bit wide System Interface (clocked up to 104 MHz) with parity support

for ATM applications.

• Provides SATURN POS-PHY Level 3ä 32-bit System Interface (clocked up to 104 MHz) for Packet

over SONET (POS), or ATM applications.

• Supports line loopback from the line side receive stream to the transmit stream and diagnostic

loopback from the line side transmit stream to the line side receive stream interface.

• Provides support for automatic protection switching via a 4-bit LVDS 777.76 MHz port.

• Provides a standard 5 signal IEEE 1149.1 JTAG test port for boundary scan board test purposes.

• Provides a generic 16-bit microprocessor bus interface for configuration, control, and status

monitoring.

• Low power 1.8V CMOS core logic with 3.3V CMOS/TTL compatible digital inputs and digital outputs.

PECL inputs and outputs are 3.3V compatible.

• Industrial temperature range (-40C to +85C).

• 416 pin UBGA package.

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1.2 SONET Section and Line / SDH Regenerator and Multiplexer Section

• Frames to the SONET/SDH receive stream and inserts the framing bytes (A1, A2) and the section

trace byte (J0) into the transmit stream; descrambles the received stream and scrambles the transmit stream.

• Calculates and compares the bit interleaved parity (BIP) error detection codes (B1, B2) for the receive

stream. Calculates and inserts B1 and B2 in the transmit stream. Accumulates near end errors (B1, B2) and far end errors (M1) and inserts line remote error indications (REI) into the M1 byte based on received B2 errors.

• Detects signal degrade (SD) and signal fail (SF) threshold crossing alarms based on received B1

errors.

• Extracted and optionally inserts on dedicated pins the SONET/SDH transport overhead for an STS-

48c/STM-16c frame.

• Extracts and serializes on dedicated pins the data communication channels (D1-D3, D4-D12) and

inserts the corresponding signals into the transmit stream.

• Extracts and filters the automatic protection switch (APS) channel (K1, K2) bytes into internal

registers. Inserts the APS channel into the transmit stream.

• Extracts and filters the synchronization status message (S1) byte into an internal register for the

receive stream. Inserts the synchronization status message (S1) byte into the transmit stream.

• Extracts a 64 byte (Bellcore compatible) or 16 byte (ITU compatible) section trace (J0) message using

an internal register bank for the receive stream. Detects an unstable message or mismatch message with an expected message. Provides access to the accepted message via the microprocessor port. Inserts a 64 byte or 16 byte section trace (J0) message using an internal register bank for the transmit stream.

• Detects loss of signal (LOS), out of frame (OOF), loss of frame (LOF), line remote defect indication

(RDI-L), line alarm indication signal (AIS-L), and protection switching byte failure alarms on the receive stream.

• Configurable to force Line AIS in the transmit stream.

• Provides automatic transmit line RDI insertion following detection of various received alarms (LOS,

LOF, LAIS, SD, SF, STIM, STIU).

• Provides automatic DROP bus line AIS insertion following detection of various received alarms (LOS,

LOF, LAIS, SD, SF, STIM, STIU).

• Support Automatic Protection Switching (APS) via a serial 4x777.76 LVDS mate protection port.

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1.3 SONET Path / SDH High Order Path

• Interprets the received payload pointer (H1, H2) and extracts the STS-48c/STM-16c synchronous

payload envelope and path overhead.

• Detects loss of pointer (LOP), path alarm indication signal (PAIS) and path (normal and enhanced)

remote defect indication (RDI) for the receive stream. Optionally inserts path alarm indication signal (PAIS) and path remote defect indication (RDI) in the transmit stream.

• Extracts and insert the entire SONET/SDH path overhead to and from dedicated pins. The path

overhead bytes may be sourced from internal registers or from bit serial path overhead input stream. Path overhead insertion may also be disabled.

• Extracts the received path payload label (C2) byte into an internal register and detects for payload

label unstable (PLU), payload label mismatch (PLM), payload unequipped (UNEQ) and payload defect indication (PDI). Inserts the path payload label (C2) byte from an internal register for the transmit stream.

• Extracts a 64 byte or 16 byte path trace (J1) message using an internal register bank for the receive

stream. Detects an unstable message or mismatch message with an expected message. Provides access to the captured, accepted and expected message via the microprocessor port. Inserts a 64 byte or 16 byte path trace (J1) message using an internal register bank for the transmit stream.

• Detects received path BIP-8 and counts received path BIP-8 errors for performance monitoring

purposes. BIP-8 errors are selectable to be treated on a bit basis or block basis. Optionally calculates and inserts path BIP-8 error detection codes for the transmit stream.

• Counts received path remote error indications (REI’s) for performance monitoring purposes.

Optionally inserts the path REI count into the path status byte (G1) based on bit or block BIP-8 errors detected in the receive path. Reporting of BIP-8 errors is on a bit or block basis independent of the accumulation of BIP-8 errors.

• Provides automatic transmit path RDI and path Enhanced RDI insertion following detection of various

received alarms (LAIS, LOP, LOPCON, PAIS, PAISCON, PTIM, PTIU, PLM, PLU, UNEQ, PDI).

1.4 The Receive ATM Processor

• Extracts ATM cells from the received STS-48c/STM16-16c channel payloads using ATM cell

delineation.

• Provides ATM cell payload de-scrambling.

• Performs header check sequence (HCS) error detection and correction, and idle/unassigned cell

filtering.

• Detects out of cell delineation (OCD) and loss of cell delineation (LCD) alarms.

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• Counts number of received cells, idle cells, erred cells and dropped cells.

• Provides UTOPIA Level 3 and POS-PHY Level 3 32-bit wide datapath interfaces (clocked up to 104

MHz) with parity support to read extracted cells from an internal 8 cell FIFO buffer.

1.5 The Receive POS Processor

• Supports packet based link layer protocols using byte synchronous HDLC framing.

• Performs self-synchronous POS data de-scrambling on the received STS-48c/STM16c-16c payloads

using the x

43

+1 polynomial.

• Performs flag sequence detection and terminates the received POS frames.

• Performs frame check sequence (FCS) validation for CRC-CCITT and CRC-32 polynomials.

• Performs control escape de-stuffing or byte de-stuffing of the POS stream.

• Detects packet abort sequence.

• Checks for minimum and maximum packet lengths. Optionally deletes short packets and marks

those exceeding the maximum length as erred.

• Permits FCS stripping on the POS-PHY output data stream.

• Provides a SATURN POS-PHY Level 3 compliant 32-bit datapath interface (clocked up to 104 MHz)

with parity support to read packet data from an internal 256 byte FIFO buffer.

1.6 The Transmit ATM Processor

• Provides idle/unassigned cell insertion.

• Optionally provides HCS generation/insertion, and ATM cell payload scrambling.

• Counts the number of transmitted cells.

• Provides UTOPIA Level 3 and POS-PHY Level 3 32-bit wide datapath interfaces (clocked up to 104

MHz) with parity support for writing cells into an internal channel FIFO.

1.7 The Transmit POS Processor

• Supports any packet based link layer protocol using byte synchronous and bit synchronous framing

like PPP, HDLC and Frame Relay.

43

• Performs self-synchronous POS data scrambling using the 1+X

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• Encapsulates packets within a POS/HDLC frame.

• Performs flag sequence insertion.

• Performs byte stuffing for transparency processing.

• Optionally performs frame check sequence generation using the CRC-CCITT and CRC-32

polynomials.

• Aborts packets under the direction of the host or when the FIFO underflows.

• Provides a SATURN POS-PHY Level 3 compliant 32-bit wide datapath (clocked up to 104 MHz) with

parity support to an internal FIFO buffer.

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2 APPLICATIONS

• ATM/ Multi-service Enterprise, Access, Edge and Core switches

• Packet Over Sonet interfaces for Access, Edge and Core routers

• SONET/SDH Add/Drop Multiplexers and Terminal Multiplexers with data processing capabilities

• DWDM Optical networking equipment requiring SONET/SDH capabilities

• Network Interface Cards and Uplinks

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PM5381 S/UNI-2488

3 REFERENCES

• Bell Communications Research - GR-253-CORE “SONET Transport Systems: Common Generic

Criteria”, Issue 2 Revision 2, January 1999.

• Bell Communications Research - GR-436-CORE “Digital Network Synchronization Plan”, Issue 1

Revision 1, June 1996..

• ANSI - T1.105-1995, “Synchronous Optical Network (SONET) – Basic Description including Multiplex

Structure, Rates, and Formats”, 1995.

• ANSI T1.107 - 1995, "Digital Hierarchy - Formats Specifications".

• ANSI T1.107a - 1990, "Digital Hierarchy - Supplement to Formats Specifications (DS3 Format

Applications)".

• ANSI T1.627 - 1993, "Broadband ISDN - ATM Layer Functionality and Specification".

• ETS 300 417-1-1, "Generic Functional Requirements for Synchronous Digital Hierarchy (SDH)

Equipment", January, 1996.

• ITU-T Recommendation G.703 - "Physical/Electrical Characteristics of Hierarchical Digital Interfaces",

1991.

• ITU-T Recommendation G.704 - "General Aspects of Digital Transmission Systems; Terminal

Equipment - Synchronous Frame Structures Used At 1544, 6312, 2048, 8488 and 44 736 kbit/s Hierarchical Levels", July 1995.

• ITU, Recommendation G.707 - "Network Node Interface For The Synchronous Digital Hierarchy",

1996.

• ITU Recommendation G781, “Structure of Recommendations on Equipment for the Synchronous

Design Hierarchy (SDH)”, January 1994.

• ITU, Recommendation G.783 - "Characteristics of Synchronous Digital Hierarchy (SDH) Equipment

Functional Blocks", 1996.

• ITU Recommendation I.432, “ISDN User Network Interfaces”, 1993.

• ITU Recommendation I.432, “ISDN User Network Interfaces”, March 93.

• ATM Forum - ATM User-Network Interface Specification, V3.1, October, 1995.

• ATM Forum – STR-PHY-UL3-01.00, “UTOPIA Level 3”, April, 1999.

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PM5381 S/UNI-2488

• IETF Network Working Group – RFC-1619, “Point to Point Protocol (PPP) over SONET/SDH

Specification”, May 1994.

• IETF Network Working Group – RFC-1661, “The Point to Point Protocol (PPP)”, July, 1994.

• IETF Network Working Group – RFC-1662, “PPP in HDLC like framing”, July 1994.

• IETF Network Working Group – RFC-2615, “Point to Point Protocol (PPP) over SONET/SDH”, June

1999.

• PMC-980495, “SATURN Compatible Interface for Packet Over SONET Physical Layer and Link Layer

Devices (Level 3)”, Issue 3, Dec. 2, 1998.

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4 DEFINITIONS

The following table defines the abbreviations for the S/UNI-2488.

A TM Asynchronous Transfer Mode CSU Clock Synthesis Unit DRU Data Recovery Unit FCS Frame Check Sequence FIFO First-In-First-Out storage element HCS Header Check Sequence LVDS Low Voltage Differential Signaling NNI Network-to-Network Interface POS Packet Over SONET PRGM PRBS Generator and Monitor RCFP Receive Cell and Frame Processor Block RHPP Receive High order Path Processor RRMP Receive Regenerator Multiplexer Processor RTTP Received Tail T race Processor RXSDQ Receive Scalable Data Queue FIFO RXSIF Receive Slave Interface (UL3 or POS L3) SRLI SONET/SDH Receive Line Interface STLI SONET/SDH Transmit Line Imterface STSI SONET/SDH Time Slot Interchange SVCA SONET/SDH Virtual Container Aligner TCFP Transmit Cell and Frame Processor Block THPP Transmit High order Path Processor TRMP Transmit Regenerator Multiplexer Processor TTTP Transmit T ail Trace Processor TXSIF Transmit Slave Interface (UL3 or POS L3)

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PM5381 S/UNI-2488

5 APPLICATION EXAMPLES

The PM5381 S/UNI-2488 is applicable to equipment implementing Asynchronous Transfer Mode (ATM) User-Network Interfaces (UNI), ATM Network-Network Interfaces (NNI), as well as Packet over SONET (POS) interfaces. The POS interface can support several packet based protocols, including the Point-to-Point Protocol (PPP). The S/UNI-2488 may find application at either end of switch-to-switch links, router to router links, switch to router links or switch-to-terminal links, in public and privite wide area networks (WAN). The S/UNI-2488 provides a comprehensive feature set as well as full compliance to WAN synchronization requirements. The S/UNI-2488 performs the mapping of either ATM cells or POS frames into the SONET/SDH STS-48 (STM-16-16c) synchronous payload envelope (SPE) and processes applicable SONET/SDH section, line and path overheads.

In a typical STS-48 (STM-16-16c) ATM application, the S/UNI-2488 performs clock and data recovery in the receive direction and clock synthesis in the transmit direction of the line interface. On the system side, the S/UNI-2488 interfaces directly with ATM layer processors and switching or adaptation functions using a UTOPIA Level 3 compliant 32-bit (clocked up to 104 MHz) synchronous FIFO style interface. An application with a UTOPIA Level 3 system side interface is shown in Figure 1. The initial configuration and ongoing control and monitoring of the S/UNI2488 are normally provided vi a a generic m ic ropr oc es sor interf ace.

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PM5381 S/UNI-2488

Figure 1: STS-48 (STM-16-16c) ATM (UTOPIA Level 3) Switch Port Application

PM7325 S/UNI-ATLAS3200 ATM Layer Device

TxClk

TxEnb

TxClav

TxSOC

TxPrty

TxData[31:0]

RxClk

RxEnb

RxClav

RxSOC

RxPrty

RxData[31:0]

PM5381

S/UNI-2488

TFCLK TENB TCA TSOC TPRTY TDAT[31:0]

RFCLK RENB RCA

POSL3_UL3B

RSOC RPRTY RDAT[31:0]

RXD+/-

SD

TXD+/-

Optical

Transceiver

0

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In a typical Packet over SONET application (i.e. using the PPP protocol) the S/UNI-2488 performs clock and data recovery in the receive direction and clock synthesis in the transmit direction of the line interface. On the system side, the S/UNI-2488 interfaces directly with a data link layer processor using a SATURN POS-PHY Level 3 32-bit (clocked up to 104 MHz) synchronous FIFO interface over which packets are transferred. The initial configuration and ongoing control and monitoring of the S/UNI-2488 are normally provided via a generic microprocessor interface.

Figure 2: STS-48 (STM-16-16c) Packet over SONET (POS-PHY Level 3) Router Application

PMC-Sierra, Inc.

PM5381 S/UNI-2488

Link Layer

Device

TFCLK

TENB DTPA TSOP

TPRTY

TDAT[31:0]

RFCLK

RENB

RSOP

RPRTY

RSX

PM5381

S/UNI-2488

TFCLK TENB

DTP A TSOP

TPRTY TDAT[31:0] TMOD[1:0]TMOD[1:0] TEOPTEOP TERRTERR

RFCLK RENB RSX RSOP

POSL3_UL3B

RPRTY

RXD+/-

SD

TXD+/-

Optical

Transceiver

1

RDAT[31:0]

RMOD[1:0]

RDAT[31:0] RMOD[1:0] REOPREOP RERRRERR

RVALRVAL

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PM5381 S/UNI-2488

APSI+/-[4:1]

ROHCLK ROHFP

RTOH

RPOH RPOHEN B3E

APSIFP

PMC-Sierra, Inc.

PGMRCLK

SD

RXD+/-

OOF

RCLK

TCLK

TXD+/-

REFCLK+/-

PGMTCLK

C0 C1 C2 C3

RES RESK

ATP[3:0]

SBER

(1)

SRLI

(1)

Rx

Line

I/F

Tx

Line

I/F

STLI

(1)

Analog

RTTP

(1)

RRMP

(4)

TRMP

(4)

TTTP

(1)

RTTP

(1)

RHPP

(4)

SVCA

(4)

TxLVRef

CSU

D8E

(4)

APISO

(4)

TXLV

(4)

RXLV

(4)

DRU

(4)

R8TB

(4)

SIRP

(1)

THPP

(4)

TTTP

(1)

PRGM

(4)

Microprocessor

STSI

(1)

STSI

(1)

RCFP

(1)

TCFP

(1)

RXSDQ

FIFO

SARC

TXSDQ

FIFO

(1)

RXPHY

(1)

TXPHY

(1)

JTAG

RMOD[1:0] RSX RERR REOP RFCLK RDAT[31:0] RPRTY RSOC/RSOP RCA/RVAL RENB

SALM

RALM

POSL3_UL3B

TMOD[1:0] TERR TEOP TFCLK TDAT[31:0] TPRTY TSOC/TSOP TCA/DTPA TENB

PRELIMINARY

ALE

CSB

RDB

INTB

WRB

A[13:0]

Figure 3:Normal Operation

TOHCLK TOHFP

DATASHEET

PMC-2000489 ISSUE 1 SATURN USER NETWORK INTERFACE FOR 2488 MBIT/S

6 BLOCK DIAGRAM

TPOHRDY

TTOH TTOHEN

APSOFP

APSMODE

APSO+/-[4:1]

D[15:0]

TPOH TPOHEN

RSTB

TDI

TDO

TCK

TMS

TRSTB

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Figure 4:Loopback modes

TOHCLK TOHFP

TTOH TTOHEN

TPOHRDY

APSO+/-[4:1]

APSOFP

APSMODE

TPOH TPOHEN

D[15:0]

A[13:0]

ALE

CSB

WRB

RDB

RSTB

INTB

RES RESK

ATP[3:0]

Analog

(1)

TxLVRef

CSU

TXLV

(4)

Microprocessor

C2 C3

TTTP

APISO

(1)

C0 C1

D8E

(4)

TTTP

REFCLK+/-

PGMTCLK

TXD+/-

LINE LOOPBACK

TCLK

RCLK

(SLLE=1)

STLI

(1)

(4)

Line

I/F

Tx

TRMP

SERIAL DIAGNOSTIC

LOOPBACK (SDLE=1)

or

PARALLEL DIAGNOSTIC

LOOPBACK (PDLB=1)

THPP

(1)

FIFO

STSI

TCFP

TXSDQ

(1)

SIRP

PRGM

(4)

SARC

(4)

(1)

OOF

I/F

RXD+/-

SD

Line

Rx

(1)

PGMRCLK

(1)

(4)

(1)

FIFO

SRLI

RRMP

RHPP

(4)

SVCA

(4)

STSI

RCFP

RXSDQ

(4)

SBER

(1)

RTTP

(1)

ROHCLK ROHFP RTOH

RTTP

(1)

RPOH RPOHEN B3E

(4)

DRU

(4)

RXLV

APSI+/-[4:1] APSIFP

R8TB

TDO

TDI

TMS

TCK

TRSTB

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JTAG

TENB

TCA/DTPA

TXPHY

(1)

TMOD[1:0]

TERR

POSL3_UL3B

TEOP

TFCLK

TDAT[31:0]

TPRTY

TSOC/TSOP

RENB

RALM

SALM

(1)

RFCLK

RDAT[31:0]

RPRTY

RSOC/RSOP

RCA/RVAL

RXPHY

REOP

RERR

RMOD[1:0]

RSX

from

protect

mate

PM5381 S/UNI-2488

PMC-Sierra, Inc.

PGMRCLK

SD

RXD+/-

OOF

RCLK

TCLK

TXD+/-

REFCLK+/-

PGMTCLK

C0 C1 C2 C3

RES RESK

ATP[3:0]

SBER

(1)

SRLI

(1)

Rx

Line

I/F

Tx

Line

I/F

STLI

(1)

Analog

RTTP

(1)

RRMP

(4)

TRMP

(4)

TTTP

(1)

ROHCLK ROHFP

RTOH

RTTP

(1)

RHPP

(4)

TxLVRef

RPOH RPOHEN B3E

SVCA

(4)

CSU

APSI+/-[4:1]

RXLV

(4)

DRU

(4)

R8TB

(4)

D8E

(4)

APISO

(4)

TXLV

(4)

APSIFP

(MODE=10,

APS Failover

APSMODE=1)

SIRP

(1)

THPP

(4)

TTTP

(1)

STSI

PRGM

(4)

STSI

Microprocessor

(1)

RCFP

(1)

TCFP

(1)

RXSDQ

FIFO

SARC

TXSDQ

FIFO

(1)

RMOD[1:0] RSX RERR

RXPHY

(1) RDAT[31:0]

TXPHY

(1)

JTAG

REOP RFCLK

RPRTY RSOC/RSOP RCA/RVAL RENB

SALM

RALM

POSL3_UL3B

TMOD[1:0] TERR TEOP TFCLK TDAT[31:0] TPRTY TSOC/TSOP TCA/DTPA TENB

PRELIMINARY

ALE

CSB

RDB

INTB

WRB

A[13:0]

Figure 5: APS Work ing

TOHCLK TOHFP

DATASHEET

PMC-2000489 ISSUE 1 SATURN USER NETWORK INTERFACE FOR 2488 MBIT/S

TPOHRDY

TTOH TTOHEN

APSOFP

APSMODE

APSO+/-[4:1]

to

mate

protect

D[15:0]

TPOH TPOHEN

RSTB

TDI

TDO

TCK

TMS

TRSTB

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from

working

mate

PM5381 S/UNI-2488

PMC-Sierra, Inc.

PGMRCLK

SD

RXD+/-

OOF

RCLK

TCLK

TXD+/-

REFCLK+/-

PGMTCLK

C0 C1 C2 C3

RES RESK

ATP[3:0]

SBER

(1)

SRLI

(1)

Rx

Line

I/F

Tx

Line

I/F

STLI

(1)

Analog

RTTP

(1)

RRMP

(4)

TRMP

(4)

TTTP

(1)

ROHCLK ROHFP

RTOH

RTTP

(1)

RHPP

(4)

TxLVRef

RPOH RPOHEN B3E

SVCA

(4)

APSI+/-[4:1]

RXLV

(4)

DRU

(4)

R8TB

(4)

APS Failover

D8E

(4)

APISO

(4)

TXLV

CSU

(4)

APSIFP

(MODE=11,

ASPMODE=0)

SIRP

(1)

THPP

(4)

TTTP

(1)

PRGM

(4)

Microprocessor

STSI

(1)

STSI

(1)

RCFP

(1)

TCFP

(1)

RXSDQ

FIFO

SARC

TXSDQ

FIFO

(1)

RMOD[1:0] RSX RERR

RXPHY

(1) RDAT[31:0]

TXPHY

(1)

JTAG

REOP RFCLK

RPRTY RSOC/RSOP RCA/RVAL RENB

SALM

RALM

POSL3_UL3B

TMOD[1:0] TERR TEOP TFCLK TDAT[31:0] TPRTY TSOC/TSOP TCA/DTPA TENB

PRELIMINARY

ALE

CSB

RDB

INTB

WRB

A[13:0]

TPOHRDY

Figure 6: APS Protect

DATASHEET

PMC-2000489 ISSUE 1 SATURN USER NETWORK INTERFACE FOR 2488 MBIT/S

TOHCLK TOHFP

TTOH TTOHEN

APSOFP

APSMODE

APSO+/-[4:1]

to

mate

working

D[15:0]

TPOH TPOHEN

RSTB

TDI

TDO

TCK

TMS

TRSTB

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7 DESCRIPTION

The PM5381 S/UNI-2488 SATURN User Network Interface is a monolithic integrated circuit that implements SONET/SDH processing, ATM mapping and Packet over SONET mapping functions at the STS-48 (STM-16-16c) 2488.32 Mbit/s rate.

The S/UNI-2488 receives SONET/SDH streams using a bit serial interface, recovers the clock and data and processes section, line, and path overhead. The S/UNI-2488 performs framing (A1, A2), de-scrambling, detects alarm conditions, and monitors section, line, and path bit interleaved parity (B1, B2, B3), accumulating error counts at each level for performance monitoring purposes. Line and path remote error indications (M1, G1) are also accumulated. The S/UNI-2488 interprets the received payload pointers (H1, H2) and extracts the synchronous payload envelope which carries the received ATM cells or POS frames.

When used to implement an ATM UNI or NNI, the S/UNI-2488 frames to the ATM payload using cell delineation. HCS error correction is provided. Idle/unassigned cells may be optionally dropped. Cells are also dropped upon detection of an uncorrectable header check sequence error. The ATM cell payloads are descrambled and are written to a 8-cell FIFO buffer. The received cells are read from the FIFO using a 32-bit wide UTOPIA Level 3 (clocked up to 104 MHz) datapath interface. Counts of received ATM cell headers that are errored and uncorrectable and those that are errored and correctable are accumulated independently for performance monitoring purposes.

When used to implement packet transmission over a SONET/SDH link, the S/UNI-2488 extracts Packet over SONET (POS) frames from the SONET/SDH synchronous payload envelope. Frames are verified for correct construction and size. The control escape characters are removed. The frame check sequence is optionally verified for correctness and the extracted packets are placed in a receive FIFO. The received packets are read from the FIFO through a 32-bit POS-PHY Level 3 (clocked up to 104 MHz) system side interface. Valid and FCS errored packet counts are provided for performance monitoring. The S/UNI-2488 Packet over SONET implementation is flexible enough to support several link layer protocols, including HDLC, PPP and Frame Relay.

The S/UNI-2488 transmits SONET/SDH streams using a bit serial interface. The S/UNI-2488 synthesizes the transmit clock from a 155.52MHz frequency reference and performs framing pattern insertion (A1, A2), scrambling, alarm signal insertion, and creates section, line, and path bit interleaved parity codes (B1, B2, B3) as required to allow performance monitoring at the far end. Line and path remote error indications (M1, G1) are also inserted. The S/UNI-2488 generates the payload pointer (H1, H2) and inserts the synchronous payload envelope that carries the ATM or POS frames. The S/UNI-2488 also supports the insertion of a large variety of errors into the transmit stream, such as framing pattern errors, bit interleaved parity errors, and illegal pointers, which are useful for system diagnostics and tester applications.

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When used to implement an ATM UNI or NNI, ATM cells are written to an internal 8 cell FIFO using a 32-bit wide UTOPIA Level 3 (clocked up to 104 MHz) datapath interface. Idle/unassigned cells are automatically inserted when the internal FIFO contains less than one complete cell. The S/UNI-2488 provides generation of the header check sequence and scrambles the payload of the ATM cells. Each of these transmit ATM cell processing functions can be enabled or bypassed.

When used to implement a Packet over SONET/SDH link, the S/UNI-2488 inserts POS frames into the SONET/SDH synchronous payload envelope. Packets to be transmitted are written into a 256-byte FIFO through a 32-bit SATURN POS-PHY Level 3 (clocked up to 104 MHz) system side interface. POS frames are built by inserting the flags, control escape characters and the FCS fields. Either the CRC-CCITT or CRC-32 can be computed and added to the frame. Several counters are provided for performance monitoring.

No line rate clocks are required directly by the S/UNI-2488 as it synthesizes the transmit clock and recovers the receive clock using a 155.52 MHz reference clock. The S/UNI-2488 outputs a differential PECL line data (TXD+/-).

The S/UNI-2488 is configured, controlled and monitored via a generic 16-bit microprocessor bus interface. The S/UNI-2488 also provides a standard 5 signal IEEE 1149.1 JTAG test port for boundary scan board test purposes.

The S/UNI-2488 is implemented in low power, +1.8 Volt, CMOS technology. It has TTL compatible digital inputs and TTL/CMOS compatible digital outputs. High speed inputs and outputs support 3.3V compatible pseudo-ECL (PECL). The S/UNI-2488 is packaged in a 416 pin UBGA package.

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8 PIN DIAGRAMS

TBD

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9 SDPIN DESCRIPTION

9.1 Serial Line Side Interface Signals (7) Pin Name Type Pin

REFCLK+ REFCLK-

RXD+ RXD-

Differential

PECL Input

Differential

PECL Input

SD TTL

Input

No.

AK10 AK9

AK16 AK15

AH24

Function

The differential refer ence clo ck inputs (REFCLK+/-) provides a jitter-free 155.52 MHz reference clock for both the clock recovery and the clock synthesis circuits. The 8kHz frame pulse, APSIFP is sampled upon a rising edge transition of REFCLK+/- (i.e. APSIFP is phase-synchronous with REFCLK+/). APSOFP is updated upon a rising edge transition of REFCLK+/- (i.e. APSOFP is phase-synchronous with REFCLK+/-).

Please refer to the Operation section for a discussion of PECL interfacing issues.

The receive differential data PECL inputs (RXD+/-) contain the NRZ bit serial receive stream. The receive clock is recovered from the RXD+/- bit stream.

Please refer to the Operation section for a discussion of PECL interfacing issues.

The receive signal detect TTL input (SD) indicates the presence of valid receive signal power from the Optical Physical Medium Dependent Device. A logic high indicates the presence of valid data. A logic low indicates a loss of signal.

Please refer to the Operation section for a discussion of interfacing issues

TXD+ TXD-

Differential

PECL Output

AK13 AK12

The transmit differential data PECL outputs (TXD+/-) contain the 2488.32 Mbit/s transmit stream. The TXD+/- outputs are driven using the synthesized clock from the CSU.

Please refer to the Operation section for a discussion of PECL interfacing issues.

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9.2 Clocks and Alarms (7) Pin Name Type Pin

No.

PGMRCLK Output AK25

RCLK Output AG23

PGMTCLK Output AH23

Function

The programmable receive clock (PGMRCLK) signal provides timing reference for the receive line interface.

PGMRCLK is a divided version of the recovered clock. When PGMRCLKSEL register bit is set low, PGMRCLK is a nominal

19.44 MHz, 50% duty cycle clock. When PGMRCLKSEL register bit is set to high, PGMRCLK is a nominal 8 KHz, 50% duty cycle clock.

The PGMRCLK output can be disabled and held low by programming the PGMRCLKEN bit in the SRLI PGM Clock Configuration register.

The receive clock (RCLK) signal provides timing reference for the receive interface.

RCLK is a nominal 77.76 MHz 50% duty cycle cloc k. The RCLK output can be disabled and held low b y programming the RCLKEN bit in the SRLI Clock Configurati on regis ter.

OOF and SALM are updated on the rising edge of RCLK. The programmable transmit clock (PGMTCLK) signal

provides timing reference for the transmit line interface.

PGMTCLK is a divided version of the recovered clock. When PGMTCLKSEL register bit is set low, PGMTCLK is a nominal

19.44 MHz, 50% duty cycle clock. When PGMTCLKSEL register bit is set to high, PGMTCLK is a nominal 8 KHz, 50% duty cycle clock.

The PGMTCLK output can be disabled and held low by programming the PGMTCLKEN bit in the STLI PGM Clock Configuration register.

TCLK Output AJ24

The transmit clock (TCLK) signal provides timing reference for the transmit interface.

TCLK is a nominal 77.76MHz 50% duty cycle clock. The TCLK output can be disabled and held low by programming the TCLKEN bit in the STLI PGM Clock Configuration register.

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PM5381 S/UNI-2488

Pin Name Type Pin

No.

OOF Output AH27

SALM Output AG26

RALM Output AK28

Function

The active high out of frame (OOF) signal indicates when an out of frame condition is declared by the framing block.

OOF is set high while the framing block is out of frame. An out of frame condition is declared when four consecutive errored framing patterns (A1 and A2 bytes) have been detected. OOF is set low while the framing block is in frame.

OOF is updated on the rising edge of RCLK. The section alarm (SALM) signal is set high when an out of

frame (OOF), loss of signal (LOS), loss of frame (LOF), line alarm indication signal (LAIS), line remote defect indication (LRDI), section trace identifier mismatch (TIM-S), section trace identifier unstable (TIU-S), signal fail (SF) or signal degrade (SD) alarm is detected. Each alarm indication can be independently enabled using bits in the S/UNI-2488 SARC Section SALM Enable regist ers . SALM is set low when non e of the enabled alarms are active.

SALM is updated on the rising edge of RCLK. The Receive Alarm (RALM) signal is a multiplexed output of

individual alarms of the receive path. Each alarm represents the logical OR of the SALM, LOP-P, AIS-P, RDI-P, ERDI-P, LOPC-P, PAISC-P, UNEQ-P, PSLU, PSLM, PDI-P, TIU-P, TIMP status of the path. The selection of alarms to be reported is controlled by the S/UNI-2488 SARC Path RALM Enable registers.

RALM is updated on the falling edge of ROHCLK.

Please refer to the individual alarm interrupt descriptions and Functional Description Section for more details on each alarm.

CSUCLKO Output AG22 This clock is used for PMC test purposes only. It must be left

as a no connect (NC) during the normal mode of operation.

CSUCLKI Input AK24

This clock is used for PMC test purposes only. It must be tied to VSS during the normal mode of operation.

CRUCLKO Output AJ23 This clock is used for PMC test purposes only. It must be left

as a no connect (NC) during the normal mode of operation.

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9.3 Receive Sect ion /Lin e/P ath Overh ead Ext r actio n Sig nals (6)

Pin Name Type Pin

No.

ROHCLK Output V30

ROHFP Output U27

RTOH Output V29

Function

The receive overhead clock (ROHCLK) signal provides timing for the receive section, line and path overhead extraction.

ROHCLK is a nominal 20.736 MHz clock generated by gapping a 25.92 MHz clock. ROHCLK has a 33% high duty cycle.

ROHFP, RTOH, RPOH, RPOHEN, B3E are updated on the falling edge of ROHCLK.

The receive overhead frame pulse (ROHFP) signal provides timing for the receive section, line and path overhead extraction.

ROHFP is used to indicate the most significant bit (MSB) on RTOH, RPOH and the first possible path BIP error on B3E.

ROHFP can be sample on the rising edge of ROHCLK.

ROHFP is updated on the falling edge of ROHCLK. The receive transport overhead (RTOH) signal contains the

received transport overhead bytes (A1, A2, J0, Z0, B1, E1, F1, D1-D3, H1-H3, B2, K1, K2, D4-D12, Z1/S1, Z2/M1, and E2) extracted from the incoming stream.

RTOH is updated on the falling edge of ROHCLK.

RPOH Output V27

The receive path overhead (RPOH) signal contains the received path overhead bytes (J1, B3, C2, G1, F2, H4, Z3, Z4, and Z5) extracted from the STS-48c/STM16c SONET/SDH path overhead

The RPOHEN signal is set high to indicate valid path overhead bytes on RPOH.

RPOH is updated on the falling edge of ROHCLK.

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Pin Name Type Pin

No.

RPOHEN Output V28

B3E Output W29

Function

The receive path overhead enable (RPOHEN) signal indicates valid path overhead bytes on RPOH

When RPOHEN signal is set high, the corresponding path overhead byte presented on RPOH is valid. When RPOHEN is set low, the corresponding path overhead byte presented on RPOH is invalid.

RPOHEN is updated on the falling edge of ROHCLK. The bit interleaved parity error (B3E) signal carries the path

BIP-8 errors detected for the STS-48c SONET payload.

B3E is set high for one ROHCLK clock cycle for each path BIP-8 error detected (up to eight errors per path per frame).

When BIP-8 errors are treated on a block basis, B3E is set high for one ROHCLK clock cycle for up to eight path BIP-8 errors detected (up to one error per path per frame).

Path BIP-8 errors are detected by comparing the extracted path BIP-8 byte (B3) with the computed path BIP-8 byte of the previous frame.

B3E is updated on the falling edge of ROHCLK.

9.4 Transmit Section/Line/Path Overhead Insertion Signals (7)

Pin Name Type Pin

Function

No.

TOHCLK Output AJ27

The transmit overhead clock (TOHCLK) signal provides timing for the transmit section, line and path overhead insertion.

TOHCLK is a nominal 20.736MHz clock generated by gapping a

25.92MHz clock. TOHCLK has a 33% high duty cycle.

TOHFP and TPOHRDY are updated on the falling edge of TOHCLK.

TTOH, TTOHEN, TPOH and TPOHEN are sampled on the rising edge of TOHCLK.

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Pin Name Type Pin

No.

TOHFP Output AG25

TTOH Input AK27

TTOHEN Input AJ26

Function

The transmit overhead frame pulse (TOHFP) signal provides timing for the transmit section, line and path overhead insertion.

TOHFP is used to indicate the most significant bit (MSB) on TTOH and TPOH.

TOHFP is set high when the MSB of the: First A1 byte should be present on TTOH. First J1 byte should be present on TPOH.

TOHFP can be sampled on the rising edge of TOHCLK.

TOHFP is updated on the falling edge of TOHCLK. The transmit transport overhead (TTOH) signal contains the

transport overhead bytes (A1, A2, J0, Z0, B1, E1, F1, D1-D3, H1-H3, B2, K1, K2, D4-D12, Z1/S1, Z2/M1, and E2) to be transmitted and the error masks to be applied on B1, B2, H1 and H2.

TTOH is sampled on the rising edge of TOHCLK. The transmit transport overhead insert enable (TTOHEN)

signal controls the insertion of the transmit transport overhead data which is inserted in the outgoing stream.

When TTOHEN is high during the most significant bit of a TOH byte on TTOH, the sampled TOH byte is inserted into the corresponding transport overhead byte positions (A1, A2, J0, Z0, E1, F1, D1-D3, H3, K1, K2, D4-D12, Z1/S1, Z2/M1, and E2 bytes). When TTOHEN is low during the most significant bit of a TOH byte on TTOH, that sampled byte is ignored and the default values are inserted into these transport overhead bytes.

When TTOHEN is high during the most significant bit of the H1, H2, B1 or B2 TOH byte positions on TTOH, the sampled TOH byte is logically XOR’ed with the associated incoming byte to force bit errors on the outgoing byte. A logic low bit in the TTOH byte allows the incoming bit to go through while a bit set to logic high will toggle the outgoing bit. A low level on TTOHEN during the MSB of the TOH byte disables the error forcing for the entire byte.

TTOHEN is sampled on the rising edge of TOHCLK.

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Pin Name Type Pin

No.

TPOH Input AH25

TPOHRDY Output AJ25

Function

The transmit path overhead (TPOH) signal contains the path overhead bytes (J1, C2, G1, F2, Z3, Z4, and Z5) to be transmitted in the STS-48c SONET path overhead and the error masks to be applied on B3 and H4.

A path overhead byte is accepted for transmission when the external source indicates a valid byte (TPOHEN set high) and the S/UNI-2488 indicates ready (TPOHRDY set high). The S/UNI-2488 will ignore the byte on TPOH when TPOHEN is set low. The TPOHRDY is set low to indicate the S/UNI-2488 is not ready, and the byte must be re-presented at the next opportunity.

TPOH is sampled on the rising edge of TOHCLK. The transmit path overhead insert ready (TPOHRDY) signal

indicates if the S/UNI-2488 is ready to accept the byte currently on TPOH.

TPOHRDY is set high during the most significant bit of a POH byte to indicate readiness to accept the byte on the TPOH input. This byte will be accepted if TPOHEN is also set high. If TPOHEN is set low, the byte is invalid and is ignored. TPOHRDY is set low to indicate that the S/UNI-2488 is unable to accept the byte on TPOH, and expects the byte to be represented at the next opportunit y.

TPOHRDY is updated on the falling edge of TOHCLK.

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Pin Name Type Pin

No.

TPOHEN Input AK26

Function

The transmit path overhead insert enable (TPOHEN) signal controls the insertion of the transmit path overhead data which is inserted in the outgoing stream.

TPOHEN shall be set high during the most significant bit of a POH byte to indicate valid data on the TPOH input. This byte will be accepted for transmission if TPOHRDY is also set high. If TPOHRDY is set low, the byte is rejected and must be represented at the next opportunit y.

Accepted bytes sampled on TPOH are inserted into the corresponding path overhead byte positions (for the J1, C2, G1, F2, Z3, Z4, and Z5 bytes). The byte on TPOH is ignored when TPOHEN is set low during the most significant bit position.

When the byte at the B3 or H4 byte position on TPOH is accepted, it is used as an error mask to modify the corresponding transmit B3 or H4 path overhead byte, respectively. The accepted error mask is XOR’ed with the corresponding B3 or H4 byte before it is transmitted.

TPOHEN is sampled on the rising edge of the TOHCLK.

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9.5 System Side Utopia and POS Signals (84)

Pin Name Type Pin

No.

POSL3_

Input B19

UL3B

RFCLK Input

RPRTY Output

E28

P29

Function

The Utopia/POS interface select (POSL3/UL3B) selects between Utopia Level 3 and POS-PHY Level 3 mode for the system side interface. When POSL3/UL3B is low, the Utopia Level 3 interface is selected. When high, the POS-PHY Level 3 interface is selected.

The UTOPIA receive FIFO read clock (RFCLK) signal is used to read ATM cells from the receive cell FIFO.

RFCLK is expected to cycle at 104 MHz. The POS-PHY receive FIFO read clock (RFCLK) signal is

used to read packet data from the 256 byte packet FIFO.

RFCLK is expected to cycle at 104 MHz. The UTOPIA receive parity (RPRTY) RPRTY signal indicates

the parity of the RDAT bus. The RPRTY signal indicates the parity on the RDAT[31:0] bus. Either odd or even parity selection can be selected.

RPRTY is updated on the rising edge of RFCLK. The POS-PHY receive parity (RPRTY) signal indicates the

parity of the RDAT bus. Either odd or even parity can be selected.

RPRTY is updated on the rising edge of RFCLK.

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Pin Name Type Pin

No.

RDAT[31] RDAT[30] RDAT[29] RDAT[28] RDAT[27] RDAT[26] RDAT[25] RDAT[24] RDAT[23] RDAT[22] RDAT[21] RDAT[20] RDAT[19] RDAT[18] RDAT[17] RDAT[16] RDAT[15] RDAT[14] RDAT[13] RDAT[12] RDAT[11] RDAT[10] RDAT[9] RDAT[8] RDAT[7] RDAT[6] RDAT[5] RDAT[4] RDAT[3] RDAT[2] RDAT[1] RDAT[0]

RENB

Output

Input U28

D30 E29 F28 G27 E30 F29 G28 H27 F30 H28 J27 G30 H29 J28 H30 J29 K28 L27 J30 L28 M27 K30 L29 M28 L30 N27 M29 N28 M30 P27 N30 P28

Function

The UTOPIA receive cell data (RDAT[31:0]) bus carries the ATM cell octets that are read from the receive FIFO.

RDAT[31:0] is updated on the rising edge of RFCLK. The POS-PHY receive packet data (RDAT[31:0]) bus carries

the POS packet octets that are read from the receive FIFO. The RDAT[31:0] signals are valid when RVAL and RENB are asserted.

RDAT[31:0] is updated on the rising edge of RFCLK.

The UTOPIA receive read enable (RENB) signal is used to initiate reads from the receive FIFO. The system may de-assert RENB at any time if it is unable to accept more data. A read is not performed and RDAT[31:0] does not change when RENB is sampled high. When RENB is sampled low, the word on the RDAT[31:0] bus is read from the receive FIFO and RDAT[31:0] changes to the next value on the next clock cycle.

RENB is sampled on the rising edge of RFCLK.

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Pin Name Type Pin

RENB

Input U28

(continued

RSOC

Output

R28

RSOP

Function

No.

The POS-PHY receive read enable (RENB) signal is used to initiate reads from the receive FIFO. During a data transfer, RVAL must be monitored since it will indicate if the data is valid. The system may deassert RENB at any time if it is unable to accept more data.

A read is not performed and RDAT[31:0] does not change when RENB is sampled high. When RENB is sampled low, the word on the RDAT[31:0] bus is read from the receive FIFO and RDAT[31:0] changes to the next value on the next clock cycle.

RENB is sampled on the rising edge of RFCLK. The UTOPIA receive start of cell (RSOC) signal marks the start

of a cell structure on the RDAT[31:0] bus. The first word of the cell structure is present on the RDAT[31:0] bus when RSOC is high.

RSOC is updated on the rising edge of RFCLK. The POS-PHY receive start of packet (RSOP) signal indicates

the start of a packet on the RDAT[31:0] bus. RSOP is set high for the first word of a packet on RDAT[31:0].

RCA Output

U30

RSOP is updated on the rising edge of RFCLK The UTOPIA receive cell available (RCA) signal provides direc t

status indication of when a cell is available in the receive FIFO. RCA can be configured to de-assert when either zero or four words remain in the FIFO. RCA will thus transition low on the rising edge of RFCLK after payload word 12 or 7 is output on the RDAT[31:0] bus depending on the configuration.

RCA is updated on the rising edge of RFCLK.

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Pin Name Type Pin

RVAL Output

U30

RERR

REOP Output

P30

Function

No.

The POS-PHY receive data valid (RVAL) signal indicates the validity of the receive data signals. When RVAL is high, the receive signals RDAT[31:0], RPRTY, RSOP, REOP, RMOD[1:0], and RERR are valid. When RVAL is low, all receive signals are invalid and must be disregarded.

RVAL will be high when valid data is on the RDAT[31:0] bus. RVAL will transition low when the FIFO is empty. RVAL will remain low until a programmable minimum number of bytes exist in the receive FIFO. The threshold is configurable.

RVAL is updated on the rising edge of RFCLK. The POS-PHY receive error (RERR) signal indicates that the

current packet is invalid due to an error such as invalid FCS, excessive length or received abort. RERR may only assert when REOP is asserted marking the last word of the packet.

RERR is only used in POS mode and is updated on the rising edge of RFCLK.

The POS-PHY receive end of packet (REOP) signal marks the end of packet on the RDAT[31:0] bus. It is legal for RSOP to be high at the same time REOP is high. REOP is set high to mark the last word of the packet presented on the RDAT[31:0] bus. When REOP is high, RMOD[1:0] specifies if the last word has 1, 2, 3, or 4 valid bytes of data.

REOP is only used for POS operation and is updated on the rising edge of RFCLK.

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Pin Name Type Pin

No.

RMOD[1]

Output

RMOD[0]

RSX Output

T28 T29

R29

Function

The POS-PHY transmit word modulo (RMOD[1:0]) bus indicates the size of the current word when configured for packet mode. During a packet transfer, every word on RDAT[31:0] must contain four valid bytes of packet data except at the end of the packet where the word is composed of 1, 2, 3, or 4 valid bytes. The number of valid bytes in this last word is specified by RMOD[1:0].

RMOD[1:0] = “00” RDAT[31:0] valid RMOD[1:0] = “01” RDAT[31:8] valid RMOD[1:0] = “10” RDAT[31:16] valid RMOD[1:0] = “11” RDAT[31:24] valid

RMOD[1:0] is considered valid only when RVAL is asserted. RMOD[1:0] is only used for POS operation and is updated on the rising edge of RFCLK.

The POS-PHY receive start of transfer (RSX) signal is used to indicate the start of a packet transfer. When RSX is high, the channel number being transferred is given on RDAT[31:0].

TFCLK

TFCLK (continued)

Input B18

RSX is only used for POS operation and is updated on the rising edge of RFCLK.

The UTOPIA transmit FIFO write clock (TFCLK) signal is used to write ATM cells to the transmit FIFO.

TFCLK is expected to cycle at a 104 MHz rate. The POS-PHY transmit FIFO write clock (TFCLK) signal is

used to write packet data into the 256 byte packet FIFO.

TFCLK is expected to cycle at a 104 MHz rate.

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Pin Name Type Pin

No.

TDA T[31] TDA T[30] TDA T[29] TDA T[28] TDA T[27] TDA T[26] TDA T[25] TDA T[24] TDA T[23] TDA T[22] TDA T[21] TDA T[20] TDA T[19] TDA T[18] TDA T[17] TDA T[16] TDA T[15] TDA T[14] TDA T[13] TDA T[12] TDAT[11] TDA T[10] TDAT[9] TDAT[8] TDAT[7] TDAT[6] TDAT[5] TDAT[4] TDAT[3] TDAT[2] TDAT[1] TDAT[0]

Input B5

D7 A5 B6 C7 D8 A6 B7 D9 A7 B8 C9 A8 B9 C10 D11 B10 C11 D12 A10 C12 A1 1 D13 B12 C13 A12 B13 D14 C14 B14 A14 C15

Function

The UTOPIA transmit cell data (TDAT[31:0]) bus carries the ATM cell octets that are written to the transmit FIFO. TDAT[31:0] is considered valid only when TENB is simultaneously asserted.

TDAT[31:0] is sampled on the rising edge of TFCLK.

The POS-PHY transmit packet data (TDAT[31:0]) bus carries the POS packet octets that are written to the transmit FIFO.

TDAT[31:0] bus is considered valid only when TENB is simultaneously asserted.

TDAT[31:0] is sampled on the rising edge of TFCLK.

TPRTY

Input B15

The UTOPIA transmit bus parity (TPRTY) signal indicates the parity on the TDAT[31:0] bus. A parity error is indicated by a status bit and a maskable interrupt. Cells with parity errors are still inserted in the transmit stream, so the TPRTY input may be unused. Odd or even parity may be selected. TPRTY is considered valid only when TENB is sim ultaneous ly asserted.

TPRTY is sampled on the rising edge of TFCLK.

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Pin Name Type Pin

TPRTY

Input B15

(continued)

TSOC

Input

D16

TSOP

Function

No.

The POS-PHY transmit bus parity (TPRTY) signal indicates the parity on the TDAT[31:0] bus. A parity error is indicated by a status bit and a maskable interrupt. Packets with parity errors are still inserted in the transmit stream, so the TPRTY input may be unused. Odd or even parity may be selected.

TPRTY is considered valid only when TENB is simultaneously asserted.

TPRTY is sampled on the rising edge of TFCLK. The UTOPIA transmit start of cell (TSOC) signal marks the

start of a cell structure on the TDAT[31:0] bus. The first word of the cell structure is present on the TDAT[31:0] bus when TSOC is high. TSOC must be present for each cell. TSOC is considered valid only when TENB is sim ultaneous ly asserted.

TSOC is sampled on the rising edge of TFCLK. The POS-PHY transmit start of packet (TSOP) signal indicates

the start of a packet on the TDAT[31:0] bus. TSOP is required to be present at all instances for proper operation.

TSOP must be set high for the first word of a packet on TDAT[31:0]. TSOP is considered valid only when TENB is simultaneously asserted.

TSOP is sampled on the rising edge of TFCLK.

TENB Input

A19

The UTOPIA transmit write enable (TENB) signal is an active low input which is used to initiate writes to the transmit FIFO. When TENB is sampled high, the information sampled on the TDAT[31:0], TPRTY and TSOC signals are invalid. When TENB is sampled low, the information sampled on the TDAT[31:0], TPRTY and TSOC signals are valid and are written into the transmit FIFO.

TENB is sampled on the rising edge of TFCLK.

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Pin Name Type Pin

TENB

TCA Output

D17

Function

No.

The POS-PHY transmit write enable (TENB) signal is an active low input which is used to initiate writes to the transmit FIFO’s. When TENB is sampled high, the information sampled on the TDA T[31:0], TPRTY, TSOP, TEOP, TMOD[1:0], and TERR signals are invalid. When TENB is sampled low, the information sampled on the TDAT[31:0], TPRTY, TSOP, TEOP, TMOD[1:0], and TERR signals are valid and are written into the transmit FIFO.

TENB is sampled on the rising edge of TFCLK.

The UTOPIA transmit cell available (TCA) signal provides direct status indication of when cell space is available in the transmit FIFO. When set high, TCA indicates that the corresponding transmit FIFO is not full and a complete cell may be written. TCA is set low to either indicate that the transmit FIFO is near full or that the transmit FIFO is full. To reduce FIFO latency, the FIFO depth at which TCA indicates "full" can be configured. Note that regardless of what fill level TCA is set to indicate "full" at, the transmit cell processors still have the full capacity of its FIFO to store cells.

TCA will transition low one TFCLK cycle after the payload word 7 or 11 (depending of the configuration) is sampled on the TDAT[31:0] bus.

TCA is updated on the rising edge of TFCLK.

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Pin Name Type Pin

No.

DTPA Output

TEOP Input

D17

B16

Function

The POS-PHY direct transmit packet available (DTPA) signal provides status indication on the fill status of the transmit FIFO. Note that regardless of what fill level DTPA is set to indicate "full" at, the transmit packet processors still have the full capacity of its FIFO to store cells. When DTPA transitions high, it indicates that the transmit FIFO has enough room to store a configurable number of data bytes.

When DTPA transitions low, it indicates that the transmit FIFO is either full or near full as configured.

DTPA is updated on the rising edge of TFCLK. The POS-PHY transmit end of packet (TEOP) signal marks

the end of packet on the TDAT[31:0] bus when configured for packet data. The TEOP signal marks the last word of a packet on the TDA T[31:0] bus. The TMOD[1:0] signal indicates how many bytes are in the last word. It is legal to set TSOP high at the same time as TEOP high in order to support one, two, three, or four byte packets. TEOP is only valid when TENB is simultaneously asserted.

TERR Input A17

TEOP is only used for POS operation and is sampled on the rising edge of TFCLK.

The POS-PHY transmit error (TERR) signal is used to indicate that the current packet must be aborted. Packets marked with TERR will have the abort sequence appended when transmitted. TERR should only be asserted during the last word of the packet being transferred on TDAT[31:0].

TERR is only considered valid when TENB and TEOP are simultaneously asserted.

TERR is ignored for the UTOPIA mode of operation and is sampled on the rising edge of TFCLK.

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Pin Name Type Pin

TMOD[1:0] Input B17

9.6 APS Serial Data Interface (20) Pin Name Type Pin

No.

A18

Function

The POS-PHY transmit word modulo (TMOD[1:0]) bus indicates the size of the current word when configured for packet mode. During a packet transfer, every word on TDAT[31:0] must contain four valid bytes of packet data except at the end of the packet where the word is composed of 1, 2, 3, or 4 valid bytes. The number of valid bytes in this last word is specified by TMOD[1:0]

TMOD[1:0] = “00” TDAT[31:0] valid TMOD[1:0] = “01” TDAT[31:8] valid TMOD[1:0] = “10” TDAT[31:16] valid TMOD[1:0] = “11” TDAT[31:24] valid

TMOD[1:0] is considered val id on ly when TENB is simultaneously asserted. TMOD[1:0] is only used for POS operation and is sampled on the rising edge of TFCLK.

Function

APSI+[4] APSI-[4]

APSI+[3] APSI-[3]

APSI+[2] APSI-[2]

APSI+[1] APSI-[1]

Analog LVDS Input

Y4 Y3

Y2 Y2

AA3 AA2

AB4 AB3

The differential APSI input (APSI+/-[4:1]) serial data links carries SONET/SDH OC-48 frame data from a mate in bit serial format. Each differential pair carries a constituent OC-12 of the data stream. Data on APSI+/-[4:1] is encoded in an 8B/10B format extended from IEEE Std. 802.3. The 8B/10B character bit ‘a’ is transmitted first and the bit ‘j’ is transmitted last.

When in working mode as set using the APSMODE input and the MODE[1:0] register bits in the S/UNI-2488 Master Reset, Configuration and Loopback register, the APSI+/-[4:1] signals carry the receive data from the protect mate. When in protect mode, the APSI+/-[4:1] signals carry the transmit data from the working mate.

The four differential pairs in APSI+/-[4:1] are frequency locked but not phase locked. APSI+/-[4:1] are nominally 777.6 Mbps data streams.

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Pin Name Type Pin

APSIFP Input P2

APSO+[4] APSO-[4]

Analog LVDS

U1 U2

Output APSO+[3] APSO-[3]

APSO+[2] APSO-[2]

APSO+[1] APSO-[1]

V3 V4

V1 V2

W2 W3

APSOFP Output P1

Function

No.

The APS input frame pulse signal (APSIFP) provides system timing of the APS input serial interface. APSIFP is set high once every 9720 APSIFPCLK cycles, or multiple thereof, to indicate that the J0 frame boundary 8B/10B character has been delivered on the differential LVDS bus (APSI+/-[4:1]).

APSIFP is sampled on the rising edge of APSIFPCLK+/-. The differential APS output (APSO+/-[4:1]) seri al data links

carries SONET/SDH OC-48 frame data to a mate in bit serial format. Each differential pair carries a constituent OC-12 of the data stream. Data on APSO+/-[4:1] is encoded in an 8B/10B format extended from IEEE Std. 802.3. The 8B/10B character bit ‘a’ is received first and the bit ‘j’ is received last.

When in working mode as set using the APSMODE input, the APSO+/-[4:1] signals carry the transmit data to the protect mate. When in protect mode, the APSO+/-[4:1] signals carry the receive data to the working mate.

The four differential pairs in APSO+/-[4:1] are frequency locked but not phase locked. APSO+/-[4:1] are nominally

777.6 Mbps data streams. The APS output frame pulse signal (APSOFP) provides

system timing of the APS output serial interface. APSOFP is set high once every 9720 APSIFPCLK cycles, or multiple thereof, to indicate that the J0 frame boundary 8B/10B character has been delivered on the differential LVDS bus (APSO+/-[4:1]).

APSOFP is updated on the rising edge of APSIFPCLK +/-.

APSIFPCLK Input P3

The APS input frame pulse clock (APSIFPCLK) provides a jitter-free reference clock with which the APS input frame pulse (APSIFP) is sampled. Also, the 777.76 MHz Clock Synthesis Unit of the APS Port uses this clock as its reference.

APSIFPCLK is expected to cycle at a 77.76 MHz rate, and must be a derivative of REFCLK+/- to ensure that APSIFPCLK is an exact divide-by-two in frequency compared to REFCLK+/-.

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9.7 Microprocessor Interface Signals (37) Pin Name Type Pin

No.

CSB Input F4

RDB Input D2

WRB Input C1

D[15] D[14] D[13] D[12] D[11] D[10] D[9] D[8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]

I/O

N1 P4 N2 M1 M2 N4 L1 M3 L2 K1 M4 K2 J1 K3 J2 H1

A[13]/TRS Input D28

Function

The active low chip sel ect (CSB) signal is low during S/UNI2488 register accesses.

Note that when not being used, CSB must be tied low. If CSB is not required (i.e. register accesses controlled using the RDB and WRB signals only), CSB must be connected to an inverted version of the RSTB input.

The active low read enable (RDB) signal is low during a S/UNI-2488 read access. The S/UNI-2488 drives the D[15:0] bus with the contents of the addressed register while RDB and CSB are low.

The active low write strobe (WRB) signal is low during a S/UNI-2488 register write access. The D[15:0] bus contents are clocked into the addressed register on the rising WRB edge while CSB is low.

The bi-directional data bus, D[15:0], is used during S/UNI-2488 read and write accesses.

The test register select signal (TRS) selects between normal and test mode register accesses. TRS is high during test mode register accesses, and is low during normal mode register accesses. TRS may be tied low.

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Pin Name Type Pin

A[12] A[11] A[10] A[9] A[8] A[7] A[6] A[5] A[4] A[3] A[2] A[1] A[0]

RSTB Schmidt

Input J3

H2 J4 H3 G2 F1 H4 G3 F2 E1 G4 E2 D1

E4

TTL Input

ALE Input E3

INTB OD Output D3

Function

No.

The address bus (A[12:0]) selects specific registers during S/UNI-2488 register accesses.

The active low reset (RSTB) signal provides an asynchronous S/UNI-2488 reset. RSTB is a Schmidt triggered input with an integral pull-up resistor.

The address latch enable (ALE) is an active-high signal and latches the address bus A[13:0] when low. W hen ALE is high, the internal address latches are transparent. It allows the S/UNI-2488 to interface to a multiplexed address/data bus. The ALE input has an integral pull up resistor.

The active low interrupt (INTB) is set low when a S/UNI-2488 enabled interrupt source is active. The S/UNI-2488 may be enabled to report many alarms or events via interrupts.

INTB is tri-stated when the interrupt is acknowledged via the appropriate register access. INTB is an open drain output.

9.8 JTAG Test Access Port (TAP) Signals (5) Pin Name Type Pin

Function

No.

TCK Input C30

The test clock (TCK) signal provides timing for test operations that can be carried out using the IEEE P1149.1 test access port.

TMS Input E27

The test mode select (TMS) signal controls the test operations that can be carried out using the IEEE P1149.1 test access port. TMS is sampled on the rising edge of TCK. TMS has an integral pull up resistor.

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Pin Name Type Pin

Function

No.

TDI Input F27 When the S/UNI-2488 is configured for JTAG operation, the

test data input (TDI) signal carries test data into the S/UNI-2488 via the IEEE P1149.1 test access port. TDI is sampled on the rising edge of TCK. TDI has an integral pull up resistor.

TDO Tristate

Output

D18

The test data output (TDO) signal carries test data out of the S/UNI-2488 via the IEEE P1149.1 test access port. TDO is updated on the falling edge of TCK. TDO is a tri-state output which is inactive except when scanning of data is in progress.

TRSTB

Schmidt

TTL Input

D28

The active low test res et (TRSTB) signal provides an asynchronous S/UNI-2488 test access port reset via the IEEE P1149.1 test access port. TRSTB is a Schmidt triggered input with an integral pull up resistor. In the event that TRSTB is not used, it must be connected to RSTB.

9.9 Analog Miscellaneous Signals (10)

Pin Name Type Pin

Function

No.

ATP[3] ATP[2] ATP[1] ATP[0]

Analog AJ18

AK18 AG2 AF3

Four analog test ports (ATP[0], ATP[1], ATP[2], ATP[3]) are provided for production testing only. These pins must be tied to analog ground (AVS) during normal operation. ATP[1] and ATP[0] are the test ports for the 2488 Mbps analog circuitry, while ATP[3] and ATP[2] are the test ports for the 777.76 MHz LVDS analog circuitry.

C0 C1

Analog

AH18 AG18

The analog C0 and C1 pins are provided for applications that must meet SONET/SDH jitter tolerance specifications. A 47nF non-polarized capacitor is attached across C0 and C1 for these applications.

When the capacitor is used, the RTYPE bit in the CRSI must be set to logic one for proper operation. When the capacitance is not used, these pins are left floating and the

RYPE register must be set to logic zero for proper operation. C2 C3

Analog

AJ20 AK20

The analog C2 and C3 pins are provided for applications that

must meet SONET/SDH jitter transfer specifications. A 4.7nF

non-polarized capacitor is attached across C2 and C3 for

these applications.

When the capacitance is not used, these pins are left floating.

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Pin Name Type Pin

No.

RES RESK

Analog

AE4 AG1

9.10 Analog Power and Ground (107) Pin Name Pin Type PIN

No.

AVDH (24) Analog

Power

AH20 AH17 AH14 AH10 AH9 AG9 AJ9 AJ10 AJ14 AJ17 AJ19 AK19 AG20 AG8

Function

Reference Resistor Connection. An off-chip 4.75kΩ ±1%

resistor is connected between the positive resistor reference pin RES and a Kelvin ground contact RESK for the APS port LVDS reference. An on-chip negative feedback path will force the 1.20V VREF voltage onto RES, therefore forcing 252µA of current to flow through the resistor.

RESK is electrically connected to AVSS within the block, but should not be connected to AVSS, either on-chip or off-chip.

Function

The analog power (AVDH) pins for the analog core. The AVDH pins should be connected through passive filtering networks to a well-decoupled +3.3V analog power supply.

Please see the Operation section for detailed information.

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Pin Name Pin Type PIN

No.

AVDL(17) Analog

Power

AG5 AG6 AG7 AH5 AH6 AH7 AJ5 AJ6 AJ7 AK5 AK6 AK7 AG21 AH21 AJ21 AK21

Function

The analog power (AVDL) pins for the analog core. The AVDL pins should be connected through passive filtering networks to a well-decoupled +1.8V analog power supply. Please see the Operation section for detailed information.

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9.11 Digital Power and Ground

Pin Name Pin Type PIN

No.

VDDDC Digital Core

Power

D29 G29 K29 N29 U29 W30 AA28 AH26 AG24 T2 R4 N3 L3 G1 F3 C6 C8 A9 B1 1 A13 C16 C17 C18 A21 D21 B29 C28 D27 D10 D15 D20

Function

The digital core power (VDDDC) pins should be connected to a well-decoupled +1.8V digital power supply.

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Pin Name Pin Type PIN

No.

VDDDC (Cont.)

Digital Core

Power

B2 C3

D4 AG27 AH28

AJ29

K27 R27 Y27

L4 T4

Function

The digital core power (VDDDC) pins should be connected to a well-decoupled +1.8V digital power supply.

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Pin Name Pin Type PIN

No.

VSS (52) Digital

Ground

A1 B1 C2 R1

W1 AA1 AC1 AC2 AC3 AD1 AD2 AE1 AH1 AK1 AJ2 AK2

AK14 AG15 AH15

AJ15 AG16 AH16

AJ16 AK17 AK22 AK23

AJ28 AK29

B28 A16 A15

B3 A2

Function

The digital ground (VSS) pins should be connected to the digital ground of the digital power supply.

T1

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Pin Name Pin Type PIN

No.

VSS (52) (Continued)

Digital

Ground

AH3 AJ3 AK3

AG4

AH4 AJ4 AK4 AJ8

AK8 AG11 AH11

AJ11 AK11 AG12 AH12

AJ12 AG13 AH13

AJ13 AK30

AJ30 AH29

T30 R30 C29 B30 A30 A29

Function

The digital ground (VSS) pins should be connected to the digital ground of the digital power supply.

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Notes on Pin Description:

1. All S/UNI-2488 inputs and bidirectionals present minimum capacitive loading and operate at CMOS/TTL logic levels except: the REFCLK+/-, RXD+/-, TXD+/-, APSI+/-[4:1], APSO+/-[4:1] pins which operate at pseudo-ECL (PECL) logic levels.

2. The S/UNI-2488 digital outputs and bidirectionals which have 2 mA drive capability are: TBD

The S/UNI-2488 digital outputs and bidirectionals which have 4 mA drive capability are: TBD

The S/UNI-2488 digital outputs and bidirectionals which have 6 mA drive capability are: TBD

3. The S/UNI-2488 digital outputs are 3.3V tolerant.

4. Inputs ALE, RSTB, TMS, TDI and TRSTB have internal pull-up resistors.

5. The single ended pseudo-ECL inputs and outputs should be terminated in a passive network and interface at PECL levels as described in the Operations section.

6. It is mandatory that every digital ground pin (VSS) be connected to the printed circuit board ground plane to ensure reliable device operation.

7. It is mandatory that every digital power pin (VDD) be connected to the printed circuit board power plane to ensure reliable device operation.

8. All analog power and ground pins can be sensitive to noise. They must be isolated from the digital power and ground. Care must be taken to correctly decouple these pins. Please refer to the Operations sections.

9. Due to ESD protection structures in the pads it is necessary to exercise caution when powering a device up or down. ESD protection devices behave as diodes between power supply pins and from I/O pins to power supply pins. Under extreme conditions it is possible to damage these ESD protection devices or trigger latch up. Please adhere to the recommended power supply sequencing as described in the Operation section of this document.

10. Do not exceed 100 mA of current on any pin during the power-up or power-down sequence. Refer to the Power Sequencing description in the Operations section.

11. Before any input activity occurs, ensure that the device power supplies are within their nominal voltage range.

12. Hold the device in the reset condition until the device power supplies are within their nominal voltage range.

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13. Ensure that all digital power is applied simultaneously, and applied before or simultaneously with the analog power. Refer to the Power Sequencing description in the Operations section.

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10 FUNCTIONAL DESCRIPTION

10.1 Receive Line Interface

The Receive Line Interface allows direct interface of the S/UNI-2488 to optical modules (ODLs) or other medium interfaces. This block performs clock and data recovery on the incoming 2488.32 Mbit/s data stream and SONET A1/A2 pattern framing.

The clock recovery unit recovers the clock from the incoming bit serial data stream and is compliant with SONET and SDH jitter tolerance requirements. The clock recovery unit utilizes a low frequency reference clock to train and monitor its clock recovery PLL. Under loss of signal conditions, the clock recovery unit continues to output a line rate clock that is locked to this reference for keep alive purposes. The clock recovery unit utilizes a 155.52 MHz reference clock. The clock recovery unit provides status bits that indicate whether it is locked to data or the reference and also supports diagnostic loopback and a loss of signal input that squelches normal input data.

Initially upon start-up, the PLL locks to the reference clock, REFCLK. When the frequency of the recovered clock is within TBD ppm of the reference clock, the PLL attempts to lock to the data. Once in data lock, the PLL reverts to the reference clock if no data transitions occur in TBD bit periods or if the recovered clock drifts beyond TBD ppm of the reference clock.

When the transmit clock is derived from the recovered clock (loop timing), the accuracy of the transmit clock is directly related to the REFCLK reference accuracy in the case of a loss of signal condition. To meet the Bellcore GR-253-CORE SONET Network Element free-run accuracy specification, the reference must be within +/- TBD ppm. When not loop timed, the REFCLK accuracy may be relaxed to +/- TBD ppm.

The loop filter transfer function is optimized to enable the PLL to track the jitter, yet tolerate the minimum transition density expected in a received SONET data signal. The total loop dynamics of the clock recovery PLL yield a jitter tolerance that exceeds the minimum tolerance specified for SONET equipment by GR-253-CORE. Please refer to the figure below.

Figure 7: Typical STS-48c (STM-16c) Jitter Tolerance

TBD

The Serial to Parallel Converter converts the received bit serial stream to a 16 bit word serial stream.

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10.2 SONET/SDH Receive Line Interface (SRLI)

The SONET/SDH receive line interface block performs byte and frame alignment on the incoming 2488 Mbit/s data stream based on the SONET/SDH A1/A2 framing pattern.

While out of frame, the SRLI monitors the receive data stream for an occurrence of the A1/A2 framing pattern. The SRLI adjusts its byte and frame alignment when three consecutive A1 bytes followed by three consecutive A2 bytes occur in the data stream. The SRLI informs the RRMP framer block when the framing pattern has been detected to reinitialize to the new transport frame alignment. While in frame, the SRLI maintains the same byte and frame alignment until the RRMP declares out of frame.

10.3 Receive Regenerator and Multiplexor Processor (RRMP)

The Receive Regenerator and Multiplexor Processor (RRMP) block extracts and process the transport overhead of the received data stream.

The RRMP frames to the data stream by operating with an upstream pattern detector (SRLI) that searches for occurrences of the A1/A2 framing pattern. Once the SRLI has found an A1/A2 framing pattern, the RRMP monitors for the next occurrence of the framing pattern 125µs later. Two framing pattern algorithms are provided to improve performance in the presence of bit errors. In algorithm 1, the RRMP declares frame alignment (removes OOF defect) when the 12 A1 and the 12 A2 bytes are seen error-free in the first STS-12 (STM-4) of the STS-48c (STM-16-16c) stream. In algorithm 2, the RRMP declares frame alignment (removes OOF defect) when only the last A1 byte and the first four bits of the first A2 byte are seen error-free in the first STS-12 (STM-4) of the STS-48c (STM-16c) . Once in frame, the RRMP monitors the framing pattern and declares OOF when one or more bit errors in the framing pattern are detected for four consecutive frames. Again, depending upon the algorithm either 24 framing bytes or 12 framing bits are examined for bit errors in the framing pattern.

The performance of these framing algorithms in the presence of bit errors and random data is robust. When looking for frame alignment the performance of each algorithm is dominated by the alignment algorithm used in the SRLI which always examines 3 A1 and 3 A2 framing bytes. The probability of falsely framing to random data is less than 0.00001% for either algorithm. Once in frame alignment, the RRMP continuously monitors the framing pattern. When the incoming

-3

stream contains a 10

BER, the first algorithm provides a 99.75% probability that the mean time between OOF occurrences is 1.3 seconds and the second algorithm provides a 99.75% probability that the mean time between OOF occurrences is 7 minutes.

The RRMP also detects loss of frame (LOF) defect and loss of signal (LOS) defect. LOF is declared when an out of frame (OOF) condition exists for a total period of 3ms during which there is no continuous in frame period of 3 ms. LOF output is removed when an in frame condition exists for a continuous period of 3 ms. LOS is declared when a continuous period of 20 µs without transitions on the received data stream is detected. LOS is removed when two consecutive framing patterns are found (based on algorithm 1 or algorithm 2) and during the

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intervening time (one frame) there are no continuous periods of 20 µs without transitions on the received data stream.

The RRMP calculates the section BIP-8 error detection code on the scrambled data of the complete frame. The section BIP-8 code is based on a bit interleaved parity calculation using even parity. The calculated BIP-8 code is compared with the BIP-8 code extracted from the B1 byte of STS-1 (STM-0) #1 of the following frame after de-scrambling. Any difference indicates a section BIP-8 error. The RRMP accumulates section BIP-8 errors in a microprocessor readable 16-bit saturating counter (up to 1 second accumulation time). Optionally, block section BIP-8 errors can be accumulated.

The RRMP optionally de-scrambles the received data stream.

The RRMP calculates the line BIP-8 error detection codes on the de-scrambled line overhead and synchronous payload envelope bytes of the constituent STS-1 (STM-0). The line BIP-8 code is based on a bit interleaved parity calculation using even parity. The calculated BIP-8 codes are compared with the BIP-8 codes extracted from the B2 byte of the constituent STS-1 (STM-0) of the following frame after de-scrambling. Any difference indicates a line BIP-8 error. The RRMP accumulates line BIP-8 errors in a microprocessor readable 24 bits saturating counter (up to 1 second accumulation time). Optionally, block BIP errors can be accumulated.

The RRMP extracts the line remote error indication (REI-L) errors from the M1 byte of STS-1 (STM-0) #3 and accumulates them in a microprocessor readable 24 bits saturating counter (up to 1 second accumulation time). Optionally, block line REI errors can be accumulated.

The RRMP extracts and filters the K1/K2 APS bytes for three frames. The filtered K1/K2 APS bytes are accessible through microprocessor readable registers. The RRMP also monitors the unfiltered K1/K2 APS bytes to detect APS byte failure (APSBF-L) defect, line alarm indication signal (AIS-L) defect and line remote defect indication (RDI-L) defect. APS byte failure is declared when twelve consecutive frames have been received where no three consecutive frames contain identical K1 bytes. The APS byte failure is removed upon detection of three consecutive frames containing identical K1 bytes. The detection of invalid APS codes must be done in software by polling the K1/K2 APS register. Line AIS is declared when the bit pattern 111 is observed in bits 6, 7, and 8 of the K2 byte for three or five consecutive frames. Line AIS is removed when any pattern other than 111 is observed for three or five consecutive frames. Line RDI is declared when the bit pattern 110 is observed in bits 6, 7, and 8 of the K2 byte for three or five consecutive frames. Line RDI is removed when any pattern other than 110 is observed for three or five consecutive frames.

The RRMP extracts and filters the synchronization status message (SSM) for eight frames. The filtered SSM is accessible through microprocessor readable registers.

RRMP optionally inserts line alarm indication signal (AIS-L).

The RRMP extracts and serially outputs all the transport overhead (TOH) bytes on the RTOH output. The TOH bytes are output in the same order that they are received (A1, A2, J0/Z0, B1,

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A

A2A2A

A

A1A1A

A

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E1, F1, D1-D3, H1-H3, B2, K1, K2, D4-D12, S1/Z1, Z2/M1/Z2 and E2). RTOHCLK is the generated output clock used to provide timing for the RTOH output. RTOHCLK is a nominal

20.736 MHz clock generated by gapping a 25.92 MHz clock. Sampling RTOHFP high with the rising edge of RTOHCLK identifies the MSB of the first A1 byte.

Figure 8: STS-48c (STM-16-16c) on RTOH

ST S1/ ST M0 #1

First order of transmission

1

Se co

B1

nd or

D1

de r

H1

of tra

B2

ns mi

D4

ssi

S-

1/

ST

M-

0

#3

#2

1

H1B2H1B2H1

ST

D7

D10

S1

Unused bytes National bytes

ST S1/ ST M0 #4

B2

Z1Z1Z1

ST S1/ ST M0 #5

H1

B2

Z1

...

1

... ... ... ... ... ... ... ...

Z0 Z0 or National bytes

ST S1/ ST M0 #1

ST

S-

1/

ST

M-

0

#2

#1

1

ST

S-

1/

ST

M-

0

#4

#3

2

2 E1 D2

H1 B2

H2 K1

H2

D5 D8

D11

Z2 Z2 Z2

Z1

M1

Z2

ST S1/ ST M0 #5

2

ST S1/ ST M0 #1

2

... ... ... ... ... ... ... ... ...

ST S1/ ST M0 #1

J0

F1 D3 H3 H3H2 H2

K2 D6 D9

D12

E2

ST S1/ ST M0 #2

Z0

H3

ST S1/ ST M0 #3

Z0

H3

ST S1/ ST M0 #4

Z0

H3

ST S1/ ST M0 #5

H3

ST S1/ ST M0 #1

Z0...Z0 ... ... ... ... ... ... ... ...

A maskable interrupt is activated to indicate any change in the status of out of frame (OOF), loss of frame (LOF), loss of signal (LOS), line remote defect indication (RDI-L), line alarm indication signal (AIS-L), synchronization status message (COSSM), APS bytes (COAPS) and APS byte failure (APSBF) or any errors in section BIP-8, line BIP-8 and line remote error indication (REI-L).

The RRMP block provides de-scrambled data and frame alignment indication signals for use by the RHPP.

10.4 Receive Tail Trace Processor (RTTP)

The Receive Tail Trace Processor (RTTP) block monitors the tail trace messages of the receive data stream for trace identifier unstable (TIU) defect and trace identifier mismatch (TIM) defect. Three tail trace algorithms are defined.

The first algorithm is BELLCORE compliant. The algorithm detects trace identifier mismatch (TIM) defect on a 16 or 64 byte tail trace message. A TIM defect is declared when none of the last 20 messages matches the expected message. A TIM defect is removed when 16 of the last 20 messages match the expected message. The expected tail trace message is a static message written in the expected page of the RTTP by an external microprocessor. Optionally, the expected message is matched when the tail trace message is all zeros.

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The second algorithm is ITU compliant. The algorithm detects trace identifier unstable (TIU) defect and trace identifier mismatch (TIM) defect on a 16 or 64 byte tail trace message. The current tail trace message is stored in the captured page of the RTTP. If the length of the message is 16 bytes, the RTTP synchronizes on the MSB of the message. The byte with the MSB set high is placed in the first location of the captured page. If the length of the message is 64 bytes, the RTTP synchronizes on the CR/LF (CR = 0Dh, LF = 0Ah) characters of the message. The following byte is placed in the first location of the captured page.

A persistent tail trace message is declared when an identical message is receive for 3 or 5 consecutive multi-frames (16 or 64 frames). A persistent message becomes the accepted message. The accepted message is stored in the accepted page of the RTTP. A TIU defect is declared when one or more erroneous bytes are detected in a total of 8 messages without any persistent message in between. A TIU defect is removed when a persistent message is received.

A TIM defect is declared when the accepted message does not match the expected message. A TIM defect is removed when the accepted message matches the expected message. The expected message is a static message written in the expected page of the RTTP by an external microprocessor. Optionally, the algorithm declares a match tail trace message when the accepted message is all zeros.

The third algorithm is not BELLCORE/ITU compliant. The algorithm detects trace identifier unstable (TIU) on a single continuous tail trace byte. A TIU defect is declared when one or more erroneous bytes are detected in three consecutive 16 byte windows. The first window starts on the first erroneous byte. A TIU defect is removed when an identical byte is received for 48 consecutive frames. A maskable interrupt is activated to indicate any change in the status of trace identifier unstable (TIU) and trace identifier mismatch (TIM).

10.5 Receive High Order Path Processor (RHPP)

The Receive High Order Path Processor (RHPP) provides pointer interpretation, extraction of path overhead, extraction of the synchronous payload envelope (virtual container), and path level alarm and performance monitoring.

10.5.1 Pointer Interpreter

The pointer interpreter extracts and validates the H1 and H2 bytes in order to identify the location of the path overhead byte (J1) and the synchronous payload envelop bytes (SPE) of the constituent STS-48c (VC-16-16c) payloads. The pointer interpreter is a time multiplexed finite state machine that can process the STS-48c (AU-16-16c) pointer. Within the pointer interpretation algorithm three states are defined as shown below:

NORM_state (NORM)

AIS_state (AIS)

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LOP_state (LOP)

The transition between states will be consecutive events (indications), e.g., three consecutive AIS indications to go from the NORM_state to the AIS_state. The kind and number of consecutive indications activating a transition is chosen such that the behavior is stable and insensitive to low BER. The only transition on a single event is the one from the AIS_state to the NORM_state after receiving a NDF enabled with a valid pointer value. It should be noted that, since the algorithm only contains transitions based on consecutive indications, this implies that, for example, nonconsecutively received invalid indications do not activate the transitions to the LOP_state.

Figure 9: Pointer interpretation state diagram

NDF_ENABLE

INC_IND/DEC_IND

NORM

8 x INV_POINT

3 x AIS_IND

8 x NDF_ENABLE

3 x EQ_NEW_POINT

3 x AIS_IND

LOP AIS

8 x INV_POINT

The following events (indications) are defined:

3 x EQ_NEW_POINT

NDF_ENABLE

3 x EQ_NEW_POINT

NORM_POINT: disabled NDF + ss + offset value equal to active offset.

NDF_ENABLE: enabled NDF + ss + offset value in range of 0 to 782.

AIS_IND: H1 = FFh + H2 = FFh.

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INC_IND: disabled NDF + ss + majority of I bits inverted + no majority

of D bits inverted + previous NDF_ENABLE, INC_IND or DEC_IND more than 3 frames ago.

DEC_IND: disabled NDF + ss + majority of D bits inverted + no majority

of I bits inverted + previous NDF_ENABLE, INC_IND or DEC_IND more than 3 frames ago.

INV_POINT: not any of the above (i.e.: not NORM_POINT, not NDF_ENABLE,

not AIS_IND, not INC_IND and not DEC_IND).

NEW_POINT: disabled NDF + ss + offset value in range of 0 to 782 but not

equal to active offset.

Note 1: active offset is defined as the accepted current phase of the SPE (VC) in

the NORM_state and is undefined in the other states.

Note 2: enabled NDF is defined as the following bit patterns:

1001, 0001, 1101, 1011 and 1000.

Note 3: disabled NDF is defined as the following bit patterns:

0110, 1110, 0010, 0100 and 0111.

Note 4: the remaining six NDF bit patterns (0000, 0011, 0101, 1010, 1100, 1111)

result in an INV_POINT indication.

Note 5: ss bits are unspecified in SONET and have bit pattern 10 in SDH.

Note 6: the use of ss bits in definition of indications may be optionally disabled.

Note 7: the requirement for previous NDF_ENABLE, INC_IND or DEC_IND be

more than 3 frames ago may be optionally disabled.

Note 8: NEW_POINT is also an INV_POINT.

Note 9: the requirement for the pointer to be within the range of 0 to 782 in

8 X NDF_ENABLE may be optionally disabled.

Note 10: LOP is not declared if all the following conditions exist:

- the received pointer is out of range (>782),

- the received pointer is static,

- the received pointer can be interpreted, according to majority voting on the I and D bits, as a positive or negative justification indication, after making the requested justification, the received pointer continues to be interpretable as a pointer justification.

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- When the received pointer returns to an in-range value, the S/UNI-2488 will interpret it correctly.

Note 11: LOP will exit at the third frame of a three frame sequence consisting of

one frame with NDF enabled followed by two frames with NDF disabled, if all three pointers have the same legal value.

The transitions indicated in the state diagram are defined as follows:

INC_IND/DEC_IND: offset adjustment (increment or decrement indication)

3 x EQ_NEW_POINT: three consecutive equal NEW_POINT indications

NDF_ENABLE: single NDF_ENABLE indication

3 x AIS_IND: three consecutive AIS indications

8 x INV_POINT: eight consecutive INV_POINT indications

8 x NDF_ENABLE eight consecutive NDF_ENABLE indications

Note 1: the transitions from NORM_state to NORM_state do not represent state

changes but imply offset changes.

Note 2: 3 x EQ_NEW_POINT takes precedence over other events and may

optionally reset the INV_POINT count.

Note 3: all three offset values received in 3 x EQ_NEW_POINT must be

identical.

Note 4: "consecutive event counters" are reset to zero on a change of state

(except the INV_POINT counter).

Note 5 "consecutive event counters" are reset to zero on a change of state

except for consecutive NDF count.

LOP is declared on entry to the LOP_state after eight consecutive invalid pointers or eight consecutive NDF enabled indications

PAIS is declared on entry to the AIS_state after three consecutive AIS indications

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10.5.2 Concatenation pointer interpreter state machine

The concatenation pointer interpreter extracts and validates the H1 and H2 concatenation bytes. Within the pointer interpretation algorithm three states are defined as shown below.

CONC_state (CONC)

AISC_state (AISC)

LOPC_state (LOPC)

The transitions between the states will be consecutive events (indications), e.g. three consecutive AIS indications to go from the CONC_state to the AISC_state. The kind and number of consecutive indications activating a transition is chosen such that the behaviour is stable and insensitive to low BER.

Figure 10: Concatenation pointer interpretation state diagram

CONC

8 x INV_POINT

3 x AIS_IND

3 x CONC_IND

3 x AIS_IND

LOPC AISC

8 x INV_POINT

The following events (indications) are defined:

CONC_IND: enabled NDF + dd + “1111111111”

3 x CONC_IND

AIS_IND: H1 = FFh + H2 = FFh

INV_POINT: not any of the above (i.e.: not CONC_IND and not AIS_IND)

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Note 1: enabled NDF is defined as the following bit patterns:

1001, 0001, 1101, 1011 and 1000.

Note 2: the remaining eleven NDF bit patterns (0000, 0010, 0011, 0100,

0101, 0110, 0111, 1010, 1100, 1110, 1111) result in an INV_POINT indication.

Note 3: dd bits are unspecified in SONET/SDH.

The transitions indicated in the state diagram are defined as follows:

3 X CONC_IND: three consecutive CONC indications

3 x AIS_IND: three consecutive AIS indications

8 x INV_POINT: eight consecutive INV_POINT indications

Note 1: "consecutive event counters" are reset to zero on a change of state.

LOPC is declared on entry to the LOPC_state after eight consecutive pointers with values other than concatenation indications

PAISC is declared on entry to the AISC_state after three consecutive AIS indications

10.5.3 Error Monitoring

The RHPP calculates the path BIP-8 error detection codes on the SONET (SDH) payloads. The path BIP-8 code is based on a bit interleaved parity calculation using even parity. The calculated BIP-8 codes are compared with the BIP-8 codes extracted from the B3 byte of the STS (VC) payload of the following frame. Any differences indicate a path BIP-8 error. The RHPP accumulates path BIP-8 errors in a microprocessor readable 16 bits saturating counter (up to 1 second accumulation time). Optionally, block BIP-8 errors can be accumulated.

The RHPP extracts the path remote error indication (REI-P) errors from bits 1, 2, 3 and 4 of the path status byte (G1) and accumulates them in a microprocessor readable 16 bits saturating counter (up to 1 second accumulation time). Optionally, block block REI errors can be accumulated.

The RHPP monitors the path signal label byte (C2) payload to validate change in the accepted path signal label (APSL). The same PSL byte must be received for three or five consecutive

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frames (selectable by the PSL5 bit in the configuration register) before being considered accepted.

The RHPP also monitors the path signal label byte (C2) to detect path payload label unstable (PLU-P) defect. A PSL unstable counter is increment every time the received PSL differs from the previously received PSL (an erroneous PSL will cause the counter to be increment twice, once when the erroneous PSL is received and once when the error free PSL is received). The PSL unstable counter is reset when the same PSL value is received for three or five consecutive frames (selectable by the PSL5 bit in the configuration register). PLU-P is declared when the PSL unstable counter reaches five. PLU-P is removed when the PSL unstable counter is reset.

The RHPP also monitors the path signal label byte (C2) to detect path payload label mismatch (PLM-P) defect. PLM-P is declared when the accepted PSL does not match the expected PSL according to Table 1. PLM-P is removed when the accepted PSL match the expected PSL according to Table 1. The accepted PSL is the same PSL value received for three or five consecutive frames (selectable by the PSL5 bit in the configuration register). The expected PSL is a programmable PSL value.

The RHPP also monitors the path signal label byte (C2) to detect path unequipped (UNEQ-P) defect. UNEQ-P is declared when the accepted PSL is 00H and the expected PSL is not 00H. UNEQ-P is removed when the accepted PSL is not 00H or when the accepted PSL is 00H and the expected PSL is 00H. The accepted PSL is the same PSL value received for three or five consecutive frames (selectable by the PSL5 bit in the configuration register). The expected PSL is a register programmable PSL value.

The RHPP also monitors the path signal label byte (C2) to detect path payload defect indication (PDI-P) defect. PDI-P is declared when the accepted PSL is a PDI defect that matches the expected PDI defect. The PDI-P defect is removed when the accepted PSL is not a PDI defect or when the accepted PSL is a PDI defect that does not match the expected PDI defect. The accepted PSL is the same PSL value received for three or five consecutive frames (selectable by the PSL5 bit in the configuration register). T able 2 gives the expected PDI defect based on the programmable PDI and PDI range register values.

Table 1: PLM-P, UNEQ-P and PDI-P defects declaration

Expected PSL Accepted PSL PLM-P UNEQ-P PDI-P

00 Unequipped

01 Equipped non specific 00 Unequipped Mismatch Active Inactive

00 Unequipped Match Inactive Inactive 01 Equipped non specific Mismatch Inactive Inac tive

02-E0

FD-FF E1-FC PDI

Equipped specific Mismatch Inactive Inactive

=expPDI Match Inactive Active

expPDI Mismatch Inactive Inactive

!=

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01 Equipped non specific Match Inactive Inactive

02-E0

FD-FF

02-FF Equipped specific

PDI

00 Unequipped Mismatch Active Inactive 01 Equipped non specific Match Inactive Inactive

Equipped specific

FD-FF E1-FC PDI

PMC-Sierra, Inc.

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=expPDI Match Inactive ActiveE1-FC PDI

expPDI Mismatch Inactive Inactive

!=

= expPSL Match Inactive Inactive02-E0

expPSL Mismatch Inactive Inactive

!=

=expPDI Match Inactive Active

expPDI Mismatch Inactive Inactive

!=

PM5381 S/UNI-2488

Table 2: Expected PDI defect based on PDI and PDI range values

PDI

register value

01100 Disable EC 11011 Disable FB

PDI range

register value

Disable Disable EF00000

Enable

Disable E1 Disable F000001

Enable E1-E1

Disable E2 Disable F100010

Enable E1-E2

Disable E3 Disable F200011

Enable E1-E3

Disable E4 Disable F300100

Enable E1-E4

Disable E5 Disable F400101

Enable E1-E5

Disable E6 Disable F500110

Enable E1-E6

Disable E7 Disable F600111

Enable E1-E7

Disable E8 Disable F701000

Enable E1-E8

Disable E9 Disable F801001

Enable E1-E9

Disable EA Disable F901010

Enable E1-EA

Disable EB Disable FA01011

Enable E1-EB

Exp PDI PDI

register value

None 01111

10000

10001

10010

10011

10100

10101

10110

10111

11000

11001

11010

PDI range

register value

Enable E1-EF

Enable E1-F0

Enable E1-F1

Enable E1-F2

Enable E1-F3

Enable E1-F4

Enable E1-F5

Enable E1-F6

Enable E1-F7

Enable E1-F8

Enable E1-F9

Enable E1-FA

Exp PDI

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Enable E1-EC Enable E1-FB

Disable ED Disable FC01101

Enable E1-ED

Disable EE01110

Enable E1-EE

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Enable E1-FC

The RHPP monitors bits 5, 6 and 7 of the path status byte (G1) to detect path remote defect indication (RDI-P) and path enhanced remote defect indication (ERDI-P) defects.

RDI-P is declared when bit 5 of the G1 byte is set high for five or ten consecutive frames (selectable by the PRDI10 bit in the configuration register). RDI-P is removed when bit 5 of the G1 byte is set low for five or ten consecutive frames. ERDI-P is declared when the same 010, 100, 101, 110 or 111 pattern is detected in bits 5, 6 and 7 of the G1 byte for five or ten consecutive frames (selectable by the PRDI10 bit in the configuration register). ERDI-P is removed when the same 000, 001 or 011 pattern is detected in bits 5, 6 and 7 of the G1 byte for five or ten consecutive frames.

The RHPP extracts and serially outputs all the path overhead (POH) bytes on the time multiplexed RPOH port. The POH bytes are output in the same order that they are received (J1, B3, C2, G1, F2, H4, Z3, Z4 and N1). RPOHCLK is the generated output clock used to provide timing for the RPOH port. RPOHCLK is a nominal 20.736 MHz clock generated by gapping a

25.92 MHz clock. Sampling RPOHFP high with the rising edge of RPOHCLK identifies the MSB of the first J1 byte.

10.6 SONET/SDH Virtual Container Aligner (SVCA)

The SONET (SDH) Virtual Container Aligner (SVCA) block aligns the payload data from an incoming SONET (SDH) data stream to a new transport frame reference. The alignment is accomplished by recalculating the STS (AU) payload pointer value based on the offset between the transport overhead of the incoming data stream and that of the outgoing data stream.

Frequency offsets (e.g., due to plesiochronous network boundaries, or the loss of a primary reference timing source) and phase differences (due to normal network operation) between the incoming data stream and the outgoing data stream are accommodated by pointer adjustments in the outgoing data stream.

10.6.1 Elastic Store

The Elastic Store performs rate adaptation between the line side interface and the system side interface. The entire incoming payload, including path overhead bytes, is written into a first-infirst-out (FIFO) buffer at the incoming byte rate. Each FIFO word stores a payload data byte and a one bit tag labeling the J1 byte. Incoming pointer justifications are accommodated by writing into the FIFO during the negative stuff opportunity byte or by not writing during the positive stuff

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opportunity byte. Data is read out of the FIFO in the Elastic Store block at the outgoing byte rate by the Pointer Generator. Analogously, outgoing pointer justifications are accommodated by reading from the FIFO during the negative stuff opportunity byte or by not reading during the positive stuff opportunity byte.

The FIFO read and write addresses are monitored. Pointer justification requests will be made to the Pointer Generator based on the proximity of the addresses relative to programmable thresholds. The Pointer Generator schedules a pointer increment event if the FIFO depth is below the lower threshold and a pointer decrement event if the depth is above the upper threshold. FIFO underflow and overflow events are detected and path AIS is optionally inserted in the outgoing data stream for three frames to alert downstream elements of data corruption.

10.6.2 Pointer Generator

The Pointer Generator generates the H1 and H2 bytes in order to identify the location of the path overhead byte (J1) and all the synchronous payload envelope bytes (SPE) of the STS-48c (VC16-16c) payloads. Within the pointer generator algorithm, five states are defined as shown below:

NORM_state (NORM)

AIS_state (AIS)

NDF_state (NDF)

INC_state (INC)

DEC_state (DEC)

The transition from the NORM to the INC, DEC, and NDF states are initiated by events in the Elastic Store block. The transition to/from the AIS state are controlled by the pointer interpreter in the Receive High Order Path Processor block. The transitions from INC, DEC, and NDF states to the NORM state occur autonomously with the generation of special pointer patterns.

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Figure 11: Pointer Generation State Diagram

PI_AIS

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INC

inc_ind

PI_AIS

norm_point

PI_LOP

ES_lowerT

PI_AIS

PI_NORM

NORM

dec_ind

ES_upperT

FO_discont

DEC

NDF_enable

AIS

PI_AIS

AIS_ind

The following events, indicated in the state diagram, are defined:

ES_lowerT: ES filling is below the lower threshold + previous inc_ind, dec_ind or

NDF_enable more than three frames ago.

ES_upperT: ES filling is above the upper threshold + previous inc_ind, dec_ind or

NDF_enable more than three frames ago.

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FO_discont: frame offset discontinuity

PI_AIS: PI in AIS state

PI_LOP: PI in LOP state

PI_NORM: PI in NORM state

Note 1 A frame offset discontinuity occurs if an incoming NDF enabled is

received, or if an ES overflow/underflow occurred.

The autonomous transitions indicated in the state diagram are defined as follows:

inc_ind: transmit the pointer with NDF disabled and inverted I bits, transmit a stuff

byte in the byte after H3, increment active offset.

dec_ind: transmit the pointer with NDF disabled and inverted D bits, transmit a

data byte in the H3 byte, decrement active offset.

NDF_enable: accept new offset as active offset, transmit the pointer with NDF enabled

and new offset.

norm_point: transmit the pointer with NDF disabled and active offset.

AIS_ind: active offset is undefined, transmit an all-1's pointer and payload.

Note 1 active offset is defined as the phase of the SPE (VC).

Note 2 the ss bits are undefined in SONET, and has bit pattern 10 in SDH

Note 3 enabled NDF is defined as the bit pattern 1001.

Note 4 disabled NDF is defined as the bit pattern 0110.

10.7 Receive Cell and Frame Processor (RCFP)

The Receive Cell and Frame Processor (RCFP) performs both ATM and PPP processing. It has the capability to process a single STS-48c (STM-16c) channel.

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10.7.1 ATM Cell Delineation

Cell Delineation is the process of framing to ATM cell boundaries using the header check sequence (HCS) field found in the cell header. The HCS is a CRC-8 calculation over the first 4 octets of the ATM cell header. When performing delineation, correct HCS calculations are assumed to indicate cell boundaries. Cells are assumed to be byte-aligned to the synchronous payload envelope. The cell delineation algorithm searches the 53 possible cell boundary candidates individually to determine the valid cell boundary location. While searching for the cell boundary location, the cell delineation circuit is in the HUNT state. When a correct HCS is found, the cell delineation state machine locks on the particular cell boundary, corresponding to the correct HCS, and enters the PRESYNC state. The PRESYNC state validates the cell boundary location. If the cell boundary is invalid, an incorrect HCS will be received within the next DELTA cells, at which time a transition back to the HUNT state is executed. If no HCS errors are detected in this PRESYNC period, the SYNC state is entered. While in the SYNC state, synchronization is maintained until ALPHA consecutive incorrect HCS patterns are detected. In such an event a transition is made back to the HUNT state. The state diagram of the delineation process is shown in below.

Figure 12: Cell Delineation State Diagram

correct HCS (byte by byte)

HUNT

Incorrect HCS (cell by cell)

ALPHA consecutive incorrect HCS's (cell by cell)

SYNC

PRESYNC

DELTA consecutive correct HCS's (cell by cell)

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The values of ALPHA and DELTA determine the robustness of the delineation process. ALPHA determines the robustness against false misalignments due to bit errors. DELTA determines the robustness against false delineation in the synchronization process. ALPHA is chosen to be 7 and DELTA is chosen to be 6. These values result in an average time to delineation of 2

µs for

the STS-48c (STM-16c) rate.

10.7.2 ATM Descrambler

The self-synchronous descrambler operates on the 48 byte cell payload only. The circuitry descrambles the information field using the x43 + 1 polynomial. The descrambler is disabled for

the duration of the header and HCS fields and may optionally be disabled for the payload.

10.7.3 ATM Cell Filter and HCS Verification

Cells are filtered (or dropped) based on HCS errors and/or a cell header pattern. Cell filtering is optional and is enabled through the RCFP registers. Cells are passed to the receive FIFO while the cell delineation state machine is in the SYNC state as described above. When both filtering and HCS checking are enabled, cells are dropped if uncorrectable HCS errors are detected, or if the corrected header contents match the pattern contained in the RCFP Idle Cell Header and Mask register. Idle cell filtering is accomplished by writing the appropriate cell header pattern into the RCFP Idle Cell Header and Mask Pattern register. Idle/Unassigned cells are assumed to contain the all zeros pattern in the VCI and VPI fields. The RCFP Idle Cell Header and Mask register allows filtering control over the contents of the GFC, PTI, and CLP fields of the header.

The HCS is a CRC-8 calculation over the first 4 octets of the ATM cell header. The RCFP block verifies the received HCS using the polynomial, x8 + x2 + x + 1. The coset polynomial, x6 + x4 + x2 + 1, is added (modulo 2) to the received HCS octet before comparison with the calculated

result.

ATM Performance Monitor

The Performance Monitor consists of two 16-bit saturating HCS error event counters and a 32-bit saturating receive cell counter. The first error counter accumulates uncorrectable HCS errors. A 32-bit receive cell counter counts all cells written into the receive FIFO. Filtered cells are not counted.

Each counter may be read through the microprocessor interface. Circuitry is provided to latch these counters so that their values can be read while simultaneously resetting the internal counters to 0 or 1, if appropriate, so that a new period of accumulation can begin without loss of any events. It is intended that the counter be polled at least once per second so as not to miss any counted events.

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10.7.5 POS Overhead Removal

The overhead removal consists of stripping SONET/SDH overhead bytes from the data stream. Once overhead bytes are removed, the data stream consists of PPP/HDLC frame octets that can be fed directly to the descrambler or the PPP/HDLC Frame Delineation block.

10.7.6 POS Descrambler

When enabled, the self-synchronous descrambler operates on the PPP Frame data, descrambling the data with the polynomial x43+1. Descrambling is performed on the raw data

stream, before any PPP frame delineation or byte destuffing is performed. Data scrambling can provide for a more robust system preventing the injection of hostile patterns into the data stream.

10.7.7 POS PPP/HDLC Frame Delineation

The PPP/HDLC Frame Delineation is performed on the descrambled data and consists of arranging the framed octets. Frame boundaries are found by searching for the Flag Character (0x7E). Flags are also used to fill inter-packet spacing. This block removes the Flag and Idle Sequences and passes the data onto the Byte Destuffing block. The PPP/HDLC Frame format is shown in the figure below.

Figure 13: PPP/HDLC Over SONET Frame Format

Flag Packet (PPP or other) FCS Flag Flag

In the event of a FIFO overflow caused by the FIFO being full while a packet is being received, the packet is marked with an error so it can be discarded by the system. Subsequent bytes associated with this now aborted frame are discarded. Reception of PPP/HDLC data resumes when a Start of Packet is encountered and the FIFO level is below a programmable Reception Initialization Level.

10.7.8 POS Byte Destuffing

The byte destuffing algorithm searches the Control Escape character (0x7D). These characters, listed in the table below are added for transparency in the transmit direction and must be removed to recover the user data. When the Control Escape character is encountered, it is removed and the following data byte is XORed with 0x20. Therefore, any escaped data byte will be processed properly by the S/UNI-2488.

POS Frame

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Table 3: Byte Destuffing

Original Escaped

7E (Flag Sequence) 7D-5E 7D (Control Escape) 7D-5D Aborted Packet 7D-7E

10.7.9 POS FCS Check

The FCS Generator performs a CRC-CCITT or CRC-32 calculation on the whole POS frame, after byte destuffing and data descrambling scrambling. A parallel implementation of the CRC polynomial is used. The CRC algorithm for the frame checking sequence (FCS) field is either a CRC-CCITT or CRC-32 function. The CRC-CCITT is two bytes in size and has a generating

polynomial g(X) = 1 + X5 + X12 + X16. The CRC-32 is four bytes in size and has a generating polynomial g(X) = 1 + X + X2 + X4 + X5 + X7 + X8 + X10 + X11 + X12 + X16 + X22 + X23 + X + X32. The first FCS bit transmitted is the coefficient of the highest term. . Packets with FCS

errors are marked as such and should be discarded by the system.

26

Figure 14: CRC Decoder

D

Message

+

0

10.7.10 POS Performance Mo nit o r

The Performance Monitor consists of four 16-bit saturating error event counters, one 32-bit saturating received good packet counter, and one 40-bit counter for accumulating packet bytes. One of the error event counters accumulates FCS errors. The second error event counter accumulates minimum length violation packets. The third error event counter accumulates maximum length violation packets. The fourth error event counter accumulates aborted packets. The 32-bit receive good packet counter counts all error free packets.

Each counter may be read through the microprocessor interface. Circuitry is provided to latch these counters so that their values can be read while simultaneously resetting the internal counters to 0 or 1, whichever is appropriate, so that a new period of accumulation can begin without loss of any events. The counters should be polled at least once per second so error events will not be missed.

g

+

g

1

D

1

2

. . .

+ +

n-1

D

n-1

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The RCFP monitors the packets for both minimum and maximum length errors. When a packet size is smaller than MINPL[7:0], the packet is marked with an error but still written into the FIFO. Malformed packets, that is packets that do not at least contain four bytes, are discarded and will be counted as a minimum packet size violation. When the packet size exceeds MAXPL[16:0] the packet is marked with an error and the bytes beyond the maximum count are discarded.

10.8 Receive Scalable Data Queue (RXSDQ)

The RXSDQ provides a FIFO to separate the line-side timing from the higher layer ATM/POS link layer timing. The RXSDQ has two modes of operations, ATM and POS.

10.8.1 Receive ATM FIFO

The RXSDQ is responsible for holding up to 48 cells until they are read by the Receive System Interface.

Receive FIFO management functions include filling the receive FIFO, indicating when cells are available to be read from the receive FIFO, maintaining the receive FIFO read and write pointers, and detecting FIFO overrun conditions. Upon detection of an overrun, the FIFO discards the current cell and discards the incoming cells until there is room in the FIFO. FIFO overruns are indicated through a maskable interrupt and register bit and are considered a system error.

10.8.2 Receive POS FIFO

The RXSDQ contains 48 sixteen byte blocks for FIFO storage, along with management circuitry for reading and writing the FIFO. The receive FIFO provides for the separation of the physical layer timing from the system timing.

Receive FIFO management functions include filling the receive FIFO, indicating when packets or bytes are available to be read from the receive FIFO, maintaining the receive FIFO read and write pointers, and detecting FIFO overrun and underrun conditions. Upon detection of an overrun, the FIFO aborts the current packet and discards the current incoming bytes until there is room in the FIFO. Once enough room is available, as defined by the BT[7:0] register bit settings, the RXSDQ will wait for the next start of packet before writing any data into the FIFO. FIFO overruns are indicated through a maskable interrupt and register bit and are considered a system error. A FIFO underrun is caused when the System Interface tries to read more data words while the FIFO is empty. This action will be detected and reported through the FUDRI interrupt, but it is not considered a system error. The system will continue to operate normally. In that situation, RVAL can be used by the Link Layer device to find out if valid or invalid data is provided on the System Interface.

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10.9 Receive Phy Interface (RXPHY)

The S/UNI-2488 receive system interface can be configured for ATM or POS mode. When configured for ATM applications, the system interface provides a 32-bit Receive UTOPIA Level 3 compatible bus to allow the transfer of ATM cells between the ATM layer device and the S/UNI-

2488. When configured for POS applications, the system interface provides either a 32-bit POSPHY Level 3 compliant bus for the transfer of ATM cells and data packets between the link layer device and the S/UNI-2488. The link layer device can implement various protocols, including PPP and HDLC.

10.9.1 Receive UTOPIA Level 3 Interface

The UTOPIA Level 3 compliant interface accepts a read clock (RFCLK) and read enable signal (RENB). The interface indicates the start of a cell (RSOC) when data is read from the receive FIFO (using the rising edges of RFCLK). The RCA signal indicates when a cell is available for transfer on the receive data bus RDAT[31:0]. The RPRTY signal reports the parity on the RDAT[31:0] bus (selectable as odd or even parity). This interface also indicates FIFO overruns via a maskable interrupt and register bits. Read accesses while RCA is deasserted will output invalid data.

10.9.2 Receiv e POS-PHY Level 3

The interface accepts a read clock (RFCLK) and read enable signal (RENB) when data is read from the receive FIFO (using the rising edge of the RFCLK). The start of packet RSOP marks the first byte of receive packet data on the RDAT[31:0]. The RPRTY signal determine the parity on the RDAT[31:0] bus (selectable as odd or even parity). The end of a packet is indicated by the REOP signal. Signal RERR is provided to indicate that an error in the received packet has occurred (the error may have several causes include an abort sequence or an FCS error). The RVAL signal is used to indicate when RSOP, REOP, RERR and RDAT[31:0] are valid. Read accesses while RVAL is logic 0 are ignored and will output invalid data. RSX indicates the start of a transfer and marks the clock cycle where the in-band channel address is given on the RDAT bus. The RXPHY performs the polling procedure to select which PHY address is serviced.

10.10 Transmit Line Interface

The Transmit Line Interface allows the S/UNI-2488 to directly interface with optical modules (ODLs) or other medium interfaces. This block performs clock synthesis and performs parallel to serial conversion of the incoming outgoing 2488.32 Mbit/s data stream.

The transmit clock is synthesized from a 155.52. MHz reference. The transfer function yields a typical low pass corner of octave. The design of the loop filter and PLL is optimized for minimum intrinsic jitter. With a jitter free 155.52MHz reference, the intrinsic jitter is typically less than using a high pass filter with a

TBD MHz above which reference jitter is attenuated at TBD dB per

TBD UI RMS when measured

TBD cutoff frequency.

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The REFCLK reference should be within ±20 ppm to meet the SONET free-run accuracy requirements specified in GR-253-CORE.

The Parallel to Serial Converter (PISO) converts the transmit byte serial stream to a bit serial stream. The transmit bit serial stream appears on the TXD+/- PECL outputs.

10.11 SONET/SDH Transmit Line Interface (STLI)

The SONET/SDH transmit line interface block properly formats the outgoing 2488 Mbit/s data stream. This block interfaces the TRMP to the Tx Line Interface block.

10.12 Transmit Regenerator Multiplexor Processor (TRMP)

The Transmit Regenerator and Multiplexor Processor (TRMP) block inserts the transport overhead bytes in the transmit data stream.

The TRMP accumulates the line BIP-8 errors detected by the RRMP during the last receive frame. The line BIP-8 errors are returned to the far end as line remote error indication (REI-L) during the next transmit frame. Because the RRMP and the TRMP are in two different clock domains, none, one or two line BIP-8 errors can be accumulated per transmit frame. The minimum value between the maximum REI-L and the accumulator count is returned as the line REI-L in the M1 byte of STS-1 (STM-0) #3. Optionally, block BIP-24 errors can be accumulated. For STS-48c (STM-16c), the maximum single BIP-8 error count is 0xFF while the maximum block BIP-24 error count is 0x10.

The TRMP serially inputs all the transport overhead (TOH) bytes from the TTOH port. The TOH bytes must be input in the same order that they are transmitted (A1, A2, J0/Z0, B1, E1, F1, D1D3, H1-H3, B2, K1, K2, D4-D12, S1/Z1, Z2/M1/Z2 and E2). TTOHCLK is the generated output clock used to provide timing for the TTOH port. TTOHCLK is a nominal 20.736 MHz clock generated by gapping a 25.92 MHz clock. Sampling TTOHFP high with the rising edge of TTOHCLK identifies the MSB of the first A1 byte. TTOHEN port is used to validate the byte insertion on a byte per byte basis. When TTOHEN is sampled high on the MSB of the serial byte, the serial byte is inserted. When TTOHEN is sampled low on the MSB of the serial byte, the serial byte is discarded.

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Figure 15: STS-48c (STM-16-16c) on TTOH

STS-1/STM-0 #3

STS-1/STM-0 #2

STS-1/STM-0 #1

First order of transmission

Second order of transmission

A1

A1A1 A1 B1 D1 H1

H1B2H1B2H1

B2

B2 D4 D7

D10

S1

Unused bytes National bytes

Z1Z1Z1

STS-1/STM-0 #4

STS-1/STM-0 #5

A1

H1

B2

Z1

STS-1/STM-0 #12

A2 A2 A2

A1

... ... ... ... ... ... ... ... ...

E1 D2 H2

H1

K1

B2

D5 D8

D11

Z2 Z2 Z2

Z1

Z0 Z0 or National bytes

A2

H2

M1

A2

H2

Z2

STS-1/STM-0 #5

A2

H2

Z2

STS-1/STM-0 #4

STS-1/STM-0 #3

STS-1/STM-0 #2

STS-1/STM-0 #1

STS-1/STM-0 #12

... ... ... ... ... ... ... ... ...

J0 F1 D3 H3 H3H2 H2 K2 D6 D9

D12

E2

Z0

H3

Z0

H3

Z0

H3

STS-1/STM-0 #5

H3

STS-1/STM-0 #4

STS-1/STM-0 #3

STS-1/STM-0 #2

STS-1/STM-0 #1

STS-1/STM-0 #12

Z0...Z0 ... ... ... ... ... ... ... ...

Note, only the overhead from the first STS-12 (STM-4) of the STS-48c (STM-16c) can be sourced. Overhead from the other three STS-12s (STM-4s) are internally generated assigned or are assigned default values as described below.

The TRMP also inserts most of the transport overhead bytes from internal registers. Since there is multiple sources for the same overhead byte, the TOH bytes must be prioritised according to Table 4 before being inserted into the data stream.

Table 4: TOH insertion priority

BYTE HIGHEST

priority

A1 76h

(A1ERR=1)

A2

J0

STS-1/STM-0 #

(J0Z0INCEN=1)

(TRACEEN=1

J0[7:0]

F6h

(A1A2EN=1)

28h

(A1A2EN=1)

J0V

(J0REGEN=1)

TTOH

(TTOHEN=1)

TTOH

(TTOHEN=1)

TTOH

(TTOHEN=1)

LOWEST

priority

A1 pass through

A2 pass through

J0 pass through

)

Z0

B1

STS-1/STM-0 #

(J0Z0INCEN=1)

Z0V

(Z0REGEN=1)

TTOH

(TTOHEN=1)

Calculated B1

xor TTOH

Z0 pass through

Calculated B1

xor B1MASK

(TTOHEN=1 &

B1MASKEN=1)

TTOH

(TTOHEN=1 &

B1MASKEN=0)

E1 E1V

(E1REGEN=1)

TTOH

(TTOHEN=1)

E1 pass through

F1 F1V TTOH F1 pass through

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D1-D3

H1

H2

H3 TTOH

B2

K1

K2 APS[7:0]

D4-D12 D4D12V

S1 S1V

Z1 Z1V

Z2

M1

E2

National NATIONALV

Unused UNUSEDV

PLD PLD

APS[15:8]

(APSEN=1)

PMC-Sierra, Inc.

(F1REGEN=1) (TTOHEN=1)

D1D3V

(D1D3REGEN=1)

K1V

(K1K2REGEN=1)

K2V

(K1K2REGEN=1)

(D4D12REGEN=1)

(S1REGEN=1)

(Z1REGEN=1)

Z2V

(Z2REGEN=1)

LREI[7:0]

(LREIEN=1)

E2V

(E2REGEN=1)

(NATIONALEN=1)

(UNUSEDEN=1)

(TTOHEN=1)

H1 pass through

xor TTOH (TTOHEN=1 & HMASKEN=1)

(TTOHEN=1 & HMASKEN=0)

H2 pass through

xor TTOH (TTOHEN=1 & HMASKEN=1)

(TTOHEN=1 & HMASKEN=0)

(TTOHEN=1)

Calculated B2

xor TTOH (TTOHEN=1 &

B2MASKEN=1)

(TTOHEN=1 &

B2MASKEN=0)

(TTOHEN=1)

TTOH

PM5381 S/UNI-2488

D1-D3 pass

through

H1 pass through

xor H1 MASK

H2 pass through

xor H2 MASK

H3 pass through

Calculated B2

xor B2MASK

K1 pass through

K2 pass through

D4-D12 pass

through

S1 pass through

Z1 pass through

Z2 pass through

M1 pass through

E2 pass through

National pass

through

Unused pass

through

pass through

The Z0DEF register bit defines the Z0/NATIONAL growth bytes for row #1. When Z0DEF is set to logic one, the Z0/NATIONAL bytes are defined according to ITU. When Z0DEF is set to logic zero, the Z0/NATIONAL bytes are defined according to BELLCORE.

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Table 5: Z0/National growth bytes definition for row #1

TRMP mode Type Z0DEF = 1 Z0DEF = 0

STS-48c (STM-16)

slave mode

Z0 From STS-1/STM-0 #1 to #4 From STS-1/STM-0 #1 to #12

National From STS-1/STM-0 #5 to #12 None

The H1, H2, B1 and B2 bytes input from the TTOH port are inserted or are used as a mask to toggle bits in the corresponding H1, H2, B1 and B2 bytes depending on the HMASK, B1MASK and B2MASK register bits of the TRMP Error Insertion register. When the HMASK, B1MASK or B2MASK register bit is set low and TTOHEN is sampled high on the MSB of the serial H1, H2, B1 or B2 byte, the serial byte is inserted in place of the corresponding byte. When the HMASK, B1MASK or B2MASK register bit is set high and TTOHEN is sampled high on the MSB of the serial H1, H2, B1 or B2 byte, the serial byte is xor with the corresponding path payload pointer (already in the data stream) or the calculated BIP-8 byte before being inserted.

The TRMP inserts the APS bytes detected by the RRMP during the last receive frame. The APS bytes are returned to the far end by the TRMP during the next transmit frame. Because the RRMP and the TRMP are in two different clock domains, none, one or two APS bytes can be sampled per transmit frame. The last received APS bytes are transmitted.

The TRMP inserts the line remote defect indication (RDI-L) into the data stream. When line RDI must be inserted, the 110 pattern is inserted in bits 6, 7 and 8 of the K2 byte of STS-1 (STM-0) #1. Line RDI insertion has priority over TOH byte insertion. The TRMP also inserts the line alarm indication signal (AIS-L) into the data stream. When line AIS must be inserted, all ones are inserted in the line overhead and in the payload (all bytes of the frame except the section overhead bytes). Line AIS insertion has priority over line RDI insertion and TOH byte insertion.

The TRMP calculates the line BIP-8 error detection codes on the transmit data stream. One line BIP-8 error detection code is calculated for each of the constituent STS-1 (STM-0). The line BIP8 byte is calculated on the unscrambled bytes of the STS-1 (STM-0) except for the 9 SOH bytes. The line BIP-8 byte is based on a bit interleaved parity calculation using even parity. For each STS-1 (STM-0), the calculated BIP-8 error detection code is inserted in the B2 byte of the following frame before scrambling. The TRMP optionally scrambles the transmit data stream.

The TRMP calculates the section BIP-8 error detection code on the transmit data stream. The section BIP-8 byte is calculated on the scrambled bytes of the complete frame. The section BIP8 byte is based on a bit interleaved parity calculation using even parity. The calculated BIP-8 error detection code is inserted in the B1 byte of STS-1 (STM-0) #1 of the following frame before scrambling.

10.13 Transmit Tail Trace Processor (TTTP)

The Transmit Tail Trace Processor (TTTP) block generates the tail trace messages to be transmitted. The TTTP can generate a 16 or 64 byte tail trace message. The message is source from an internal RAM and must have been previously written by an external micro processor. Optionally, the tail trace message can be reduced to a single continuous tail trace byte.

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The tail trace message must include synchronisation because the TTTP does not add synchronisation. The synchronisation mechanism is different for a 16 bytes message and for a 64 bytes message. When the message is 16 bytes, the synchronisation is based on the MSB of the tail trace byte. Only one of the 16 bytes has is MSB set high. The byte with its MSB set high is considered the first byte of the message. When the message is 64 bytes, the synchronisation is based on the CR/LF (CR = 0Dh, LF = 0Ah) characters of tail trace message. The byte following the CR/LF bytes is considered the first byte of the message.

To avoid generating an unstable/mismatch message, the TTTP forces the message to all zeros while the microprocessor updates the internal RAM.

10.14 Transmit High Order Path Processor (THPP)

The Transmit High Order Path Processor (THPP) block inserts the path overhead bytes in the transmit data stream.

The THPP accumulates the path BIP-8 errors detected by the RHPP during the last receive frame. The path BIP-8 errors are returned to the far end as path remote error indication (REI-P) during the next transmit frame. Because the RHPP and the THPP are in two different clock domains, none, one or two path BIP-8 errors can be accumulated per transmit frame. The minimum value between the maximum REI-P and the accumulator count is returned as the path REI in the G1 byte. Optionally, block BIP-8 errors can be accumulated.

The THPP serially inputs all the path overhead (POH) bytes from the TPOH port. The POH bytes must be input in the same order that they are transmitted (J1, B3, C2, G1, F2, H4, F3, K3 and N1). TOHCLK is the generated output clock used to provide timing for the TPOH port. TOHCLK is a nominal 20.736 MHz clock generated by gapping a 25.92 MHz clock. Sampling TPOHRDY high with the rising edge of TOHCLK identifies the MSB of the first J1 byte. TPOHEN port is used to validate the byte insertion on a byte per byte basis. When TPOHEN is sampled high on the MSB of the serial byte, the serial byte is inserted. When TPOHEN is sampled low on the MSB of the serial byte, the serial byte is discarded.

The THPP calculates the path BIP-8 error detection code on the transmit data stream. The path BIP-8 byte is calculated on all the payload bytes. The path BIP-8 byte is based on a bit interleaved parity calculation using even parity. The calculated BIP-8 error detection code is inserted in the B3 byte of the following frame.

10.15 Transmit Cell and Frame Processor (TCFP)

The Transmit Cell and Frame Processor (TCFP) performs both ATM and PPP processing. It has the capability to process a single STS-48c (STM-16c) channel. In ATM mode, the TCFP performs provides rate adaptation via idle/unassigned cell insertion, provides HCS generation and insertion, and performs ATM cell scrambling. In POS mode, the TCFP provides rate adaptation by transmitting flag sequences (0x7E) between packets, provides FCS generation and insertion, performs packet data scrambling, and provides performance monitoring functions.

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10.15.1 ATM Idle/Unassigned Cell Generator

The Idle/Unassigned Cell Generator inserts idle or unassigned cells into the cell stream when enabled. Registers are provided to program the GFC, PTI, and CLP fields of the idle cell header and the idle cell payload. The idle cell HCS is automatically calculated and inserted.

10.15.2 ATM Scrambler

The Scrambler scrambles the 48 octet information field. Scrambling is performed using a parallel implementation of the self-synchronous scrambler (x43 + 1 polynomial) described in the

references. The cell headers are transmitted unscrambled, and the scrambler may optionally be disabled.

10.15.3 ATM HCS Generator

The HCS Generator performs a CRC-8 calculation over the first four header octets. A parallel implementation of the polynomial, x8+x2+x+1, is used. The coset polynomial, x6+x4+x2+1, is

added (modulo 2) to the residue. The HCS Generator optionally inserts the result into the fifth octet of the header.

10.15.4 POS PPP/HDLC Frame Generato r

The PPP/HDLC Frame Generator runs off of the SONET sequencer to create the POS frames to be transmitted. Flags are inserted whenever the Transmit FIFO is empty and there is no data to transmit. When there is enough data to be transmitted, the block operates normally; it removes packets from the Transmit FIFO and transmits them. In addition, FCS generation, error insertion, byte stuffing, and scrambling can be optionally enabled.

In the event of a FIFO underflow caused by the FIFO being empty while a packet is being transmitted, the packet is aborted by transmitting the Abort Sequence. The PPP Abort Sequence consists of an Escape Control character (0x7D) followed by the Flag Sequence (0x7E). Bytes associated with this aborted frame are still read from the FIFO but are discarded and replaced with the Flag Sequence in the outgoing data stream. If an overflow occurs, the packet being transmitted will also be aborted and the same abort sequence will be added. Transmission of data resumes when a Start of Packet is encountered in the FIFO data stream.

The POS Frame Generator also performs Inter Packet Gapping. This operation consists of inserting a programmable number of Flag and Idle Sequence characters between each PPP/HDLC Frame transmission. This feature allows one to control the system effective data transmission rate if required.

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10.15.5 POS FCS Generator

The FCS Generator performs a CRC-CCITT or CRC-32 calculation on the whole POS frame, before byte stuffing and data scrambling. A parallel implementation of the CRC polynomial is used. The CRC algorithm for the frame checking sequence (FCS) field is either a CRC-CCITT or CRC-32 function. The CRC-CCITT is two bytes in size and has a generating polynomial g(X) = 1

+ X5 + X12 + X16. The CRC-32 is four bytes in size and has a generating polynomial g(X) = 1 + X + X2 + X4 + X5 + X7 + X8 + X10 + X11 + X12 + X16 + X22 + X23 + X26 + X32. The first FCS

bit transmitted is the coefficient of the highest term. When transmitting a packet from the Transmit FIFO, the FCS Generator appends the result after the last data byte, before the closing flag. Note that the Frame Check Sequence is the one's complement of the CRC register after calculation ends. FCS calculation and insertion can be disabled.

Figure 16: CRC Generator

g

D

0

+

LSB

An error insertion mechanism is provided for system diagnosis purposes. Error insertion is performed by inverting the resulting FCS value, before transmission. This should cause an FCS Error at the far end.

10.15.6 POS Byte Stuffing

The PPP Frame generator provides transparency by performing byte stuffing. This operation is done after the FCS calculation. Two characters are being escaped, the Flag Sequence (0x7E) and the Escape Character itself (0x7D). When a character is being escaped, it is XORed with 0x20 before transmission and preceded by the Control Escape (0x7D) character.

Table 6: Byte Stuffing

g

1

2

n-1

Message

D

1

+ +

Parity Check Digits

. . .

D

n-1

+

MSB

Original Escaped

7E (Flag Sequence) 7D-5E 7D (Control Escape) 7D-5D Abort Sequence 7D- 7E

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10.15.7 Data Scrambling

The Scrambler will optionally scramble the whole packet data, including the FCS and the flags. Scrambling is performed after the POS frame is formed using a parallel implementation of the

self-synchronous scrambler polynomial, x43+1. On reset, the scrambler is set to all ones to ensure scrambling on start-up. The scrambler may optionally be completely disabled. Data scrambling can provide for a more robust system preventing the injection of hostile patterns into the data stream.

10.16 Transmit Scalable Data Queue (TXSDQ)

The TXSDQ provides a FIFO to separate the line-side timing from the higher layer ATM/POS link layer timing. The TXSDQ has two modes of operations, ATM and POS.

10.16.1 Transmit ATM FIFO

The TXSDQ is responsible for holding up to 48 cells until they can be read and transmitted. The cells are written in with a single 32-bit data bus running off TFCLK and are read out at the channel rate. Internal read and write pointers track the cells and indicate the fill status of the Transmit FIFO. Separate read and write clock domains provide for separation of the physical layer line timing from the System Link layer timing (TFCLK).

10.16.2 Transmit POS FIFO

The TXSDQ contains 48 sixteen byte blocks for FIFO storage, along with management circuitry for reading and writing the FIFO. Octets are written in with a single 32-bit data bus running off TFCLK and are read out with a single 32-bit data bus. Separate read and write clock domains provide for separation of the physical layer line timing from the System Link layer timing.

Internal read and write pointers track the insertion and removal of octets, and indicate the fill status of the Transmit FIFO. These status indications are used to detect underrun and overrun conditions, abort packets as appropriate on both System and Line sides, control flag insertion and to generate the DTPA output.

10.17 Transmit Phy Interfaces (RXPHY and TXPHY)

The S/UNI-2488 transmit system interface can be configured for ATM or POS mode. When configured for ATM applications, the system interface provides a 32-bit transmit UTOPIA Level 3 compatible bus to allow the transfer of ATM cells between the ATM layer device and the S/UNI-

2488. When configured for POS applications, the system interface provides either a 32-bit POSPHY Level 3 compliant bus for the transfer of ATM cells and data packets between the link layer device and the S/UNI-2488. The link layer device can implement various protocols, including PPP and HDLC.

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Datasheet PM5381-BI Datasheet (PMC)

Specifications and Main Features

Frequently Asked Questions

User Manual

CONTENTS

LIST OF REGISTERS

LIST OF TABLES

1.2 SONET Section and Line / SDH Regenerator and Multiplexer Section

1.3 SONET Path / SDH High Order Path

1.4 The Receive ATM Processor

1.5 The Receive POS Processor

1.6 The Transmit ATM Processor

1.7 The Transmit POS Processor