• On each channel, provides clear-channel mapping of three 49.536 Mbit/s or 48.384 Mbit/s
arbitrary data streams into an STS-3 (STM-1/AU-3) frame. Provides clear-channel mapping
of a single 149.76 Mbit/s arbitrary data stream into an STS-3c (STM-1/AU-4) frame.
• Supports line loopback from the line side receive stream to the transmit stream and diagnostic
loopback from a Telecom Add bus interface to a Telecom Drop bus interface.
• Provides a standard 5 signal P1149.1 JTAG test port for boundary scan board test purposes.
• Provides a generic 8-bit microprocessor bus interface for configuration, control, and status
monitoring.
• Low power 3.3 V CMOS with TTL compatible digital inputs and CMOS/TTL digital outputs.
PECL inputs and outputs are 3.3 V and 5 V compatible.
• Industrial temperature range (-40 °C to +85 °C).
• 520 pin Super BGA package.
• Complies with Telcordia GR-253-CORE (1995) jitter tolerance, jitter transfer and intrinsic
jitter criteria.
1.2 SONET Section and Line/SDH Regenerator and Multiplexer
Section
• Frames to the STS-3/3c (STM-1/AU-3/AU-4) receive stream and inserts the framing bytes
(A1, A2) and the STS identification byte (J0) into the transmit stream; descrambles the
receive stream and scrambles the transmit stream.
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• Calculates and compares the bit interleaved parity (BIP) error detection codes (B1, B2) for
the receive stream and calculates and inserts B1 and B2 in the transmit stream; accumulates
near end errors (B1, B2) and far end errors (M1) and inserts line remote error indications
(REI) into the Z2 (M1) growth byte based on received B2 errors.
• Detects signal degrade (SD) and signal fail (SF) threshold crossing alarms based on received
B2 errors.
• Extracts and serializes the order wire channels (E1, E2), the data communication channels
(D1-D3, D4-D12) and the section user channel (F1) from the receive stream, and inserts the
corresponding signals into the transmit stream.
• Extracts and serializes the automatic protection switch (APS) channel (K1, K2) bytes,
filtering and extracting them into internal registers for the receive stream. Inserts the APS
channel into the transmit stream.
• Extracts and filters the synchronization status message (Z1/S1) byte into an internal register
for the receive stream. Inserts the synchronization status message (Z1/S1) byte into the
transmit stream.
• Extracts a 64-byte or 16-byte section trace (J0) message using an internal register bank for the
receive stream. Detects an unstable section trace message or mismatch with an expected
message, and optionally inserts Line and Path AIS on the system Drop side upon either of
these conditions. Inserts a 64-byte or 16-byte section trace (J0) message using an internal
register bank for the transmit stream.
• Detects loss of signal (LOS), out-of-frame (OOF), loss-of-frame (LOF), line remote defect
indication (RDI), line alarm indication signal (LAIS), and protection switching byte failure
alarms on the receive stream. Optionally returns line RDI in the transmit stream.
• Provides a transmit and receive ring control port, allowing alarm and maintenance signal
control and status to be passed between mate SPECTRA-155s for ring-based Add/Drop
multiplexer and line multiplexer applications.
• Configurable to force Line AIS in the transmit stream.
1.3 SONET Path / SDH High Order Path
• Accepts a multiplex of three STS-1 (STM-0/AU-3) streams or a single STS-3c (STM-1/AU-
4) stream, interprets the STS (AU) pointer bytes (H1, H2, and H3), extracts the synchronous
payload envelope(s) and processes the path overhead for the receive stream.
• Constructs a byte serial multiplex of three STS-1 (STM-0/AU-3) streams or an STS-3c
(STM-1/AU-4) stream on the transmit side.
• Detects loss of pointer (LOP), loss of tributary multiframe (LOM), path alarm indication
signal (PAIS) and path (auxiliary and enhanced) remote defect indication (RDI) for the
receive stream. Optionally inserts PAIS, path RDI in the transmit stream.
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• Extracts and serializes the entire path overhead from the three STS-1 (STM-0/AU-3) or the
single STS-3c (STM-1/AU-4) receive streams. Inserts the path overhead bytes in the three
STS-1 (STM-0/AU-3) or single STS-3c (STM-1/AU-4) stream for the transmit stream. The
path overhead bytes may be sourced from internal registers or from bit serial path overhead
input streams. Path overhead insertion may also be disabled.
• Extracts the received path signal label (C2) byte into an internal register and detects for path
signal label unstable and for signal label mismatch with the expected signal label that is
downloaded by the microprocessor. Inserts the path signal label (C2) byte from an internal
register for the transmit stream.
• Extracts a 64-byte or 16-byte path trace (J1) message using an internal register bank for the
receive stream. Detects an unstable path trace message or mismatch with an expected
message, and inserts Path RAI upon either of these conditions. Inserts a 64-byte or 16-byte
path trace (J1) message using an internal register bank for the transmit stream.
• Detects received path BIP-8 and counts received path BIP-8 errors for performance
monitoring purposes. BIP-8 errors are selectable to be treated on a bit basis or block basis.
Optionally calculates and inserts path BIP-8 error detection codes for the transmit stream.
• Counts received path REIs for performance monitoring purposes. Optionally inserts the path
REI count into the path status byte (G1) basis on bit or block BIP-8 errors detected in the
receive path. Reporting of BIP-8 errors is on a bit or block bases independent of the
accumulation of BIP-8 errors.
• Maintains the existing tributary multiframe sequence on the H4 byte until a new phase
alignment has been verified.
• Provides a serial alarm port communication of path REI and path RDI alarms to the transmit
stream of a mate SPECTRA-4x155 in the returning direction.
• Maintains the existing tributary multiframe sequence on the H4 byte until a new phase
alignment has been verified.
1.4 System Side Interfaces
• Supports TelecomBus interfaces by indicating/accepting the location of the STS identification
byte (C1), optionally the path trace byte(s) (J1), optionally the first tributary overhead byte(s)
(V1), and all synchronous payload envelope (SPE) bytes in the byte serial stream.
• Configurable to support four 19.44 MHz byte TelecomBus interfaces or a single 77.76 MHz
byte TelecomBus interface.
• For TelecomBus interface, accommodates phase and frequency differences between the
receive/transmit streams and the Add/Drop buses via pointer adjustments.
• Provides TSI function to interchange or groom 12 STS-1 (STM-0/AU-3) paths or four STS-
3/3c (STM-1/AU-3/AU-4) paths at the Telecom Add/Drop buses.
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5 Application Examples
The PM5316 SPECTRA-4x155 is designed for use in various SONET/SDH network elements
including switches, terminal multiplexers, and Add/Drop multiplexers. In these applications, the
line interface of the SPECTRA-4x155 typically interfaces directly with the electrical optical
modules and the system side interface connects directly with a TelecomBus.
Figure 1 shows how the SPECTRA-4x155 is used to implement four 155 Mbit/s aggregate
interfaces. In this application, the SPECTRA-4x155 performs SONET/SDH section, line, and
path termination and the PM5362 TUPP-PLUS performs tributary pointer processing and
performance monitoring.
Figure 1 STS-3 (STM-0/AU-3) or STS-3c (STM-1/AU-4) Application with 19.44 MHz Byte
The system side interface of the SPECTRA-4x155 can be configured to have a 77.76 MHz byte
TelecomBus interface. Figure 2 shows how the SPECTRA-4x155 is used to implement a 622
Mbit/s aggregate interface using the high-speed TelecomBus on the system side interface. In this
application, the SPECTRA-4x155 performs SONET/SDH section, line, and path termination.
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7 Functional Description
The PM5316 SPECTRA 4X155 SONET/SDH Payload Extractor/Aligner terminates the transport
and path overhead of four STS-3 (STM-1/AU-3) and STS-3c (STM-1/AU-4) streams at 155
Mbit/s. The device implements significant receive and transmit functions for a SONET/SDHcompliant line interface.
In the receive direction, the SPECTRA-4x155 receives SONET/SDH frames via bit serial
interfaces, recovers clock and data, and terminates the SONET/SDH section (regenerator section),
line (multiplexer section), and path. The device performs framing (A1, A2), descrambling, alarm
detection, and section and line bit interleaved parity (BIP) (B1, B2) monitoring, accumulating
error counts at each level for performance monitoring purposes. The B2 errors are monitored to
detect signal fail and degrade threshold crossing alarms. As part of this process, the device
accumulates line REIs (M1) and may buffer and compare the 16 or 64-byte section trace (J0)
message against the expected message.
The device also interprets the received payload pointers (H1, H2), detects path alarm conditions,
and detects and accumulates path BIPs (B3). The path REIs are monitored and accumulated.
Also, the 16 or 64-byte path trace (J1) message is accumulated and compared against the
expected result. The device then extracts the SPE (VC). All transport and path overhead bytes are
extracted and serialized on lower rate interfaces, allowing additional external processing of
overhead, if desired.
The extracted SPE (VC) is placed on a Telecom Drop bus. Frequency offsets, for exampe, due to
plesiochronous network boundaries, or the loss of a primary reference timing source, and phase
differences, due to normal network operation, between the received data stream and the Drop bus
are accommodated by pointer adjustments in the Drop bus.
In the transmit direction, the SPECTRA-4x155 transmits SONET/SDH frames, via bit serial
interfaces, and formats section (regenerator section), line (multiplexer section), and path overhead
appropriately. The device provides transmit path origination for a SONET/SDH STS-3 (STM1/AU-3) or STS-3c (STM-1/AU-4) stream. It performs framing pattern insertion (A1, A2),
scrambling, alarm signal insertion, and creates section and line BIPs (B1, B2) as required to allow
performance monitoring at the far end. Line REIs (M1) and a 16 or 64-byte section trace (J0)
message may be optionally inserted. The device also generates the transmit payload pointers (H1,
H2) and creates and inserts the path BIP. A 16 or 64-byte path trace (J1) message and the path
status byte (G1) is optionally inserted.
In Addition to its basic processing of the transmit SONET/SDH overhead, the SPECTRA-4x155
provides convenient access to all overhead bytes, which are inserted serially on lower rate
interfaces, allowing additional external sourcing of overhead, if desired. The SPECTRA-4x155
also supports the insertion of a large variety of errors into the transmit stream, such as framing
pattern errors and BIP errors, which are useful for system diagnostics and tester applications.
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The inserted SPE (VC) is sourced from a TelecomBus Add stream. The SPECTRA-4x155 maps
the SPE (VC) from a Telecom Add bus into the transmit stream. As with the TelecomBus Drop
stream, frequency offsets and phase differences between the transmit data stream and the Add bus
are accommodated by pointer adjustments in the transmit stream.
The SPECTRA-4x155 supports Time-Slot Interchange (TSI) on the Telecom Add and Drop
buses. On the Drop side, the TSI views the receive stream as 12 independent time-division
multiplexed columns of data (12 constituent STS-1 (STM-0/AU-3) or equivalent streams or timeslots or columns). Any column can be connected to any time-slot on the Drop bus, independently
of the channel they originate from. Both column swapping and broadcast are supported. TSI is
independent of the underlying payload mapping formats. Similarly, on the Add side, data from the
Add bus is treated as 12 independent time-division multiplexed columns. Assignment of data
columns to transmit time-slots (STS-1 (STM-0/AU-3) or equivalent streams) is arbitrary.
The transmitter and receiver are independently configurable to allow for asymmetric interfaces.
Ring control ports are provide to pass control and status information between mate transceivers.
The SPECTRA-4x155 is configured, controlled and monitored via a generic 8-bit microprocessor
bus interface.
The SPECTRA-4x155 is implemented in low power, +3.3 Volt, CMOS technology. It has TTL
and pseudo ECL (PECL) compatible inputs and outputs and is packaged in a 520 pin SBGA
package.
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8 Pin Diagrams
The SPECTRA-4x155 is available in a 520 pin SBGA package having a body size of 40 mm by
40 mm and a ball pitch of 1.27 mm.
Figure 4 Pin diagram of SPECTRA-4x155 (Bottom Top right going clockwise)
The SPECTRA-4x155 is available in a 520 pin SBGA package having a body size of 40.0 mm by
40.0 mm and a ball pitch of 1.27 mm.
9.1 Serial Line side Interface Signals
Production
Pin NameTypePin
Function
No.
REFCLKInputB4The reference clock input (REFCLK) provides a jitter-free 19.44 MHz
reference clock. It is used as the reference clock by both clock
recovery and clock synthesis circuits.
All channels share this pin.
RXD1-RXD1+
RXD2RXD2+
RXD3RXD3+
RXD4RXD4+
SD1
SD2
SD3
SD4
TXD1TXD1+
TXD2TXD2+
TXD3TXD3+
TXD4TXD4+
TCLKOutputC6The transmit byte clock (TCLK) output provides a timing reference
Diff PECL
Input
SingleEnded
PECL Input
Diff. TTL
Output
(Externally
converted
to PECL
)
K3
K2
M2
M1
Y2
Y1
AB2
AB3
K4
M3
Y3
AB1
J2
J3
L2
L3
W3
W2
AA3
AA2
The receive differential data inputs (RXD[4:1]+, RXD[4:1]-) contain
the 155.52 Mbit/s receive STS-3/3c (STM-1/AU-3/AU-4) stream of
each channel. The receive clocks are recovered from the RXD+/- bit
stream.
RXD[4:1]+/- inputs are expected to be NRZ encoded.
The Signal Detect pin (SD[4:1]) indicates the presence of valid
receive signal power from the Optical Physical Medium Dependent
Device. A PECL high indicates the presence of valid data and a
PECL low indicates a Loss of Signal (LOS). It is mandatory that
SD[4:1] be terminated into the equivalent network that RXD1-4+/- is
terminated into.
This pin is available independently for each channel.
The transmit differential data outputs (TXD[4:1]+, TXD[4:1]-) contain
the 155.52 Mbit/s transmit STS-3/3c (STM-1/AU-3/AU-4) stream.
TXD[4:1]+/- outputs are NRZ encoded.
for the SPECTRA-4x155 self-timed channels. TCLK always provides
a divide-by-eight of the synthesized line rate clock and thus has a
nominal frequency of 19.44 MHz.
TCLK does not apply to internally loop-timed channels, in which case
the channel’s RCLK1-4 provides transmit timing information.
When not used, TCLK can be held low using the TCLKEN bit in the
SPECTRA-4x155 Clock Control register.
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PGMTCLKOutputE6The programmable transmit clock (PGMTCLK) signal provides timing
CP1
CN1
CP2
CN2
CP3
CN3
CP4
CN4
PECLVInputD2The PECL receiver input voltage (PECLV) pin configures the PECL
Output
Analog
C7
D7
B6
E7
G2
G3
N3
N2
U3
U2
AD2
AD3
The Receive Clock (RCLK1-4) signal provides a timing reference for
the SPECTRA-4x155 receive line interface outputs. The signal is
nominally 19.44 MHz. It is a divide-by-eight of the recovered clock.
When not used, RCLK1-4 can be held low using the RCLKEN bit in
the SPECTRA-4x155 Clock Control register.
The programmable receive clock (PGMRCLK) signal provides timing
reference for the receive line interface.
PGMRCLK is a divided version of one of the RCLK clocks. The
PGMRCHSEL bits of the Master Clock Control register are used to
select which of the four clocks is the source for PRGMRCLK. When
the PGMRCLKSEL bit of the Master Clock Control register is set low,
PGMRCLK is a nominal 19.44 MHz, 40-60% duty cycle clock. When
PGMRCLKSEL register bit is set to high, PGMRCLK is a nominal 8
KHz, 40-60% duty cycle clock.
PGMRCLK output can be disabled and held low by programming the
PGMRCLKEN bit in the Master Clock Control register.
reference for the transmit line interface.
PGMTCLK is a divided version of the TCLK clock. When the
PGMTCLKSEL register bit is set low, PGMTCLK is a nominal 19.44
MHz, 40-60% duty cycle clock. When the PGMTCLKSEL bit of the
Master Clock Control register is set high, PGMTCLK is a nominal 8
KHz, 40-60% duty cycle clock.
PGMTCLK output can be disabled and held low by programming the
PGMTCLKEN bit in the Master Clock Control register.
The analog CP1-4 and CN1-4 pins are provided for applications that
must meet SONET/SDH jitter transfer specifications. A 220 nF X7R
10% ceramic capacitor can be attached across each CP1-4 and
CN1-4 pair.
receiver level shifter. When PECLV is set to logic zero, the PECL
receivers are configured to operate with a 3.3V input voltage. When
PECLV is set to logic one, the PECL receivers are configured to
operate with a 5.0 V input voltage.
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The section alarm (SALM1-4) output may be set high when an OOF,
LOS, LOF, LAIS, LRDI, section trace identifier mismatch (RS-TIM),
section trace identifier unstable (RS-TIU), signal fail (SF) or signal
degrade (SD) alarm is detected. Each alarm indication can be
independently enabled using bits in the Section Alarm Output Control
#1 and #2 registers. SALM1-4 is set low when none of the enabled
alarms are active.
SALM1-4 is updated on the rising edge of RCLK1-4.
The Loss of Frame (LOF1-4) output is set high when an OOF
condition exists for a total OOF period of 3 ms during which there is
no continuous, in-frame period of 3 ms. LOF1-4 is cleared when an
in-frame condition exists for a continuous period of 3 ms
The LOF1-4 output is updated on the rising edge of RCLK1-4
Loss of Signal (LOS1-4) is active when the ring control port is
disabled. LOS1-4 is set high when a violating period (20 ± 2.5 µs) of
consecutive all zeros patterns is detected in the incoming stream.
LOS1-4 is set low when two valid framing words (A1, A2) are
detected, and during the intervening time (125 µs), there are no other
violating period with all zeros patterns is observed.
LOS1-4 is updated on the rising edge of RCLK1-4.
The Receive ring control port frame position (RRCPFP1-4) signal
identifies bit positions in the receive ring control port data
(RRCPDAT1-4) when the ring control port is enabled. RRCPFP1-4 is
set high during the filtered K1 and K2 bit positions, the change of
APS value bit position, the protection switch byte failure bit position,
and the send line AIS and send line RDI bit positions of the
RRCPDAT1-4 streams (21 bits). RRCPFP1–4 is set low during the
reserved L-REI clock cycles. RRCPFP1-4 can be connected directly
to the TRCPFP1-4 inputs of a mate SPECTRA-4x155 in ring-based
Add/Drop multiplexer applications.
The RCPEN bit in the Ring Control register of the corresponding
channel controls the enabling and disabling of the ring control port.
The RRCPFP1-4 signal is updated on the falling edge of
RRCPCLK1-4.
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The RDI (LRDI1-4) signal is active when the ring control port is
disabled. LRDI1-4 is set high when line RDI is detected in the
corresponding incoming stream. LRDI is declared when the 110
binary pattern is detected in bits 6, 7, and 8 of the K2 byte for three
or five consecutive frames. LRDI is removed when any pattern other
than 110 is detected in bits 6, 7, and 8 of the K2 byte for three or five
consecutive frames.
The LRDIDET bit in the RLOP Control and Status register of the
corresponding channel controls the selection of three or five
consecutive frames.
LRDI1-4 is updated on the rising edge of RCLK1-4.
The Receive ring control port clock (RRCPCLK1-4) signal provides
timing for the receive ring control port when the ring control port is
enabled. RRCPCLK1-4 is nominally a 3.24 MHz clock and can be
connected directly to the TRCPCLK1-4 inputs of a mate SPECTRA4x155 in ring-based Add-Drop multiplexer applications.
The RCPEN bit in the Ring Control register of the corresponding
channel controls the enabling and disabling of the ring control port.
The RRCPFP1-4 and RRCPDAT1-4 signals are updated on the
falling edge of RRCPCLK1-4.
The line alarm indication (LAIS1-4) signal is active when the ring
control port is disabled. LAIS1-4 is set high when line AIS is detected
in the corresponding incoming stream. Line AIS is declared when the
111 binary pattern is detected in bits 6, 7, and 8 of the K2 byte for
three or five consecutive frames. Line AIS is removed when any
pattern other than 111 is detected in bits 6, 7, and 8 of the K2 byte
for three or five consecutive frames.
The LAISDET bit in the RLOP Control and Status register of the
corresponding channel controls the selection of three or five
consecutive frames.
The LAIS1-4 outputs are updated on the rising edge of RCLK1-4.
The Receive ring control port data (RRCPDAT1-4) signal contains
the receive ring control port data stream when the ring control port is
enabled. The receive ring control port data consists of the filtered K1,
K2 byte values, the change of APS value bit position, the protection
switch byte failure status bit position, the send line AIS and send line
RDI bit positions, and the line REI bit positions. RRCPDAT1-4 can
be connected directly to the TRCPDAT1-4 inputs of a mate
SPECTRA-4x155 in ring-based Add-Drop multiplexer applications.
The RCPEN bit in the Ring Control register of the corresponding
channel controls the enabling and disabling of the ring control port.
The RRCPDAT1-4 signal is updated on the falling edge of
RRCPCLK1-4.
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The receive line AIS insertion (RLAIS1-4) signal controls the
insertion of line AIS in the received stream by the RSOP block, when
the ring control port is disabled. When one of the RLAIS1-4 pins is
set high, line AIS is inserted in the corresponding received stream.
When RLAIS1-4 is set low, line AIS may be optionally inserted
automatically upon detection of LOS, LOF, section trace alarms or
line AIS in the incoming stream.
The Receive LAIS Control register contains the register bits that
control the alarms that are inserted using the RLAIS pin of the
corresponding channel. RLAIS signals are internally retimed.
RLAIS1-4 must be asserted for a minimum period of one
SONET/SHD frame (125 us) to be detected by the SPECTRA-4x155.
Line AIS must be held for a minimum of three SONET/SDH frames
to be compliant to the SONET/SDH standards.
The Transmit ring control port clock (TRCPCLK1-4) signal provides
timing for the transmit ring control port when the ring control port is
enabled. The TRCPCLK1-4 signal is nominally a 3.24 MHz clock and
can be connected directly to the RRCPCLK output of a mate
SPECTRA-4x155 in ring-based Add/Drop multiplexer applications.
The RCPEN bit in the Ring Control register of the corresponding
channel controls the enabling and disabling of the ring control port.
The TRCPFP1-4 and TRCPDAT1-4 signals are sampled on the
rising edge of TRCPCLK1-4.
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The active high transmit RDI (TLRDI1-4) signal controls the insertion
of a remote defect indication in the transmit outgoing stream when
the ring control port is disabled. When TLRDI1-4 is set high, bits 6, 7,
and 8 of the K2 byte are set to the pattern 110. When TLRDI1-4 is
set low, line RDI may also be inserted using the LRDI bit in the TLOP
Control register of the corresponding channel. Line RDI may also be
inserted upon detection of LOS, LOF, or line AIS in the receive
stream, using the bits in the Transmit Line RDI Control register of the
corresponding channel. The TLRDI1-4 input takes precedence over
the TTOH1-4 and TTOHEN1-4 inputs. TLRDI signals are internally
retimed. TLRDI1-4 must be asserted for a minimum period of one
SONET/SHD frame (125 us) to be detected by the SPECTRA-4x155.
Line RDI must be held for a minimum of three SONET/SDH frames
to be compliant to the SONET/SDH standards.
The Transmit ring control port frame position (TRCPFP1-4) signal
identifies bit positions in the transmit ring control port data
(TRCPDAT1-4) when the ring control port is enabled. TRCPFP1-4 is
high during the send line AIS and the send line RDI bit positions in
the TRCPDAT1-4 stream. TRCPFP1-4 is set high for 19 bits
locations prior to those 2 bit locations. These 19 bit locations are
reserved. TRCPFP1–4 is set low during the reserved L-REI clock
cycles. TRCPFP1-4 can be connected directly to the RRCPFP1-4
output of a mate SPECTRA-4x155 in ring-based Add-Drop
multiplexer applications.
The RCPEN bit in the Ring Control register of the corresponding
channel controls the enabling and disabling of the ring control port.
The TRCPFP1-4 signal is sampled on the rising edge of TRCPCLK1-
4.
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The active high transmit AIS (TLAIS1-4) controls the insertion of line
AIS in the transmit outgoing stream when the ring control port is
disabled. When TLAIS1-4 is set high, the complete frame (except the
section overhead or line/regenerator section) is overwritten with the
all-ones pattern (before scrambling). The TLAIS1-4 input takes
precedence over the TTOH1-4 and TTOHEN1-4 inputs. TLAIS
signals are internally retimed.
TLAIS1-4 is required to be asserted for a minimum period of one
SONET/SHD frame (125 us) to be detected by the SPECTRA-4x155.
Line AIS must be held for a minimum of three SONET/SDH frames
to be compliant to the SONET/SDH standards.
The Transmit ring control port data (TRCPDAT1-4) signal contains
the transmit ring control port data stream when the ring control port is
enabled. The transmit ring control port data consists of the send line
AIS and the send line RDI bit positions, and the line REI bit positions.
TRCPDAT1-4 can be connected directly to the RRCPDAT1-4 output
of a mate SPECTRA-4x155 in ring-based Add/Drop multiplexer
applications. The K1/K2, COAPSI, PSBFI and PSBFV position of the
RRCPDAT lines are not used by the TRCPDAT.
The RCPEN bit in the Ring Control register of the corresponding
channel controls the enabling and disabling of the ring control port.
TRCPDAT1-4 is sampled on the rising edge of TRCPCLK1-4.
The receive transport overhead clock (RTOHCLK1-4) output is used
to update the received transport overhead outputs (RTOH1-4 and
RTOHFP1-4).
RTOHCLK1-4 is nominally a 5.184 MHz clock generated by gapping
a 6.48 MHz clock. RTOHCLK1-4 has a 33% high duty cycle.
The RTOHFP1-4 and RTOH1-4 outputs are updated on the falling
edge of RTOHCLK1-4.
The receive transport overhead (RTOH1-4) bit serial output signal
contains the received transport overhead bytes (A1, A2, J0, Z0, B1,
E1, F1, D1-D3, H1-H3, B2, K1, K2, D4-D12, Z1/S1, Z2/M1, and E2)
from the incoming stream.
The RTOH1-4 output is updated on the falling edge of RTOHCLK1-4
and should be sampled externally on the rising edge of RTOHCLK1-
4.
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RPOHCLKOutputA27The receive path overhead clock (RPOHCLK1-4) provides timing to
RPOHFPOutputC26The receive path overhead frame position signal (RPOHFP) may be
RPOHOutputE25The receive path overhead data signal (RPOH) contains the path
RPOHENOutputB26
Output
AH7
AG9
AJ10
AJ12
The receive transport overhead frame position (RTOHFP1-4) signal
is used to locate the most significant bit (MSB) on the RTOH1-4
serial stream.
RTOHFP1-4 is set high when bit 1 (the most significant bit) of the
first framing byte (A1) is present in the RTOH1-4 stream.
RTOHFP1-4 can also be sampled on the rising edge of RSLDCLK14 to locate the MSB of the RSLD1-4 serial output stream. The
generation of this clock is aligned with the generation of RTOHFP1-
4.
RTOHFP1-4 is updated on the falling edge of RTOHCLK1-4.
process the B3E signal, receive alarm port (RAD), path Z5 growth
byte (tandem path incoming error count and data link), and to sample
the extracted path overhead of the four STS-3/3c (STM-1/AU-3/AU-
4) streams. RPOHCLK is a nominally 12.96 MHz, 50% duty cycle
clock.
RTCEN and RTCOH are sampled on the rising edge of the
RPOHCLK signal.
B3E, RAD, RALM, RPOH, RPOHEN and RPOHFP are updated on
the falling edge of the RPOHCLK signal.
used to locate the individual path overhead bits in the path overhead
data stream (RPOH). RPOHFP signal is logic one when bit 1 (the
most significant bit) of the path trace byte (J1) of channel one’s first
STS-1 (STM-0/AU-3) or STS-3c (STM-1/AU-4) is present in the
RPOH stream.
RPOHFP may also be used to locate the BIP error count and path
RDI indication bits on the receive alarm port data signal (RAD).
RPOHFP is logic one when the first of eight BIP error positions of
channel one’s first STS-1 (STM-0/AU-3) or STS-3c (STM-1/AU-4)
stream is present on the receive alarm data signal (RAD).
RPOHFP is also used to help find the alignment of the B3E output
and RTCEN/RTCOH inputs.
RPOHFP signal is updated on the falling edge of the RPOHCLK
signal.
overhead bytes (J1, B3, C2, G1, F2, H4, Z3, Z4, and Z5) extracted
from the path overhead of the three STS-1 (STM-0/AU-3) streams or
STS-3c (STM-1/AU-4) streams in all four channels. The
corresponding RPOHEN signal is set high to identify the valid
overhead bytes that are presented.
RPOH is updated on the falling edge of RPOHCLK.
The receive path overhead enable signal (RPOHEN) indicates the
validity of the path overhead bytes extracted to the RPOH from the
path overhead of the three STS-1 (STM-0/AU-3) streams or STS-3c
(STM-1/AU-4) streams in all four channels. When RPOHEN signal is
set high, the corresponding path overhead byte presented on the
RPOH is valid. When RPOHEN is set low, the corresponding path
overhead byte presented on the RPOH is invalid. RPOHEN also
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RADOutputThe receive alarm port data signal (RAD) contains the path BIP error
count and the path remote alarm indication status of the three STS-1
(STM-0/AU-3) streams or STS-3c (STM-1/AU-4) streams for all four
channels. In Addition, the RAD contains the transmit K1 and K2
bytes of the four transmit streams when not generating AIS-L on the
transmit stream.
RPOHFP is used to determine the alignment of the RAD output.
RAD is updated on the falling edge of RPOHCLK.
B3EOutputC21The bit interleaved parity error signal (B3E) carries the path BIP-8
error detected for each STS-1 (STM-0/AU-3) and STS-3c (STM1/AU-4) in the receive stream. It is set high for one RPOHCLK period
for each path BIP-8 error detected (up to eight per frame) or when
errors are treated on a block basis, is set high for only one
RPOHCLK period if any of the path BIP-8 bits are in error. Path BIP8 errors are detected by comparing the extracted path BIP-8 byte
(B3) with the computed BIP-8 for the previous frame.
The B3E signal toggles during the B3 time periods on RPOH and is
valid only during RPOHEN set high. RPOHFP is used to determine
the alignment of the B3E output.
B3E is updated on the falling edge of RPOHCLK.
RTCENInputD24The receive tandem connection overhead insert enable signal
(RTCEN) controls the insertion of incoming error count and data link
into the tandem connection maintenance byte (Z5) on the Drop bus,
on a bit-by-bit basis for each STS-1 (STM-0/AU3) or STS-3c
(STM-1/AU4) stream. When RTCEN is set high, the data on the
corresponding RTCOH stream is inserted into the associated bit in
the Z5 byte. RTCEN has significance only during the J1 byte
positions in the RPOHCLK clock sequence where RPOHEN is also
set high and is ignored at all other times. Setting low the RTC_EN
control bit in the RPOP Z5 Growth Control Register disables the
RTCEN and RTCOH ports completely.
RTCEN is sampled on the rising edge of RPOHCLK.
RTCOHInputC24The receive tandem connection overhead data signal (RTCOH)
contains the incoming error count and data link message to be
inserted into the tandem connection maintenance byte (Z5) in each
STS-1 (STM-0/AU-3) or STS-3c (STM-1/AU-4) stream. When
RTCEN is set high and RPOHEN is high, the values sampled on
RTCOH are inserted into the Z5 byte of the corresponding stream on
the Drop bus. When RTCEN is set low, the received Z5 byte is
passed through unmodified. Setting low the RTC_EN control bit in
the RPOP Z5 Growth Control Register disables the RTCEN and
RTCOH ports completely.
RTCOH is sampled on the rising edge of RPOHCLK.
RALMOutputB21
The Receive Alarm (RALM) signal is a multiplexed output of
individual alarms of the receive STS-1 (STM-0/AU3) or STS-3c
(STM-1/AU4) streams. Each alarm represents the logical OR of the
LOP, PAIS, PRDI, PERDI, LOM, LOPCON, PAISCON, UNEQ,
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PSLU, PSLM, TIU-P, TIM-P status of the corresponding stream. In
Addition to these alarms, the LOS (LOS), LOF (LOF) or line AIS
(LAIS) in the corresponding STS-3 (STM-1) SONET/SDH streams
can also be reported on RALM. The RPPS RALM Output Control #1
and #2 registers control the selection of alarms to be reported.
RALM is updated on the falling edge of RPOHCLK and may
transition anywhere during the individual STS-1 time slot period.
The loss of pointer signal (LOP) indicates the loss of pointer state in
the corresponding STS-1 (STM-0/AU-3) or STS-3c (STM-1/AU-4)
SONET/SDH stream. LOP is set high when invalid pointers are
received in eight consecutive frames, or if eight consecutive enabled
NDFs are detected in the stream.
The path alarm indication signal (PAIS) indicates the path AIS state
of the corresponding STS-1 (STM-0/AU3) or STS-3c (STM-1/AU4)
SONET/SDH stream. PAIS is set high when an all-ones pattern is
observed in the pointer bytes (H1 and H2) for three consecutive
frames in the stream.
The path remote defect indication signal (PRDI) indicates the path
remote state of the corresponding STS-1 (STM-0/AU-3) or STS-3c
(STM-1/AU-4) SONET/SDH stream. PRDI is set high when the path
RDI alarm bit (bit 5) of the path status (G1) byte is set high for five or
ten consecutive frames. The RDI10 bit in the RPOP Pointer MSB
register controls whether five or ten consecutive frames will cause a
PRDI indication.
The path enhanced remote defect indication signal (PERDI)
indicates the path enhanced remote state of the corresponding STS1 (STM-0/AU-3) or STS-3c (STM-1/AU-4) SONET/SDH stream.
PERDI is set high when the path ERDI alarm code (bits 5,6,7) of the
path status (G1) byte is set to the same alarm codepoint for five or
ten consecutive frames. The RDI10 bit in the RPOP Pointer MSB
register controls whether five or ten consecutive frames will cause a
PRDI indication.
The loss of multiframe signal (LOM) indicates the tributary multiframe
synchronization status of the corresponding STS-1 (STM-0/AU3) or
STS-3c (STM-1/AU-4) SONET/SDH stream. LOM is set high if a
correct four frame sequence is not detected in eight frames.
The loss of pointer concatenation and path AIS concatenation
signals (LOPCON and PAISCON) are the concatenated alarms for
STS-3c (STM-1/AU-4) SONET/SDH streams.
The receive path unequipped status (UNEQ) indicates the
unequipped status of the path signal label of the corresponding STS1 (STM-0/AU-3) or STS-3c (STM-1/AU-4) SONET/SDH stream.
UNEQ is set high when the filtered path signal label indicates
unequipped and is dependent on the selected UNEQ mode.
The receive path signal label unstable status (PSLU) reports the
stable/unstable status (mode 1) of the path signal label in the
corresponding STS-1 (STM-0/AU-3) or STS-3c (STM-1/AU-4)
SONET/SDH stream. PSLU is set high when the current received C2
byte differs from the previous C2 byte for five consecutive frames.
The receive path signal label mismatch (PSLM) status reports the
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match/mismatch status (mode 1 and mode 2) for the path signal
label of the corresponding STS-1 (STM-0/AU-3) or STS-3c (STM1/AU-4) SONET/SDH stream. In mode 1, PSLM is set high when the
accepted PSL differs from the expected PSL written by the
microprocessor. In mode 2, PSLM is set high when 5 consecutive
mismatches have been declared
The receive path trace identifier unstable status (TIU-P) reports the
stable/unstable status (mode 1 and mode 2) of the path trace
identifier framer of the corresponding STS-1 (STM-0/AU-3) or STS3c (STM-1/AU-4) SONET/SDH stream. In mode 1, TIU is set high
when the current message differs from its immediate predecessor for
eight consecutive frames. In mode 2, TIU is set high when three
consecutive 16-byte windows of trace bytes are detected to have
errors. TIU2 is set low when the same trace byte is received in
forty-eight consecutive SONET/SDH frames.
The receive path trace identifier mismatch (TIM-P) status reports the
match/mismatch status (mode 1) of the path identifier message
framer of the corresponding STS-1 (STM-0/AU-3) or STS-3c (STM1/AU-4) SONET/SDH stream. TIM-P is set high when the accepted
identifier message differs from the expected message written by the
microprocessor.
Please refer to the individual alarm interrupt descriptions and
Functional Description Section for more details on each alarm.
The transmit transport overhead clock (TTOHCLK1-4) is used to
clock in the transport overhead (TTOH1-4) to be transmitted along
with the overhead enable (TTOHEN1-4).
TTOHCLK1-4 is nominally a 5.184 MHz clock generated by gapping
a 6.48 MHz clock. TTOHCLK1-4 has a 33% high duty cycle.
TTOHFP1-4 and TTOH1-4.are updated on the falling edge of
TTOHCLK1-4.
The transmit transport overhead (TTOH1-4) bit serial input signal
contains the transport overhead bytes (A1, A2, J0, Z0, B1, E1, F1,
D1-D3, H1-H3, B2, K1, K2, D4-D12, Z1/S1, Z2/M1, and E2) to be
transmitted and errors masks to be applied on the B1, B2, H1 and
H2 transmitted bytes. Insertion of the bytes must be accompanied
by a high TTOHEN1-4 signal.
TTOH1-4 is sampled on the rising edge of TTOHCLK1-4.
The transmit transport overhead insert enable (TTOHEN1-4) signal
controls the source of the transport overhead data which is inserted
in the outgoing stream. When TTOHEN1-4 is high during bit 1 (most
significant bit) of a TOH byte on TTOH, the sampled TOH byte is
inserted into the corresponding transport overhead byte positions
(A1, A2, J0, Z0, E1, F1, D1-D3, H3, K1, K2, D4-D12, Z1/S1, Z2/M1,
and E2 bytes). While TTOHEN1-4 is low during the most significant
bit of a TOH byte on TTOH, that sampled byte is ignored and the
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default values are inserted into these transport overhead bytes. The
overhead byte enabled by the TTOHEN input takes precedence
over the TSLD input.
When TTOHEN1-4 is high during the most significant bit of the H1,
H2, B1 or B2 TOH byte positions on TTOH1-4, the sampled TOH
byte is logically XOR’ed with the associated incoming byte to force
bit errors on the outgoing byte. A logic low bit in the TTOH1-4 byte
allows the incoming bit to go through while a bit set to logic high will
toggle the incoming bit. A low level on TTOHEN1-4 during the MSB
of the TOH byte disables the error forcing for the entire byte.
When the transmit trace enable (TREN) bit in the TTOC Transport
Overhead Byte Control register of the corresponding channel is a
logic one, the J0 byte contents are sourced from the section trace
buffer, regardless of the state of TTOHEN1-4.
TTOHEN1-4 is sampled on the rising edge of TTOHCLK1-4.
TTOHFP1
TTOHFP2
TTOHFP3
TTOHFP4
TADInputA24
TAFPInputB24The transmit alarm port frame pulse signal (TAFP) marks the first bit
TACKInputE23The transmit alarm port clock (TACK) provides timing for transmit
OutputAL7
AK9
AJ11
AH13
The transmit transport overhead frame position (TTOHFP1-4) signal
is used to locate the most significant bit (MSB) on the TTOH1-4
serial stream.
TTOHFP1-4 is set high when bit 1 (the most significant bit) of the
first framing byte (A1) should be present on the TTOH1-4 stream.
TTOHFP1-4 can be sampled on the rising edges of TSLDCLK1-4 to
locate the MSB of the TSLD serial input stream. The generation of
this clock is aligned with the generation of TTOHFP1-4.
TTOHFP1-4 is updated on the falling edge of TTOHCLK1-4.
The transmit alarm port data signal (TAD) contains the path REI
count and the path RDI status to be inserted into the four STS-3/3c
(STM-1/AU-3/AU-4) streams. In Addition, the TAD input contains
the K1 and K2 bytes from a mate SPECTRA-4x155 to be inserted
into the four channels transport overhead. TAD takes precedence
over TTOHEN1-4 when enabled.
The RXSEL[1:0] bits in the TPPS Path Configuration register control
the source of the transmit P-REI and P-RDI.
TAD is sampled on the rising edge of TACK.
of the transmit alarm message in each SONET/SDH frame. TAFP is
pulsed high to mark the first path REI bit location of channel one’s
first STS-1 (STM-0/AU-3) stream or the first path REI bit location of
the STS-3c (STM-1/AU-4) stream.
TAFP is sampled on the rising edge of TACK.
alarm port. TACK is nominally a 12.96 MHz, 50% duty cycle clock.
Inputs TAD and TAFP are sampled on the rising edge of TACK.
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The receive section or line data communication channel (DCC) clock
(RSLDCLK1-4) is used to update the received section or line DCC
(RSLD1–4).
When selecting to clock the section DCC, RSLDCLK1-4 is a 192 kHz
clock with nominal 50% duty cycle. When selecting to clock the line
DCC, RSLDCLK1-4 is a 576 kHz clock with nominal 50% duty cycle.
RTOHFP1-4 may be sampled high at the same time as bit 1 (MSB)
on RSLD1-4.
The RTOC Overhead Control register of the corresponding channel
contains the RSLDSEL register bit used to select the section or line
DCC. The same register also contains the RSLD_TS register bit that
can be used to tri-state RSLDCLK1-4 and RSLD1-4 outputs.
In both cases, RSLD1-4 is updated on the falling edge of
RSLDCLK1-4.
The receive section or line DCC (RSLD1-4) bit serial output signal
contains the received section data communication channel (D1-D3)
or the line data communication channel (D4-D12).
The RTOC Overhead Control register of the corresponding channel
contains the RSLDSEL register bit used to select the section or line
DCC. The same register also contains the RSLD_TS register bit that
can be used to tri-state RSLDCLK1-4 and RSLD1-4 outputs.
RSLD1-4 is updated on the falling edge of RSLDCLK1-4 and should
be sampled externally on the rising edge of RSLDCLK1-4.
9.6 Transmit Section/Line DCC Insertion Signals
Pin NameTypePin
No.
TSLDCLK1
TSLDCLK2
TSLDCLK3
TSLDCLK4
TSLD1
TSLD2
TSLD3
TSLD4
Tristate
Output
InputAK14
AJ14
AJ15
AJ17
AJ18
AK15
AH17
AH18
Function
The transmit section or line data communication channel (DCC)
clock (TSLDCLK1-4) is used to clock in the transmit section or line
DCC (TSLD1-4).
When clocking the section DCC, TSLDCLK1-4 is a 192 kHz clock
with nominal 50% duty cycle. When clocking the line DCC,
TSLDCLK1-4 is a 576 kHz clock with nominal 50% duty cycle.
TTOHFP1-4 is used to identify when bit 1 (MSB) of the first A1 byte
should be present on TSLD1-4.
The TTOC Overhead Control register of the corresponding channel
contains the TSLD_SEL register bit used to select the section or
line DCC. The same register also contains the TSLD_TS register bit
that can be used to tri-state the TSLDCLK1-4 output.
In both cases, TSLD1-4 is sampled on the rising edge of
TSLDCLK1-4.
The transmit section or line DCC (TSLD) bit serial input signal
contains the section data communication channel (D1-D3) or the
line data communication channel (D4-D12) to be transmitted.
TTOHFP1-4 is used to identify the required alignment of TSLD.
The TTOH1-4 and TTOHEN1-4 inputs take precedence over
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The TTOC Overhead Control register of the corresponding channel
contains the TSLD_SEL register bit used to select the section or
line DCC. The same register also contains the TSLD_VAL register
bit used to specify a value for the DCC not inserted via TSLD.
TSLD1-4 is sampled on the rising edge of TSLDCLK1-4.
9.7 Transmit Path AIS Insertion Signals
Pin NamePin TypePin
No.
DPAISCKInputD27The Drop bus path alarm indication clock signal (DPAISCK) provides
DPAISFPInputB28
DPAISInputC27The active high Drop bus path alarm indication signal (DPAIS) is a
TPAISCKInputE26The Transmit path alarm indication clock signal (TPAISCK) provides
Function
timing for system Drop path alarm indication signal (DPAIS).
DPAISCK is a clock of arbitrary phase and frequency within the limits
specified in the A.C. Timing section of this document.
Inputs DPAIS and DPAISFP are sampled on the rising edge of
DPAISCK.
The active high Drop bus path alarm indication frame pulse signal
(DPAISFP) is used to identify the alignment of the DPAIS signal.
DPAISFP is set high to mark the path request of channel one’s the
first Drop bus STS-1 (STM-0/AU-3) stream or STS-3c (STM-1/AU-4)
stream. In the absence of a frame pulse, the device will maintain the
last alignment and wrap around on its own.
DPAISFP is sampled on the rising edge of DPAISCK.
timeslot multiplexed signal that controls the insertion of path alarm
indication signal (PAIS) on the Drop bus (DD[31:24], DD[23:16],
DD[15:8], DD[7:0]) on a per STS-1/STM-1(AU3) or STS3c/STM1(AU4)basis.
A high level on DPAIS during a specific timeslot forces the insertion
of the all-ones pattern into the corresponding SPE and the payload
pointer bytes (H1, H2, and H3) presented on the Drop bus. A high
during the first time slot of a channel carrying an STS-3c/STM1(AU4) stream will force the entire concatenated SPE to all-ones. A
high during the second or third time slot of a channel carrying an
STS-3c/STM-1(AU4) will have no effect.
Path AIS can also be inserted by setting the IPAIS control bit in the
RTAL Control register or in response to receive alarms by the RPPS
Path AIS Control #1 and #2 registers.
DPAIS may be enabled or disabled on a per slice basis via the
DPAIS_EN bit in the RPPS Path AIS Control register #1.
DPAIS is sampled on the rising edge of DPAISCK.
timing for system Add side path alarm indication signal (PAIS)
assertion.
TPAISCK is a clock of arbitrary phase and frequency within the limits
specified in the A.C. Timing section of this document.
Inputs TPAIS and TPAISFP are sampled on the rising edge of
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TPAISInputD26The active high Transmit path alarm indication signal (TPAIS) is a
The active high Transmit path alarm indication frame pulse signal
(TPAISFP) is used to identify the alignment of the TPAIS signal.
TPAISFP is set high to mark the path request of channel one’s the
first transmit STS-1 (STM-0/AU-3) stream or STS-3c (STM-1/AU-4)
stream. In the absence of a frame pulse, the device will maintain the
last alignment and wrap around on its own.
TPAISFP is sampled on the rising edge of TPAISCK.
timeslot multiplexed signal that controls the insertion of path in the
transmit stream on a per STS-1/STM-1(AU3) or STS-3c/STM1(AU4)
basis.
A high level on TPAIS during a specific timeslot forces the insertion
of the all-ones pattern into the corresponding SPE and the payload
pointer bytes (H1, H2, and H3). A high during the first time slot of a
channel carrying an STS-3c/STM-1(AU4) stream will force the entire
concatenated SPE to all-ones. A high during the second or third time
slot of a channel carrying an STS-3c/STM-1(AU4) will have no effect.
Path AIS can also be inserted by setting the PAIS control bit in the
TTAL Control register or in response to Add Bus alarms by the TPPS
Path AIS Control register.
TPAIS may be enabled or disabled on a per slice basis via the
TPAIS_EN bit in the TPPS Path AIS Control register.
TPAIS is sampled on the rising edge of TPAISCK.
9.8 Drop Bus Telecom Interface Signals
Pin NamePin Type
Pin
No.
DCKInputAH30The Drop bus clock (DCK) provides timing for the Drop bus
DFPInputAG29The active high Drop bus reference frame position signal (DFP)
Function
interface. DCK is nominally a 77.76 MHz, 50% duty cycle clock
when the Drop interface is configured as a single bus interface.
DCK is nominally a 19.44 MHz, 50% duty cycle clock when the Drop
interface is configured as a quad STS-3 (STM-1) interface.
Frequency offsets between line side clock (or divided by 4 version
of) and DCK are accommodated by pointer justification events on
the Drop bus.
DFP is sampled on the rising edge of DCK.
Outputs DPL[4:1], DC1J1V1[4:1], DDP[4:1] and DD[31:0] are
updated on the rising edge of DCK when used.
indicates when the first byte of the synchronous payload envelope
(SPE byte #1) is available on the DD[7:0], DD[15:8], DD[23:16] and
DD[31:24] buses. For the single bus interface the first SPE byte of
channel one STS-1 #1 is identified. For the quad bus STS-3 (STM-
1) interface the first SPE byte of all channels STS-1 #1 on the four
output buses identified. Note that DFP has a fixed relationship to the
SONET/SDH frame; the start of payload is determined by the STS
(AU) pointer and may change relative to DFP. Forced changes of
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the Drop bus frame alignment by displacing of the regular DFP
pulse will cause errors and will force the need to resynchronize or
regenerate the RPPS PRBS monitors and generators.
The SPECTRA-4x155 will flywheel in the absence of a DFP pulse.
DFP is sampled on the rising edge of DCK.
In single Drop bus interface mode, the Drop bus data (DD[7:0])
contains the multiplexed STS-3/3c(STM-1/AU-3/AU-4) received
SONET/SDH payload data of all four channels. In quad Drop bus
interface STS-3(STM-1) mode, the Drop bus data (DD[7:0]) contains
the channel one STS-3/3c (STM-1/AU-3/AU-4) received
SONET/SDH payload data. When the Drop bus TSI functionality is
disabled, the Dropped payload multiplexing corresponds to the
SONET/SDH data received on channel #1. TSI may be used to
reorder this multiplexing on the Drop bus. STS-1/STM-1(AU3)’s
within a channel or between channels, along with entire channels
may be swapped. The transport overhead bytes, with the exception
of the H1, H2 pointer bytes and when there are no negative pointer
justifications the H3, are set to zeros. The fixed framing patterns for
the A1 and A2 framing bytes may be inserted. The GEN_A1A2_EN
bit in the DPGM Generator Control #1 register enables insertion of
the A1 and A2 framing bytes. The fixed stuff columns in a tributary
mapped SPE (VC) may also be optionally set to zero or NPI. The
H4BYP and CLRFS bits in the RTAL Control register control the
insertion of the H4 byte and the value of the fixed stuff columns.
DD[7] is the most significant bit (corresponding to bit 1 of each serial
word, the first bit received). DD[0] is the least significant bit
(corresponding to bit 8 of each serial word, the last bit received).
DD[7:0] is updated on the rising edge of DCK. The Drop interface
mode is set via the DTMODE register bit in the Drop Bus
Configuration register.
In single Drop bus interface mode, the Drop bus data (DD[15:8]) is
forced low. In quad Drop bus interface STS-3(STM-1) mode, the
Drop bus data (DD[15:8]) contains the channel two STS-3/3c (STM1/AU-3/AU-4) received SONET/SDH payload data. When the Drop
bus TSI functionality is disabled, the Dropped payload corresponds
to the SONET/SDH data received on channel #2. TSI may be used
to reorder this multiplexing on the Drop bus. STS-1/STM-1(AU3)’s
within a channel or between channels, along with entire channels
may be swapped. The transport overhead bytes, with the exception
of the H1, H2 pointer bytes and when there are no negative pointer
justifications the H3, are set to zeros. The fixed framing patterns for
the A1 and A2 framing bytes may be inserted. The GEN_A1A2_EN
bit in the DPGM Generator Control #1 register enables insertion of
the A1 and A2 framing bytes. The fixed stuff columns in a tributary
mapped SPE (VC) may also be optionally set to zero or NPI. The
H4BYP and CLRFS bits in the RTAL Control register control the
insertion of the H4 byte and the value of the fixed stuff columns.
DD[15] is the most significant bit (corresponding to bit 1 of each
serial word, the first bit received). DD[8] is the least significant bit
(corresponding to bit 8 of each serial word, the last bit received).
DD[15:8] is updated on the rising edge of DCK. The Drop interface
mode is set via the DTMODE register bit in the Drop Bus
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DPL[1]OutputH31The active high Drop bus payload active signal #1 (DPL[1])
Output
OutputAE31
W27
Y31
Y30
Y29
Y28
Y27
AA30
AA29
AE30
AE29
AE28
AE27
AF30
AF29
AG31
In single Drop bus interface mode, the Drop bus data (DD[23:16]) is
forced low. In quad bus interface STS-3(STM-1) mode, the Drop
bus data (DD[15:8]) contains the channel three STS-3/3c (STM1/AU-3/AU-4) received SONET/SDH payload data. When the Drop
bus TSI functionality is disabled, the Dropped payload corresponds
to the SONET/SDH data received on channel #3. TSI may be used
to reorder this multiplexing on the Drop bus. STS-1/STM-1(AU3)’s
within a channel or between channels, along with entire channels
may be swapped. The transport overhead bytes, with the exception
of the H1, H2 pointer bytes and when there are no negative pointer
justifications the H3, are set to zeros. The fixed framing patterns for
the A1 and A2 framing bytes may be inserted. The GEN_A1A2_EN
bit in the DPGM Generator Control #1 register enables insertion of
the A1 and A2 framing bytes. The H4 byte may also be inserted.
The fixed stuff columns in a tributary mapped SPE (VC) may also be
optionally set to zero or NPI. The H4BYP and CLRFS bits in the
RTAL Control register control the insertion of the H4 byte and the
value of the fixed stuff columns. DD[23] is the most significant bit
(corresponding to bit 1 of each serial word, the first bit received).
DD[16] is the least significant bit (corresponding to bit 8 of each
serial word, the last bit received).
DD[23:16] is updated on the rising edge of DCK. The Drop interface
mode is set via the DTMODE register bit in the Drop Bus
Configuration register.
In single Drop bus interface mode, the Drop bus data (DD[31:24]) is
forced low. In quad bus interface STS-3(STM-1) mode, the Drop
bus data (DD[31:24]) contains the channel four STS-3/3c (STM1/AU-3/AU-4) received SONET/SDH payload data. When the Drop
bus TSI functionality is disabled, the Dropped payload corresponds
to SONET/SDH data received on channel #4. TSI may be used to
reorder this multiplexing on the Drop bus. STS-1/STM-1(AU3)’s
within a channel or between channels, along with entire channels
may be swapped. The transport overhead bytes, with the exception
of the H1, H2 pointer bytes and when there are no negative pointer
justifications the H3, are set to zeros. The fixed framing patterns for
the A1 and A2 framing bytes may be inserted. The GEN_A1A2_EN
bit in the DPGM Generator Control #1 register enables insertion of
the A1 and A2 framing bytes. The H4 byte may also be inserted.
The fixed stuff columns in a tributary mapped SPE (VC) may also be
optionally set to zero or NPI. The H4BYP and CLRFS bits in the
RTAL Control register control the insertion of the H4 byte and the
value of the fixed stuff columns. DD[31] is the most significant bit
(corresponding to bit 1 of each serial word, the first bit received).
DD[24] is the least significant bit (corresponding to bit 8 of each
serial word, the last bit received).
DD[31:24] is updated on the rising edge of DCK. The Drop interface
mode is set via the DTMODE register bit in the Drop Bus
Configuration register.
indicates when the DD[7:0] is carrying a payload byte. It is set high
during path overhead and payload bytes and low during transport
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Document ID: PMC-1990822, Issue 4
overhead bytes. DPL[1] is set high during the H3 byte to indicate a
negative pointer justification event and set low during the byte
following H3 to indicate a positive pointer justification event.
DPL[1] is updated on the rising edge of DCK. The Drop interface
mode is set via the DTMODE register bit in the Drop Bus
Configuration register.
DPL[2]OutputN31The active high Drop bus payload active signal #2 (DPL[2])
indicates when the DD[15:8] is carrying a payload byte. It is set high
during path overhead and payload bytes and low during transport
overhead bytes. DPL[2] is set high during the H3 byte to indicate a
negative pointer justification event and set low during the byte
following H3 to indicate a positive pointer justification event.
DPL[2] is updated on the rising edge of DCK. This output is forced
low in single Drop bus mode. The Drop interface mode is set via the
DTMODE register bits in the Drop Bus Configuration register.
DPL[3]OutputW29The active high Drop bus payload active signal #3 (DPL[3])
indicates when the DD[23:16] is carrying a payload byte. It is set
high during path overhead and payload bytes and low during
transport overhead bytes. DPL[3] is set high during the H3 byte to
indicate a negative pointer justification event and set low during the
byte following H3 to indicate a positive pointer justification event.
DPL[3] is updated on the rising edge of DCK. This output is forced
low in single Drop bus mode. The Drop interface mode is set via the
DTMODE register bit in the Drop Bus Configuration register.
DPL[4]OutputAD28The active high Drop bus payload active signal #4 (DPL[4])
indicates when the DD[31:24] is carrying a payload byte. It is set
high during path overhead and payload bytes and low during
transport overhead bytes. DPL[4] is set high during the H3 byte to
indicate a negative pointer justification event and set low during the
byte following H3 to indicate a positive pointer justification event.
DPL[4] is updated on the rising edge of DCK. This output is forced
low in single Drop bus mode. The Drop interface mode is set via the
DTMODE register bit in the Drop Bus Configuration register.
DC1J1V1[1]OutputH30The Drop bus composite timing signal #1 (DC1J1V1[1]) indicates
the frame, payload and tributary multiframe boundaries on the Drop
data bus signals DD[7:0]. DC1J1V1[1] pulses high with the Drop bus
payload active signal (DPL[1]) set low to mark the first STS-1 (STM0/AU-3) Identification byte or equivalently the STM identification
byte (C1). DC1J1V1[1] pulses high with DPL[1] set high to mark the
path trace byte (J1). Optionally, the DC1J1V1[1] signal pulses high
on the V1 byte to indicate tributary multiframe boundaries using the
DISDV1 bit in the SPECTRA-4x155 RPPS Path Configuration
register. The Drop interface mode is set via the DTMODE register
bit in the Drop Bus Configuration register.
DC1J1V1[1] is updated on the rising edge of DCK.
DC1J1V1[2]OutputN30The Drop bus composite timing signal #2 (DC1J1V1[2]) indicates
the frame, payload and tributary multiframe boundaries on the Drop
data bus signals DD[15:8]. DC1J1V1[2] pulses high with the Drop
bus payload active signal (DPL[2]) set low to mark the first STS-1
(STM-0/AU-3) Identification byte or equivalently the STM
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identification byte (C1). DC1J1V1[2] pulses high with DPL[2] set
high to mark the path trace byte (J1). Optionally, the DC1J1V1[2]
signal pulses high on the V1 byte to indicate tributary multiframe
boundaries using the DISDV1 bit in the SPECTRA-4x155 RPPS
Path Configuration register. This output is forced low in single Drop
bus mode. The Drop interface mode is set via the DTMODE register
bit in the Drop Bus Configuration register.
DC1J1V1[2] is updated on the rising edge of DCK.
DC1J1V1[3]OutputW28
DC1J1V1[4]OutputAD27
DDP[1]OutputK31
DDP[2]OutputR28The Drop bus data parity signal #2 (DDP[2]) indicates the parity of
The Drop bus composite timing signal #3 (DC1J1V1[3]) indicates
the frame, payload and tributary multiframe boundaries on the Drop
data bus signals DD[23:16]. DC1J1V1[3] pulses high with the Drop
bus payload active signal (DPL[3]) set low to mark the first STS-1
(STM-0/AU-3) Identification byte or equivalently the STM
identification byte (C1). DC1J1V1[3] pulses high with DPL[3] set
high to mark the path trace byte (J1). Optionally, the DC1J1V1[3]
signal pulses high on the V1 byte to indicate tributary multiframe
boundaries using the DISDV1 bit in the SPECTRA-4x155 RPPS
Path Configuration register. This output is forced low in single Drop
bus mode. The Drop interface mode is set via the DTMODE register
bit in the Drop Bus Configuration register.
DC1J1V1[3] is updated on the rising edge of DCK.
The Drop bus composite timing signal #4 (DC1J1V1[4]) indicates
the frame, payload and tributary multiframe boundaries on the Drop
data bus signals DD[31:24]. DC1J1V1[4] pulses high with the Drop
bus payload active signal (DPL[4]) set low to mark the first STS-1
(STM-0/AU-3) Identification byte or equivalently the STM
identification byte (C1). DC1J1V1[4] pulses high with DPL[4] set
high to mark the path trace byte (J1). Optionally, the DC1J1V1[4]
signal pulses high on the V1 byte to indicate tributary multiframe
boundaries using the DISDV1 bit in the SPECTRA-4x155 RPPS
Path Configuration register. This output is forced low in single Drop
bus mode. The Drop interface mode is set via the DTMODE register
bit in the Drop Bus Configuration register.
DC1J1V1[4] is updated on the rising edge of DCK.
The Drop bus data parity signal #1 (DDP[1]) indicates the parity of
the Drop bus signals. The Drop data bus signals (DD[7:0]) are
always included in parity calculations. Register bits in the Drop Bus
Configuration register control the inclusion of the DPL[1] and
DC1J1V1[1] signals in parity calculation and the sense (odd/even)
of the parity. The Drop interface mode is set via the DTMODE
register bit in the Drop Bus Configuration register.
DDP[1] is updated on the rising edge of DCK.
the Drop bus signals. The Drop data bus signals (DD[15:8]) are
always included in parity calculations. Register bits in the Drop Bus
Configuration register control the inclusion of the DPL[2] and
DC1J1V1[2] signals in parity calculation and the sense (odd/even)
of the parity. This output is forced low in single Drop bus mode. The
Drop interface mode is set via the DTMODE register bit in the Drop
Bus Configuration register.
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DDP[3]OutputAA28The Drop bus data parity signal #3 (DDP[3]) indicates the parity of
the Drop bus signals. The Drop data bus signals (DD[23:16]) are
always included in parity calculations. Register bits in the Drop Bus
Configuration register control the inclusion of the DPL[3] and
DC1J1V1[3] signals in parity calculation and the sense (odd/even)
of the parity. This output is forced low in single Drop bus mode. The
Drop interface mode is set via DTMODE register bit in the Drop Bus
Configuration register.
DDP[3] is updated on the rising edge of DCK.
DDP[4]OutputAF28The Drop bus data parity signal #4 (DDP[4]) indicates the parity of
the Drop bus signals. The Drop data bus signals (DD[31:24]) are
always included in parity calculations. Register bits in the Drop Bus
Configuration register control the inclusion of the DPL[4] and
DC1J1V1[4] signals in parity calculation and the sense (odd/even)
of the parity. This output is forced low single Drop bus mode. The
Drop interface mode is set via DTMODE register bit in the Drop Bus
Configuration register.
DDP[4] is updated on the rising edge of DCK.
9.9 Add Bus Telecom Interface Signals
Pin NamePin TypePin
No.
ACKInputE31
AD[0]
AD[1]
AD[2]
AD[3]
AD[4]
AD[5]
AD[6]
AD[7]
InputE28
F30
F29
F28
F27
G31
G30
G29
Function
The Add bus clock (ACK) provides timing for the Add bus interface.
ACK is nominally a 77.76 MHz, 50% duty cycle clock when the Add
interface is configured as a single bus interface. ACK is nominally a
19.44 MHz, 50% duty cycle clock when the Add interface is
configured as a quad STS-3 (STM-1) interface.
Inputs AD[31:0], APL[4:1], ADP[4:1], and AC1J1V1[4:1]/AFP[4:1]
are sampled on the rising edge of ACK.
In single Add bus interface mode, the Add bus data (AD[7:0])
contains the STS-3/c(STM-1/AU-3/AU-4) SONET/SDH payload data
to transmit on the four channels. In quad Add bus interface STS-3
(STM-1) mode, the Add bus data (AD[7:0]) contains the 1
3/3c (STM-1/AU-3/AU-4) SONET/SDH payload data to transmit.
When Add bus TSI functionality is disabled, the SONET/SDH
payload data provided on AD[7:0] will be transmitted on channel #1.
When Add bus TSI functionality is enabled, the association of Add
bus payloads to the transmitted payloads is software configurable in
the SPECTRA-4x155 Add Bus STM-1 #1..4 AU-3 #1..3 Select
registers. The Add bus transport overhead bytes are ignored with
the programmable exception of the H1 and H2 pointer bytes. The
phase relation of the SPE (VC) to the transport frame is determined
by the Add bus composite timing signal (AC1J1V1[1]) or optionally
by interpreting the H1 and H2 pointer bytes. AD[7] is the most
significant bit (corresponding to bit 1 of each serial word, the first bit
transmitted). AD[0] is the least significant bit (corresponding to bit 8
of each serial word, the last bit transmitted).
AD[7:0] is sampled on the rising edge of ACK. The Add interface
st
STS-
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Document ID: PMC-1990822, Issue 4
mode is set via ATMODE register bit in the Add Bus Configuration
register.
In single Add bus interface mode, the Add bus data (AD[15:8]) is
disabled. In quad Add bus interface STS-3 (STM-1) mode, the Add
bus data (AD[15:8]) contains the 2
SONET/SDH payload data to transmit. When Add bus TSI
functionality is enabled, the association of Add bus payloads to the
transmitted payloads is software configurable in the SPECTRA4x155 Add Bus STM-1 #1..4 AU-3 #1..3 Select registers. The Add
bus transport overhead bytes are ignored with the programmable
exception of the H1 and H2 pointer bytes. The phase relation of the
SPE (VC) to the transport frame is determined by the Add bus
composite timing signal (AC1J1V1[2]) or optionally by interpreting
the H1 and H2 pointer bytes. AD[15] is the most significant bit
(corresponding to bit 1 of each serial word, the first bit transmitted).
AD[8] is the least significant bit (corresponding to bit 8 of each serial
word, the last bit transmitted).
AD[15:8] is sampled on the rising edge of ACK. The Add interface
mode is set via ATMODE register bit in the Add Bus Configuration
register.
In single Add bus interface mode, the Add bus data (AD[23:16]) is
disabled. In quad Add bus interface STS-3 (STM-1) mode, the Add
bus data (AD[23:16]) contains the 3
SONET/SDH payload data to transmit. When Add bus TSI
functionality is enabled, the association of Add bus payloads to the
transmitted payloads is software configurable in the SPECTRA4x155 Add Bus STM-1 #1..4 AU-3 #1..3 Select registers. The Add
bus transport overhead bytes are ignored with the programmable
exception of the H1 and H2 pointer bytes. The phase relation of the
SPE (VC) to the transport frame is determined by the Add bus
composite timing signal (AC1J1V1[3]) or optionally by interpreting
the H1 and H2 pointer bytes. AD[23] is the most significant bit
(corresponding to bit 1 of each serial word, the first bit transmitted).
AD[16] is the least significant bit (corresponding to bit 8 of each
serial word, the last bit transmitted).
AD[23:16] is sampled on the rising edge of ACK. The Add interface
mode is set via ATMODE register bit in the Add Bus Configuration
register.
In single Add bus interface mode, the Add bus data (AD[31:24]) is
disabled. In quad Add bus interface STS-3 (STM-1) mode, the Add
bus data (AD[31:24]) contains the 4
SONET/SDH payload data to transmit. When Add bus TSI
functionality is enabled, the association of Add bus payloads to the
transmitted payloads is software configurable in the SPECTRA4x155 Add Bus STM-1 #1..4 AU-3 #1..3 Select registers. The Add
bus transport overhead bytes are ignored with the programmable
exception of the H1 and H2 pointer bytes. The phase relation of the
SPE (VC) to the transport frame is determined by the Add bus
composite timing signal (AC1J1V1[4]) or optionally by interpreting
the H1 and H2 pointer bytes. AD[31] is the most significant bit
(corresponding to bit 1 of each serial word, the first bit transmitted).
AD[24] is the least significant bit (corresponding to bit 8 of each
nd
STS-3/3c (STM-1/AU-3/AU-4)
rd
STS-3/3c (STM-1/AU-3/AU-4)
th
STS-3/3c (STM-1/AU-3/AU-4)
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AD[31:24] is sampled on the rising edge of ACK. The Add interface
mode is set via ATMODE register bit in the Add Bus Configuration
register.
APL[1]InputE30
APL[2]InputK30The Add bus payload active signal #2 (APL[2]) indicates when
APL[3]InputU31
APL[4]InputAB31The Add bus payload active signal #4 (APL[4]) indicates when
AC1J1V1[1]/InputE29
The Add bus payload active signal #1 (APL[1]) indicates when
AD[7:0] is carrying a payload byte. It is set high during path
overhead and payload bytes and low during transport overhead
bytes. APL[1] is set high during the H3 byte to indicate a negative
pointer justification event and set low during the byte following H3 to
indicate a positive pointer justification event. The APL[1] input must
be strapped low when the AFPEN bit in the Add Bus Configuration
register is set high. The INCAPL bit in the Add Bus Configuration
#1 register controls whether APL[1] is to be included in the Add Bus
parity ADP[1] or the activity monitor.
APL[1] is sampled on the rising edge of ACK.
AD[15:8] is carrying a payload byte. It is set high during path
overhead and payload bytes and low during transport overhead
bytes. APL[2] is set high during the H3 byte to indicate a negative
pointer justification event and set low during the byte following H3 to
indicate a positive pointer justification event. The APL[2] input must
be strapped low when the AFPEN bit in the Add Bus Configuration
register is set high. The INCAPL bit in the Add Bus Configuration
#1 register controls whether APL[2] is to be included in the Add Bus
parity ADP[2] or the activity monitor.
APL[2] is sampled on the rising edge of ACK.
The Add bus payload active signal #3 (APL[3]) indicates when
AD[23:16] is carrying a payload byte. It is set high during path
overhead and payload bytes and low during transport overhead
bytes. APL[3] is set high during the H3 byte to indicate a negative
pointer justification event and set low during the byte following H3 to
indicate a positive pointer justification event. The APL[3] input must
be strapped low when the AFPEN bit in the Add Bus Configuration
register is set high.The INCAPL bit in the Add Bus Configuration #1
register controls whether APL[3] is to be included in the Add Bus
parity ADP[3] or the activity monitor.
APL[3] is sampled on the rising edge of ACK.
AD[31:24] is carrying a payload byte. It is set high during path
overhead and payload bytes and low during transport overhead
bytes. APL[4] is set high during the H3 byte to indicate a negative
pointer justification event and set low during the byte following H3 to
indicate a positive pointer justification event. The APL[4] input must
be strapped low when the AFPEN bit in the Add Bus Configuration
register is set high.The INCAPL bit in the Add Bus Configuration #1
register controls whether APL[4] is to be included in the Add Bus
parity ADP[4] or the activity monitor.
APL[4] is sampled on the rising edge of ACK.
The Add bus composite timing signal #1 (AC1J1V1[1]) is defined
when the AFPEN bit in the Add Bus Configuration register is set
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Document ID: PMC-1990822, Issue 4
low. AC1J1V1[1] identifies the frame and optionally the payload and
tributary multiframe boundaries on the Add data bus signals
AD[7:0]. AC1J1V1[1] pulses high with the Add bus payload active
signal #1 (APL[1]) set low to mark the first STS-1 (STM-0/AU-3)
Identification byte (C1). Optionally, the AC1J1V1[1] pulses high with
APL[1] set high to mark the path trace byte (J1). Optionally, the
AC1J1V1[1] signal pulses high on the V1 byte to indicate tributary
multiframe boundaries.
Optional marking of the J1 and V1 bytes is controlled using the
DISJ1V1 bit in the SPECTRA-4x155 TPPS Path Configuration
register. Setting DISJ1V1 bit high enables pointer interpretation on
the Add bus. Valid H1 and H2 pointer bytes must be provided on the
Add data bus signals (AD[7:0]) to allow the J1 position to be
identified. Optionally, the H4 byte could be provided on the Add data
bus signals (AD[7:0]) to allow the V1 position to be identified.
The AD[7:0], AD[15:8], AD[23:16] and AD[31:24] Add buses must
be frame aligned with the C1 pulses of the associated AC1J1V1
signals. All C1 pulses must be aligned.
If the AC1J1V1[1] frame alignment changes, all the slices are
affected by the realignment. Errors may occur in some or all slices
and the APGMs need to be manually regenerated or resynchronized
if used.
The ATSI_ISOLATE bit can be used to disable the realignment of
the 12 TPPS slice clocks by AC1J1V1/AFP[1] Add BUS. This bit
should only be used when all 12 TPPS slices are placed in
Autonomous mode and the AC1J1V1/AFP[1] (and/or APL) Add BUS
interface can not maintain a constant frame alignment.
AC1J1V1[1] is sampled on the rising edge of ACK.
AFP[1]E29The active high Add bus reference frame position signal #1 (AFP[1])
is defined when the AFPEN bit in the Add Bus Configuration register
is set high. AFP[1] indicates when the first byte of the synchronous
payload envelope (SPE byte 1 of STS-1 #1) of the SONET/SDH
stream is available on the AD[7:0] bus. Note that AFP[1] has a fixed
relationship to the SONET/SDH frame; the start of the SPE is
determined by the STS (AU) pointer and may change relative to
AFP[1]. The DISJ1V1 bit in the SPECTRA-4x155 TPPS Path
Configuration register must be set high in this mode to enable
pointer interpretation on the Add bus. Valid H1 and H2 pointer bytes
must be provided on the Add data bus (AD[7:0]) to allow the J1
position to be identified. Optionally, the H4 byte could be provided
on the Add data bus to allow the V1 position to be identified.
The AD[7:0], AD[15:8], AD[23:16] and AD[31:24] Add buses must
be frame aligned with the C1 pulses of the associated AC1J1V1
signals. All C1 pulses must be aligned.
If the AC1J1V1[1] frame alignment changes, all the slices are
affected by the realignment. Errors may occur in some or all slices
and the APGMs need to be manually regenerated or resynchronized
if used.
The ATSI_ISOLATE bit can be used to disable the realignment of
the 12 TPPS slice clocks by AC1J1V1/AFP[1] Add BUS. This bit
should only be used when all 12 TPPS slices are placed in
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Document ID: PMC-1990822, Issue 4
Autonomous mode and the AC1J1V1/AFP[1] (and/or APL) Add BUS
interface can not maintain a constant frame alignment.
AFP[1] is sampled on the rising edge of ACK.
AC1J1V1[2]/InputK29The Add bus composite timing signal #2 (AC1J1V1[2]) is defined
when the AFPEN bit in the Add Bus Configuration register is set
low. AC1J1V1[2] identifies the frame and optionally the payload and
tributary multiframe boundaries on the Add data bus signals
AD[15:8]. AC1J1V1[2] pulses high with the Add bus payload active
signal #2 (APL[2]) set low to mark the first STS-1 (STM-0/AU-3)
Identification byte (C1). Optionally, the AC1J1V1[2] pulses high with
APL[2] set high to mark the path trace byte (J1). Optionally, the
AC1J1V1[2] signal pulses high on the V1 byte to indicate tributary
multiframe boundaries.
Optional marking of the J1 and V1 bytes is controlled using the
DISJ1V1 bit in the SPECTRA-4x155 TPPS Path Configuration
register. Setting DISJ1V1 bit high enables pointer interpretation on
the Add bus. Valid H1 and H2 pointer bytes must be provided on the
Add data bus signals (AD[15:8]) to allow the J1 position to be
identified. Optionally, the H4 byte could be provided on the Add data
bus signals (AD[15:8]) to allow the V1 position to be identified.
When using the Add bus TSI functionality, the AD[7:0], AD[15:8],
AD[23:16] and AD[31:24] Add buses must be frame aligned to have
the C1 pulses of the associated AC1J1V1 signals high
simultaneously.
AC1J1V1[2] is sampled on the rising edge of ACK.
AFP[2]K29The active high Add bus reference frame position signal #2 (AFP[2])
is defined when the AFPEN bit in the Add Bus Configuration register
is set high. AFP[2] indicates when the first byte of the synchronous
payload envelope (SPE byte 1 of STS-1 #1) of the SONET/SDH
stream is available on the AD[15:8] bus. Note that AFP[2] has a
fixed relationship to the SONET/SDH frame; the start of the SPE is
determined by the STS (AU) pointer and may change relative to
AFP[2]. The DISJ1V1 bit in the SPECTRA-4x155 TPPS Path
Configuration register must be set high in this mode to enable
pointer interpretation on the Add bus. Valid H1 and H2 pointer bytes
must be provided on the Add data bus (AD[15:8]) to allow the J1
position to be identified. Optionally, the H4 byte could be provided
on the Add data bus to allow the V1 position to be identified.
When using the Add bus TSI functionality, the AD[7:0], AD[15:8],
AD[23:16] and AD[31:24] Add buses must be frame aligned to have
the C1 pulses of the associated AC1J1V1 signals high
simultaneously.
AFP[2] is sampled on the rising edge of ACK.
AC1J1V1[3]/InputU30
The Add bus composite timing signal #3 (AC1J1V1[3]) is defined
when the AFPEN bit in the Add Bus Configuration register is set
low. AC1J1V1[3] identifies the frame and optionally the payload and
tributary multiframe boundaries on the Add data bus signals
AD[23:16]. AC1J1V1[3] pulses high with the Add bus payload active
signal #3 (APL[3]) set low to mark the first STS-1 (STM-0/AU-3)
Identification byte (C1). Optionally, the AC1J1V1[3] pulses high with
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APL[3] set high to mark the path trace byte (J1). Optionally, the
AC1J1V1[3] signal pulses high on the V1 byte to indicate tributary
multiframe boundaries.
Optional marking of the J1 and V1 bytes is controlled using the
DISJ1V1 bit in the TPPS Path Configuration register. Setting
DISJ1V1 bit high enables pointer interpretation on the Add bus.
Valid H1 and H2 pointer bytes must be provided on the Add data
bus signals (AD[23:16]) to allow the J1 position to be identified.
Optionally, the H4 byte could be provided on the Add data bus
signals (AD[23:16]) to allow the V1 position to be identified.
When using the Add bus TSI functionality, the AD[7:0], AD[15:8],
AD[23:16] and AD[31:24] Add buses must be frame aligned to have
the C1 pulses of the associated AC1J1V1 signals high
simultaneously.
AC1J1V1[3] is sampled on the rising edge of ACK.
AFP[3]U30The active high Add bus reference frame position signal #3 (AFP[3])
is defined when the AFPEN bit in the Add Bus Configuration register
is set high. AFP[3] indicates when the first byte of the synchronous
payload envelope (SPE byte 1 of STS-1 #1) of the SONET/SDH
stream is available on the AD[31:24] bus. Note that AFP[3] has a
fixed relationship to the SONET/SDH frame; the start of the SPE is
determined by the STS (AU) pointer and may change relative to
AFP[3]. The DISJ1V1 bit in the SPECTRA-4x155 TPPS Path
Configuration register must be set high in this mode to enable
pointer interpretation on the Add bus. Valid H1 and H2 pointer bytes
must be provided on the Add data bus (AD[23:16]) to allow the J1
position to be identified. Optionally, the H4 byte could be provided
on the Add data bus to allow the V1 position to be identified.
When using the Add bus TSI functionality, the AD[7:0], AD[15:8],
AD[23:16] and AD[31:24] Add buses must be frame aligned to have
the C1 pulses of the associated AC1J1V1 signals high
simultaneously.
AFP[3] is sampled on the rising edge of ACK.
AC1J1V1[4]/InputAB30
The Add bus composite timing signal #4 (AC1J1V1[4]) is defined
when the AFPEN bit in the Add Bus Configuration is set low.
AC1J1V1[4] identifies the frame and optionally the payload and
tributary multiframe boundaries on the Add data bus signals
AD[31:24]. AC1J1V1[4] pulses high with the Add bus payload active
signal #4 (APL[1]) set low to mark the first STS-1 (STM-0/AU-3)
Identification byte (C1). Optionally, the AC1J1V1[4] pulses high with
APL[4] set high to mark the path trace byte (J1). Optionally, the
AC1J1V1[4] signal pulses high on the V1 byte to indicate tributary
multiframe boundaries.
Optional marking of the J1 and V1 bytes is controlled using the
DISJ1V1 bit in the TPPS Path Configuration register. Setting
DISJ1V1 bit high enables pointer interpretation on the Add bus.
Valid H1 and H2 pointer bytes must be provided on the Add data
bus signals (AD[31:24]) to allow the J1 position to be identified.
Optionally, the H4 byte could be provided on the Add data bus
signals (AD[31:24]) to allow the V1 position to be identified.
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When using the Add bus TSI functionality, the AD[7:0], AD[15:8],
AD[23:16] and AD[31:24] Add buses must be frame aligned to have
the C1 pulses of the associated AC1J1V1 signals high
simultaneously.
AC1J1V1[4] is sampled on the rising edge of ACK.
AFP[4]AB30
ADP[1]InputG28The Add bus data parity signal #1 (ADP[1]) indicates the parity of
ADP[2]InputM28
ADP[3]InputW31The Add bus data parity signal #3 (ADP[3]) indicates the parity of
ADP[4]InputAD30
The active high Add bus reference frame position signal #4 (AFP[4])
is defined when the AFPEN bit in the Add Bus Configuration is set
high. AFP[4] indicates when the first byte of the synchronous
payload envelope (SPE byte 1 of STS-1 #1) of the SONET/SDH
stream is available on the AD[31:24] bus. Note that AFP[4] has a
fixed relationship to the SONET/SDH frame; the start of the SPE is
determined by the STS (AU) pointer and may change relative to
AFP[4]. The DISJ1V1 bit in the TPPS Path Configuration register
must be set high in this mode to enable pointer interpretation on the
Add bus. Valid H1 and H2 pointer bytes must be provided on the
Add data bus (AD[31:24]) to allow the J1 position to be identified.
Optionally, the H4 byte could be provided on the Add data bus to
allow the V1 position to be identified.
When using the Add bus TSI functionality, the AD[7:0], AD[15:8],
AD[23:16] and AD[31:24] Add buses must be frame aligned to have
the C1 pulses of the associated AC1J1V1 signals high
simultaneously.
AFP[4] is sampled on the rising edge of ACK.
the Add bus #1 signals. The Add data bus (AD[7:0]) is always
included in parity calculations. Register bits in the Add Bus
Configuration register control the inclusion of the APL[1] and
AC1J1V1[1]/AFP[1] signals in parity calculations and the sense
(odd/even) of the parity.
ADP[1] is sampled on the rising edge of ACK.
The Add bus data parity signal #2 (ADP[2]) indicates the parity of
the Add bus #2 signals. The Add data bus (AD[15:8]) is always
included in parity calculations. Register bits in the Add Bus
Configuration register control the inclusion of the APL[2] and
AC1J1V1[2]/AFP[2] signals in parity calculations and the sense
(odd/even) of the parity.
ADP[2] is sampled on the rising edge of ACK.
the Add bus #3 signals. The Add data bus (AD[23:16]) is always
included in parity calculations. Register bits in the Add Bus
Configuration register control the inclusion of the APL[3] and
AC1J1V1[3]/AFP[3] signals in parity calculations and the sense
(odd/even) of the parity.
ADP[3] is sampled on the rising edge of ACK.
The Add bus data parity signal #4 (ADP[4]) indicates the parity of
the Add bus #4 signals. The Add data bus (AD[31:24]) is always
included in parity calculations. Register bits in the Add Bus
Configuration register control the inclusion of the APL[4] and
AC1J1V1[4]/AFP[4] signals in parity calculations and the sense
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RDB/InputB14The active low read enable (RDB) signal is low during a SPECTRA-
EB14The active high external access signal (E) is set high during
WRB/InputD14The active low write strobe (WRB) signal is low during a SPECTRA-
RWBD14The read/write select signal (RWB) selects between SPECTRA-
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
A[13]InputE18
A[12]
A[11]
A[10]
A[9]
Schmidt
TTL Input
I/OD20
InputC18
E15
C20
B20
A20
E19
D19
C19
B19
D18
B18
A18
Function
The active low Motorola bus enable (MBEB) signal configures the
SPECTRA-4x155 for Motorola bus mode where the RDB/E signal
functions as E, and the WRB/RWB signal functions as RWB. When
MBEB is high, the SPECTRA-4x155 is configured for Intel bus mode
where the RDB/E signal functions as RDB. The MBEB input has an
integral pull up resistor.
The active low chip select (CSB) signal is low during SPECTRA4x155 register accesses.
Note that when not being used, CSB must be tied low. If CSB is not
required (i.e. register accesses controlled using the RDB and WRB
signals only), CSB must be connected to an inverted version of the
RSTB input.
4x155 read access. The SPECTRA-4x155 drives the D[7:0] bus with
the contents of the Addressed register while RDB and CSB are low.
SPECTRA-4x155 register access while in Motorola bus mode.
4x155 register write access. The D[7:0] bus contents are clocked into
the Addressed register on the rising WRB edge while CSB is low.
4x155 register read and write accesses while in Motorola bus mode.
The SPECTRA-4x155 drives the data bus D[7:0] with the contents of
the Addressed register while CSB is low and RWB and E are high.
The contents of D[7:0] are clocked into the Addressed register on the
falling E edge while CSB and RWB are low.
The bi-directional data bus, D[7:0], is used during SPECTRA-4x155
read and write accesses.
The test register select signal (A[13]) selects between normal and
test mode register accesses. A[13] is high during test mode register
accesses, and is low during normal mode register accesses. A[13]
may be tied low.
The Address bus (A[13:0]) selects specific registers during
SPECTRA-4x155 register accesses.
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The active low reset (RSTB) signal provides an asynchronous
SPECTRA-4x155 reset. RSTB is a Schmidt triggered input with an
integral pull-up resistor.
The Address latch enable (ALE) is an active-high signal and latches
the Address bus A[13:0] when low. When ALE is high, the internal
Address latches are transparent. It allows the SPECTRA-4x155 to
interface to a multiplexed Address/data bus. The ALE input has an
integral pull up resistor.
The active low interrupt (INTB) is set low when a SPECTRA-4x155
enabled interrupt source is active. The SPECTRA-4x155 may be
enabled to report many alarms or events via interrupts.
INTB is tri-stated when the interrupt is acknowledged via the
appropriate register access. INTB is an open drain output.
9.11 Analog Miscellaneous Signals
Pin NameTypePin
Function
No.
ATP[0]
ATP[1]
ATP[2]
ATP[3]
AnalogV3
V4
W1
V5
Four analog test ports (ATP0, ATP1, ATP2, ATP3) are provided for
production testing only. These pins must be tied to analog ground
(AVS) during normal operation.
9.12 JTAG Test Access Port (TAP) Signals
Pin NameTypePin
No.
TCKSchmidt
TTL Input
TMSInputAG6The test mode select (TMS) signal controls the test operations that
TDIInputAK5When the SPECTRA-4x155 is configured for JTAG operation, the
TDOTristate
Output
AK4The test clock (TCK) signal provides timing for test operations that
AH6The test data output (TDO) signal carries test data out of the
Function
can be carried out using the IEEE P1149.1 test access port.
can be carried out using the IEEE P1149.1 test access port. TMS is
sampled on the rising edge of TCK. TMS has an integral pull up
resistor.
test data input (TDI) signal carries test data into the SPECTRA4x155 via the IEEE P1149.1 test access port. TDI is sampled on the
rising edge of TCK.
TDI has an integral pull up resistor.
SPECTRA-4x155 via the IEEE P1149.1 test access port. TDO is
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updated on the falling edge of TCK. TDO is a tri-state output which is
inactive except when scanning of data is in progress.
The active low test reset (TRSTB) signal provides an asynchronous
SPECTRA-4x155 test access port reset via the IEEE P1149.1 test
access port. TRSTB is a Schmidt triggered input with an integral pull
up resistor. In the event that TRSTB is not used, it must be
connected to RSTB.
Pin NamePin TypePIN
Function
No.
Reserved1OutputD25This output can be left floating.
Reserved2OutputC25This output can be left floating.
The analog power (AVD) pins for the analog core. The AVD pins
should be connected through passive filtering networks to a welldecoupled +3.3V analog power supply.
Please see the Operation section for detailed information.
RAVS1_A - Channel #1 PECL Input Buffer
RAVS1_B - Channel #1 CRU
RAVS1_C - Channel #1 CRU
RAVS2_A - Channel #2 PECL Input Buffer
RAVS2_B - Channel #2 CRU
RAVS2_C - Channel #2 CRU
RAVS3_A - Channel #3 PECL Input Buffer
RAVS3_B - Channel #3 CRU
RAVS3_C - Channel #3 CRU
RAVS4_A - Channel #4 PECL Input Buffer
RAVS4_B - Channel #4 CRU
RAVS4_C - Channel #4 CRU
TAVS1_A – CSU
TAVS1_B – CSU
The analog ground (AVS) pins for the analog core. The AVS pins
should be connected to the analog ground of the analog power
supply.
Please see the Operation section for detailed information.
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1. All SPECTRA-4x155 inputs and bi-directional pins present minimum capacitive loading and operate at
TTL logic levels except the SD and RXD± inputs, which operate at pseudo-ECL (PECL) logic levels.
2. The SPECTRA-4x155 digital outputs and bidirectionals that have a 2 mA drive capability are: D[7:0],
B3E, INTB, LOF1-4, LAIS/RRCPDAT1-4, LRDI/RRCPCLK1-4, LOS/RRCPFP1-4, RTOH1-4,
RTOHCLK1-4, RTOHFP1-4, RSLD1-4, RSLDCLK1-4, RAD, RALM, RPOH, RPOHCLK, RPOHEN,
RPOHFP, SALM1-4, TDO, Reserved1, Reserved2, Reserved5, TSLDCLK1-4, TTOHCLK1-4,
TTOHFP1-4.
3. The SPECTRA-4x155 digital outputs and bidirectionals that have a 6 mA drive capability are:
DC1JV1[4:1], DD[31:0], DDP[4:1], DPL[4:1], PGMRCLK, PGMTCLK, RCLK1-4, TCLK
4. The SPECTRA-4x155 digital outputs that are not 5 volt tolerant are: DC1JV1[4:1], DD[31:0], DDP[4:1],
DPL[4:1], PGMRCLK, PGMTCLK, RCLK1-4, TCLK. All other outputs are 5 volt tolerant.
5. The inputs ALE, MBEB, RSTB, TMS, TDI, and TRSTB have internal pull-up resistors.
6. The differential pseudo-ECL inputs and outputs should be terminated in a passive network and interface
at PECL levels as described in the Operations section.
7. It is mandatory that every digital ground pin (VSS) be connected to the printed circuit board ground
plane to ensure reliable device operation.
8. It is mandatory that every digital power pin (VDD) be connected to the printed circuit board power plane
to ensure reliable device operation.
9. All analog power pins can be sensitive to noise. They must be isolated from the digital power. Care
must be taken to correctly decouple these pins. Please refer to the Operations sections
10. Due to ESD protection structures in the pads, caution must be taken when powering the device up or
down. ESD protection devices behave as diodes between power supply pins and from I/O pins to power
supply pins. Under extreme conditions it is possible to damage these ESD protection devices or trigger
latch up. Please adhere to the recommended power supply sequencing described in the Operation
section of this document.
11. Do not exceed 100 mA of current on any pin during the power-up or power-down sequence. Refer to
the Power Sequencing description in the Operations section.
12. Before any input activity occurs, ensure that the device power supplies are within their nominal voltage
range.
13. Hold the device in the reset condition until the device power supplies are within their nominal voltage
range.
Digital
Power
Ground
The digital power (VDD) pins should be connected to a well-decoupled +3.3 V
digital power supply.
14. Ensure that all digital power is applied simultaneously, and applied before or simultaneously with the
analog power. Refer to the Power Sequencing description in the Operations section.
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The Receive Line Interface and the Clock Recover/Serial-to-Parallel Convertor (CRSI) blocks
perform PECL conversion, clock and data recovery on the incoming 155.52 Mbit/s data stream,
and serial-to-parallel conversion based on the recovered SONET/SDH A1/A2 framing pattern.
The blocks allow the SPECTRA-4x155 to directly interface with optical modules (ODLs) or
other medium interfaces.
10.1.1 Clock Recovery Unit (CRU)
The clock recovery unit (CRU) inside the CRSI block recovers a clock from the incoming bit
serial data stream. The CRU is fully compliant with SONET/SDH jitter tolerance requirements. It
uses a low frequency 19.44 MHz reference clock to train and monitor its clock recovery phaselocked loop (PLL). Under LOS conditions, the CRU will continue to output a line rate clock that
is locked to this reference for keep-alive purposes. As part of its feature set, the CRU provides
status bits that indicate whether it is locked to data or to the reference clock. The unit also
supports diagnostic loopback and a LOS input that squelches normal input data.
Production
Initially, the PLL locks to the reference clock, REFCLK. Once the frequency of the recovered
clock is within 488 ppm of the reference clock, the PLL attempts to lock to the data. Once in data
lock, the PLL will revert to the reference clock if no data transitions occur in 80 bit periods or if
the recovered clock drifts beyond approximately 488 ppm of the reference clock.
When the transmit clock is derived from the recovered clock (loop timing), the accuracy of the
transmit clock is directly related to the REFCLK reference accuracy under LOS conditions. In
applications that are required to meet the Telcordia GR-253-CORE SONET Network Element
free-run accuracy specification, the reference must be within +/-20 ppm. When not loop timed,
the REFCLK accuracy may be relaxed to +/-50 ppm.
The loop filter transfer function is optimized to enable the PLL to track the jitter, yet tolerate the
minimum transition density expected in a received SONET/SDH data signal. The total loop
dynamics of the clock recovery PLL yield a jitter tolerance that exceeds the minimum tolerance
proposed for SONET equipment by GR-253-CORE as shown in Figure 5.
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The Serial-to-Parallel Converter (SIPO) inside the CRSI converts the received bit serial
SONET/SDH stream into a byte serial stream. The SIPO searches for the SONET/SDH framing
pattern (A1, A2) in the incoming stream and performs serial-to-parallel conversion on octet
boundaries.
While out-of-frame, the CRSI block monitors the receive bit-serial STS-3 (STM-1) data stream
for an occurrence of the framing pattern (A1, A2). The CRSI adjusts its byte alignment of the
SIPO when three consecutive A1 bytes followed by three consecutive A2 bytes occur in the data
stream. The CRSI informs the RSOP Framer block when the framing pattern has been detected to
reinitialize the RSOP to the new frame alignment. While in-frame, the CRSI maintains the byte
alignment of the SIPO until RSOP declares OOF.
Mask25'C 3.3 V
10.2 Receive Section Overhead Processor (RSOP)
The Receive Section Overhead Processor (RSOP) block processes the section overhead
(regenerator section) of the receive STS-3 (STM-1) stream, providing frame synchronization, descrambling, section level alarm, and performance monitoring.
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The RSOP may also force Line AIS. AIS-L is inserted in the receive data stream using input
RLAIS or, optionally, automatically when LOS, LOF, or when section trace mismatch or unstable
events occur. Line AIS may also be inserted automatically on signal degrade or signal failure
events. This line AIS is forced after the RLOP. The automatic insertion of receive line AIS is
controlled by the Receive Line AIS Control Register.
The RSOP-declared OOF, LOF, and LOS events can be optionally reported on the SALM or
RALM outputs.
The RSOP block provides descrambled data and frame alignment indication signals for use by the
Receive Line Overhead Processor (RLOP).
10.2.1 Framer
The Framer Block of RSOP determines the in-frame/OOF status of the receive stream.
While in-frame, the framing bytes (A1, A2) in each frame are compared against the expected
pattern. OOF is declared when four consecutive frames containing one or more framing pattern
errors have been received.
The RSOP block frames to the data stream by operating with an upstream pattern detector (the
SIPO block) that searches for occurrences of the framing pattern (A1, A2) in the bit serial data
stream. Once the SIPO has found byte alignment, the RSOP block monitors for the next
occurrence of the framing pattern 125 µs or later. The block declares frame alignment when either
all A1 and A2 bytes are seen error-free or when only the first A1 byte and the first four bits of the
last A2 byte are seen error-free. The first algorithm examines 24 bytes of A1 and A2 in the STS-3
(STM-1) stream. The second algorithm examines only the first occurrence of A1 and the first four
bits of the last occurrence of A2 in the sequence. Once in-frame, the RSOP block monitors the
framing pattern sequence and declares an OOF when one or more bit errors in each framing
pattern are detected for four consecutive frames. Again, depending upon the algorithm either 24
framing bytes are examined for bit errors in each frame, or only the A1 byte and the first four bits
of the last A2 byte (that is, 12 bits total) are examined for bit errors in each frame.
These framing algorithms perform robustly in the presence of bit errors and random data. When
searching for frame alignment, each algorithm’s performance is dominated by the SIPO’s
alignment algorithm, which always examines all framing bits. The probability of falsely framing
to random data is less than 0.00001% for either algorithm. Once in frame alignment, the
SPECTRA-4x155 continuously monitors the framing pattern. When the incoming stream contains
-3
BER, the first algorithm provides a 99.75% probability that the mean time between OOF
a 10
occurrences is 1.3 seconds in STS-3 (STM-1) SONET/SDH mode. The second algorithm
provides a 99.75% probability that the mean time between OOF occurrences is 7 minutes.
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10.2.2 Descramble
The Descramble Block of RSOP uses a frame-synchronous descrambler to process the receive
stream. The generating polynomial is x7 + x6 + 1 and the sequence length is 127. Details of the
de-scrambling operation are provided in the references. Note that the framing bytes (A1 and A2)
and the trace/growth bytes (J0/Z0) are not descrambled. A register bit is provided to disable the
de-scrambling operation.
10.2.3 Error Monitor
The Error Monitor Block of RSOP calculates the received section BIP-8 error detection code (B1)
based on the scrambled data of the complete STS-3c (STM-1) frame. The section BIP-8 code is
based on a bit interleaved parity calculation using even parity. Details are provided in the
references. The calculated BIP-8 code is compared with the BIP-8 code extracted from the B1
byte of the following frame. Differences indicate that a section level bit error has occurred. Up to
64000 (8 x 8000) bit errors can be detected per second. The Error Monitor Block accumulates
these section-level bit errors in a 16-bit saturating counter that can be read via the microprocessor
interface. Circuitry is provided to latch this counter so that its value can be read while
simultaneously resetting the internal counter to zero or one, if appropriate, so that a new period of
accumulation can begin without loss of any events. It is intended that this counter be polled at
least once per second so as not to miss bit error events.
The LOS Block of RSOP monitors the scrambled data of the receive stream for the absence of allones. When 20 ± 3 µs of all zeros patterns is detected, a LOS is declared. LOS is cleared when
two valid framing words are detected and during the intervening time, no LOS condition is
detected. The LOS signal is optionally reported on the RALRM output pin when enabled by the
LOSEN Receive Alarm Control Register bit.
10.2.5 Loss of Frame (LOF)
The LOF Block monitors the in-frame/OOF status of the Framer Block of RSOP. A LOF is
declared when an OOF condition persists for 3 ms. It is cleared when an in-frame condition
persists for a period of 3 ms. To provide for intermittent OOF (or in-frame) conditions, the 3 ms
timer is not reset to zero until an in-frame (or OOF) condition persists for 3 ms. The LOF and
OOF signals are optionally reported on the RALRM output pin when they are enabled by the
LOFEB and OOFEN Receive Alarm Control Register bits.
10.3 Receive Section Trace Buffer (SSTB)
In mode 1 operation, the receive portion of the SONET/SDH Section Trace Buffer (SSTB)
captures the received section trace identifier message (J0 byte) into microprocessor readable
registers. It contains four pages of trace message memory:
• The transmit message page.
• The capture page.
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Section trace identifier data bytes from the receive stream are written into the capture page. The
expected identifier message is downloaded by the microprocessor into the expected page. On
receipt of a trace identifier byte, it is written into the next location in the capture page. The
received byte is compared with the data from the previous message in the capture page. The
identifier message is accepted if it is received unchanged three times, or optionally, five times.
The accepted message is then compared with the expected message.
If enabled, an interrupt is generated if the accepted message changes from “matching” the
expected message to “mismatching” and vice versa. If the current message differs from the
previous message for eight consecutive messages, the received message is declared unstable. The
received message is declared stable once the received message passes the persistency criterion
(three or five identical receptions) for being accepted. Note: An interrupt may be optionally
generated on entry to and exit from the unstable state. Optionally, line AIS may be inserted in the
received stream when the receive message is in the mismatched or unstable state.
The length of the section trace identifier message is selectable between 16-bytes and 64-bytes.
When programmed for 16-byte messages, the section trace buffer synchronizes to the byte with
the most significant bit set to high and places the byte at the first location in the capture page.
When programmed for 64-byte messages, the section trace buffer synchronizes to the trailing
carriage return (CR = 0DH), line feed (LF = 0AH) sequence and places the next byte at the head
of the capture page. This enables the section trace message to be appropriately aligned for
interpretation by the microprocessor. Synchronization may be disabled. In this case, the memory
acts as a circular buffer.
Mode 2 section trace identifier operation is also supported. For mode 2 support, a stable message
is declared when forty-eight of the same section trace identifier message (J0) bytes are received.
Once in the stable state, an unstable state is declared when one or more errors are detected in
three consecutive 16-byte windows.
10.4 Receive Line Overhead Processor (RLOP)
The Receive Line Overhead Processor block (RLOP) processes the line overhead (multiplexer
section) of the receive STS-3 (STM-1) stream. The block delares the LAIS and LRDI alarms. In
Addition the RLOP detects and accumulates B2 errors, accumulated L-REI and extracts the
K1/K2 APS bytes. The extracted automatic protection switch bytes (K1, K2) are supplied to the
RASE block for further processing and alarm declaration.
An interrupt output is provided that may be activated by declaration or removal of line AIS, line
RDI, protection switching byte failure alarm, a change of APS code value, a single B2 error
event, or a single line REI event. Each interrupt source is individually maskable.
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10.4.1 Line RDI Detect
The Line RDI Detect Block within the RLOP detects the presence of remote defect indication
(LRDI) in the receive stream. Line RDI is declared when a 110 binary pattern is detected in bits
6, 7, and 8 of the K2 byte, for three or five consecutive frames. Line RDI is removed when any
pattern other than 110 is detected in bits 6, 7, and 8 of the K2 byte for three or five consecutive
frames. The LRDI signal is optionally reported on the SALM output pin when enabled by the
LRDISALM Section Alarm Output Control #2 Register bit.
10.4.2 Line AIS Detect
The Line AIS Block detects the presence of an alarm indication signal (LAIS) in the receive
stream. Line AIS is declared when a 111 binary pattern is detected in bits 6, 7, and 8 of the K2
byte, for three or five consecutive frames. Line AIS is removed when any pattern other than 111
is detected in bits 6, 7, and 8 of the K2 byte for three or five consecutive frames. The LRDI signal
is optionally reported on the SALM output pin when enabled by the LAISSALM Section Alarm
Output Control #1 Register bit.
The Error Monitor Block calculates the received line BIP-8 error detection codes based on the
Line Overhead bytes and SPEs of the STS-3 (STM-1) stream. The line BIP-8 code is a bit
interleaved parity calculation using even parity. Details are provided in the references. The
calculated BIP-8 codes are compared with the BIP-8 codes extracted from the following frame.
Any differences indicate that a line layer bit error has occurred. As well, the RLOP can be
configured to count a maximum of only one BIP error per frame. Accumulated B2 errors are
passed to the RASE block for processing and the declaration of signal degrade and signal failure.
This block also extracts the line REI code from the M1 byte. The REI code is contained in bits 2
to 8 of the M1 byte, and represents the number of line BIP-8 errors that were detected in the last
frame by the far end. The REI code value has 25 legal values (0 to 24) for an STS-3 (STM-1)
stream. Illegal values are interpreted as zero errors.
The Error Monitor Block accumulates B2 error events and REI events in two 20-bit saturating
counters that can be read via the microprocessor interface. The contents of these counters may be
transferred to internal holding registers by writing to any one of the counter addresses, or by
using the TIP register bit feature. During a transfer, the counter value is latched and the counter is
reset to zero (or one, if there is an outstanding event). Note: these counters should be polled at
least once per second to avoid saturation.
The B2 error event and REI event counters can be optionally configured to accumulate only
“word” errors. A B2 word error is defined as the occurrence of one or more B2 bit error events
during a frame. In STS-3 (STM-1) framing, a REI word event is defined as the occurrence of one
or more REI bit events during a frame. The B2 error or REI event counter is incremented by one
for each frame in which a B2 word error or REI event occurs.
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10.5 The Receive APS, Synchronization Extractor and Bit Error
Monitor (RASE)
The RASE block performs APS control, monitors the bit error rate, and extracts the
synchronization status.
10.5.1 Automatic Protection Switch (APS) Control
The Automatic Protection Switch (APS) control block of RASE filters and captures the receive
APS channel bytes (K1 and K2) allowing them to be read via the RASE APS K1 register and the
RASE APS K2 register. The bytes are filtered for three frames before being written to these
registers. A protection switching byte-failure-alarm is declared when 12 successive frames have
been received, where no three consecutive frames contain identical K1 bytes. The protection
switching byte failure alarm is removed upon detection of three consecutive frames containing
identical K1 bytes. The detection of invalid APS codes is done in software by polling the RASE
APS K1 Register and the RASE APS K2 Register.
10.5.2 Bit Error Rate Monitor (BERM)
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The Bit Error Monitor Block (BERM) of RASE calculates the received line BIP-24 error
detection code (B2) based on the line overhead and SPE of the STS-3c (STM-1) receive data
stream. The line BIP-24 code is a BIP calculation using even parity. Details are provided in the
references. The calculated BIP-24 code is compared with the BIP-24 code extracted from the B2
byte(s) of the following frame. Any differences indicate that a line layer bit error has occurred.
Up to 192000 (24 BIP/frame x 8000 frames/second) bit errors can be detected per second for
STS-3c (STM-1) rate.
The BERM accumulates these line layer bit errors in a 20 bit saturating counter that can be read
via the microprocessor interface. During a read, the counter value is latched and the counter is
reset to zero (or one, if there is an outstanding event). Note this counter should be polled at least
once per second to avoid saturation that in turn may result in missed bit error events.
The BERM block is able to simultaneously monitor for SF or SD threshold crossing and provide
alarms through software interrupts. The bit error rates associated with the SF or SD alarms are
-3
programmable over a range of 10
to 10-9. Details are provided in the Operations section.
In both declaring and clearing detection states, the accumulated BIP count is continuously
compared against the threshold. This allows to rapidly declaring in the presence of error bursts or
error rates that significantly exceed the monitored BER. This behavior allows meeting the ITU-T
G.783 detection requirements at various error rates (where the detection time is a function of the
actual BER, for a given monitored BER.
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The Synchronization Status Extraction (SSE) Block of RASE extracts the synchronization status
(S1) byte from the line overhead. The SSE block can be configured to capture the S1 nibble after
three or after eight frames with the same value (filtering turned on) or after any change in the
value (filtering turned off). The S1 nibble can be read via the microprocessor interface.
Optionally, the SSE can be configured to perform filtering based on the whole S1 byte. Although
this mode of operation is not standard, it might become useful in the future.
10.6 Receive Transport Overhead Controller (RTOC)
The Receive Transport Overhead Controller block (RTOC) extracts the entire receive transport
overhead on RTOH1-4, along with the nominal 5.184 MHz transport overhead clock,
RTOHCLK1-4, and the transport overhead frame position signal, RTOHFP1-4, allowing
identification of the bit positions in the transport overhead stream.
Individual data channels are also generated on the RSLD1-4 output. RTOHFP1-4 can be used to
identify the required byte alignment on the serial input. The extracted TOH bytes on the above
port may also be forced to all-ones on declaration of LOS/LOF/LAIS/TIM alarms.
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10.7 Ring Control Port
The transmit and receive Ring Control ports provide bit-serial access to the section and line layer
alarm and the maintenance signal status and control. These ports are useful in ring-based
Add/Drop multiplexer applications where alarm status and maintenance signal insertion control
must be passed between separate SPECTRA-4x155s (possibly residing on separate cards). Each
ring control port consists of three signals: clock, data, and frame position. It is intended that the
clock, data, and frame position outputs of the receive ring control port are connected directly to
the clock, data, and frame position inputs of the transmit ring control port of the mate SPECTRA4x155. The alarm status and maintenance signal control information that is passed on the ring
control ports consists of:
• Filtered APS (K1 and K2) byte values.
• Change of filtered APS byte value status.
• Protection switch byte failure alarm status.
• Change of protection switch byte-failure-alarm status.
• Line RDI maintenance signal insertion in the mate SPECTRA-4x155.
• Line AIS maintenance signal insertion in the mate SPECTRA-4x155.
• Line REI information insertion in the mate SPECTRA-4x155.
The same APS byte values must be seen for three consecutive frames before being shifted out on
the receive ring control port. The change of filtered APS byte value status is high for one frame
when a new, filtered APS value is shifted out.
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The protection switch byte failure alarm bit position is high when, after 12 consecutive frames
since the last frame containing a previously consistent byte, no three consecutive frames
containing identical K1 bytes have been received. The bit position is set low when three
consecutive frames containing identical K1 bytes have been received. The change of the
protection switch byte-failure-alarm status bit position is set high for one frame when the alarm
state changes.
The insert line RDI bit position is set high under register control, or when LOS, LOF, or line AIS
alarms are declared. The insert line AIS bit position is set high under register control only.
The insert line REI bit positions are high for one bit position for each detected B2 bit error. Up to
24 line REIs may be indicated per frame for an STS-3 (STM-3c) stream.
10.8 Receive De-multiplexer (RX_DEMUX)
The receive de-multiplexer (RX_DEMUX) block within each channel de-multiplexes the STS3(STM-1) stream into three STS-1(STM-1/AU3) streams or three equivalent STS-1(STM1/AU3)
streams for an STS-3c(ATM1(AU4). In the case of an STS-3(STM1/AU3) stream, the
demultiplexed streams are fed into three master RPPSs. In the case of an STS-3c(STM1/AU4)
stream, the demultiplexed streams are fed into one master RPPS and two slave RPPSs. The slave
slices receiving the equivalent STS-1 #2 and #3.
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The de-multiplexer also generates the low speed clock to accompany the streams into the slices.
10.9 Receive Path Processing Slice (RPPS)
The Receive Path Processing Slice (RPPS) of the RASE block provides path-processing
termination for the four STS-3/3c (STM-1/AU-3/AU-4) streams received from the RLOP blocks.
The path processing includes:
• Pointer interpretation.
• Path overhead and SPE (VC) extraction.
• Path level alarm and performance monitoring.
• Path trace identifier message (J1 bytes) extraction and processing.
Plesiochronous frequency offsets between the receive data stream and the Drop bus are
accommodated by pointer adjustments. PRBS payload generation and monitoring is also
supported on a per STS (AU) basis.
12 RPPSs (RPPS#1 to RPPS#12), arranged in four groups of three RPPSs each, are required to
process the four STS-3 (STM-1) receive streams from the RLOP blocks. Each channel can be
independently configured to process STS-3 (STM-1/AU-3) or STS-3c (STM-1/AU-4) streams.
An STS-3 (STM-1/AU-3) stream is processed as three independent STS-1 (STM-0/AU-3)
streams by the individual RPPSs in the group.
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In processing an STS-3c (STM-1/AU-4), the first STS-1 (STM-0/AU-3) equivalent stream will be
processed by an RPPS (for example, RPPS#1) configured as the master. The master RPPS
controls two slave RPPSs (for example, RPPS#2, RPPS#3) that process the second and third
STS-1 (STM-0/AU-3) equivalent streams respectively. The processing of a concatenated stream
is coordinated by the control signals originating from the master RPPS and status information fed
back from the slave RPPSs.
The path overhead bytes extracted by the RPPSs from all the receive STS-1 (STM-0/AU-3) or
STS-3c (STM-1/AU-4) streams are extracted and serialized on an output RPOH, which is a
multiplexed output signal. The path overhead bytes of all four channels are multiplexed onto
RPOH. Output RPOHFP is provided to identify the most significant bit of the path trace byte (J1)
of channel #1 first STS-1 (STM-0/AU-3) or STS-3c (STM-1/AU-4) on RPOH.
Note: The path overhead bytes are provided on RPOH at close to twice the rate in which they are
received to facilitate the multiplexing of the extracted data from the various RPPSs on to a single
serial output. Output RPOHEN is provided to mark the valid (fresh) path overhead bytes on
RPOH. The path overhead clock, RPOHCLK, is nominally a 12.96 MHz clock. RPOH,
RPOHEN, and RPOHFP are updated with timing aligned to RPOHCLK.
Received path BIP errors and receive path alarms for all the receive STS-1 (STM-0/AU-3) or
STS-3c (STM-1/AU-4) streams of a SPECTRA-4x155 channel are communicated to the
corresponding transmit path processing slices (TPPSs) in a mate SPECTRA-4x155 via the receive
alarm port. The port carries the count of received path BIP errors. Detected receive alarms are
reported in the alarm port and will trigger the corresponding remote TPOP to signal path RDI in
the transmit stream.
Under a no transmit AIS-L condition, the receive alarm port also reports the APS bytes (K1, K2)
that are placed on the transmit stream of the SPECTRA-4x155. In conjunction with the transmit
alarm port of a mate SPECTRA-4x155, the working SPECTRA-4x155 can control the APS bytes
of the protection SPECTRA-4x155. Under AIS-L generation on the transmit stream, the K1 and
K2 bytes extracted are those that would have been transmited if it were not for the forcing of AISL.
The PRBS generator of an RPPS can be enabled to generate the Drop bus transport frame in
addition to the payload. For an STS-3c (STM-1/AU-4) stream, the PRBS generator in each of the
three RPPSs required to process the concatenated stream will generate one third (one in three) of
the PRBS payload sequence. A complete PRBS payload sequence is produced when these three
partial sequences are byte interleaved. The PRBS generator in the master RPPS co-ordinates the
PRBS generation by itself and by its counterparts in the two slave RPPSs.
When enabled, the PRBS monitor of an RPPS will synchronize itself to the receive payload
sequence in an STS-1 (STM-0/AU-3) or equivalent stream. If it is successful in finding the
pseudo-random sequence, then pattern errors detected will be accumulated in the corresponding
error counter. For an STS-3c (STM-1/AU-4) stream, the PRBS monitor, in each of the three
RPPSs required to process the concatenated stream, will independently validate one third (one in
three) of the PRBS payload sequence.
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The Receive Path Overhead Processor (RPOP) of RPPS provides pointer interpretation,
extraction of path overhead, extraction of the SPE (VC), and path level alarm and performance
monitoring.
Pointer Interpreter
The Pointer Interpreter interprets the incoming pointer (H1, H2) as specified in the references.
The pointer value is used to determine the location of the path overhead (the J1 byte) in an STS-1
(STM-0/AU-3) or equivalent stream. A finite state machine can model the algorithm. Within the
pointer interpretation algorithm three states are defined as shown below:
• NORM_state (NORM).
• AIS_state (AIS).
• LOP_state (LOP).
The transition between states will be consecutive events (indications). Refer to Figure 6. An
example is when three consecutive AIS indications to go from the NORM_state to the AIS_state.
The kind and number of consecutive indications activating a transition is chosen such that the
behavior is stable and insensitive to low BER. The only transition on a single event is the one
from the AIS_state to the NORM_state after receiving a NDF enabled with a valid pointer value.
Note: Since the algorithm only contains transitions based on consecutive indications, this implies
that, for example, non-consecutively received invalid indications do not activate the transitions to
the LOP_state.
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inc_reqMajority of I bits inverted + no majority of D bits inverted.
dec_reqMajority of D bits inverted + no majority of I bits inverted.
Notes
1. Active offset is defined as the accepted current phase of the SPE (VC) in the NORM_state and is
undefined in the other states.
2. Enabled NDF is defined as the following bit patterns: 1001, 0001, 1101, 1011, 1000.
3. Disabled NDF is defined as the following bit patterns: 0110, 1110, 0010, 0100, 0111.
4. The remaining six NDF codes (0000, 0011, 0101, 1010, 1100, 1111) result in an inv_ndf indication.
5. The ss bits are unspecified in SONET and has bit pattern 10 in SDH.
6. The use of ss bits in definition of indications may be optionally disabled.
7. The requirement for previous NDF_enable, inc_ind or dec_ind be more than 3 frames ago may be
optionally disabled.
8. new_point is also an inv_point.
9. LOP is not declared if all the following conditions exist:
• The received pointer is out of range (>782),
• The received pointer is static,
• The received pointer can be interpreted, according to majority voting on the I and D bits, as a
positive or negative justification indication,
•After making the requested justification, the received pointer continues to be interpretable as a
pointer justification.
When the received pointer returns to an in-range value, the SPECTRA-4x155 will interpret it correctly.
10. LOP will exit at the third frame of a three frame sequence consisting of one frame with NDF enabled
followed by two frames with NDF disabled, if all three pointers have the same legal value.
11. For the purposes of 8xNDF_enable only, the requirement of the pointer to be within the range of 0 to
782 may be optionally disabled.
Table 2 defines the transitions indicated in the state diagram.
2. 3 x new_point takes precedence over other events and if the IINVCNT bit is set resets the inv_point
count.
3. All three offset values received in 3 x eq_new_point must be identical.
4. "Consecutive event counters" are reset to zero on a change of state except for consecutive NDF count.
In an STS-1 (STM-0/AU-3) stream, the Pointer Interpreter detects:
• Loss of Pointer (LOP).
• Path AIS (PAIS).
• LOP-concatenated (LOPCON), when RPOP is operating as in a slave RPPS.
• Path AIS-concatenated (PAISCON), when RPOP is operating as in a slave RPPS.
The Pointer Interpretor declares LOP on entry to the LOP_state as a result of eight consecutive
invalid pointers or eight consecutive NDF-enabled indications. Path AIS is optionally inserted in
the Drop bus when LOP is declared. The alarm condition is reported in the receive alarm port and
is optionally returned to the source node by signaling the corresponding Transmit Path Overhead
Processor in the local SPECTRA-4x155 to insert a path RDI indication.
The Pointer Interpretor declares PAIS on entry to the AIS_state after three consecutive AIS
indications. Path AIS is inserted in the Drop bus when AIS is declared. The alarm condition
reported in the receive alarm port and is optionally returned to the source node by signaling the
corresponding Transmit Path Overhead Processor in the local SPECTRA-4x155 to insert a path
RDI indication.
In an equivalent STS-1 (STM-0/AU-3) stream when RPOP is operating in a slave RPPS, the
Pointer Interpretor declares LOPCON on entry to the LOPCON_state as a result of eight
consecutive pointers with values other than concatenation indications (‘b1001 xx 1111111111).
Path AIS is optionally inserted in the Drop bus when LOPCON is declared. The alarm condition
is reported in the receive alarm port and is optionally returned to the source node by signaling the
corresponding Transmit Path Overhead Processor in the local SPECTRA-4x155 to insert a path
RDI indication. Alternatively, if in-band error reporting is enabled, the path RDI bit in Drop bus
G1 byte is set to indicate the LOP alarm to the TPOP in a remote SPECTRA-4x155.
In an equivalent STS-1 (STM-0/AU-3) stream when RPOP is operating in a slave RPPS, the
Pointer Interpretor declares PAISCON on entry to the AISC_state after three consecutive AIS
indications. Path AIS is optionally inserted in the Drop bus when AISC is declared. The alarm
condition reported in the receive alarm port and is optionally returned to the source node by
signaling the corresponding Transmit Path Overhead Processor in the local SPECTRA-4x155 to
insert a path RDI indication. Alternatively, if in-band error reporting is enabled, the path RDI bit
in Drop bus G1 byte is set to indicate the PAIS alarm to the TPOP in a remote SPECTRA-4x155.
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Invalid pointer indications (inv_point), invalid NDF codes, new pointer indications (new_point),
discontinuous change of pointer alignment, and illegal pointer changes are also detected and
reported by the Pointer Interpreter block via register bits. An invalid NDF code is any NDF code
that does not match the NDF-enabled or NDF-disabled definitions. The third occurrence of equal
new_point indications (3 x eq_new_point) is reported as a discontinuous change of pointer
alignment event (DISCOPA) instead of a new pointer event and the active offset is updated with
the receive pointer value. An illegal pointer change is defined as a inc_ind or dec_ind indication
that occurs within three frames of the previous inc_ind, dec_ind or NDF_enable indications.
Illegal pointer changes may be optionally disabled via register bits.
The active offset value is used to extract the path overhead from the incoming stream and can be
read from an internal register.
Multiframe Framer
The multiframe alignment sequence in the path overhead H4 byte is monitored for the bit patterns
of 00, 01, 10, 11 in the two least significant bits. If an unexpected value is detected, the primary
multiframe will be kept, and a second multiframe process will, in parallel, check for a phase shift.
The primary process will enter an out-of-multiframe state (OOM). A new multiframe alignment is
chosen, and OOM state is exited when four consecutive correct multiframe patterns are detected.
Loss-of-multiframe (LOM) is declared after residing in the OOM state for eight frames without
re-alignment. A new multiframe alignment is chosen, and LOM state is exited when four
consecutive correct multiframe patterns are detected.
Error Monitoring
Three 16-bit counters are provided to accumulate path BIP-8 errors (B3) and path remote error
indications (REI). The contents of the counters may be transferred to holding registers, and the
counters reset under microprocessor control.
Path BIP-8 errors are detected by comparing the path BIP-8 byte (B3) extracted from the current
frame with the path BIP-8 computed for the previous frame. BIP-8 errors are selectable to be
counted as bit errors or as block errors via register bits. When processing a concatenated stream,
the RPOP in a master RPPS will include the BIP-8 values computed by its slave RPPSs in the
generation of the actual BIP-8 for the stream. When in-band error reporting is enabled, the error
count is inserted into the path status byte (G1) of the Drop bus.
Path REIs are detected by extracting the 4-bit path REI field from the path status byte (G1). The
legal range for the 4-bit field is between 0000 and 1000, representing zero to eight errors. Any
other value is interpreted as zero errors
Path RDI alarm is detected by extracting bit 5 of the path status byte. The PRDI signal is set high
when bit 5 is set high for five/ten consecutive frames. PRDI is set low when bit 5 is low for
five/ten consecutive frames.
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The Enhanced RDI alarm is detected when the enhanced RDI code in bits 5, 6, 7 of the path
status byte indicates the same error codepoint for five/ten consecutive frames. The Enhanced RDI
alarm is removed when the enhanced RDI code in bits 5, 6, 7 of the path status byte indicates the
same non error codepoint for five/ten consecutive frames.
The SPECTRA-4x155 receive section does not support inband error reporting of RDI codes.
Path Overhead Extract
Path overhead bytes are extracted from an STS-1 (STM-0/AU-3) or equivalent stream that is
being processed by the RPOP. When processing a concatenated stream, only the RPOP in a
master RPPS will provide valid path overhead bytes. The extracted path overhead bytes will be
serialized and multiplexed on to RPOH by higher level logic.
Receive Alarm Port
Path BIP errors and path RDIs for an STS-1 (STM-0/AU-3) or equivalent stream that are being
processed by the RPOP are provided to the higher level logic for communicating via the Receive
Alarm Port to the corresponding transmit path overhead processor (TPOP) in a mate SPECTRA4x155. There is an independent Receive Alarm Port stream for each four channels of the
SPECTRA-4X155. When processing a concatenated stream, only the RPOP in the master RPPS
will provide the valid path BIP error count and path RDI code for the stream.
10.9.2 Receive Path Trace Buffer (SPTB)
In mode 1 operation, the receive portion of the SONET/SDH Path Trace Buffer (SPTB) of RPPS
captures the received path trace identifier message (J1 bytes) into microprocessor readable
registers. It contains four pages of trace message memory. They are:
• The transmit message page.
• The capture page.
• The accepted page.
• The expected page.
Path trace identifier data bytes from the receive stream are written into the capture page. The
expected identifier message is downloaded by the microprocessor into the expected page. On
receipt of a trace identifier byte, it is written into next location in the capture page. The received
byte is compared with the data from the previous message in the capture page. The identifier
message is accepted if it is received unchanged three times, or optionally, five times. The
accepted message is then compared with the expected message.
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If enabled, an interrupt is generated when the accepted message changes from “matching” the
expected message to “mismatching” vice versa. If the current message differs from the previous
message the unstable counter is incremented by one. When the unstable count reaches eight, the
received message is declared unstable. The received message is declared stable and the unstable
counter reset, when the received message passes the persistency criterion (three or five identical
receptions) for being accepted. An interrupt may be optionally generated on entry to and exit from
the unstable state. Optionally, path AIS may be inserted in the Drop bus when the receive
message is in the mismatched or unstable state.
The length of the path trace identifier message is selectable between 16-bytes and 64-bytes. When
programmed for 16-byte messages, the SPTB synchronizes to the byte with the most significant
bit set to high and places the byte at the first location in the capture page. When programmed for
64-byte messages, the SPTB synchronizes to the trailing carriage return (CR = 0DH), line feed
(LF = 0AH) sequence and places the next byte at the head of the capture page. This enables the
path trace message to be appropriately aligned for interpretation by the microprocessor.
Synchronization may be disabled, in which case, the memory acts as a circular buffer.
Mode 2 path trace identifier operation is supported. For mode 2 support, a stable message is
declared when forty eight of the same section trace identifier message (J1) bytes are received.
Once in the stable state, an unstable state is declared when one or more errors are detected in
three consecutive sixteen byte windows.
The path signal label (PSL) found in the path overhead byte (C2) is processed. An incoming PSL
is accepted when it is received unchanged for five consecutive frames. The accepted PSL is
compared with the provisioned value. The PSL match/mismatch state is determined as follows:
Table 3 Path Signal Label Match/Mismatch State Table.
Expected PSLAccepted PSLPSLM State
0000Match
0001Mismatch
00
0100Mismatch
0101Match
01
X ≠ 00, 01
X ≠ 00, 01
X ≠ 00, 01
X ≠ 00, 01
X ≠ 00
X ≠ 01
00Mismatch
01Match
XMatch
YMismatch
Mismatch
Match
Each time an incoming PSL differs from the one in the previous frame, the PSL unstable counter
is incremented. Thus, a single bit error in the PSL in a sequence of constant PSL values will cause
the counter to increment twice, once on the errored PSL and again on the first error-free PSL. The
incoming PSL is considered unstable, when the counter reaches five. The counter is cleared when
the same PSL is received for five consecutive frames.
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In normal operation, only the status of the SPTB in a master RPPS should be monitored.
10.9.3 Receive TelecomBus Aligner (RTAL)
The Receive TelecomBus Aligner (RTAL) block of RPPS takes the payload data from an STS-1
(STM-0/AU-3) or equivalent stream from the RPOP and inserts it in a TelecomBus Drop bus. It
aligns the frame of the received STS-1 (STM-0/AU-3) or equivalent stream to the frame of the
Drop bus. The alignment is accomplished by recalculating the STS (AU) payload pointer value
based on the offset between the transport overhead of the receive stream and that of the Drop bus.
When processing a concatenated stream, only the RTAL in the master RPPS will be performing
the pointer adjustment calculation. The RTALs in the slave RPPSs will follow the new alignment
of the RTAL in the master RPPS.
Frequency offsets from plesiochronous network boundaries, or the loss of a primary reference
timing source and phase differences from normal network operation between the receive data
stream and the Drop bus are accommodated by pointer adjustments in the Drop bus. Drop bus
pointer justification events are indicated and are accumulated in the Performance Monitor
(PMON) block. Large differences between the number and type of received pointer justification
events as indicated by the RPOP block, and pointer justification events generated by the RTAL
block may indicate network synchronization failure.
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When the RPOP block detects a loss of multiframe, the RTAL may optionally insert all-ones in
the tributary portion of the SPE. The path overhead column and the fixed stuff columns are
unaffected.
The RTAL may optionally insert the tributary multiframe sequence and clear the fixed stuff
columns. The tributary multiframe sequence is a 4-byte pattern ('hFC, 'hFD, 'hFE, 'hFF) applied
to the H4 byte. The H4 byte of the frame containing the tributary V1 bytes is set to 'hFD. The
fixed stuff columns of a SPE (VC) may optionally be over-written all-zeros in the fixed stuff
bytes.
Elastic Store
The Elastic Store perform rate adaptation between the receive data stream and the Drop bus. The
entire received payload, including path overhead bytes, is written into in a first-in-first-out (FIFO)
buffer at the receive byte rate. Each FIFO word stores a payload data byte and a one bit tag
labeling the J1 byte. Receive pointer justifications are accommodated by writing into the FIFO
during the negative stuff opportunity byte or by not writing during the positive stuff opportunity
byte. Data is read out of the FIFO in the Elastic Store block at the Drop bus rate by the Pointer
Generator. Analogously, pointer justifications on the Drop bus are accommodated by reading
from the FIFO during the negative stuff opportunity byte or by not reading during the positive
stuff opportunity byte.
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The FIFO read and write Addresses are monitored. Pointer justification requests will be made to
the Pointer Generator based on the proximity of the Addresses relative to programmable
thresholds. The Pointer Generator schedules a pointer increment event if the FIFO depth is below
the lower threshold and a pointer decrement event if the depth is above the upper threshold. FIFO
underflow and overflow events are detected and path AIS is optionally inserted in the Drop bus
for three frames to alert downstream elements of data corruption.
Pointer Generator
The Pointer Generator generates the Drop bus pointer (H1, H2) as specified in the references. The
pointer value is used to determine the location of the path overhead (the J1 byte) in the Drop bus
STS-1 (STM-0/AU-3) stream. The algorithm can be modeled by a finite state machine. Within the
pointer generator algorithm, five states are defined as shown below:
• NORM_state (NORM).
• AIS_state (AIS).
• NDF_state (NDF).
• INC_state (INC).
• DEC_state (DEC).
The transition from the NORM to the INC, DEC, and NDF states is initiated by events in the
Elastic Store (ES) block. The transition to/from the AIS state are controlled by the pointer
interpreter (PI) in the Receive Path Overhead Processor block. The transitions from INC, DEC,
and NDF states to the NORM state occur autonomously with the generation of special pointer
patterns.
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1. A frame offset discontinuity occurs if an incoming NDF enabled is received, or if an ES
overflow/underflow occurred.
The autonomous transitions indicated in the state diagram are defined in Table 5.
Table 5 Pointer Generator Transition Description
TransitionDescription
inc_indTransmit the pointer with NDF disabled and inverted I bits, transmit a stuff byte in
the byte after H3, increment active offset.
dec_indTransmit the pointer with NDF disabled and inverted D bits, transmit a data byte
in the H3 byte, decrement active offset.
NDF_enableAccept new offset as active offset, transmit the pointer with NDF enabled and
new offset.
norm_pointTransmit the pointer with NDF disabled and active offset.
AIS_indActive offset is undefined, transmit an all-1's pointer and payload.
Notes
1. Active offset is defined as the phase of the SPE (VC).
2. The ss bits are undefined in SONET, and has bit pattern 10 in SDH
3. Enabled NDF is defined as the bit pattern 1001.
4. Disabled NDF is defined as the bit pattern 0110.
When operating in a slave RPPS, the concatenation indications (‘b1001 xx 1111111111) will be
generated in the pointer bytes (H1 and H2).
A piece of tandem connection originating equipment should signal incoming signal failure by
setting the IEC field and the payload bytes to all-ones. A piece of tandem connection terminating
equipment should detect ISF by only examining the IEC field for all-ones. If the upstream tandem
connection originating equipment inserts a malformed, non-compliant ISF condition where the
payload bytes are not all-ones, the SPECTRA-4X155 toggles in and out of the ISF state.
However, in real systems, this behaviour should not be observed because the upstream tandem
connection originating equipment inserts a standards compliant ISF condition.
10.9.4 Drop Bus PRBS Generator and Monitor (DPGM)
The Drop bus Pseudo-random bit sequence Generator and Monitor (DPGM) block of RPPS
generates and monitors an unframed 2
equivalent stream on the Drop bus.
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23
-1 payload test sequence in an STS-1 (STM-0/AU-3) or
The PRBS generator of the DPGM can be configured to overwrite the payload bytes on the Drop
bus as well as autonomously generate both the payload bytes and the framing on the Drop bus.
The path overhead column and, optionally, the fixed stuff columns in an STS-1 (STM-0/AU-3)
stream are not overwritten with PRBS payload bytes.
When processing a concatenated stream, the DPGM in a master RPPS co-ordinate the distributed
PRBS generation by itself and its counterparts in the slave RPPSs. Each DPGM will generate one
third (1 in 3) of the complete PRBS sequence for an STS-3c (STM-1/AU-4) stream. The master
DPGM will be generating the partial sequence for the 1
and subsequent SPE bytes occurring at a 3-byte interval. The next partial sequence for the 2
st
(after the transport overhead columns)
nd
and
every third bytes thereafter will be generated by the first (in the order of payload generation)
slave DPGM and so on. This corresponds to each DPGM processing an equivalent STS-1 (STM0/AU-3) stream in the concatenated stream.
To ensure that the DPGM blocks in the slave RPPSs are synchronized with the DPGM in the
master RPPS, a signature derived from its current state is continuously broadcasted by the master
DPGM to allow the slave DPGM blocks to check their relative states. A DPGM operating in a
slave RPPS continuously generates a matching signature based on its own state. A signature mismatch is flagged as an out-of-signature state by the slave DPGM. A re-synchronization of the
PRBS generation is initiated by the master DPGM (under software control) when one or more
slave DPGMs report an out-of-signature state in relation to that of the master DPGM. This
involves a re-starting of PRBS generation in each DPGM from a pre-determined state according
to the order of generation (transmission or reception) assigned to a particular DPGM.
When a path overhead byte position is encountered by the master DPGM in an STS-3c (STM1/AU-4) stream, the master DPGM will not generate the next PRBS data byte, this task is left to
the (first) slave DPGM which is next in line to generate a PRBS data byte. The second slave
DPGM (in the order of generation) will now generate the PRBS data byte which is supposed to be
generated by the first slave DPGM and so on. This means that the current states of the slave
DPGM blocks will be re-aligned relative to the new state of the master DPGM to collectively skip
over the path overhead byte position encountered by the master DPGM.
The PRBS monitor of the DPGM block monitors the recovered payload data for the presence of
an unframed 2
23
-1 test sequence and accumulates pattern errors detected based on this pseudorandom pattern. The DPGM declares synchronization when a sequence of 32 correct pseudorandom patterns (bytes) are detected consecutively. Pattern errors are only counted when the
DPGM is in synchronization with the input sequence. When 16 consecutive pattern errors are
detected, the DPGM will fall out of synchronization and it will continuously attempt to resynchronize to the input sequence until it is successful.
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When processing a concatenated stream, individual DPGM blocks, including the master DPGM,
independently monitor their corresponding one third (1 in 3) of the complete PRBS payload
sequence according to the SONET/SDH concatenated mode of the stream. The master DPGM
will be monitoring the partial sequence contained in the 1
and subsequent SPE bytes occurring at a 3-byte interval. The next partial sequence contained in
nd
and every third bytes thereafter will be validated by the first (in the order of payload
the 2
st
(after the transport overhead columns)
reception) slave DPGM and so on. Individual DPGM synchronization status and error count
accumulation are provided. Optionally, an interrupt can be generated by the DPGM whenever a
loss of synchronization or re-synchronization occurs.
Path overhead bytes and fixed stuff columns in the receive concatenated stream will be
collectively skipped over as described for the PRBS generator of the DPGM. To ensure that all
payload bytes (all STS-1 (STM-0/AU-3) or equivalent streams) in a concatenated stream together
contain a single PRBS sequence, the signature generation by the master DPGM and signature
matching by the slave DPGM monitors will be performed as described for the PRBS generation.
Individual DPGM can only declared that has synchronized to the receive PRBS sequence when it
has synchronized to its corresponding partial sequence and its has detected no signature
mismatch.
10.9.5 Pointer Justification Monitor
The Pointer Justification Monitor (PMON) of RPPS accumulates pointer justification events
(PJE) events in counters over intervals which are defined by the supplied transfer clock signal.
The counters saturate at 255. Four counters are provided in order to accumulate four types of
events; increment and decrement of receive or transmit pointers. The receive pointer events can
be those of the receive stream before the FIFO or can be those of the Drop bus after rate adaption
in the RTAL FIFO.
When the transfer signal is applied by writing to the TIP register bit, the PMON transfers the
counter values into holding registers and resets the counters to begin accumulating error events
for the next interval. The counters are reset in such a manner that error events occurring during
the reset period are not missed. Writing to internal registers can also trigger this transfer.
10.10 Transmit Path Processing Slice (TPPS)
The Transmit Path Processing Slice (TPPS) generates transport frame alignment, inserts path
overhead and the SPE as well as path level alarm signals and path BIP-8 (B3) for an STS-1
(STM-0/AU-3) SPE (VC-3) or equivalent data stream from the Add bus. Path trace identifier
message (J1 bytes) can also be inserted. Plesiochronous frequency offsets and phase differences,
from normal network operation, between the Add bus and the line are accommodated by pointer
adjustments in the transmit stream. The TPPS can optionally interpret the pointer (H1, H2) and
detect alarm conditions (for example, PAIS) in the STS-1 (STM-0/AU-3) SPE (VC-3) or
equivalent data stream from the Add bus. PRBS payload generation and monitoring is also
supported on a per STS (AU) basis.
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12 TPPSs (TPPS#1 to TPPS#12), arranged in four groups of three TPPSs, are required to process
the four STS-3/3c (STM-1/AU-3/AU-4) stream from the Add bus. Each channel can be
independently configured to process STS-3 (STM-1/AU-3) or STS-3c (STM-1/AU-4) streams.
An STS-3 (STM-1/AU-3) stream is processed as three independent STS-1 (STM-0/AU-3)
streams by the individual TPPSs in the group.
In processing an STS-3c (STM-1/AU-4), the first STS-1 (STM-0/AU-3) equivalent stream will be
processed by a TPPS (for example, TPPS#1) configured as the master. The master TPPS controls
two slave TPPSs (for example, TPPS#2, TPPS#3) which process the second and third STS-1
(STM-0/AU-3) equivalent streams respectively. Processing of a concatenated stream is
coordinated by the control signals originating from the master TPPS and status information
feedback from the slave TPPSs.
Received path BIP errors (REI) and path RDIs for all the receive STS-1 (STM-0/AU-3) streams
or STS-3c (STM-1/AU-4) streams from the RPPSs in a remote SPECTRA-4x155 are
communicated to the corresponding TPPSs in the local SPECTRA-4x155 via the transmit alarm
port. The transmit alarm port also contains the transmit APS bytes (K1, K2) of the (remote)
working SPECTRA-4x155. In the protection (local) SPECTRA-4x155, the APS bytes in the
transmit stream may be optionally sourced from the transmit alarm port.
The PRBS generator of an TPPS can be enabled to overwrite the transmit stream framing in
addition to the payload. For an STS-3c (STM-1/AU-4) stream, the PRBS generator in each of the
three TPPSs required to process the concatenated stream will generate one third (1 in 3) of the
PRBS payload sequence. A complete PRBS payload sequence is produced when these three
partial sequences are byte interleaved downstream. The PRBS generator in the master TPPS coordinates the PRBS generation by itself and its counterparts in the two slave TPPSs.
When enabled, the PRBS monitor of a TPPS will attempt to synchronize to the payload sequence
in the STS-1 (STM-0/AU-3) SPE (VC-3) or equivalent data stream from the Add bus. If it is
successful in finding the supported pseudo-random sequence then pattern errors detected will be
accumulated in the corresponding error counter. For an STS-3c (STM-1/AU-4) stream, the PRBS
monitor in each of the three TPPSs required to process the concatenated stream will
independently validate one third (1 in 3) of the PRBS payload sequence.
10.10.1 Add Bus PRBS Generator and Monitor (APGM)
The Add bus Pseudo-random bit sequence Generator and Monitor (APGM) block of TPPS
generates and monitors an unframed 2
(VC-3) or equivalent data stream from the Add bus.
The PRBS generator of the APGM can be configured to overwrite the payload bytes of the Add
bus STS-1 (STM-0/AU-3) SPE (VC3) data stream with an unframed 2
autonomously generate both the payload bytes and the SPE (VC3) frames. The PRBS monitor of
the APGM block monitors the payload data from the Add bus for the presence of an unframed
23
2
-1 sequence and accumulates pattern errors detected based on this pseudo-random pattern.
23
-1 payload test sequence in an STS-1 (STM-0/AU-3) SPE
23
-1 sequence as well as
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The Transmit Pointer Interpreter Processor (TPIP) block of TPPS takes STS-1 (STM-0/AU-3)
SPE (VC-3) or equivalent data stream from the Add bus, interprets the pointer (H1, H2), indicates
the J1 byte location and detects alarm conditions (for example, PAIS).The indicated J1 byte
position will be used only when the APFEN bit in the Add Bus Configuration register is set high
or the DISJ1V1 bit is set high in the TPPS Path Configuration register of a specific TPPS. When
supplying a valid telecom Add interface with valid J1 pulse, the TPIP pointer alarms may still be
used.
Pointer Interpreter
The TPIP block allows the SPECTRA-4x155 to operate with TelecomBus-like back plane
systems that do not indicate the J1 byte position. The TPIP block can be enabled using the
DISJ1V1 bit in the SPECTRA-4x155 Path Configuration register. When enabled, the TPIP takes
a STS-1 (STM-0/AU-3) SONET/SDH stream from the System Side Interface block, processes the
stream, identifies the J1 byte location and provides the stream to the corresponding Transmit
TelecomBus Aligner block. The block will interpret the Add Bus pointer to determine the J1 byte
location. Refer to section 10.9.1 for details of the interpreter state machine.
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The same pointer interpreter will be used to determine the J1 byte location when the APFEN
control bit is set high. In this mode the Add bus will only a frame pulse identifying the 1
st
SPE
byte of the Add bus.
When supplying a valid J1 pulse which is to be used from the Add Bus (DISJ1V1 and AFP set
low), the pointer interpreter will still run and all declared alarms are still valid provided there are
valid H1, H2 pointers on the Add bus. These alarms can also be used to force consequential
actions.
Slave TPIP blocks are also able to verify for a valid concatenation indicator in the H1 and H2
bytes.
The LOP, LOPCON or PAISCON alarms declared by the pointer interpreter block can be used to
force transmit path AIS.
Error Monitoring
Three 16-bit counters are provided to accumulate path BIP-8 errors (B3) and path REI. The
contents of the counters may be transferred to holding registers, and the counters reset under
microprocessor control. Refer to section 10.9.1 for details on error monitoring.
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The multiframe alignment sequence in the path overhead H4 byte is monitored for the bit patterns
of 00, 01, 10, 11 in the two least significant bits. If an unexpected value is detected, the primary
multiframe will be kept, and a second multiframe process will, in parallel, check for a phase shift.
The primary process will enter OOM. A new multiframe alignment is chosen, and OOM state is
exited when four consecutive correct multiframe patterns are detected. LOM is declared after
residing in the OOM state for eight frames without re-alignment. A new multiframe alignment is
chosen, and LOM state is exited when four consecutive correct multiframe patterns are detected.
The LOM alarm declared by block can be used to force transmit tributary AIS.
10.10.3 Transmit TelecomBus Aligner (TTAL)
The Transmit TelecomBus Aligner (TTAL) block of TPPS takes the STS-1 (STM-0/AU-3) SPE
(VC-3) or equivalent data stream from the Add bus and aligns it to the frame of the transmit
stream. The alignment is accomplished by recalculating the STS (AU) payload pointer value
based on the offset between the transport overhead of the Add bus and the transmit stream. In
processing a concatenated stream, the TTAL in the master TPPS will perform the pointer offset
recalculation and the TTAL’s in the slave TPPSs will follow the new pointer offset.
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Frequency offsets from plesiochronous network boundaries, or the loss of a primary reference
timing source and phase differences, from normal network operation, between the Add bus and
the transmit stream are accommodated by pointer adjustments in the transmit stream. For a
concatenated stream, the master TTAL will compute and perform the appropriate pointer
adjustment to which the slave TTALs will follow.
The TTAL may optionally insert the tributary multiframe sequence and clear the fixed stuff
columns. The tributary multiframe sequence is a four byte pattern ('hFC, 'hFD, 'hFE, 'hFF)
applied to the H4 byte. The H4 byte of the frame containing the tributary V1 bytes is set to 'hFD.
The fixed stuff columns of an SPE (VC) may optionally be over-written with all-zeros in the
fixed stuff bytes.
Elastic Store
The Elastic Store block performs rate adaptation between the Add bus and the transmit stream.
The entire Add bus payload, including path overhead bytes, is written into in a FIFO buffer at the
Add bus byte rate. Each FIFO word stores a payload data byte and a one bit tag labeling the J1
byte. Add bus pointer justifications are accommodated by writing into the FIFO during the
negative stuff opportunity byte or by not writing during the positive stuff opportunity byte. Data
is read out of the FIFO in the Elastic Store block at the transmit stream rate by the Pointer
Generator block. Analogously, pointer justifications on the transmit stream are accommodated by
reading from the FIFO during the negative stuff-opportunity-byte or by not reading during the
positive stuff-opportunity-byte.
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The FIFO read and write addresses are monitored. Pointer justification requests are made to the
Pointer Generator block based on the proximity of the addresses relative to programmable
thresholds. The Pointer Generator block schedules a pointer increment event if the FIFO depth is
below the lower threshold and a pointer decrement event if the depth is above the upper
threshold. FIFO underflow and overflow events are detected and path AIS is inserted in the
transmit stream for three frames to alert downstream elements of data corruption.
Pointer Generator
The Pointer Generator Block generates the transmit stream pointer (H1, H2) as specified in the
references. The pointer value is used to determine the location of the path overhead (the J1 byte)
in the transmit STS-1 (STM-0/AU-3) or equivalent stream. The algorithm is identical to that
described in the Receive TelecomBus Aligner (RTAL) block. Refer to section 10.9.3.
When operating in a slave TPPS, the concatenation indications (‘b1001 xx 1111111111) will be
generated in the pointer bytes (H1 and H2) when enabled in the TPOP block.
A piece of tandem connection originating equipment should signal incoming signal failure by
setting the IEC field and the payload bytes to all-ones. Likewise, the equipment should detect ISF
by only examining the IEC field for all-ones. If the upstream tandem connection originating
equipment inserts a malformed, non-compliant ISF condition where the payload bytes are not allones, the SPECTRA-4X155 toggles in and out of the ISF state. However, in real systems, this
behavior should not be observed because the upstream tandem connection originating equipment
inserts a standards compliant ISF condition.
10.10.4 Transmit Path Trace Buffer (SPTB)
The transmit portion of the SONET/SDH Path Trace Buffer (SPTB) sources the path trace
identifier message (J1) for the Transmit Path Overhead Processor (TPOP) block. The length of
the trace message is selectable between 16 bytes and 64 bytes. The SPTB contains one page of
transmit trace identifier message memory. Identifier message data bytes are written by the
microprocessor into the message buffer and delivered serially to the TPOP block for insertion in
the transmit stream. When the microprocessor is updating the transmit page buffer, SPTB may be
programmed to transmit null characters to prevent transmission of partial messages.
10.10.5 Transmit Path Overhead Processor (TPOP)
The Transmit Path Overhead Processor (TPOP) of TPPS provides transport frame alignment
generation, path overhead insertion, insertion of the SPE, insertion of path level alarm signals and
path BIP-8 (B3) insertion.
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The BIP-8 Calculate Block performs a path bit interleaved parity calculation on the SPE (VC) of
the outgoing STS-1 (STM-0/AU-3) or equivalent stream. The fixed stuff columns in the VC-3
format may be optionally excluded from BIP calculations. The resulting parity byte is inserted in
the path BIP-8 (B3) byte position of the subsequent frame. BIP-8 errors may be continuously
inserted under register control for diagnostic purposes.
In processing a concatenated stream, the BIP-8 Calculate Block of the TPOP in the master TPPS
will include calculated BIP-8 values from the slave TPPSs in the final computation of the path
BIP-8 (B3) value of the stream.
Path REI Calculate
The Path REI Calculate Block accumulates path REIs on a per frame basis, and inserts the
accumulated value (up to maximum value of eight) in the path REI bit positions of the path status
(G1) byte. The path REI information is derived from path BIP-8 errors detected by the
corresponding RPOP. The asynchronous nature of these signals implies that more than eight path
REI events may be accumulated between transmit G1 bytes. If more than eight receive Path BIP8 errors are accumulated between transmit G1 bytes, the accumulation counter is decremented by
eight, and the remaining path REIs are transmitted at the next opportunity. Alternatively, path REI
can be accumulated from path REI counts reported on the transmit alarm port when the local
SPECTRA-4x155 is paired with a receive section of a remote SPECTRA-4x155. FEBE errors
may be inserted under register control for diagnostic purposes. Optionally, path REI insertion
may be disabled and the incoming G1 byte passes through unchanged to support applications
where the received path processing does not reside in the local SPECTRA-4x155.
Path RDI Insert
Path RDI may be inserted via the TPOP block. The RDI codes to be inserted into the transmit
stream may be supplied externally via the transmit Alarm Data Port (TAD) or may be
automatically inserted via the receive side of the device and the detected receive alarms. The
RXSEL register bits define the source of the RDI.
Transmit Alarm Port
Received path BIP errors (REI) and RDIs from the RPOPs in a remote SPECTRA-4x155 are
communicated to the corresponding TPOP’s in the local SPECTRA-4x155 via the transmit alarm
port. When the port is enabled, the path BIP error count and the remote defect indication for each
TPOP are sampled from the transmit alarm port and inserted in the path REI and path RDI
positions of the path status byte (G1) in the transmit stream. The APS bytes K1/K2 received on
the the TAD port are inserted by the appropriate channel’s TTOC.
The TAD port can accumulate up to 15 BIP errors. Given the timings of the RAD port, a mate
SPECTRA-4x155 could output 16 errors within one frame period. If eight errors are detected in
two consecutive frames and the timing makes them appear within one frame period, the 16
could be lost.
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The SPE Multiplexer Block multiplexes the payload pointer bytes, the SPE stream, and the path
overhead bytes into the transmit stream. When in-band error reporting is enabled, the path REI
and path RDI bits of the path status (G1) byte has already been formed by the corresponding
Receive Path Overhead Processor and is transmitted unchanged.
10.11 Transmit Multiplexer (TX_REMUX)
The transmit multiplexer (TX_REMUX) block within each channel multiplexes the three STS1(STM-1/AU3) streams or three equivalent STS-1(STM1/AU3) streams into an STS-3(STM1/AU3) or STS-3c(STM1/AU4) stream. In the case of an STS-3(STM1/AU3) stream, the STS1(STM1/AU3) streams are fed in from three master TPPSs. In the case of an STS3c(STM1/AU4) stream, the equivalent STS-1(STM1/AU3) streams are fed in from one master
TPPS and two slave TPPSs. The slave slices fedding in the equivalent STS-1 #2 and #3.
The multiplexer also generates the low speed clock used to time the data stream out of the slices.
10.12 Transmit Transport Overhead Controller (TTOC)
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The Transmit Transport Overhead Controller block (TTOC) allows the transmit transport
overhead bytes (manually), the section or line BIP errors, or payload pointer byte errors to be
inserted.
The complete transport overhead to be inserted at once per channel using TTOH1-4, along with
the nominal 5.184 MHz transport overhead clock, TTOHCLK1-4, and the transport overhead
frame position, TTOHFP1-4. The transport overhead enable signal, TTOHEN1-4, controls the
insertion of transport overhead from TTOH1-4.
The APS bytes K1/K2 received via the TAD port may be optionally inserted via the TTOC logic.
The received K1/K2 on TAD match the transmitted K1/K2 that a mate SPECTRA transmitted.
Individual data channels can be sourced from TSLD1-4. TTOHFP1-4 can be used to identify the
required byte alignment on the serial inputs.
The TTOC block also allows the Unused and National Use bytes in the SONET/SDH TOH to be
set. Refer to Figure 8. Specific registers exist to program fixed values in the Z0 bytes and the S1
byte of the TOH. The REI in the M1 byte may also be manually set by the TTOH1-4 input.
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The Transmit Line Overhead Processor block (TLOP) processes the line overhead of a transmit
STS-3 (STM-1) stream.
10.13.1 APS Insert
The APS Insert Block of TLOP inserts the two APS channel bytes of the Line Overhead (K1 and
K2) into the transmit stream when enabled by an internal register. The inserted K1 and K2 may
also be overwritten via insertion by the TTOC block.
10.13.2 Line BIP Calculate
The Line BIP Calculate Block of TLOP calculates the line BIP-24/8 error detection code (B2)
based on the line overhead and SPE of the transmit stream. The line BIP-24/8 code is a bit
interleaved parity calculation using even parity. Details are provided in the references. The
calculated BIP-24/8 code is inserted into the B2 byte positions of the following frame. BIP-24/8
errors may be continuously inserted under register control for diagnostic purposes. Errors may be
inserted in the B2 code for diagnostic purposes.
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10.13.3 Line RDI Insert
The Line RDI Insert Block of TLOP controls the insertion of RDI. Line RDI may be inserted in
the transmit stream under the control of an external input (TLRDI1-4), or a writeable register. The
bits in the SPECTRA-4x155 Line RDI Control Register controls the immediate insertion of Line
RDI upon detection of various errors in the received SONET/SDH stream. Line RDI may also be
inserted when enabling the Transmit Ring Control port (TRCP) and by setting high the
SENDLRDI bit position. Line RDI is inserted by transmitting the code 110 (binary) in bit
positions 6, 7, and 8 of the K2 byte contained in the transmit stream.
10.13.4 Line REI Insert
The Line REI Insert Block of TLOP accumulates line BIP-24/8 errors (B2) detected by the
Receive Line Overhead Processor and encodes remote error indications in the transmit M1 byte.
Line REI may be inserted automatically in the SONET/SDH stream under the control of the
AUTOLREI bit in the SPECTRA-4x155 Ring Control Register. Receive B2 errors are
accumulated and optionally inserted automatically in bits 2 to 8 of the third Z2/M1 byte of the
transmit STS-3 (STM-1) stream. Up to 24 errors may be inserted per frame.
Line REI may also be inserted when enabling the Transmit Ring Control port (TRCP) and by
setting high the REI bit positions.
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The Transmit Section Overhead Processor (TSOP) provides frame pattern insertion (A1, A2),
scrambling, section level alarm signal insertion, and section BIP-8 (B1) insertion. The TSOP
block operates with a downstream serializer (the PISO block) that accepts the transmit stream in
byte serial format and serializes it at the line rate.
10.14.1 Line AIS Insert
Line AIS insertion results in all bits of the SONET/SDH frame being set to “one” before
scrambling except for the section overhead. The Line AIS Insert Block of TSOP substitutes allones as described when enabled through an internal register or he AIS may optionally be inserted
into the data stream under the control of an external input (TLAIS). Activation or deactivation of
line AIS insertion is synchronized to frame boundaries.
10.14.2 BIP-8 Insert
The BIP-8 Insert Block of TSOP calculates and inserts the BIP-8 error detection code (B1) into
the transmit stream.
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The BIP-8 calculation is based on the scrambled data of the complete STS-3 (STM-1) frame. The
section BIP-8 code is based on a bit interleaved parity calculation using even parity. Details are
provided in the references. The calculated BIP-8 code is then inserted into the B1 byte of the
following frame before scrambling. BIP-8 errors may be continuously inserted under register
control for diagnostic purposes.
10.14.3 Framing and Identity Insert
The Framing and Identity Insert Block of TSOP inserts the framing bytes (A1, A2) and
trace/growth bytes (J0/Z0) into the STS-3 (STM-1) frame. Framing bit errors may be
continuously inserted under register control for diagnostic purposes.
10.14.4 Scrambler
The Scrambler Block of TSOP uses a frame synchronous scrambler to process the transmit stream
when enabled through an internal register accessed via the microprocessor interface. The
7
generating polynomial is x
the references. Note that the framing bytes and the identity bytes are not scrambled. All zeros may
be continuously inserted (after scrambling) under register control for diagnostic purposes.
+ x6 + 1. Precise details of the scrambling operation are provided in
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Document ID: PMC-1990822, Issue 4
The transmit portion of the SONET/SDH Section Trace Buffer (SSTB) sources the section trace
identifier message (J0) for the Transmit Transport Overhead Access block. The length of the trace
message is selectable between 16-bytes and 64-bytes. The section trace buffer contains one page
of transmit trace identifier message memory. Identifier message data bytes are written by the
microprocessor into the message buffer and delivered serially to the Transport Overhead Access
block for insertion in the transmit stream. When the microprocessor is updating the transmit page
buffer, the buffer may be programmed to transmit null characters to prevent transmission of
partial messages.
10.16 Transmit Line Interface
The Transmit Line Interface allows to directly interface the SPECTRA-4x155 with optical
modules (ODLs) or other medium interfaces. This block performs clock synthesis and parallel-toserial conversion on the outgoing 155.52 Mbit/s data stream.
10.16.1 Clock Synthesis
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The transmit clock of the SSTB block may be synthesized from a 19.44 MHz reference. The PLL
filter transfer function is optimized to enable the PLL to track the reference, yet attenuate high
frequency jitter on the reference signal. This transfer function yields a typical low pass corner of
2 MHz, above which reference jitter is attenuated at 12 dB per octave. The design of the loop
filter and PLL is optimized for minimum intrinsic jitter. With a jitter free reference, the intrinsic
jitter is less than 0.01 UI RMS when measured using a band pass filter with a low cutoff
frequency of 12 KHz and a high cutoff frequency of 1.3 MHz.
10.16.2 Parallel-to-Serial Converter (PISO)
The Parallel to Serial Converter (PISO) of SSTB converts the transmit byte serial stream to a bit
serial stream. The transmit bit serial stream appears on the TXD1-4+/- PECL output.
10.17 Add/Drop Bus Time-Slot Interchange (TSI)
The Time-Slot Interchange (TSI) logic at the Telecom Add and Drop buses supports the grooming
of the corresponding receive and transmit SONET/SDH streams by performing column (timeslot) switching in those streams. The Add or Drop bus TSI logic treats the four channels STS-3
(STM-1) SONET/SDH streams as consecutive blocks consisting of 12 independent time-division
multiplexed columns (time-slots) of data. The 12 columns correspond to the 12 constituent STS-1
(STM-0/AU-3) or equivalent payload streams. The relationship between the columns and the
payload streams is summarized in the columns and STS-1 (STM-0/AU-3) streams association
table (Table 6). The columns are numbered in the order of transmission (reception) and the
corresponding payload streams are labeled according to their STS-3 (STM-1) channel and STS-1
(STM-0/AU-3) sub-group.
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Document ID: PMC-1990822, Issue 4
Table 6 Columns and STS-1 (STM-0/AU-3) Streams Association.
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Column #
(Tx/Rx Order)
1
2
3
4
5
6
7
8
9
10
11
12
STS-1 (STM-0/AU-3)
Streams
Channel/STS-3 (STM-1) #1, STS-1 (STM-0/AU-3) #1
Channel/STS-3 (STM-1) #2, STS-1 (STM-0/AU-3) #1
Channel/STS-3 (STM-1) #3, STS-1 (STM-0/AU-3) #1
Channel/STS-3 (STM-1) #4, STS-1 (STM-0/AU-3) #1
Channel/STS-3 (STM-1) #1, STS-1 (STM-0/AU-3) #2
Channel/STS-3 (STM-1) #2, STS-1 (STM-0/AU-3) #2
Channel/STS-3 (STM-1) #3, STS-1 (STM-0/AU-3) #2
Channel/STS-3 (STM-1) #4, STS-1 (STM-0/AU-3) #2
Channel/STS-3 (STM-1) #1, STS-1 (STM-0/AU-3) #3
Channel/STS-3 (STM-1) #2, STS-1 (STM-0/AU-3) #3
Channel/STS-3 (STM-1) #3, STS-1 (STM-0/AU-3) #3
Channel/STS-3 (STM-1) #4, STS-1 (STM-0/AU-3) #3
Switching of columns (time-slots) is arbitrary, thus any column can be switched to any of the
time-slots. Concatenated streams should be switched as a group to keep the constituent STS-1
(STM-0/AU-3) streams in the correct transmit or receive order within the group.
The software configuration of the Add or Drop bus TSI logic to perform grooming at the
respective Add or Drop buses is described in the Operations section.
10.17.1 Drop TSI
On the Drop side, the Drop bus TSI logic grooms the four STS-3/3c (STM-1/AU-3/AU-4) receive
streams provided by the 12 RPPSs into the corresponding column of a Drop bus stream. The
Drop TSI also generates the STS-1 rate clocks into the RPPS from the Drop DCK clock. 12
staggard clocks are generated sequencing the order of data out of the 12 slices. The staggard
clocks and clock divider are slave to the Drop bus frame alignment and DFP. A frame realignment
caused by moving the DFP pulse position will reset the staggard clock generator and briefly
corupt the data sequencing out of the RPPSs. The Drop TSI also sets the frame alignment of the
STS-1 or STS-1 equivalent frames out of the slices. It does so by forcing the alignment on the
output of the RTAL FIFO.
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Document ID: PMC-1990822, Issue 4
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