Datasheet PM4354-PI Datasheet (PMC)

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DATASHEET

PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1

PM4354 COMET-QUAD

TRANSCEIVER / FRAMER

PM4354

COMET-QUAD

FOUR CHANNEL COMBINED E1/T1/J1

TRANSCEIVER/FRAMER

DATASHEET

RELEASED

ISSUE 6: MAY 2001

PMC-Sierra, Inc. 105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 .415.6000

RELEASED

DATASHEET

PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1

PM4354 COMET-QUAD

TRANSCEIVER / FRAMER

1 FEATURES........................................................................................................................ 1

1.1 RECEIVER SECTION: ......................................................................................... 2

1.2 TRANSMITTER SECTION:.................................................................................. 3

2 APPLICATIONS................................................................................................................. 6

3 REFERENCES .................................................................................................................. 7

4 APPLICATION EXAMPLE ...............................................................................................10

5 BLOCK DIAGRAM........................................................................................................... 11

6 DESCRIPTION ................................................................................................................ 12

7 PIN DIAGRAM................................................................................................................. 14

8 PIN DESCRIPTION ......................................................................................................... 16

9 FUNCTIONAL DESCRIPTION ........................................................................................ 33

9.1 QUADRANTS ..................................................................................................... 33

9.2 RECEIVE INTERFACE.......................................................................................33

9.3 CLOCK AND DATA RECOVERY (CDRC) .......................................................... 36

9.4 RECEIVE JITTER ATTENUATOR (RJAT) ......................................................... 38

9.5 T1 INBAND LOOPBACK CODE DETECTOR (IBCD)........................................ 39

9.6 T1 PULSE DENSITY VIOLATION DETECTOR (PDVD).................................... 39

9.7 T1 FRAMER (T1-FRMR) .................................................................................... 39

9.8 E1 FRAMER (E1-FRMR).................................................................................... 40

9.9 RECEIVE ELASTIC STORE (RX-ELST)............................................................ 46

9.10 SIGNALING EXTRACTOR (SIGX)..................................................................... 47

9.11 PERFORMANCE MONITOR COUNTERS (T1/E1-PMON) ...............................47

9.12 T1 AUTOMATIC PERFORMANCE REPORT GENERATION (APRM) .............. 48

9.13 T1 ALARM INTEGRATOR (ALMI) ...................................................................... 48

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PM4354 COMET-QUAD

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9.14 HDLC RECEIVER (RDLC) .................................................................................49

9.15 BIT ORIENTED CODE DETECTOR (RBOC) ....................................................49

9.16 RECEIVE PER-CHANNEL SERIAL CONTROLLER (RPSC) ............................ 50

9.17 PSEUDO RANDOM BINARY SEQUENCE GENERATION AND DETECTION

(PRBS) ...............................................................................................................50

9.18 BACKPLANE RECEIVE SYSTEM INTERFACE (BRIF)..................................... 50

9.19 BACKPLANE TRANSMIT SYSTEM INTERFACE (BTIF) .................................. 54

9.20 TRANSMIT PER-CHANNEL SERIAL CONTROLLER (TPSC) .......................... 57

9.21 TRANSMIT ELASTIC STORE (TX-ELST) .........................................................58

9.22 T1 BASIC TRANSMITTER (T1-XBAS) ..............................................................58

9.23 E1 TRANSMITTER (E1-TRAN).......................................................................... 59

9.24 T1 INBAND LOOPBACK CODE GENERATOR (XIBC) ..................................... 59

9.25 PULSE DENSITY ENFORCER (XPDE)............................................................. 59

9.26 T1 SIGNALING ALIGNER (SIGA) ...................................................................... 59

9.27 BIT ORIENTED CODE GENERATOR (XBOC).................................................. 60

9.28 HDLC TRANSMITTER (TDPR).......................................................................... 60

9.29 TRANSMIT JITTER ATTENUATOR (TJAT) ....................................................... 61

9.30 LINE TRANSMITTER ......................................................................................... 66

9.31 TIMING OPTIONS (TOPS) ................................................................................ 66

9.32 JTAG TEST ACCESS PORT .............................................................................. 66

9.33 MICROPROCESSOR INTERFACE ...................................................................66

10 NORMAL MODE REGISTER DESCRIPTION ................................................................ 68

10.1 NORMAL MODE REGISTER MEMORY MAP ................................................... 68

11 TEST FEATURES DESCRIPTION................................................................................ 328

11.1 JTAG TEST PORT ...........................................................................................328

12 OPERATION.................................................................................................................. 331

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PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1

PM4354 COMET-QUAD

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12.1 CONFIGURING THE COMET-QUAD FROM RESET ..................................... 331

12.2 SERVICING INTERRUPTS.............................................................................. 338

12.3 USING THE PERFORMANCE MONITORING FEATURES ............................338

12.4 USING THE INTERNAL HDLC TRANSMITTER..............................................343

12.5 USING THE INTERNAL HDLC RECEIVER ..................................................... 346

12.6 T1 AUTOMATIC PERFORMANCE REPORT FORMAT ..................................350

12.7 USING THE TRANSMIT LINE PULSE GENERATOR ..................................... 352

12.8 USING THE LINE RECEIVER.......................................................................... 372

12.9 USING THE PRBS GENERATOR AND DETECTOR ......................................381

12.10 USING THE PER-CHANNEL SERIAL CONTROLLERS AND SIGX ............... 381

12.10.1 INITIALIZATION .................................................................................. 381

12.10.2 DIRECT ACCESS MODE.................................................................... 382

12.10.3 INDIRECT ACCESS MODE ................................................................382

12.11 T1/E1 FRAMER LOOPBACK MODES............................................................. 383

12.11.1 LINE LOOPBACK................................................................................ 383

12.11.2 PAYLOAD LOOPBACK .......................................................................383

12.11.3 PER-CHANNEL LOOPBACK .............................................................. 384

12.11.4 DIAGNOSTIC DIGITAL LOOPBACK...................................................385

12.12 RSYNC GENERATION .................................................................................... 385

12.13 BACKPLANE CONFIGURATION..................................................................... 386

12.13.1 RECEIVE CLOCK MASTER: FULL T1/E1 MODE SETTINGS ...........387

12.13.2 RECEIVE CLOCK MASTER: NX64KBIT/S MODE SETTINGS .......... 388

12.13.3 RECEIVE CLOCK MASTER: CLEAR CHANNEL MODE SETTINGS 388

12.13.4 RECEIVE CLOCK SLAVE: FULL T1/E1 MODE SETTINGS............... 389

12.13.5 RECEIVE CLOCK SLAVE: H-MVIP MODE SETTINGS...................... 389

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE iii

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PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1

PM4354 COMET-QUAD

TRANSCEIVER / FRAMER

12.13.6 RECEIVE CLOCK SLAVE: FULL T1/E1 WITH CCS H-MVIP MODE

SETTINGS .......................................................................................... 391

12.13.7 TRANSMIT CLOCK MASTER: FULL T1/E1 MODE SETTINGS ........392

12.13.8 TRANSMIT CLOCK MASTER: NX64KBIT/S MODE SETTINGS .......393

12.13.9 TRANSMIT CLOCK MASTER: CLEAR CHANNEL MODE SETTINGS393

12.13.10 TRANSMIT CLOCK SLAVE: FULL T1/E1 MODE SETTINGS .......... 394

12.13.11 TRANSMIT CLOCK SLAVE: CLEAR CHANNEL MODE SETTINGS394

12.13.12 TRANSMIT CLOCK SLAVE: H-MVIP MODE SETTINGS................. 395

12.13.13 TRANSMIT CLOCK SLAVE: FULL T1/E1 WITH CCS H-MVIP MODE

SETTINGS .......................................................................................... 397

12.14 H-MVIP DATA FORMAT ................................................................................... 398

12.15 JTAG SUPPORT .............................................................................................. 401

12.15.1 TAP CONTROLLER ............................................................................ 403

13 FUNCTIONAL TIMING .................................................................................................. 410

13.1 BACKPLANE RECEIVE SERIAL CLOCK AND DATA INTERFACE TIMING ... 410

13.2 BACKPLANE RECEIVE H-MVIP TIMING ........................................................ 415

13.3 BACKPLANE TRANSMIT SERIAL CLOCK AND DATA INTERFACE TIMING 416

13.4 BACKPLANE TRANSMIT H-MVIP TIMING ..................................................... 424

14 ABSOLUTE MAXIMUM RATINGS ................................................................................ 426

15 D.C. CHARACTERISTICS ............................................................................................427

16 MICROPROCESSOR INTERFACE TIMING CHARACTERISTICS.............................. 429

17 COMET-QUAD TIMING CHARACTERISTICS ............................................................. 433

17.1 RSTB TIMING .................................................................................................. 433

17.2 XCLK INPUT TIMING....................................................................................... 433

17.3 TRANSMIT BACKPLANE INTERFACE (FIGURE 83, FIGURE 84)................. 434

17.4 RECEIVE BACKPLANE INTERFACE (FIGURE 85, FIGURE 86) ................... 437

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PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1

PM4354 COMET-QUAD

TRANSCEIVER / FRAMER

18 ORDERING AND THERMAL INFORMATION............................................................... 445

19 MECHANICAL INFORMATION .....................................................................................446

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE v

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PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1

PM4354 COMET-QUAD

TRANSCEIVER / FRAMER

LIST OF FIGURES

FIGURE 1 - WIRELESS BASE STATION APPLICATION....................................................... 10

FIGURE 2 - V5.2 INTERFACE APPLICATION........................................................................ 10

FIGURE 3 - COMET-QUAD BLOCK DIAGRAM ..................................................................... 11

FIGURE 4 - PIN DIAGRAM ..................................................................................................... 15

FIGURE 5 - EXTERNAL ANALOG INTERFACE CIRCUITS...................................................34

FIGURE 6: - T1 JITTER TOLERANCE .................................................................................... 37

FIGURE 7: - COMPLIANCE WITH ITU-T SPECIFICATION G.823 FOR E1 INPUT JITTER .. 38

FIGURE 8: - CRC MULTIFRAME ALIGNMENT ALGORITHM................................................. 43

FIGURE 9: - RECEIVE CLOCK MASTER: FULL T1/E1 ..........................................................51

FIGURE 10: - RECEIVE CLOCK MASTER: NX64KBIT/S .........................................................51

FIGURE 11: - RECEIVE CLOCK MASTER: CLEAR CHANNEL ...............................................52

FIGURE 12: - RECEIVE CLOCK SLAVE: FULL T1/E1.............................................................. 52

FIGURE 13: - RECEIVE CLOCK SLAVE: H-MVIP..................................................................... 52

FIGURE 14: - RECEIVE CLOCK SLAVE: FULL T1/E1 WITH CCS H-MVIP .............................53

FIGURE 15: - TRANSMIT CLOCK MASTER: FULL T1/E1 .......................................................54

FIGURE 16: - TRANSMIT CLOCK MASTER: NX64KBIT/S ...................................................... 55

FIGURE 17: - TRANSMIT CLOCK MASTER: CLEAR CHANNEL............................................. 55

FIGURE 18: - TRANSMIT CLOCK SLAVE: FULL T1/E1 ........................................................... 55

FIGURE 19: - TRANSMIT CLOCK SLAVE: CLEAR CHANNEL ................................................ 56

FIGURE 20: - TRANSMIT CLOCK SLAVE: H-MVIP.................................................................. 56

FIGURE 21: - TRANSMIT CLOCK SLAVE: FULL T1/E1 WITH CCS H-MVIP........................... 57

FIGURE 22: - TJAT JITTER TOLERANCE................................................................................ 63

FIGURE 23: - TJAT MINIMUM JITTER TOLERANCE VS. XCLK ACCURACY......................... 64

FIGURE 24: - TJAT JITTER TRANSFER...................................................................................65

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PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1

PM4354 COMET-QUAD

TRANSCEIVER / FRAMER

FIGURE 25 - TRANSMIT TIMING OPTIONS ........................................................................... 91

FIGURE 26: - FER COUNT VS. BER (E1 MODE)................................................................... 340

FIGURE 27: - CRCE COUNT VS. BER (E1 MODE)................................................................ 341

FIGURE 28: - FER COUNT VS. BER (T1 ESF MODE) ........................................................... 341

FIGURE 29: - CRCE COUNT VS. BER (T1 ESF MODE) ........................................................ 342

FIGURE 30: - CRCE COUNT VS. BER (T1 SF MODE) ..........................................................343

FIGURE 31: - TYPICAL DATA FRAME ....................................................................................349

FIGURE 32: - EXAMPLE MULTI-PACKET OPERATIONAL SEQUENCE ...............................349

FIGURE 33: - LINE LOOPBACK.............................................................................................. 383

FIGURE 34: - PAYLOAD LOOPBACK ..................................................................................... 384

FIGURE 35: - DIAGNOSTIC DIGITAL LOOPBACK................................................................. 385

FIGURE 36 - RSYNC GENERATION ..................................................................................... 386

FIGURE 37: - BOUNDARY SCAN ARCHITECTURE ..............................................................402

FIGURE 38: - TAP CONTROLLER FINITE STATE MACHINE ................................................404

FIGURE 39: - INPUT OBSERVATION CELL (IN_CELL) ......................................................... 407

FIGURE 40: - OUTPUT CELL (OUT_CELL) OR ENABLE CELL (ENABLE)........................... 408

FIGURE 41: - BIDIRECTIONAL CELL (IO_CELL)................................................................... 409

FIGURE 42: - LAYOUT OF OUTPUT ENABLE AND BIDIRECTIONAL CELLS ...................... 409

FIGURE 43: - T1 RECEIVE CLOCK MASTER : FULL T1/E1 MODE ...................................... 410

FIGURE 44: - E1 RECEIVE CLOCK MASTER : FULL T1/E1 MODE ..................................... 410

FIGURE 45: - T1 RECEIVE CLOCK MASTER: NX64KBIT/S MODE ...................................... 411

FIGURE 46: - E1 RECEIVE CLOCK MASTER : NX64KBIT/S MODE ..................................... 411

FIGURE 47: - T1/E1 RECEIVE CLOCK MASTER : CLEAR CHANNEL MODE ......................412

FIGURE 48: - T1 RECEIVE CLOCK SLAVE: FULL T1/E1 MODE ........................................... 412

FIGURE 49: - E1 RECEIVE CLOCK SLAVE: FULL T1/E1 MODE........................................... 412

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PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1

PM4354 COMET-QUAD

TRANSCEIVER / FRAMER

FIGURE 50: - E1 RECEIVE CLOCK SLAVE: FULL T1/E1 MODE (CMS=1) ...........................413

FIGURE 51: - T1 RECEIVE 2.048 MHZ CLOCK SLAVE: FULL T1/E1 MODE ........................ 413

FIGURE 52: - CONCENTRATION HIGHWAY INTERFACE TIMING, EXAMPLE 1 .................. 414

FIGURE 53: - CONCENTRATION HIGHWAY INTERFACE TIMING, EXAMPLE 2 .................. 414

FIGURE 54: - RECEIVE CLOCK SLAVE: H-MVIP MODE ........................................................ 415

FIGURE 55: - T1 RECEIVE CLOCK SLAVE: H-MVIP MODE................................................... 415

FIGURE 56: - E1 RECEIVE CLOCK SLAVE: H-MVIP MODE................................................... 416

FIGURE 57: - TRANSMIT BACKPLANE: CMS=0, FE=1, DE=1, BTFP IS INPUT..................... 417

FIGURE 58: - TRANSMIT BACKPLANE: CMS=0, FE=1, DE=0, BTFP IS INPUT..................... 417

FIGURE 59: - TRANSMIT BACKPLANE: CMS=1, FE=1, DE=1, BTFP IS INPUT..................... 417

FIGURE 60: - TRANSMIT BACKPLANE: CMS=1, FE=0, DE=1, BTFP IS INPUT..................... 417

FIGURE 61: - TRANSMIT BACKPLANE: CMS=0, FE=1, DE=1, BTFP IS OUTPUT ................ 417

FIGURE 62: - TRANSMIT BACKPLANE: CMS=0, FE=1, DE=0, BTFP IS OUTPUT ................ 418

FIGURE 63: - T1 TRANSMIT CLOCK MASTER : FULL T1/E1 MODE..................................... 418

FIGURE 64: - E1 TRANSMIT CLOCK MASTER : FULL T1/E1 MODE ....................................418

FIGURE 65: - T1 TRANSMIT CLOCK MASTER: NX64KBIT/S MODE (DE=1, FE=0) .............419

FIGURE 66: - E1 TRANSMIT CLOCK MASTER : NX64KBIT/S MODE (DE=1, FE=0) ............ 419

FIGURE 67: - T1 TRANSMIT CLOCK MASTER: NX64KBIT/S MODE (DE=0, FE=0) ..............419

FIGURE 68: - E1 TRANSMIT CLOCK MASTER: NX64KBIT/S MODE (DE=0, FE=0) .............. 420

FIGURE 69: - T1/E1 TRANSMIT CLOCK MASTER : CLEAR CHANNEL MODE ....................420

FIGURE 70: - T1 TRANSMIT CLOCK SLAVE: FULL T1/E1 MODE .........................................421

FIGURE 71: - E1 TRANSMIT CLOCK SLAVE : FULL T1/E1 MODE ........................................ 421

FIGURE 72: - T1 TRANSMIT 2.048 MHZ CLOCK SLAVE : FULL T1/E1 MODE...................... 422

FIGURE 73: - T1/E1 TRANSMIT CLOCK SLAVE : CLEAR CHANNEL MODE ......................... 422

FIGURE 74: - CONCENTRATION HIGHWAY INTERFACE TIMING, EXAMPLE1 .................... 423

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PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1

PM4354 COMET-QUAD

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FIGURE 75: - CONCENTRATION HIGHWAY INTERFACE TIMING, EXAMPLE 2 .................. 423

FIGURE 76: - TRANSMIT CLOCK SLAVE: H-MVIP MODE .....................................................424

FIGURE 77: - T1 TRANSMIT CLOCK SLAVE: H-MVIP MODE ................................................ 424

FIGURE 78: - E1 TRANSMIT CLOCK SLAVE: H-MVIP MODE ................................................ 425

FIGURE 79: - MICROPROCESSOR INTERFACE READ TIMING.......................................... 430

FIGURE 80: - MICROPROCESSOR INTERFACE WRITE TIMING........................................432

FIGURE 81: - RSTB TIMING ................................................................................................... 433

FIGURE 82: - XCLK INPUT TIMING........................................................................................ 433

FIGURE 83 - BACKPLANE TRANSMIT INPUT TIMING DIAGRAM ...................................... 434

FIGURE 84 - BACKPLANE TRANSMIT OUTPUT TIMING DIAGRAM ..................................436

FIGURE 85 - BACKPLANE RECEIVE INPUT TIMING DIAGRAM ......................................... 438

FIGURE 86 - BACKPLANE RECEIVE OUTPUT TIMING DIAGRAM..................................... 439

FIGURE 87: - H-MVIP TRANSMIT DATA AND FRAME PULSE TIMING ................................ 440

FIGURE 88: - H-MVIP RECEIVE DATA TIMING......................................................................441

FIGURE 89: - TRANSMIT LINE INTERFACE TIMING ............................................................ 442

FIGURE 90: - JTAG PORT INTERFACE TIMING.................................................................... 443

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PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1

PM4354 COMET-QUAD

TRANSCEIVER / FRAMER

LIST OF TABLES

TABLE 1: - EXTERNAL COMPONENT DESCRIPTIONS ..................................................... 35

TABLE 2 : - TERMINATION RESISTORS, TRANSFORMER RATIOS AND TRL.................. 35

TABLE 3: - E1-FRMR FRAMING STATES ............................................................................ 44

TABLE 4 - NORMAL MODE REGISTER MEMORY MAP ....................................................68

TABLE 5 - TJAT FIFO OUTPUT CLOCK SOURCE ............................................................88

TABLE 6 - TJAT PLL SOURCE............................................................................................. 89

TABLE 7 - TRANSMIT TIMING OPTIONS SUMMARY ........................................................ 89

TABLE 8 - LOSS OF SIGNAL THRESHOLDS ...................................................................103

TABLE 9 - RECEIVE BACKPLANE NX64KBIT/S MODE SELECTION.............................. 126

TABLE 10 - RECEIVE BACKPLANE RATE..........................................................................128

TABLE 11 - E1 RECEIVE BACKPLANE FRAME PULSE CONFIGURATIONS................... 131

TABLE 12 - RECEIVE BACKPLANE BIT OFFSET FOR CMS = 0....................................... 137

TABLE 13 - RECEIVE BACKPLANE BIT OFFSET FOR CMS = 1....................................... 137

TABLE 14 - TRANSMIT BACKPLANE NX64KBIT/S MODE SELECTION........................... 141

TABLE 15 - TRANSMIT BACKPLANE RATE .......................................................................143

TABLE 16 - TRANSMIT BACKPLANE BIT OFFSET FOR CMS = 0 ....................................150

TABLE 17 - TRANSMIT BACKPLANE BIT OFFSET FOR CMS = 1 ....................................150

TABLE 18 - T1 FRAMING MODES....................................................................................... 152

TABLE 19 - LOOPBACK CODE CONFIGURATIONS.......................................................... 157

TABLE 20 - SIGX INDIRECT REGISTER MAP.................................................................... 170

TABLE 21 - SIGX INDIRECT REGISTERS 10H - 1FH: CURRENT TIMESLOT/CHANNEL

SIGNALING DATA ......................................................................................................................172

TABLE 22 - SIGX INDIRECT REGISTERS 20H - 3FH: DELAYED TIMESLOT/CHANNEL

SIGNALING DATA ...................................................................................................................... 172

TABLE 23 - INDIRECT REGISTERS 40H - 5FH: PER-TIMESLOT CONFIGURATION ......173

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PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1

PM4354 COMET-QUAD

TRANSCEIVER / FRAMER

TABLE 24 - SIGX PER-CHANNEL T1 DATA CONDITIONING ............................................ 174

TABLE 25 - SIGX PER-CHANNEL E1 DATA CONDITIONING ............................................174

TABLE 26 - T1 FRAMING FORMATS .................................................................................. 177

TABLE 27 - T1 ZERO CODE SUPPRESSION FORMATS................................................... 177

TABLE 28 - TRANSMIT IN-BAND CODE LENGTH ............................................................. 179

TABLE 29 - T1 FRAMING MODES....................................................................................... 192

TABLE 30 - TPSC INDIRECT REGISTER MAP................................................................... 208

TABLE 31 - TPSC INDIRECT REGISTERS 20H-3FH: PCM DATA CONTROL BYTE......... 210

TABLE 32 - TPSC TRANSMIT DATA CONDITIONING ........................................................ 211

TABLE 33 - TRANSMIT TEST PATTERN MODES .............................................................. 211

TABLE 34 - TRANSMIT ZERO CODE SUPPRESSION FORMATS ....................................212

TABLE 35 - TPSC INDIRECT REGISTERS 40H-5FH: IDLE CODE BYTE.......................... 213

TABLE 36 - TPSC INDIRECT REGISTERS 60H-7FH: SIGNALING/E1 CONTROL BYTE .213

TABLE 37 - TRANSMIT PER-TIMESLOT DATA MANIPULATION....................................... 214

TABLE 38 - A-LAW DIGITAL MILLIWATT PATTERN ...........................................................214

TABLE 39 - µ-LAW DIGITAL MILLIWATT PATTERN ........................................................... 215

TABLE 40 - RPSC INDIRECT REGISTER MAP .................................................................. 219

TABLE 41 - RPSC INDIRECT REGISTERS 20H-3FH: PCM DATA CONTROL BYTE ........221

TABLE 42 - RECEIVE TEST PATTERN MODES ................................................................. 221

TABLE 43 - RPSC INDIRECT REGISTERS 40H-5FH: DATA TRUNK CONDITIONING CODE BYTE 222

TABLE 44 - RPSC INDIRECT REGISTERS 61H-7FH: SIGNALING TRUNK CONDITIONING BYTE 223

TABLE 45 - NMNI SETTINGS .............................................................................................. 232

TABLE 46 - E1 SIGNALING INSERTION MODE .................................................................233

TABLE 47 - E1 TIMESLOT 0 BIT 1 INSERTION CONTROL SUMMARY............................ 235

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PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1

PM4354 COMET-QUAD

TRANSCEIVER / FRAMER

TABLE 48 - NATIONAL BITS CODEWORD SELECT .......................................................... 243

TABLE 49 - G.704 CRC-4 MULTIFRAME .............................................................................244

TABLE 50 - EXAMPLE SA BIT PROGRAMMING ................................................................245

TABLE 51 - TIMESLOT 0 BIT POSITION ALLOCATION ..................................................... 260

TABLE 52 - SIGNALING MULTIFRAME TIMESLOT 16, FRAME 0 BIT POSITIONS .......... 263

TABLE 53 - E1-FRMR CODEWORD SELECT..................................................................... 265

TABLE 54 - RECEIVE PACKET BYTE STATUS................................................................... 294

TABLE 55 - CLOCK SYNTHESIS MODE .............................................................................299

TABLE 56 - ALOS DETECTION/CLEARANCE THRESHOLDS........................................... 320

TABLE 57 - BOUNDARY SCAN REGISTER........................................................................ 329

TABLE 58 - DEFAULT SETTINGS........................................................................................ 331

TABLE 59 - ESF FRAME FORMAT...................................................................................... 332

TABLE 60 - SF FRAME FORMAT ........................................................................................334

TABLE 61 - T1DM FRAME FORMAT ................................................................................... 335

TABLE 62 - E1 FRAME FORMAT......................................................................................... 336

TABLE 63 - PMON POLLING SEQUENCE ..........................................................................337

TABLE 64 - ESF FDL PROCESSING ................................................................................... 338

TABLE 65: - PMON COUNTER SATURATION LIMITS (E1 MODE) ..................................... 339

TABLE 66: - PMON COUNTER SATURATION LIMITS (T1 MODE) .....................................339

TABLE 67: - PERFORMANCE REPORT MESSAGE STRUCTURE AND CONTENTS .......350

TABLE 68: - PERFORMANCE REPORT MESSAGE STRUCTURE NOTES ....................... 351

TABLE 69: - PERFORMANCE REPORT MESSAGE CONTENTS....................................... 351

TABLE 70 - T1.102 TRANSMIT WAVEFORM VALUES FOR T1 LONG HAUL (LBO 0 DB):353

TABLE 71 - T1.102 TRANSMIT WAVEFORM VALUES FOR T1 LONG HAUL (LBO 7.5 DB):

354

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PM4354 COMET-QUAD

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TABLE 72 - T1.102 TRANSMIT WAVEFORM VALUES FOR T1 LONG HAUL (LBO 15 DB):

355

TABLE 73 - T1.102 TRANSMIT WAVEFORM VALUES FOR T1 LONG HAUL (LBO 22.5 DB):

356

TABLE 74 - T1.102 TRANSMIT WAVEFORM VALUES FOR T1 SHORT HAUL (0 - 110 FT.):

357

TABLE 75 - T1.102 TRANSMIT WAVEFORM VALUES FOR T1 SHORT HAUL (110 – 220 FT.): 358

TABLE 76 - T1.102 TRANSMIT WAVEFORM VALUES FOR T1 SHORT HAUL (220 – 330 FT.): 359

TABLE 77 - T1.102 TRANSMIT WAVEFORM VALUES FOR T1 SHORT HAUL (330 – 440 FT.): 360

TABLE 78 - T1.102 TRANSMIT WAVEFORM VALUES FOR T1 SHORT HAUL (440 – 550 FT.): 361

TABLE 79 - T1.102 TRANSMIT WAVEFORM VALUES FOR T1 SHORT HAUL (550 – 660 FT.): 362

TABLE 80 - TR62411 TRANSMIT WAVEFORM VALUES FOR T1 LONG HAUL (LBO 0 DB):

363

TABLE 81 - TR62411 TRANSMIT WAVEFORM VALUES FOR T1 SHORT HAUL (0 - 110 FT.):364

TABLE 82 - TR62411 TRANSMIT WAVEFORM VALUES FOR T1 SHORT HAUL (110 – 220 FT.): 365

TABLE 83 - TR62411 TRANSMIT WAVEFORM VALUES FOR T1 SHORT HAUL (220 – 330 FT.): 366

TABLE 84 - TR62411 TRANSMIT WAVEFORM VALUES FOR T1 SHORT HAUL (330 – 440 FT.): 367

TABLE 85 - TR62411 TRANSMIT WAVEFORM VALUES FOR T1 SHORT HAUL (440 – 550 FT.): 368

TABLE 86 - TR62411 TRANSMIT WAVEFORM VALUES FOR T1 SHORT HAUL (550 – 660 FT.): 369

TABLE 87 - TRANSMIT WAVEFORM VALUES FOR E1 120 OHM:.................................... 370

TABLE 88 - TRANSMIT WAVEFORM VALUES FOR E1 75 OHM:...................................... 371

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PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1

PM4354 COMET-QUAD

TRANSCEIVER / FRAMER

TABLE 89 - LINE RECEIVER CONFIGURATION REGISTERS .......................................... 372

TABLE 90 - LINE RECEIVER RAM PROGRAMMING REGISTERS ................................... 373

TABLE 91 - SEQUENCE TO FOLLOW RLPS RAM PROGRAMMING................................ 374

TABLE 92 - RLPS EQUALIZER RAM TABLE (T1 MODE) ...................................................375

TABLE 93 - RLPS EQUALIZER RAM TABLE (E1 MODE) ................................................... 378

TABLE 94: - DATA AND CAS T1 H-MVIP FORMAT .............................................................. 399

TABLE 95: - DATA AND CAS E1 H-MVIP FORMAT.............................................................. 399

TABLE 96: - CCS T1 H-MVIP FORMAT ................................................................................400

TABLE 97: - CCS E1 H-MVIP FORMAT ................................................................................ 400

TABLE 98: - ABSOLUTE MAXIMUM RATINGS .................................................................... 426

TABLE 99: - D.C. CHARACTERISTICS ................................................................................427

TABLE 100: - MICROPROCESSOR INTERFACE READ ACCESS........................................ 429

TABLE 101: - MICROPROCESSOR INTERFACE WRITE ACCESS...................................... 431

TABLE 102: - RTSB TIMING ................................................................................................... 433

TABLE 103: - XCLK INPUT (FIGURE 82) ............................................................................... 433

TABLE 104 - TRANSMIT BACKPLANE INTERFACE ............................................................434

TABLE 105 - RECEIVE BACKPLANE INTERFACE ............................................................... 437

TABLE 106: - H-MVIP TRANSMIT TIMING (FIGURE 87) ....................................................... 440

TABLE 107: - H-MVIP RECEIVE TIMING (FIGURE 88).......................................................... 441

TABLE 108: - TRANSMIT LINE INTERFACE TIMING (FIGURE 89) ...................................... 441

TABLE 109: - JTAG PORT INTERFACE .................................................................................442

TABLE 110: - ORDERING INFORMATION ............................................................................. 445

TABLE 111: - THERMAL INFORMATION................................................................................ 445

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE xiv

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PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1

PM4354 COMET-QUAD

TRANSCEIVER / FRAMER

1 FEATURES

• Monolithic device which integrates four, full-featured T1 and E1 framers and T1 and E1 short haul and long haul line interfaces.

• Software selectable between T1/J1 and E1 operation on a per-device basis.

• Meets or exceeds T1 and E1 shorthaul and longhaul network access specifications including ANSI

T1.102, T1.403, T1.408, AT&T TR 62411, ITU-T G.703, G.704 as well as ETSI 300-011, CTR-4, CTR12 and CTR-13.

• Provides encoding and decoding of B8ZS, HDB3 and AMI line codes.

• Provides receive equalization, clock recovery and line performance monitoring.

• Provides transmit and receive jitter attenuation.

• Provides digitally programmable long haul and short haul line build out.

• Provides four full-featured HDLC controllers, each with 128-byte transmit and receive FIFO buffers.

• Automatically generates and transmits DS-1 performance report messages to ANSI T1.231 and ANSI

T1.408 specifications.

• Supports Nx64Kbit/s fractional bandwidth backplane.

• Supports transfer of PCM data to/from 1.544MHz and 2.048MHz system-side devices. Also supports

a fractional T1 or E1 system interface with independent backplane receive/backplane transmit Nx64Kbit/s rates. Supports a 2.048 MHz system-side interface for T1 mode without external clock gapping.

• Supports 8.192 Mbit/s, H-100 compatible, H-MVIP on the system interface for all T1 or E1 links, a separate 8.192 Mbit/s H-MVIP system interface for all T1 or E1 CAS channels and a separate 8.192 Mbit/s H-MVIP system interface for all T1 or E1 CCS, V5.1/V5.2, and GR.303 channels.

• Provides a selectable, per channel independent de-jittered T1 or E1 recovered clock for system timing and redundancy.

• Provides PRBS generators and detectors on each tributary for error testing at DS1, E1 and Nx64Kbit/s rates as recommended in ITU-T O.151 and O.152.

• Provides robbed bit signaling extraction and insertion on a per-DS0 basis.

• Register level compatibility with the PM4388 TOCTL Octal T1 Framer, the PM6388 EOCTL Octal E1

Framer, the PM4351 COMET E1/T1 transceiver, and the PM8315 TEMUX T1/E1 Framer with integrated Mapper and M13 MUX.

• Provides an 8-bit microprocessor bus interface for configuration, control, and status monitoring.

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PM4354 COMET-QUAD

TRANSCEIVER / FRAMER

• Uses line rate system clock.

• Provides an IEEE P1149.1 (JTAG) compliant test access port (TAP) and controller for boundary scan

test.

• Implemented in a low power 5 V tolerant 2.5/3.3 V CMOS technology.

• Available in a high density 208-pin fine pitch PBGA (17 mm by 17 mm) package.

• Provides a -40°C to +85°C Industrial temperature operating range.

1.1 Receiver section:

• Typical signal recovery of up to -43dB at 1024kHz (E1) and up to -44dB at 772kHz (T1/J1).

• Guaranteed minimum signal recovery of -32dB at 1024kHz (E1) and -36dB at 772kHz (T1/J1).

• Recovers clock and data using a digital phase locked loop for high jitter tolerance.

• Frames to ITU-T G.704 basic and CRC-4 multiframe formatted E1 signals. The framing procedures

are consistent ITU-T G.706 specifications.

• Frames to DSX/DS-1 signals in SF and ESF formats.

• Frames to TTC JT-G704 multiframe formatted J1 signals. Supports the alternate CRC-6 calculation

for Japanese applications. Frames in the presence of and detects the “Japanese Yellow” alarm.

• Tolerates more than 0.3 UI peak-to-peak, high frequency jitter as required by AT&T TR 62411 and Bellcore TR-TSY-000170.

• Detects violations of the ANSI T1.403 12.5% pulse density rule over a moving 192-bit window.

• Provides loss of signal detection as per ITU-T G.775 and ANSI T1.231. Red, Yellow, and AIS alarm

detection and integration are according to ANSI T1.231 specifications.

• Provides programmable in-band loopback activate and deactivate code detection.

• Supports line and path performance monitoring according to AT&T and ANSI specifications.

Accumulators are provided for counting ESF CRC-6 errors, framing bit errors, line code violations and loss of frame or change of frame alignment events.

• Provides performance monitoring counters sufficiently large as to allow performance monitor counter polling at a minimum rate of once per second. Optionally, updates the performance monitoring counters and interrupts the microprocessor once per second, timed to the receive line.

Based on actual results using PIC-22 gauge cable emulation. Refer to the COMET-QUAD Evaluator

Board for design recommendations (PMC-1991237).

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PM4354 COMET-QUAD

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• Provides ESF bit-oriented code detection and an HDLC/LAPD interface for terminating the ESF facility data link.

• Supports polled or interrupt-driven servicing of the HDLC interface.

• Extracts the data link in ESF mode and extracts a datalink in the E1 national use bits.

• Extracts 4-bit codewords from the E1 national use bits as specified in ETS 300 233

• Extracts up to three HDLC links, to an H-MVIP Bus, to support the D-channel for ISDN Primary Rate

Interfaces and the C-channels for V5.1/V5.2 interfaces. Detects the V5.2 link identification signal.

• Provides a two-frame elastic store buffer for backplane rate adaptation that performs controlled slips and indicates slip occurrence and direction.

• Provides DS-1 robbed bit signaling extraction, with optional data inversion, programmable idle code substitution, digital milliwatt code substitution, bit fixing, and two superframes of signaling debounce on a per-channel basis.

• Frames to the E1 signaling multiframe alignment when enabled and extracts channel associated signaling. Alternatively, a common channel signaling data link may be extracted from timeslot 16.

• Indicates signaling state change, and two superframes of signaling debounce on a per-DS0 basis.

• Provides trunk conditioning which forces programmable trouble code substitution and signaling

conditioning on all channels or on selected channels.

• Provides diagnostic, line loopbacks and per-DS0 payload loopback.

• A pseudo-random sequence user selectable from 2

–1, 215 –1 or 220 –1, may be detected in the T1/E1 stream in either the backplane receive or backplane transmit directions. The detector counts pattern errors using a 24-bit saturating PRBS error counter.

• Provides four single-rail PCM and signaling data outputs for 1.544 Mbit/s or 2.048 Mbit/s backplane buses.

1.2 Transmitter section:

• Supports transfer of transmitted single rail PCM and signaling data from 1.544 Mbit/s and 2.048 Mbit/s backplane buses.

• Generates DSX-1 shorthaul and DS-1 longhaul pulses with programmable pulse shape compatible with AT&T, ANSI and ITU requirements.

• Generates E1 pulses compliant to G.703 recommendations.

• Provides a digitally programmable pulse shape extending up to 5 transmitted bit periods for custom

long haul pulse shaping applications.

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PM4354 COMET-QUAD

TRANSCEIVER / FRAMER

• Provides line outputs that are current limited and may be tristated for protection or in redundant applications.

• Provides a digital phase locked loop for generation of a low jitter transmit clock complying with all jitter attenuation, jitter transfer and residual jitter specifications of AT&T TR 62411 and ETSI TBR 12 and TBR 13.

• Provides a FIFO buffer for jitter attenuation and rate conversion in the transmit path.

• Provides a two-frame payload slip buffer to allow independent backplane and line timing.

• A pseudo-random sequence user selectable from 2

–1, 215 –1 or220 –1, may be inserted into or

detected from the T1 or E1 stream in either the backplane receive or backplane transmit directions.

• Transmits G.704 basic and CRC-4 multiframe formatted E1 signals or D4, SF or ESF formatted DSX/DS-1 signals.

• Transmits the “Japanese Yellow” alarm. Transmits TTC JT-G704 multiframe formatted J1 signals. Supports the alternate ESF CRC-6 calculation for Japanese applications.

• Supports unframed mode and framing bit, CRC, or data link by-pass.

• Provides signaling insertion, programmable idle code substitution, digital milliwatt code substitution,

and data inversion on a per channel basis.

• Provides trunk conditioning which forces programmable trouble code substitution and signaling conditioning on all channels or on selected channels.

• Provides minimum ones density through Bell (bit 7), GTE or DDS zero code suppression on a per channel basis.

• Detects violations of the ANSI T1.403 12.5% pulse density rule over a moving 192-bit window and optionally stuffs ones to maintain minimum ones density.

• Allows insertion of framed or unframed in-band loopback code sequences.

• Allows insertion of a data link in ESF mode. Optionally inserts a datalink in the E1 national use bits.

• Supports 4-bit codeword insertion in the E1 national use bits as specified in ETS 300 233

• Inserts, from an H-MVIP bus, up to three HDLC links to support the D-channel for ISDN Primary Rate

Interfaces and the C-channels for V5.1/V5.2 interfaces.

• Supports transmission of the alarm indication signal (AIS) and the Yellow alarm signal. Supports “Japanese Yellow” alarm generation.

• Provides ESF bit-oriented code generation.

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PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1

PM4354 COMET-QUAD

TRANSCEIVER / FRAMER

Synchronous System Interfaces:

• Provides an 8.192 Mbit/s H-MVIP data interface for synchronous access to all the T1 DS0s or E1 timeslots. Compatible with H-MVIP PCM backplanes supporting 8.192 Mbit/s.

• Provides an 8.192 Mbit/s H-MVIP interface for synchronous access to all channel associated signaling (CAS) bits for all T1 DS0s or E1 timeslots. The CAS bits occupy one nibble of every byte on the HMVIP interfaces and are repeated over the entire T1 or E1 multi-frame.

• Provides an 8.192 Mbit/s H-MVIP interface for common channel signaling (CCS) channels as well as V5.1 and V5.2 channels. In T1 mode DS0 24 is available through this interface. In E1 mode timeslots 15, 16 and 31 are available through this interface.

• All links accessed via the H-MVIP interface will be synchronously timed to the common H-MVIP clock and frame alignment signals: CMV8MCLK, CMVFPB, CMVFPC

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE 5

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PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1

PM4354 COMET-QUAD

TRANSCEIVER / FRAMER

2 APPLICATIONS

• Wireless Base Station, Transceiver or Digital Loop Carrier

• DSLAM

• Metro Optical Access Equipment

• Voi ce Gateway

• Enterprise Router

• SONET/SDH Multiplexer

• Channel and Data Service Units (CSU/DSU)

• Digital Private Branch Exchanges (PBX)

• Digital Access Cross-Connect Systems (DACS)

• ISDN Primary Rate Interfaces (PRI)

• Test Equipment

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE 6

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PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1

PM4354 COMET-QUAD

TRANSCEIVER / FRAMER

3 REFERENCES

1. ANSI - T1.101-1987 - American National Standard for Telecommunications - Digital Hierarchy

- Timing Synchronization.

2. ANSI - T1.102-1993 - American National Standard for Telecommunications - Digital Hierarchy

- Electrical Interfaces.

3. ANSI - T1.107-1995 - American National Standard for Telecommunications - Digital Hierarchy

- Formats Specification.

4. ANSI - T1.231-1993 - American National Standard for Telecommunications - Layer 1 InService Digital Transmission Performance Monitoring

5. ANSI - T1.403-1995 - American National Standard for Telecommunications - Carrier to Customer Installation - DS-1 Metallic Interface Specification.

6. ANSI - T1.408-1990 - American National Standard for Telecommunications - Integrated Services Digital Network (ISDN) Primary Rate - Customer Installation Metallic Interfaces Layer 1 Specification.

7. T1M1.3/91-003R3 - American National Standard for Telecommunications - In-Service Digital Transmission Performance Monitoring Draft Standard.

8. TA-TSY-000147 - Bell Communications Research - DS-1 Rate Digital Service Monitoring Unit Functional Specification, Issue 1, October, 1987.

9. AT&T - PUB 54016 - Requirements For Interfacing Digital Terminal Equipment To Services Employing The Extended Superframe Format, October 1984.

10. AT&T - TR 62411 - Accunet T1.5 - Service Description and Interface Specification, December 1990.

11. AT&T - TR 62411 - Accunet T1.5 - Service Description and Interface Specification, Addendum 1, March 1991.

12. AT&T - TR 62411 - Accunet T1.5 - Service Description and Interface Specification, Addendum 2, October 1992.

13. AT&T - Interface Specification - Concentration Highway Interface - November 1990.

14. TR-TSY-000170 - Bellcore – Digital Cross-Connect System Requirements and Objectives, Issue 1, November 1985.

15. TR-N1WT-000233 - Bell Communications Research - Wideband and Broadband Digital Cross-Connect Systems Generic Criteria, Issue 3, November 1993.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE 7

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PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1

PM4354 COMET-QUAD

TRANSCEIVER / FRAMER

16. TR-NWT-000303 - Bell Communications Research - Integrated Digital Loop Carrier Generic Requirements, Objectives, and Interface, Issue 2, December, 1992.

17. TR-TSY-000499 - Bell Communications Research - Transport Systems Generic Requirements (TSGR): Common Requirement, Issue 5, December, 1993.

18. TR-TSY-000820 - Bell Communications Research - OTGR: Network Maintenance Transport Surveillance - Generic Digital Transmission Surveillance, Section 5.1, Issue 1, June 1990.

19. ETSI - ETS 300 011 - ISDN Primary Rate User-Network Interface Specification and Test Principles, 1992.

20. ETSI - ETS 300 233 - Access Digital Section for ISDN Primary Rates.

21. ETSI - ETS 300 324-1 - Signaling Protocols and Switching (SPS); V interfaces at the Digital Local Exchange (LE) V5.1 Interface for the Support of Access Network (AN) Part 1: V5.1 Interface Specification, February 1994.

22. ETSI - ETS 300 347-1 - Signaling Protocols and Switching (SPS); V Interfaces at the Digital Local Exchange (LE) V5.2 Interface for the Support of Access Network (AN) Part 1: V5.2 Interface Specification, September 1994.

23. ETSI - CTR 4 - Integrated Services Digital Network (ISDN); Attachment requirements for terminal equipment to connect to an ISDN using ISDN primary rate access, November 1995.

24. ETSI - CTR 12 - Business Telecommunications (BT); Open Network Provision (ONP) technical requirements; 2 048 kbit/s digital unstructured leased lines (D2048U) Attachment requirements for terminal equipment interface, December 1993.

25. ETSI - CTR 13 - Business Telecommunications (BTC); 2 048 kbit/s digital structured leased lines (D2048S); Attachment requirements for terminal equipment interface, January 1996.

26. FCC Rules - Part 68.308 - Signal Power Limitations.

27. ITU-T - Recommendation G.703 - Physical/Electrical Characteristics of Hierarchical Digital Interface, Geneva, 1991.

28. ITU-T - Recommendation G.704 - Synchronous Frame Structures Used at Primary Hierarchical Levels, July 1995.

29. ITU-T - Recommendation G.706 - Frame Alignment and CRC Procedures Relating to G.704 Frame Structures, 1991.

30. ITU-T - Recommendation G.732 – Characteristics of Primary PCM Multiplex Equipment Operating at 2048 kbit/s, 1993.

31. ITU-T - Recommendation G.711 – Pulse Code Modulation (PCM) of Voice Frequencies, 1993.

32. ITU-T - Recommendation G.775 - Loss of Signal (LOS), November 1994.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE 8

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PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1

PM4354 COMET-QUAD

TRANSCEIVER / FRAMER

33. ITU-T Recommendation G.802, - Interworking Between Networks Based on Different Digital Hierarchies and Speech Encoding Laws, 1993.

34. ITU-T Recommendation G.823, - The Control of Jitter and Wander Within Digital Networks Which are Based on the 2048 kbit/s Hierarchy, 1993.

35. ITU-T Recommendation G.964, - V-Interfaces at the Digital Local Exchange (LE) - V5.1 Interface (Based on 2048 kbit/s) for the Support of Access Network (AN), June 1994.

36. ITU-T Recommendation G.965, - V-Interfaces at the Digital Local Exchange (LE) - V5.2 Interface (Based on 2048 kbit/s) for the Support of Access Network (AN), March 1995.

37. ITU-T - Recommendation I.431 - Primary Rate User-Network Interface – Layer 1 Specification, 1993.

38. ITU-T Recommendation O.151, - Error Performance Measuring Equipment For Digital Systems at the Primary Bit Rate and Above, 1988.

39. ITU-T Recommendation O.152 - Error Performance Measuring Equipment for Bit Rates of 64 kbit/s and N X 64 kbit/s, October 1992

40. ITU-T Recommendation O.153 - Basic Parameters for the Measurement of Error Performance at Bit Rates below the Primary Rate, October 1992.

41. ITU-T Recommendation Q.921 - ISDN User-Network Interface Data Link Layer Specification, March 1993.

42. International Organization for Standardization, ISO 3309:1984 - High-Level Data Link Control Procedures -- Frame Structure.

43. TTC Standard JT-G703 - Physical/Electrical Characteristics of Hierarchical Digital Interfaces,

1995.

44. TTC Standard JT-G704 - Frame Structures on Primary and Secondary Hierarchical Digital Interfaces, 1995.

45. TTC Standard JT-G706 - Frame Synchronization and CRC Procedure

46. TTC Standard JT-I431 - ISDN Primary Rate User-Network Interface Layer 1 - Specification,

1995.

47. Nippon Telegraph and Telephone Corporation - Technical Reference for High-Speed Digital Leased Circuit Services, Third Edition, 1990.

48. GO-MVIP - Multi-Vendor Integration Protocol, MVIP-90 Release 1.1, 1994.

49. GO-MVIP – H-MVIP Standard, Release 1.1a, 1997.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE 9

RELEASED

PM4354 COMET-QUAD

DATASHEET

PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1

TRANSCEIVER / FRAMER

4 APPLICATION EXAMPLE

Figure 1 - Wireless Base Station Application

Fibre Optics

Public

DS3

PM8313

PM5342

SPECTRA

D3MX

Basestation

Switch Fabric

PM43 54 COMET-Qua d

Switched

Telephone

PM43 54 COMET-Qua d

Network

Base Station Controller

Figure 2 - V5.2 Interface Application

PM5342

SPECTRA

-155

Intel or

Motorola

µµµµP

PM5362

TUPP+

PM7364

FREEDM-32

Switch Fabric

T1/E1/J1

PM4354 COMET-Quad

Framer

T1/E1/J1

LH/SH

LIU

Software

Selectable

T1/E1/J1

Framer

T1/E1/J1 Longhaul/ Shorthaul

LIU

PM4354 COMET-Quad

V5.2

4 x E1

Bundle

PM4351 COMET

CDMA/TDMA/GSM

Base Transceiver Station

●●●●

T1/E1/J1

LH/SH

Framer

LIU

PM4354 COMET-Quad

µµµµP

Access Concentrator

Int el or Mo torola

Switch Fabr ic

FREEDM-32

Tx/Rx

Subsystem

µµµµ

Linecard Linecard

●●●●

Linecard

PM7364

Central Office Switch

Subs cribers

STM-1

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE 10

●●●●●●●●●●●●

RELEASED

PM4354 COMET-QUAD

DATASHEET

PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1

TRANSCEIVER / FRAMER

5 BLOCK DIAGRAM

Figure 3 - COMET-QUAD Block Diagram

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PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE 11

RELEASED

DATASHEET

PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1

PM4354 COMET-QUAD

TRANSCEIVER / FRAMER

6 DESCRIPTION

The PM4354 Four Channel Combined E1/T1/J1 Transceiver and Framer (COMET-QUAD) is a feature-rich monolithic integrated circuit suitable for use in long haul and short haul T1, J1 and E1 systems with a minimum of external circuitry. The COMET-QUAD is software configurable, allowing feature selection without changes to external wiring.

Analog circuitry is provided to allow direct reception of long haul E1 and T1/J1 compatible signals typically with up to 43 dB cable loss at 1024 kHz (E1) and up to 44 dB cable loss at 772 kHz (T1/J1) using a minimum of external components. Typically, only line protection, a transformer and a line termination resistor are required.

The COMET-QUAD recovers clock and data from the line and frames to incoming data. In T1 mode, it can frame to SF and ESF signal formats. In E1 mode, the COMET-QUAD frames to basic G.704 E1 signals and CRC-4 multiframe alignment signals, and automatically performs the G.706 interworking procedure. AMI, HDB3 and B8ZS line codes are supported.

The COMET-QUAD supports detection of various alarm conditions such as loss of signal, pulse density violation, Red alarm, Yellow alarm, and AIS alarm in T1 mode and loss of signal, loss of frame, loss of signaling multiframe and loss of CRC multiframe in E1 mode. The COMET-QUAD also supports reception of remote alarm signal, remote multiframe alarm signal, and alarm indication signal in E1 mode. The presence of Yellow and AIS patterns in T1 mode and remote alarm and AIS patterns in E1 mode is detected and indicated. In T1 mode, the COMET-QUAD integrates Yellow, Red, and AIS alarms as per industry specifications. In E1 mode, the COMETQUAD integrates Red and AIS alarms.

Performance monitoring with accumulation of CRC-6 errors, framing bit errors, line code violations, and loss of frame events are provided in T1 mode. In E1 mode, CRC-4 errors, far end block errors, framing bit errors, and line code violation are monitored and accumulated.

The COMET-QUAD provides one receive HDLC controller per channel for the detection and termination of messages in the ESF facility data link (T1), national use bits (E1), or in any arbitrary timeslot (T1 or E1). In T1 mode, the COMET-QUAD also detects the presence of in-band loop back codes and ESF bit oriented codes. Detection and optional debouncing of the 4-bit Sa-bit codewords defined in ITU-T G.704 and ETSI 300-233 is supported. An interrupt may be generated on any change of state of the Sa codewords.

Dual (transmit and receive) elastic stores for slip buffering and rate adaptation to backplane timing are provided, as is a signaling extractor that supports signaling debounce, signaling freezing, idle code substitution, digital milliwatt tone substitution, data inversion, and signaling bit fixing on a perchannel basis. Receive side data and signaling trunk conditioning is also provided.

In T1 mode, the COMET-QUAD generates framing for SF and ESF formats. In E1 mode, the COMET-QUAD generates framing for a basic G.704 E1 signal. The signaling multiframe

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE 12

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PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1

PM4354 COMET-QUAD

TRANSCEIVER / FRAMER

alignment structure and the CRC multiframe structure may be optionally inserted. Framing can be optionally disabled.

Internal analog circuitry allows direct transmission of long haul and short haul T1 and E1 compatible signals using a minimum of external components. Typically, only line protection, a transformer and an optional line termination resistor are required. Digitally programmable pulse shaping allows transmission of DSX-1 compatible signals up to 655 feet from the cross-connect, E1 short haul pulses into 120 ohm twisted pair or 75 ohm coaxial cable, E1 long haul pulses into 120 ohm twisted pair as well as long haul DS-1 pulses into 100 ohm twisted pair with integrated support for LBO filtering as required by the FCC rules. In addition, the programmable pulse shape extending over 5-bit periods allows customization of short haul and long haul line interface circuits to application requirements.

In the transmit path, the COMET-QUAD supports signaling insertion, idle code substitution, digital milliwatt tone substitution, data inversion, and zero code suppression on a per-channel basis. Zero code suppression may be configured to Bell (bit 7), GTE, or DDS standards, and can also be disabled. Transmit side data and signaling trunk conditioning is also provided. Signaling bit transparency from the backplane may be enabled.

The COMET-QUAD provides one transmit HDLC controller per channel. These controllers may be used for the transmission of messages in the ESF data link (T1), national use bits (E1), or in any timeslot (T1 or E1). In T1 mode, the COMET-QUAD can be configured to generate in-band loop back codes and ESF bit oriented codes. In E1 mode, transmission of the 4-bit Sa codewords defined in ITU-T G.704 and ETSI 300-233 is supported.

To provide for V5 applications where up to three HDLC channels are contained in each E1, the COMET-QUAD provides a CCS H-MVIP interface. This interface allows the HDLC channels to be inserted or extracted for external processing.

Each channel of the COMET-QUAD can generate a low jitter transmit clock from a variety of clock references, and also provides jitter attenuation in the receive path. A low jitter recovered T1 clock can be routed outside the COMET-QUAD for network timing applications.

Serial PCM interfaces to each T1/E1 framer allow 1.544 Mbit/s or 2.048 Mbit/s backplane receive/backplane transmit system interfaces to be directly supported. Tolerance of gapped clocks allows other backplane rates to be supported with a minimum of external logic.

For synchronous backplane systems, 8.192 Mbit/s H-MVIP interfaces are provided for access to PCM data, channel associated signaling (CAS) and common channel signaling (CCS) for each T1 or E1. The CCS signaling H-MVIP interface is independent of the 64 Kbit/s PCM and CAS H-MVIP access. The use of the H-MVIP interface requires that common clocks and frame pulse be used along with T1/E1 elastic stores.

The COMET-QUAD is configured, controlled and monitored via a generic 8-bit microprocessor bus through which all internal registers are accessed. All sources of interrupts can be masked and acknowledged through the microprocessor interface.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE 13

RELEASED

DATASHEET

PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1

PM4354 COMET-QUAD

TRANSCEIVER / FRAMER

7 PIN DIAGRAM

The COMET-QUAD is packaged in a 208-pin PBGA package having a body size of 17mm by 17mm and a ball pitch of 1.0 mm. The center 16 balls are not used as signal I/Os and are thermal balls.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE 14

RELEASED

PM4354 COMET-QUAD

DATASHEET

PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1

TRANSCEIVER / FRAMER

Figure 4 - Pin Diagram

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

D (2) D (1)

D (3) VSS33 (1) D (0) TXTIP1 (1) TAVS3 (1) TXTIP2 (1) RAVD2 (1) RAVD1 (1) RAVD1 (2) RAVS2 (2)

D (4) D (5) VDD33 (1) TAVS2 (1) TXCM (1) TAVS1 (1) RXTIP (1) QAVD (1) RVREF (2)

VSS33 (2) D (6) D (7) VDD33 (2)

CASBRD_

RPC M (1 )

CMVFPC CMVFPB BTCLK (1)

VDDC25

(1)

V SSC 25

(2)

VDDC25

(3)

MVBTD CCSBTD

VDDC25

(4)

TXR I N G 1

TAVD2 (1)TAVD3 (1)TAVD1 (1)

(1)

BRCLK ( 1) BRSIG ( 1) BRFP (1)

CASBTD_B

TPC M ( 1 )

V SSC 25

(1)

VDDQ33

(1)

V SS33 ( 3)

BTC LK (3 )

CMV8MC

V SSQ 33

BTSIG (1 )

VDDC25

V SSC 25

(1)

BTFP (1) GND GND GND GND BTPCM (2) BTFP (2)

(2)

RES[4] GND GND GND GND XCLK BTSIG (2) RES[3]

(3)

VDD33 (3) GND GND GND GND

MVBRD_C

(4)

CSBRD

TXR I N G 2

RAVS2 (1) RAVS1 (1) RES (5) Q AVS (1) RXTIP (2) TA VS1 (2) TXCM (2) TA VD2 (2) RD B A (10) A (9)

(1)

RXRI N G

RVREF (1) RAVS1 (2) RAVD2 (2) TXTIP2 (2) TAVS3 (2) TXTIP1 (2) A (1) A (3) A (5)

(1)

208 PBGA

GND GND GND GND

TOP VIEW

RXRI N G

(2)

TXR I N G 2

TAVS2 (2) A (0) A (2) A (4) A (6)

(2)

TA V D 1 ( 2) TA V D 3 (2 )

TXR I N G 1

VSS33 (9) A (7) A (8)

(2)

RSTB A LE WRB C SB

BRPCM (2) VSS33 (5) INTB BRCLK (2)

V SSC 25

BRFP (2) BRSIG (2) VDD33 (5)

(5)

V SSQ 33

VDDQ33

(2)

V SS33 ( 6) RE S[ 1]

VDDC25

BTC LK (2 )

(5)

VDDC25

(6)

V SSC 25

(7)

V SSC 25

CTCLK

(2)

(8)

(6)

BTFP (3) VSS33 (8) BTSIG (3) BTPCM (3)

BRC LK (3) VDD33 (4) RES[2] TAV S2 (3)

BRPCM (3) BRSIG (3) TRSTB TXTIP1 (3) TXCM (3) TAVS1 (3) RXTIP (3) RES (6) RVREF (4)

BRFP (3) VSS33 (4) TM S

TD O TC K TD I TA V D 2 ( 3 ) TA V D3 ( 3) TA V D 1 (3 )

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

TXR I N G 2

RAVS2 (3) RAVS1 (3) CA VS C AVD RXTIP (4) TAVS1 (4) TXCM (4) BTFP (4) VDD33 (6) BRPCM (4) BRC LK (4)

(3)

TXR I N G 1

TAVS3 (3) TXTIP2 (3) RAVD2 (3) RAV D1 (3) RAVS1 (4) RAVS2 (4)

(3)

RXRI N G

RVREF (3) RAVD1 (4) RAVD2 (4) TXTIP2 (4) TAVS3 (4)

(3)

RXRI N G

TA VD1 (4) TA VD3 (4) TA VD2 (4) VSS33 (7) BRFP (4) BRSIG (4)

(4)

TXR I N G 2

(4)

VDDC25

BTCLK (4) BTSIG (4) BTPCM (4)

(7)

TAVS2 (4) TXTIP1 (4) QA VD (2) PIO RSYNC

TXR I N G 1

QAV S (2) RES (8) RES (7)

(4)

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE 15

RELEASED

DATASHEET

PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1

PM4354 COMET-QUAD

TRANSCEIVER / FRAMER

8 PIN DESCRIPTION

By convention, where a bus of four pins is present, the index indicates to which quadrant the pin applies. With BRCLK[1:4], for example, BRCLK[1] applies to quadrant #1, BRCLK[2] applies to quadrant #2, BRCLK[3] applies to quadrant #3, and BRCLK[4] applies to quadrant #4.

Pin Name Type Pin No. Function

T1 and E1 System Side Serial Clock and Data Interface

BRCLK[1] BRCLK[2] BRCLK[3] BRCLK[4]

I/O E2

F16 N1 N16

Backplane Receive Clocks (BRCLK[1:4]). The Backplane Receive Clock, BRCLK[x], is used to update BRPCM[x] and BRSIG[x] and to either update o sample BRFP[x], depending on the direction of BRFP[x]. The active edge of BRCLK[x] for sampling/updating BRPCM[x], BRSIG[x], and BRFP[x] is configurable.

In Receive Clock Master Mode, BRCLK[x] is configured as an output and can be either a 1.544 MHz or 2.048 MHz clock derived from the recovered line rate timing, with optional jitter attenuation.

When in Receive Clock Master: Nx64Kbit/s mode, BRCLK[x] is gapped during the framing bit position (T1 mode only) and optionally for between 1 and 24 DS0 channels or 1 and 32 timeslots in the associated BRPCM[x] stream.

When in Receive Clock Slave: Full T1/E1 mode, BRCLK[x] is configured as an input and is either a 1.544MHz clock in T1 mode or a 2.048MHz clock in T1 or E1 modes. BRCLK[x] is a nominal 1.544 or 2.048 MHz clock +/50ppm with a 50% duty cycle.

When in Receive Clock Slave: H-MVIP mode, BRCLK[x] is configured as an input and is unused. In this mode, it is recommended that BRCLK[x] be connected via an external resistor to ground.

After a reset, BRCLK[x] is configured as an input.

BRSIG[1] BRSIG[2] BRSIG[3] BRSIG[4]

Output E3

G15 P2 P16

Backplane Receive Signaling (BRSIG[1:4]). Each BRSIG[x] contains the extracted channel associated signaling bits for each channel in the frame, repeated for the entire superframe. Each channel's associated signaling bits are valid in bit locations 5,6,7,8 of the channel and are channel-aligned with the BRPCM[x] data stream.

When in Receive Clock Slave: H-MVIP mode, BRSIG[x] is unused and driven low.

BRSIG[x] is updated on the active edge of BRCLK[x].

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE 16

RELEASED

DATASHEET

PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1

PM4354 COMET-QUAD

TRANSCEIVER / FRAMER

Pin Name Type Pin No. Function

BRFP[1] BRFP[2] BRFP[3] BRFP[4]

I/O E4

G14 R1 P15

Backplane Receive Frame Pulse (BRFP[1:4]). When the Receive Clock Master mode is active, BRFP[x] is configured as an output and indicates the frame alignment or the superframe alignment of the backplane receive stream, BRPCM[x]. BRFP[x] is updated on the active edge of BRCLK[x].

Receive Clock Master T1 mode:

If basic frame alignment is desired, BRFP[x] pulses high for one BRCLK[x] cycle during bit 1 of each 193-bit frame. Optionally, BRFP[x] may pulse high every second frame to ease the identification of data link bits. If superframe alignment is desired, BRFP[x] pulses high for one BRCLK[x] cycle during bit 1 of frame 1 of every 12-frame or 24-frame superframe. Optionally, BRFP[x] may pulse high every second superframe to ease the conversion between SF and ESF.

Receive Clock Master E1 mode:

If basic frame alignment is desired, BRFP[x] pulses high for one BRCLK[x] cycle during bit 1 of each 256-bit frame. Optionally, BRFP[x] may pulse high every second frame to ease the identification of NFAS frames. If multiframe alignment is desired, BRFP[x] transitions high to mark bit 1 of frame 1 of every 16-frame signaling multiframe and transitions low following bit 1 of frame 1 of every 16-frame CRC multiframe. Note that if the signaling and CRC multiframe alignments are coincident, BRFP[x] pulses high for one BRCLK[x] cycle every 16 frames.

Receive Clock Slave mode:

When the elastic store is enabled (and Clock Slave mode is active on the backplane receive side), BRFP[x] is configured as an input and is used to frame align the backplane receive data to the system frame alignment. When frame alignment is required, a pulse at least 1 BRCLK[x] cycle wide must be provided on BRFP[x] a maximum of once every frame (193 bit times in T1, 256 bit times in E1). BRFP[x] is sampled on the active edge of BRCLK[x].

When in the Receive Clock Master: Clear Channel or Receive Clock Slave: H-MVIP mode, BRFP[x] is unused and it is recommended that BRFP[x] be configured as an input and be connected via an external resistor to ground.

After a reset, BRFP[x] is configured as an input.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE 17

RELEASED

DATASHEET

PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1

PM4354 COMET-QUAD

TRANSCEIVER / FRAMER

Pin Name Type Pin No. Function

BRPCM[1] / CASBRD BRPCM[2] BRPCM[3] BRPCM[4]

Output E1

F13 P1 N15

Backplane Receive Data (BRPCM[1:4]). Each BRPCM[x] signal contains the recovered data stream that may have been passed through the elastic store.

When a Clock Slave backplane receive mode is active, the BRPCM[x] stream has passed through the elastic store and is aligned to the backplane receive timing.

When in T1 Receive Clock Slave mode with BRCLK[x] configured as a

2.048MHz clock, the mapping of the BRPCM[x] data stream is configurable.

In Receive Clock Slave: H-MVIP mode, BRPCM[2], BRPCM[3], and BRPCM[4] are unused and driven low. BRPCM[1] shares the same pin as the H-MVIP CAS signal CASBRD. In Receive Clock Slave: H-MVIP mode, the output becomes CASBRD. Out of reset, this output defaults to BRPCM[1].

When in Receive Clock Master: Clear Channel mode, the unframed backplane receive data appears on BRPCM[x] with no frame alignment or signaling.

BRPCM[x] is updated on the active edge of BRCLK[x].

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE 18

RELEASED

DATASHEET

PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1

PM4354 COMET-QUAD

TRANSCEIVER / FRAMER

Pin Name Type Pin No. Function

BTCLK[1] BTCLK[2] BTCLK[3] BTCLK[4]

I/O F3

H16 L2 M14

Backplane Transmit Clock (BTCLK[1:4]). The active edge of the Backplane Transmit Clock, BTCLK[x], is used to sample the associated BTSIG[x] and BTPCM[x], and is used to update BTFP[x]. The active edge is configured in the BTIF Configuration register.

When a Transmit Clock Master mode is active, BTCLK[x] is an output and is a version of the transmit clock[x] which is generated from the receive recovered clock or the common transmit clock, CTCLK.

When in T1 Transmit Clock Master: Nx64Kbit/s mode, BTCLK[x] is gapped during the framing bit position and optionally for between 1 and 23 DS0 channels in the associated BTPCM[x] stream. When in E1 Transmit Clock Master: Nx64Kbit/s mode, BTCLK[x] is gapped for between 1 and 31 channel timeslots in the associated BTPCM[x] stream.

When in Transmit Clock Master: Clear Channel mode, the unframed backplane transmit data is sampled on BTPCM[x] with no frame alignment or signaling.

When in a Transmit Clock Slave mode, BTCLK[x] is configured as an input and is used to time the backplane transmit interface. BTCLK[x] is either a

1.544MHz clock in T1 mode or a 2.048MHz clock in T1 or E1 modes. BTCLK[x] is a nominal 1.544 or 2.048 MHz clock +/- 50ppm with a 50% duty cycle.

When in Transmit Clock Slave: H-MVIP mode, BTCLK[x] is configured as an input and is unused. In this mode, it is recommended that BTCLK[x] be connected via an external resistor to ground.

After a reset, BTCLK[x] is configured as an input.

BTSIG[1] BTSIG[2] BTSIG[3] BTSIG[4]

Input G3

J14 M3 M15

Backplane Transmit Signaling (BTSIG[1:4]). The BTSIG[x] input carries the signaling bits for each channel in the transmit data frame, repeated for the entire superframe. Each channel's signaling bits are in bit locations 5,6,7,8 of the channel and are channel-aligned with the BTPCM[x] data stream. When in Transmit Clock Slave: H-MVIP mode, BTSIG[x] is unused.

BTSIG[x] is sampled on the active edge of BTCLK[x].

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE 19

RELEASED

DATASHEET

PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1

PM4354 COMET-QUAD

TRANSCEIVER / FRAMER

Pin Name Type Pin No. Function

BTFP[1] BTFP[2] BTFP[3] BTFP[4]

I/O H4

H14 M1 N13

Backplane Transmit Frame Pulse (BTFP[1:4]). When BTFP[x] is configured as an input, and may be used to frame align the transmitters to the system backplane.

T1 mode:

If only frame alignment is required, a pulse at least one BTCLK[x] cycle wide must be provided on BTFP[x] at multiples of 193 bit periods. If superframe alignment is required, transmit superframe alignment must be enabled, and BTFP[x] must be brought high for at least one BTCLK[x] cycle to mark bit 1 of frame 1 of every 12-frame or 24-frame superframe.

E1 mode:

If basic frame alignment only is required, a pulse at least one BTCLK[x] cycle wide must be provided on BTFP[x] at multiples of 256 bit periods. If multiframe alignment is required, transmit multiframe alignment must be enabled, and BTFP[x] must be brought high to mark bit 1 of frame 1 of every 16-frame signaling multiframe and brought low following bit 1 of frame 1 of every 16-frame CRC multiframe. This mode allows both multiframe alignments to be independently controlled using the single BTFP[x] signal. Note that if the signaling and CRC multiframe alignments are coincident, BTFP[x] must pulse high for one BTCLK[x] cycle every 16 frames.

When BTFP[x] is configured as an output (only valid when the transmit backplane clock rate is no greater than 2.048 MHz), transmit frame alignment is derived internally, and BTFP[x] is updated on the active edge of BTCLK[x]. BTFP[x] pulses high for one cycle to indicate the first bit of each frame or multiframe, as optioned.

When in Transmit Clock Slave: H-MVIP mode, BTFP[x] is configured as an input and is unused. In this mode, it is recommended that BTFP[x] be connected via an external resistor to ground.

After a reset, BTFP[x] is configured as an input.

BTPCM[1] / CASBTD BTPCM[2] BTPCM[3] BTPCM[4]

Input F4

H13 M4 M16

Backplane Transmit Data (BTPCM[1:4]). The non-return to zero, digital backplane transmit data streams to be transmitted are input on these pins. BTPCM[x] may present a 1.544 Mbit/s, 2.048 Mbit/s or sub-rate Nx64Kbit/s data stream. BTPCM[x] is sampled on the active edge of BTCLK[x].

BTPCM[2:4] are unused in Transmit Clock Slave: H-MVIP mode. BTPCM[1] shares the same pin as the Transmit Clock Slave: H-MVIP Channel Associated Signaling pin, CASBTD. By default this input is BTPCM[1].

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE 20

RELEASED

DATASHEET

PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1

PM4354 COMET-QUAD

TRANSCEIVER / FRAMER

Pin Name Type Pin No. Function

MVIP System Side Interfaces

MVBTD Input K1

CASBTD /

Input F4

BTPCM[1]

MVIP Backplane Transmit Data (MVBTD). In Transmit Clock Slave: HMVIP mode, the 8.192 Mbit/s backplane transmit data streams to be transmitted are input on MVBTD. MVBTD carries the channels of four complete T1’s or E1’s formatted according to the H-MVIP standard. MVBTD carries the backplane transmit data equivalent to BTPCM[1:4].

MVBTD is aligned to the common H-MVIP 16.384 MHz clock, CMV8MCLK, the 4.096 MHz frame pulse clock, CMVFPC, and frame pulse, CMVFPB. MVBTD is sampled on every second rising edge of CMV8MCLK as fixed by the common H-MVIP frame pulse clock, CMVFPC.

When not in Transmit Clock Slave: H-MVIP mode, MVBTD is unused.

Channel Associated Signaling Backplane Transmit Data (CASBTD).

CASBTD carries the Channel Associated Signaling (CAS) stream to be transmitted in the T1 DS0s or E1 timeslots. CASBTD carries CAS for four complete T1’s or E1’s formatted according to the H-MVIP standard. CASBTD carries the backplane transmit signaling equivalent to BTSIG[1:4]. CASBTD carries the corresponding CAS values of the channel data carried in MVBTD.

CASBTD is aligned to the common H-MVIP 16.384MHz clock, CMV8MCLK, the 4.096 MHz frame pulse clock, CMVFPC, and frame pulse, CMVFPB. CASBTD is sampled on every second rising edge of CMV8MCLK as fixed by the common H-MVIP frame pulse clock, CMVFPC.

CASBTD shares the same pin as BTPCM[1]. In Transmit Clock Slave: HMVIP Mode, this input is CASBTD. In all other Transmit modes, this input is BTPCM[1].

CCSBTD Input K2

Common Channel Signaling Backplane Transmit Data (CCSBTD). In T1 mode, CCSBTD carries the common channel signaling to be transmitted in timeslot 24 of each of the 4 T1’s. In E1 mode, CCSBTD carries up to 3 timeslots (15,16, 31) to be transmitted in each of the 4 E1’s. CCSBTD is formatted according to the H-MVIP standard.

CCSBTD is aligned to the common H-MVIP 16.384 MHz clock, CMV8MCLK, the 4.096 MHz frame pulse clock, CMVFPC, and frame pulse, CMVFPB. CCSBTD is sampled on every second rising edge of CMV8MCLK as fixed by the common H-MVIP frame pulse clock, CMVFPC.

CCSBTD can be optionally enabled in either Transmit Clock Slave: Full T1/E1 mode or Transmit Clock Slave: H-MVIP mode. In other modes, CCSBTD is unused.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE 21

RELEASED

DATASHEET

PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1

PM4354 COMET-QUAD

TRANSCEIVER / FRAMER

Pin Name Type Pin No. Function

CMV8MCLK Input K3

CMVFPB Input F2

Common 8M H-MVIP Clock (CMV8MCLK). The Common 8.192 Mbit/s HMVIP Data Clock, CMV8MCLK, provides the data clock for receive and transmit links configured for operation in 8.192 Mbit/s H-MVIP mode.

CMV8MCLK is used to sample data on MVBRD, MVBTD, CASBRD, CASBTD, CCSBRD and CCSBTD. CMV8MCLK is nominally a 50% duty cycle clock with a frequency of 16.384 MHz.

The Transmitter and Receiver streams are independently enabled for HMVIP access. When enabled, all four Transmitter (or Receiver) streams are enabled for H-MVIP access. When both the Transmitter and the Receiver HMVIP accesses are disabled, CMV8MCLK is unused.

Common H-MVIP Frame Pulse (CMVFPB). The active low Common HMVIP Frame Pulse, CMVFPB, for 8.192 Mbit/s H-MVIP signals references the beginning of each frame for interfaces operating in 8.192 Mbit/s H-MVIP mode.

The CMVFPB frame pulse occurs every 125us and is sampled on the falling edge of CMVFPC.

The Transmitter and Receiver interfaces are independently enabled for HMVIP access. When enabled, all four Transmitter (or Receiver) streams are enabled for H-MVIP access. When both the Transmitter and the Receiver HMVIP accesses are disabled, CMVFPB is unused.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE 22

RELEASED

DATASHEET

PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1

PM4354 COMET-QUAD

TRANSCEIVER / FRAMER

Pin Name Type Pin No. Function

MVBRD /

CCSBRD

Output L4

H-MVIP Backplane Receive Data (MVBRD). MVBRD carries the recovered T1 or E1 channels that have passed through the elastic store. Each MVBRD signal carries the channels of four complete T1’s or E1’s. MVBRD carries the T1 or E1 data equivalent to BRPCM[1:4].

MVBRD is aligned to the common H-MVIP 16.384 MHz clock, CMV8MCLK, frame pulse clock, CMVFPC, and frame pulse, CMVFPB. MVBRD is updated on every second rising edge of the common H-MVIP 16.384 MHz clock, CMV8MCLK, as fixed by the common H-MVIP frame pulse clock, CMVFPC.

Common Channel Signaling Backplane Receive Data (CCSBRD). In T1 mode, CCSBRD carries the Common Channel Signaling (CCS) channels extracted from each of the 4 T1’s. In E1 mode, CCSBRD carries up to 3 timeslots (15,16, 31) from each of the 4 E1’s. CCSBRD is formatted according to the H-MVIP standard.

CCSBRD is aligned to the common H-MVIP 16.384 MHz clock, CMV8MCLK, the 4.096 MHz frame pulse clock, CMVFPC, and frame pulse, CMVFPB. CCSBRD is updated on every second rising edge of CMV8MCLK as fixed by the common H-MVIP frame pulse clock, CMVFPC.

CCSBRD shares the same pin as MVBRD. In Receive Clock Slave: H-MVIP mode, this output is MVBRD. In Receive Clock Slave: Full T1/E1 mode, CCSBRD can be optionally enabled. In all other modes, this output is unused and driven low.

CASBRD / BRPCM[1]

Output E1

Channel Associated Signaling Backplane Receive Data (CASBRD).

CASBRD carries the Channel Associated Signaling (CAS) stream extracted from all the T1 or E1 channels. CASBRD carries CAS for four complete T1’s or E1’s. CASBRD carries the T1 or E1 signaling equivalent to BRSIG[1:4]. CASBRD carries the corresponding CAS values of the channel carried in MVBRD.

CASBRD is aligned to the common H-MVIP 16.384 MHz clock, CMV8MCLK, the 4.096 MHz frame pulse clock, CMVFPC, and frame pulse, CMVFPB. CASBRD is updated on every second rising edge of CMV8MCLK as fixed by the common H-MVIP frame pulse clock, CMVFPC.

CASBRD shares the same pin as BRPCM[1]. In Receive Clock Slave: HMVIP mode, this output is CASBRD. In all other modes, this output is BRPCM[1]. By default this output is BRPCM[1].

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE 23

RELEASED

DATASHEET

PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1

PM4354 COMET-QUAD

TRANSCEIVER / FRAMER

Pin Name Type Pin No. Function

CMVFPC Input F1

Transmit Line Interface

TXTIP1[1] TXTIP1[2] TXTIP1[3] TXTIP1[4]

TXTIP2[1] TXTIP2[2] TXTIP2[3] TXTIP2[4]

Analog OutputB4A13

P4 R13

B6 A11 R6 T11

Common H-MVIP Frame Pulse Clock (CMVFPC). The common H-MVIP frame pulse clock provides the frame pulse clock for operation with 8.192 Mbit/s H-MVIP access.

CMVFPC is used to sample CMVFPB. CMVFPC is nominally a 50% duty cycle clock with a frequency of 4.096 MHz. The falling edge of CMVFPC must be aligned with the falling edge of CMV8MCLK with no more than ±10ns skew.

The Transmitter and Receiver streams are independently enabled for HMVIP access. When H-MVIP access is enabled, all four Transmitter (or Receiver) streams are enabled for H-MVIP access. When both the Transmitter and the Receiver H-MVIP accesses are disabled, CMVFPC is unused.

Transmit Analog Positive Pulse (TXTIP1[1:4] and TXTIP2[1:4]). When the transmit analog line interface is enabled, the TXTIP1[x] and TXTIP2[x] analog outputs drive the transmit line pulse signal through an external matching transformer. Both TXTIP1[x] and TXTIP2[x] are normally connected to the positive lead of the transformer primary. Two outputs are provided for better signal integrity and must be shorted together on the board.

After a reset, TXTIP1[x] and TXTIP2[x] are high impedance. The HIGHZ bit of the quadrant’s XLPG Line Driver Configuration register (addresses 0F0H, 1F0H, 2F0H, 3F0H) must be programmed to logic 0 to remove the high impedance state.

TXRING1[1] TXRING1[2] TXRING1[3] TXRING1[4]

TXRING2[1] TXRING2[2] TXRING2[3] TXRING2[4]

Analog OutputA3C13

R4 T13

D5 B11 N5 R11

Transmit Analog Negative Pulse (TXRING1[1:4] and TXRING2[1:4]).

When the transmit analog line interface is enabled, the TXRING1[x] and TXRING2[x] analog outputs drive the transmit line pulse signal through an external matching transformer. Both TXRING1[x] and TXRING2[x] are normally connected to the negative lead of the transformer primary. Two outputs are provided for better signal integrity and must be shorted together on the board.

After a reset, TXRING1[x] and TXRING2[x] are high impedance. The HIGHZ bit of the quadrant’s XLPG Line Driver Configuration register (addresses 0F0H, 1F0H, 2F0H, 3F0H) must be programmed to logic 0 to remove the high impedance state.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE 24

RELEASED

DATASHEET

PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1

PM4354 COMET-QUAD

TRANSCEIVER / FRAMER

Pin Name Type Pin No. Function

TXCM[1] TXCM[2] TXCM[3] TXCM[4]

Analog I/O

C5 D12 P5 N12

Receive Line Interface

RXTIP[1] RXTIP[2] RXTIP[3] RXTIP[4]

RVREF[1] RVREF[2] RVREF[3] RVREF[4]

RXRING[1] RXRING[2] RXRING[3] RXRING[4]

Analog InputC7D10

P7 N10

Analog I/O

A8 C9 T8 P9

Analog InputA7C10

T7 P10

Timing Options Control

XCLK Input J13

Transmit Common Mode (TXCM[1:4]). This pin is the common mode for the Transmit analog. It requires a 4.7µF capacitor to analog ground and two

12.7Ω resistors to the corresponding TXRING and TXTIP.

Receive Analog Positive Pulse (RXTIP[1:4]). When the analog receive line interface is enabled, RXTIP[x] samples the received line pulse signal from an external isolation transformer. RXTIP[x] is normally connected directly to the positive lead of the receive transformer secondary.

Receive Voltage Reference (RVREF[1:4]). This pin must be connected to an external RC network consisting of a 100 kΩ resistor connected in parallel with a 10 nF capacitor to analog ground.

Receive Analog Negative Pulse (RXRING[1:4]). When the analog receive line interface is enabled, RXRING[x] samples the received line pulse signal from an external isolation transformer. RXRING[x] is normally connected directly to the negative lead of the receive transformer secondary.

Crystal Clock Input (XCLK). This signal provides a stable, global timing reference for the COMET-QUAD internal circuitry via an internal clock synthesizer. XCLK is a nominally jitter free clock at 1.544 MHz in T1 mode and 2.048 MHz in E1 mode.

In T1 mode, a 2.048 MHz clock may be used as a reference. When used in this way, however, the intrinsic jitter specifications to AT&T TR62411 may not be met.

CTCLK Input L16

Common Transmit Clock (CTCLK). This input signal can be used as a reference for the transmit line rate generation. CTCLK may be any multiple of 8 kHz (N x 8 kHz, where 1≤N≤256) so long as CTCLK has minimal jitter when divided down to 8 kHz. When the CTCLK frequency differs from the transmit line rate, the transmit jitter attenuation block (TJAT) must be enabled to synthesize and jitter attenuate the transmit clock. When the CTCLK frequency is the same as the transmit line rate, CTCLK is optionally jitter attenuated by the TJAT. When CTCLK jitter attenuation is enabled, the CTCLK frequency should be programmed into the TJAT Jitter Attenuation Divider N1 Control register.

The COMET-QUAD may be configured to ignore the CTCLK input and utilize the Receive recovered clock or the backplane transmit clock.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE 25

RELEASED

DATASHEET

PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1

PM4354 COMET-QUAD

TRANSCEIVER / FRAMER

Pin Name Type Pin No. Function

RSYNC Output R16

PIO I/O R15

RES[1] RES[2] RES[3] RES[4] RES[8]

RES[5] RES[6]

Output L14

N3 J15 J4 T15

Analog I/O

D8 P8

Recovered Clock Synchronization Signal (RSYNC). This output signal is the jitter attenuated recovered receiver line rate clock (1.544 or 2.048 MHz) of one of the four T1 or E1 channels or, optionally, the jitter attenuated recovered clock synchronously divided by 193 (T1 mode) or 256 (E1 mode) to create a 8 kHz timing reference signal. When 8 kHz, the RSYNC phase is independent of frame alignment and is not affected by framing events. The default is to source RSYNC from quadrant #1. The RJATBYP register bit has no effect on RSYNC.

When the COMET-QUAD is in a loss of signal state, RSYNC is derived from the XCLK input or, optionally, is held high.

Programmable I/O (PIO). PIO is an input/output pin controlled by a COMET-QUAD register bit. When configured as an output, the PIO pin can, under software control, be used to configure external circuitry. When configured as an input, a COMET-QUAD register bit reflects the state of the PIO pin.

Reserved (RES[1:4], RES[8]). Reserved.

These pins must be left unconnected.

Reserved (RES[5:6]). Reserved.

These pins must be connected to an analog ground.

RES[7] Input T16

Reserved (RES[7]). Reserved.

This pin must be tied low.

ATB[1 ] ATB[2 ]

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE 26

Analog I/O

D8 P8

Analog Test Bus (ATB[1:2]). Reserved for COMET-QUAD production test. This pin must be connected to an analog ground for normal operation.

RELEASED

DATASHEET

PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1

PM4354 COMET-QUAD

TRANSCEIVER / FRAMER

Pin Name Type Pin No. Function

Microprocessor Interface

A[0] A[1] A[2] A[3] A[4] A[5] A[6] A[7] A[8] A[9] A[10]

Input B13

A14 B14 A15 B15 A16 B16 C15 C16 D16 D15

RDB Input D14

WRB Input E15

CSB Input E16

Address Bus (A[10:0]). This bus selects specific registers during COMETQUAD register accesses.

Active Low Read Enable (RDB). This signal is low during COMET-QUAD register read accesses. The COMET-QUAD drives the D[7:0] bus with the contents of the addressed register while RDB and CSB are low.

Active Low Write Strobe (WRB). This signal is low during a COMET-QUAD register write access. The D[7:0] bus contents are clocked into the addressed register on the rising WRB edge while CSB is low.

Active Low Chip Select (CSB). CSB must be low to enable COMET-QUAD register accesses. CSB must go high at least once after power up to clear internal test modes. If CSB is not used, it should be tied to an inverted version of RSTB, in which case, RDB and W RB determine register accesses. To ensure normal operation, the RSTB pin should be driven low and the CSB pin driven high concurrently following power up.

ALE Input E14

Address Latch Enable (ALE). This signal is active high and latches the address bus contents, A[10:0], when low. When ALE is high, the internal address latches are transparent. ALE allows the COMET-QUAD to interface to a multiplexed address/data bus. The ALE input has an internal pull up resistor.

INTB OutputODF15

Active low Open-Drain Interrupt (INTB). This signal goes low when an unmasked interrupt event is detected on any of the internal interrupt sources. Note that INTB will remain low until all active, unmasked interrupt sources are acknowledged at their source at which time, INTB will tristate.

RSTB Input E13

Active Low Reset (RSTB). This signal provides an asynchronous COMETQUAD reset. RSTB is a Schmidt triggered input with an internal pull up resistor.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE 27

RELEASED

DATASHEET

PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1

PM4354 COMET-QUAD

TRANSCEIVER / FRAMER

Pin Name Type Pin No. Function

D[0] D[1] D[2] D[3] D[4] D[5] D[6] D[7]

I/O B3

A2 A1 B1 C1 C2 D2 D3

JTAG Interface

TDO Output T1

TDI Input T3

TCK Input T2

TMS Input R3

Bidirectional Data Bus (D[7:0]). This bus provides COMET-QUAD register read and write accesses.

Test Data Output (TDO). This signal carries test data out of the COMETQUAD via the IEEE P1149.1 test access port. TDO is updated on the falling edge of TCK. TDO is a tri-state output that is tri-stated except when scanning of data is in progress.

Test Data Input (TDI). This signal carries test data into the COMET-QUAD via the IEEE P1149.1 test access port. TDI is sampled on the rising edge of TCK. TDI has an internal pull up resistor.

Test Clock (TCK). This signal provides timing for test operations that can be carried out using the IEEE P1149.1 test access port.

Test Mode Select (TMS). This signal controls the test operations that can be carried out using the IEEE P1149.1 test access port. TMS is sampled on the rising edge of TCK. TMS has an internal pull up resistor.

TRSTB Input P3

Active low Test Reset (TRSTB). This signal provides an asynchronous COMET-QUAD test access port reset via the IEEE P1149.1 test access port. TRSTB is a Schmidt triggered input with an internal pull up resistor. TRSTB must be asserted during the power up sequence.

Note that if not used, TRSTB must be connected to the RSTB input.

Analog Power and Ground Pins

TAVD1[1] TAVD1[2] TAVD1[3] TAVD1[4]

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE 28

Analog PowerA6C11

T6 P11

Transmit Analog Power (TAVD1[1:4]). TAVD1[1:4] provides power for the transmit LIU reference circuitry. TAVD1[1:4] should be connected to analog +3.3 V.

RELEASED

DATASHEET

PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1

PM4354 COMET-QUAD

TRANSCEIVER / FRAMER

Pin Name Type Pin No. Function

TAVD2[1] TAVD2[2]

Analog

PowerA4D13 TAVD2[3] TAVD2[4]

TAVD3[1] TAVD3[2] TAVD3[3] TAVD3[4]

CAVD Analog

Power

TAVS1[1] TAVS1[2]

Analog

GroundC6D11 TAVS1[3] TAVS1[4]

TAVS2[1] TAVS2[2]

Analog

GroundC4B12 TAVS2[3] TAVS2[4]

TAVS3[1] TAVS3[2] TAVS3[3] TAVS3[4]

T4 P13

A5 C12 T5 P12

P6 N11

N4 R12

B5 A12 R5 T12

Transmit Analog Power (TAVD2[1:4], TAVD3[1:4]). TAVD2[1:4] and TAVD3[1:4] supply power for the transmit LIU output drivers. TAVD2[1:4] and TAVD3[1:4] should be connected to analog +3.3 V.

Clock Synthesis Unit Analog Power (CAVD). CAVD supplies power for the transmit clock synthesis unit. CAVD should be connected to analog +3.3 V.

Transmit Analog Ground (TAVS1[1:4]). TAVS1[1:4] provides ground for the transmit LIU reference circuitry. TAVS1[1:4] should be connected to analog GND.

Transmit Analog Ground (TAVS2[1:4], TAVS3[1:4]). TAVS2[1:4] and TAVS3[1:4] supply ground for the transmit LIU output drivers. TAVS2[1:4] and TAVS3[1:4] should be connected to analog GND.

CAVS Analog

Ground

Clock Synthesis Unit Analog Ground (CAVS). CAVS supplies ground for the transmit clock synthesis unit. CAVS should be connected to analog GND.

RAVD1[1] RAVD1[2] RAVD1[3] RAVD1[4]

RAVD2[1] RAVD2[2] RAVD2[3] RAVD2[4]

RAVS1[1] RAVS1[2] RAVS1[3] RAVS1[4]

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE 29

Analog

PowerB8B9

R8 T9

Analog

PowerB7A10

R7 T10

Analog

GroundD7A9

N7 R9

Receive Analog Power (RAVD1[1:4]). RAVD1[1:4] supplies power for the receive LIU input equalizer. RAVD1[1:4] should be connected to analog +3.3 V.

Receive Analog Power (RAVD2[1:4]). RAVD2[1:4] supplies power for the receive LIU peak detect and slicer. RAVD2[1:4] should be connected to analog +3.3 V.

Receive Analog Ground (RAVS1[1:4]). RAVS1[1:4] supplies ground for the receive LIU input equalizer. RAVS1[1:4] should be connected to analog GND.

RELEASED

DATASHEET

PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1

PM4354 COMET-QUAD

TRANSCEIVER / FRAMER

Pin Name Type Pin No. Function

RAVS2[1] RAVS2[2] RAVS2[3] RAVS2[4]

QAVD[1] QAVD[2]

QAVS[1] QAVS[2]

Analog

GroundD6B10

N6 R10

Analog

PowerC8R14

Analog

GroundD9T14

Receive Analog Ground (RAVS2[1:4]). RAVS2[1:4] supplies ground for the receive LIU peak detect and slicer. RAVS2[1:4] should be connected to analog GND.

Quiet Analog Power (QAVD[1:2]). QAVD[1:2] supplies power for the core analog circuitry. QAVD[x] should be connected to analog +3.3 V.

Quiet Analog Ground (QAVS[1:2]). QAVS[1:2] supplies ground for the core analog circuitry. QAVS[x] should be connected to analog GND.

Digital Power and Ground Pins

VDDC25[1] VDDC25[2] VDDC25[3] VDDC25[4] VDDC25[5] VDDC25[6] VDDC25[7] VDDC25[8]

Power G1

H3 J1 L1 H15 K15 M13 J16

Core Power (VDDC25[1:8]). The VDDC25[1:8] pins should be connected to a well decoupled +2.5V DC power supply.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE 30

RELEASED

DATASHEET

PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1

PM4354 COMET-QUAD

TRANSCEIVER / FRAMER

Pin Name Type Pin No. Function

VSSC25[1] VSSC25[2] VSSC25[3] VSSC25[4] VSSC25[5] VSSC25[6] VSSC25[7]

GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND

Ground G2

H1 J3 L3 G13 K16 L15

G7 G8 G9 G10 H7 H8 H9 H10 J7 J8 J9 J10 K7 K8 K9 K10

Core Ground (VSSC25[1:7]). The VSSC25[1:7] pins should be connected to GND. The 16 thermal balls should also be connected to GND.

VDDQ33[1] VDDQ33[2]

VSSQ33[1] VSSQ33[2]

VDD33[1] VDD33[2] VDD33[3] VDD33[4] VDD33[5] VDD33[6]

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE 31

Power H2

K14

Ground G4

K13

Power C3

D4 K4 N2 G16 N14

Quiet Power (VDDQ33[1:2]). The VDDQ33[1:2] pins should be connected to a well decoupled +3.3V DC power supply.

Quiet Ground (VSSQ33[1:2]). The VSSQ33[1:2] pins should be connected to GND.

Switching Power (VDD33[1:6]). The VDD33[1:6] pins should be connected to a well decoupled +3.3V DC power supply.

RELEASED

DATASHEET

PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1

PM4354 COMET-QUAD

TRANSCEIVER / FRAMER

Pin Name Type Pin No. Function

VSS33[1] VSS33[2] VSS33[3] VSS33[4] VSS33[5] VSS33[6] VSS33[7] VSS33[8] VSS33[9]

Ground B2

Switching Ground (VSS33[1:9]). The VSS33[1:9] pins should be

connected to GND. J2 R2 F14 L13 P14 M2 C14

NOTES ON PIN DESCRIPTIONS:

1. All COMET-QUAD inputs and bi-directionals present minimum capacitive loading.

2. All COMET-QUAD inputs and bi-directionals, when configured as inputs, tolerate TTL logic levels.

3. All COMET-QUAD outputs and bi-directionals have at least 2 mA drive capability. The data bus outputs, D[7:0], the INTB output, and the BRCLK[1:4] and BTCLK[1:4] outputs has 4 mA drive capability. The transmit analog outputs (TXTIP and TXRING) have built-in short circuit current limiting.

4. Inputs RSTB, ALE, TMS, TDI and TRSTB have internal pull-up resistors.

5. Input PIO has an internal pull-down resistor.

6. All unused inputs should be connected to GROUND.

7. It is recommended that the VSS33 and VSSC25 pins be connected to a common GROUND Plane.

8. The 3.3 Volt power pins (i.e., TAVD1, TAVD2, TAVD3, CAVD, RAVD1, RAVD2, QAVD, VDD33, and VDDQ33) will be collectively referred to as V

9. Power to V

DDall33

should be applied before power to the VDDC25 pins is applied. Similarly,

DDall33

power to the VDDC25 pins should be removed before power to V

10. The V

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE 32

DDall33

voltage level should not be allowed to drop below the VDDC25 voltage level.

in this document.

DDall33

is removed.

RELEASED

DATASHEET

PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1

PM4354 COMET-QUAD

TRANSCEIVER / FRAMER

9 FUNCTIONAL DESCRIPTION

9.1 Quadrants

The COMET-QUAD’s four E1/T1 transceivers/framers operate independently and can be configured to operate uniquely. The COMET-QUAD transceiver/framers (or quadrants) do share a common XCLK crystal clock input and internal clock synthesizer; hence a single CSU Configuration register is present and all quadrants share a common E1/T1B mode register bit. When an H-MVIP interface is enabled, the interface interacts with all four quadrants, and hence some common settings are required.

9.2 Receive Interface

The analog receive interface is configurable to operate in both E1 and T1 short-haul and long-haul applications. Short-haul T1 is defined as transmission over less than 655 ft of cable. Short-haul E1 is defined as transmission on any cable that attenuates the signal by less than 6 dB.

For long-haul signals, unequalized long- or short-haul bipolar alternate mark inversion (AMI) signals are received as the differential voltage between the RXTIP and RXRING inputs. The COMET-QUAD typically accepts unequalized signals that are attenuated for both T1 and E1 signals and are non-linearly distorted by typical cables.

For short-haul, the slicing threshold is set to a fraction of the input signal’s peak amplitude, and adapts to changes in this amplitude. The slicing threshold is programmable, but is typically 67% and 50% for DSX-1 and E1 applications, respectively. Abnormally low input signals are detected when the input level is below a programmable threshold, which is typically 140 mV for E1 and 105 mV for T1.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE 33

RELEASED

DATASHEET

PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1

PM4354 COMET-QUAD

TRANSCEIVER / FRAMER

Figure 5 - External Analog Interface Circuits

TXTIP1 TXTIP2

TV REF

TXRING1 TXRING2

ATB

RXTIP

RXRING

T1 or E1 Transc eiver / Framers

One of Four

Figure 5 gives the recommended external protection circuitry for designs required to meet the major surge immunity and electrical safety standards including FCC Part 68, UL1950, and Bellcore TR-NWT-001089. Standards compliance testing of this circuitry has not completed as of the date of publication of this document.

For systems not requiring phantom feed or inter-building line protection, the Bi-directional Transient Surge Suppressors (Z1-Z4), their associated ground connection and the center tap of the transformer can be removed from the circuit.

See Table 1 for the descriptions of components for Figure 5. See Table 2 for the descriptions of values for the transformer turns ratio, n, Rt1 and Rt2 for Figure 5.

Note that the crowbar devices (Z1 – Z4) are not required if the transformer’s isolation rating is not exceeded.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE 34

RELEASED

DATASHEET

PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1

PM4354 COMET-QUAD

TRANSCEIVER / FRAMER

Table 1: - External Component Descriptions

Component

Rt1 & Rt2

Description Part # Source

Typically 12.7Ω ±1% Resistors (see Table

Rterm

18.2Ω ±1% Resistor for T1 & 120Ω E1 13Ω ±1% Resistor for 75Ω E1

(assuming a 1:2.42 transformer)

C0 & C1

4.7µF±10% Capacitors

F1 – F4 1 Amp, 600V Fuses

Rf1 – Rf4

TVS1 & TVS2 6V Bi-directional Transient Voltage

2Ω ±1%, 2W, Resistors

LC01-6 Semtech

Suppressor Diode

D1 Surge Protector Diode Array SRDA3.3-4 Semtech

Z1 – Z4 Bi-directional Transient Surge Suppressors SGT27B13 Harris

T1 & T2 Generally 1:2.42CT Transformers (see

Table 2)

50436 (single)

T1137 (dual)

TG23-1505NS

(single)

TG23-1505N1

(dual)

Midcom

Pulse

Halo

Table 2 : - Termination Resistors, Transformer Ratios and TRL

Case

SH T1: Zo=100Ω

SH E1: Zo=120Ω

SH E1: Zo=75Ω

LH T1 LBO=0dB: Zo=100Ω

LH T1 LBO=-7.5dB: Zo=100Ω

LH T1 LBO=-15dB: Zo=100Ω

LH T1 LBO=-22.5dB:

n Rt1 Rt2 Typical TRL

1:2.42

12.7Ω ±1% 12.7Ω ±1%

12.7Ω ±1%

8.06Ω ±1%

12.7Ω ±1%

8.06Ω ±1%

12.7Ω ±1% 12.7Ω ±1%

14.1dB

19.4dB

9.6dB

18.8dB

14.1dB

Zo=100Ω

Notes:

1) Headroom power is about 30% higher in this case.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE 35

RELEASED

DATASHEET

PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1

PM4354 COMET-QUAD

TRANSCEIVER / FRAMER

9.3 Clock and Data Recovery (CDRC)

The Clock and Data Recovery function is provided by the Clock and Data Recovery (CDRC) block. The CDRC provides clock and PCM data recovery, B8ZS and HDB3 decoding, line code violation detection, and loss of signal detection. It recovers the clock from the incoming RZ data pulses using a digital phase-locked-loop and reconstructs the NRZ data. Loss of signal is indicated after a programmable threshold of consecutive bit periods of the absence of pulses on both the positive and negative line pulse inputs and is cleared after the occurrence of a single line pulse. An alternate loss of signal indication is provided which is cleared upon meeting an 1-in-8 pulse density criteria for T1 and a 1-in-4 pulse density criteria for E1. If enabled, a microprocessor interrupt is generated when a loss of signal is detected and when the signal returns. A line code violation is defined as a bipolar violation (BPV) for AMI-coded signals, is defined as a BPV that is not part of a zero substitution code for B8ZS-coded signals, and is defined as a bipolar violation of the same polarity as the last bipolar violation for HDB3-coded signals.

In T1 mode, the input jitter tolerance of the COMET-QUAD complies with the Bellcore Document TA-TSY-000170 and with the AT&T specification TR62411, as shown in Figure 6. The tolerance is measured with a QRSS sequence (2

-1 with 14 zero restriction). The CDRC block provides two algorithms for clock recovery that result in differing jitter tolerance characteristics. The first algorithm (when the ALGSEL register bit is logic 0) provides good low frequency jitter tolerance, but the high frequency tolerance is close to the TR62411 limit. The second algorithm (when ALGSEL is logic 1) provides much better high frequency jitter tolerance at the expense of the low frequency tolerance; the low frequency tolerance of the second algorithm is approximately 80% that of the first algorithm.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE 36

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PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1

PM4354 COMET-QUAD

TRANSCEIVER / FRAMER

Figure 6: - T1 Jitter Tolerance

Acceptable Range

Sine W ave

Jitter

Amplitude

P. to P. (UI)

Log Scale

1.0

0.3

0.2

Bellcore Spec.

AT&T Spec.

0.1

0.310.30

100101.0

Sine Wave Jitter Frequency (kHz) Log Scale

For E1 applications, the input jitter tolerance complies with the ITU-T Recommendation G.823 "The Control of Jitter and Wander Within Digital Networks Which are Based on the 2048 kbit/s Hierarchy." Figure 7 illustrates this specification and the performance of the phase-locked loop when the ALGSEL register bit is logic 0.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE 37

RELEASED

DATASHEET

PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1

PM4354 COMET-QUAD

TRANSCEIVER / FRAMER

Figure 7: - Compliance with ITU-T Specification G.823 for E1 Input Jitter

DPLL TOLERANCE

WITH AMI ENCODED

2 -1 PRBS

SINEWAVE

JITTER AMPLITUDE P. TO P. (UI) LOG SCALE

IN SPEC REGION

DPLL TOLERANCE WITH HDB3 ENCODED

2 -1 PRBS

1.5

0.2

0.1 34

2.4

10 10 10

SINEWAVE JITTER FREQUENCY, Hz - LOG SCALE

9.4 Receive Jitter Attenuator (RJAT)

The Receive Jitter Attenuator (RJAT) digital PLL attenuates the jitter present on the RXTIP/RXRING inputs. The attenuation is only performed when the RJATBYP register bit is a logic 0.

The jitter characteristics of the Receive Jitter Attenuator (RJAT) are the same as the Transmit Jitter Attenuator (TJAT).

REC. G823 JITTER TOLERANCE SPECIFICATION

1.8

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9.5 T1 Inband Loopback Code Detector (IBCD)

The T1 Inband Loopback Code Detection function is provided by the IBCD block. This block detects the presence of either of two programmable INBAND LOOPBACK ACTIVATE and DEACTIVATE code sequences in either framed or unframed data streams. Each INBAND LOOPBACK code sequence is defined as the repetition of the programmed code in the PCM stream for at least 5.1 seconds. The code sequence detection and timing is compatible with the specifications defined in T1.403-1993, TA-TSY-000312, and TR-TSY-000303. LOOPBACK ACTIVATE and DEACTIVATE code indication is provided through internal register bits. An interrupt is generated to indicate when either code status has changed.

9.6 T1 Pulse Density Violation Detector (PDVD)

The Pulse Density Violation Detection function is provided by the PDVD block. The block detects pulse density violations of the requirement that there be N ones in each and every time window of 8(N+1) data bits (where N can equal 1 through 23). The PDVD also detects periods of 16 consecutive zeros in the incoming data. Pulse density violation detection is provided through an internal register bit. An interrupt is generated to signal a 16 consecutive zero event, and/or a change of state on the pulse density violation indication.

9.7 T1 Framer (T1-FRMR)

The T1 framing function is provided by the T1-FRMR block. This block searches for the framing bit position in the backplane receive stream. It works in conjunction with the FRAM block to search for the framing bit pattern in the standard superframe (SF), or extended superframe (ESF) framing formats. When searching for frame, the FRMR simultaneously examines each of the 193 (SF) or each of the 772 (ESF) framing bit candidates. The FRAM block is addressed and controlled by the FRMR while frame synchronization is acquired.

The time required to acquire frame alignment to an error-free backplane receive stream, containing randomly distributed channel data (i.e. each bit in the channel data has a 50% probability of being 1 or 0), is dependent upon the framing format. For SF format, the T1-FRMR block will determine frame alignment within 4.4 ms 99 times out of 100. For ESF format, the T1FRMR will determine frame alignment within 15 ms 99 times out of 100.

Once the T1-FRMR has found frame, the backplane receive data is continuously monitored for framing bit errors, bit error events (a framing bit error in SF or a CRC-6 error in ESF), and severely errored framing events. The T1-FRMR also detects out of frame, based on a selectable ratio of framing bit errors.

The T1-FRMR can also be disabled to allow reception of unframed data.

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9.8 E1 Framer (E1-FRMR)

The E1 framing function is provided by the E1-FRMR block. The E1-FRMR block searches for basic frame alignment, CRC multiframe alignment, and channel associated signaling (CAS) multiframe alignment in the incoming recovered PCM stream.

Once the E1-FRMR has found basic (or FAS) frame alignment, the incoming PCM data stream is continuously monitored for FAS/NFAS framing bit errors. Framing bit errors are accumulated in the framing bit error counter contained in the PMON block. Once the E1-FRMR has found CRC multiframe alignment, the PCM data stream is continuously monitored for CRC multiframe alignment pattern errors, and CRC-4 errors. CRC-4 errors are accumulated in the CRC error counter of the PMON block. Once the E1-FRMR has found CAS multiframe alignment, the PCM data is continuously monitored for CAS multiframe alignment pattern errors. The E1-FRMR also detects and indicates loss of basic frame, loss of CRC multiframe, and loss of CAS multiframe, based on user-selectable criteria. The reframe operation can be initiated by software (via the E1-FRMR Frame Alignment Options register), by excessive CRC errors, or when CRC multiframe alignment is found by the offline framer. The E1-FRMR also identifies the position of the frame, the CAS multiframe, and the CRC multiframe.

The E1-FRMR extracts the contents of the International bits (from both the FAS frames and the NFAS frames), the National bits, and the Extra bits (from timeslot 16 of frame 0 of the CAS multiframe), and stores them in the E1-FRMR International/National Bits register and the E1-FRMR Extra Bits register. Moreover, the E1-FRMR also extracts submultiframe-aligned 4-bit codewords from each of the National bit positions Sa4 to Sa8, and stores them in microprocessoraccessible registers that are updated every CRC submultiframe.

The E1-FRMR identifies the raw bit values for the Remote (or distant frame) Alarm (bit 3 in timeslot 0 of NFAS frames) and the Remote Signaling Multiframe (or distant multiframe) Alarm (bit 6 of timeslot 16 of frame 0 of the CAS multiframe) via the E1-FRMR International/National Bits Register, and the E1-FRMR Extra Bits Register respectively. Access is also provided to the "debounced" remote alarm and remote signaling multiframe alarm bits which are set when the corresponding signals have been a logic 1 for 2 or 3 consecutive occurrences, as per Recommendation O.162. Detection of AIS and timeslot 16 AIS are provided. AIS is also integrated, and an AIS Alarm is indicated if the AIS condition has persisted for at least 100 ms. The out of frame (OOF=1) condition is also integrated, indicating a Red Alarm if the OOF condition has persisted for at least 100 ms.

An interrupt may be generated to signal a change in the state of any status bits (OOF, OOSMF, OOCMF, AIS or RED), and to signal when any event (RAI, RMAI, AISD, TS16AISD, COFA, FER, SMFER, CMFER, CRCE or FEBE) has occurred. Additionally, interrupts may be generated every frame, CRC submultiframe, CRC multiframe or signaling multiframe.

Basic Frame Alignment Procedure

The E1-FRMR searches for basic frame alignment using the algorithm defined in ITU-T Recommendation G.706 sections 4.1.2 and 4.2.

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The algorithm finds frame alignment by using the following sequence:

1. Search for the presence of the correct 7-bit FAS (‘0011011’);

2. Check that the FAS is absent in the following frame by verifying that bit 2 of the assumed nonframe alignment sequence (NFAS) TS 0 byte is a logic 1;

3. Check that the correct 7-bit FAS is present in the assumed TS 0 byte of the next frame.

If either of the conditions in steps 2 or 3 are not met, a new search for frame alignment is initiated in the bit immediately following the second 7-bit FAS sequence check. This "hold-off" is done to ensure that new frame alignment searches are done in the next bit position, modulo 512. This facilitates the discovery of the correct frame alignment, even in the presence of fixed timeslot data imitating the FAS.

These algorithms provide robust framing operation even in the presence of random bit errors: framing with algorithm #1 or #2 provides a 99.98% probability of finding frame alignment within 1 ms in the presence of 10-3 bit error rate and no mimic patterns.

Once frame alignment is found, the block sets the OOF indication low, indicates a change of frame alignment (if it occurred), and monitors the frame alignment signal, indicating errors occurring in the 7-bit FAS pattern and in bit 2 of NFAS frames, and indicating the debounced value of the Remote Alarm bit (bit 3 of NFAS frames). Using debounce, the Remote Alarm bit has <0.00001% probability of being falsely indicated in the presence of a 10-3 bit error rate. The block declares loss of frame alignment if 3 consecutive FAS's have been received in error or, additionally, if bit 2 of NFAS frames has been in error for 3 consecutive occasions. In the presence of a random 10-3 bit error rate the frame loss criteria provides a mean time to falsely lose frame alignment of >12 minutes.

The E1-FRMR can be forced to initiate a basic frame search at any time when any of the following conditions are met:

• the software re-frame bit in the E1-FRMR Frame Alignment Options register goes to logic 1;

• the CRC Frame Find Block is unable to find CRC multiframe alignment; or

• the CRC Frame Find Block accumulates excessive CRC evaluation errors (≥ 915 CRC errors

in 1 second) and is enabled to force a re-frame under that condition.

CRC Multiframe Alignment Procedure

The E1-FRMR searches for CRC multiframe alignment by observing whether the International bits (bit 1 of TS 0) of NFAS frames follow the CRC multiframe alignment pattern. Multiframe alignment is declared if at least two valid CRC multiframe alignment signals are observed within 8 ms, with the time separating two alignment signals being a multiple of 2 ms

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Once CRC multiframe alignment is found, the OOCMFV register bit is set to logic 0, and the E1-FRMR monitors the multiframe alignment signal, indicating errors occurring in the 6-bit MFAS pattern, errors occurring in the received CRC and the value of the FEBE bits (bit 1 of frames 13 and 15 of the multiframe). The E1-FRMR declares loss of CRC multiframe alignment if basic frame alignment is lost. However, once CRC multiframe alignment is found, it cannot be lost due to errors in the 6-bit MFAS pattern.

Under the CRC-to-non-CRC interworking algorithm, if the E1-FRMR can achieve basic frame alignment with respect to the incoming PCM data stream, but is unable to achieve CRC-4 multiframe alignment within the subsequent 400 ms, the distant end is assumed to be a non CRC4 interface. The details of this algorithm are illustrated in the state diagram in Figure 8.

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Figure 8: - CRC Multiframe Alignment Algorithm

Out of Frame

3 consecutive FASor NFAS errors; manual reframe; or excessive CRC errors

FAS_Find_1

FAS found

NFAS_Find

NFAS found next fram e

FAS_Find_2

FAS found next fram e

CRCMFA

NFAS not found next fram e

FAS not found next fram e

Start 400ms timer and 8ms timer

BFA

8ms expire

8ms expire and NOT(400ms expire)

Reset BFA to most recently found alignment

FAS_Find_1_Par

FAS found

NFAS_Find_Par

NFAS found next fram e

FAS_Find_2_Par

FAS found next fram e

BFA_Par

CRCMFA_Par

NFAS not found next fram e

FAS not found next fram e

Start 8m s tim er

400ms expire

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Table 3: - E1-FRMR Framing States

State Out of Frame Out of Offline Frame

FAS_Find_1 Yes No NFAS_Find Yes No FAS_Find_2 Yes No BFA No No CRC to CRC Interworking No No FAS_Find_1_Par No Yes NFAS_Find_Par No Yes FAS_Find_2_Par No Yes BFA_Par No No CRC to non-CRC Interworking No No

The states of the primary basic framer and the parallel/offline framer in the E1-FRMR block at each stage of the CRC multiframe alignment algorithm are shown in Table 3.

From an out of frame state, the E1-FRMR attempts to find basic frame alignment in accordance with the FAS/NFAS/FAS G.706 Basic Frame Alignment procedure outlined above. Upon achieving basic frame alignment, a 400 ms timer is started, as well as an 8 ms timer. If two CRC multiframe alignment signals separated by a multiple of 2 ms are observed before the 8 ms timer has expired, CRC multiframe alignment is declared.

If the 8 ms timer expires without achieving multiframe alignment, a new offline search for basic frame alignment is initiated. This search is performed in accordance with the Basic Frame Alignment procedure outlined above. However, this search does not immediately change the actual basic frame alignment of the system (i.e., PCM data continues to be processed in accordance with the first basic frame alignment found after an out of frame state while this frame alignment search occurs as a parallel operation).

When a new basic frame alignment is found by this offline search, the 8 ms timer is restarted. If two CRC multiframe alignment signals separated by a multiple of 2 ms are observed before the 8 ms timer has expired, CRC multiframe alignment is declared and the basic frame alignment is set accordingly (i.e., the basic frame alignment is set to correspond to the frame alignment found by the parallel offline search, which is also the basic frame alignment corresponding to the newly found CRC multiframe alignment).

Subsequent expirations of the 8 ms timer will likewise reinitiate a new search for basic frame alignment. If, however, the 400 ms timer expires at any time during this procedure, the E1-FRMR stops searching for CRC multiframe alignment and declares CRC-to-non-CRC interworking. In this mode, the E1-FRMR may be optionally set to either halt searching for CRC multiframe altogether, or may continue searching for CRC multiframe alignment using the established basic frame alignment. In either case, no further adjustments are made to the basic frame alignment, and no offline searches for basic frame alignment occur once CRC-to-non-CRC interworking is declared: it is assumed that the established basic frame alignment at this point is correct.

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AIS Detection

When an unframed all-ones receive data stream is received, an AIS defect is indicated by setting the AISD bit of the E1-FRMR Maintenance/Alarm Status register to logic 1 when fewer than three zero bits are received in 512 consecutive bits or, optionally, in each of two consecutive periods of 512 bits. The AISD bit is reset to logic 0 when three or more zeros in 512 consecutive bits or in each of two consecutive periods of 512 bits. Finding frame alignment will also cause the AISD bit to be set to logic 0.

Signaling Frame Alignment

Once the basic frame alignment has been found, the E1-FRMR searches for Channel Associated Signaling (CAS) multiframe alignment using the following G.732 compliant algorithm: signaling multiframe alignment is declared when at least one non-zero timeslot 16 bit is observed to precede a timeslot 16 containing the correct CAS alignment pattern, namely four zeros (“0000”) in the first four bit positions of timeslot 16.

Once signaling multiframe alignment has been found, the E1-FRMR sets the OOSMFV bit of the E1-FRMR Framing Status register to logic 0, and monitors the signaling multiframe alignment signal, indicating errors occurring in the 4-bit pattern, and indicating the debounced value of the Remote Signaling Multiframe Alarm bit (bit 6 of timeslot 16 of frame 0 of the multiframe). Using debounce, the Remote Signaling Multiframe Alarm bit has < 0.00001% probability of being falsely indicated in the presence of a 10-3 bit error rate.

This E1-FRMR also indicates the reception of TS 16 AIS when timeslot 16 has been received with three or fewer zeros in each of two consecutive multiframe periods. The TS16AIS signal is cleared when each of two consecutive signaling multiframe periods contain four or more zeros OR when the signaling multiframe signal is found.

The block declares loss of CAS multiframe alignment if two consecutive CAS multiframe alignment signals have been received in error, or additionally, if all the bits in timeslot 16 are logic 0 for 1 or 2 (selectable) CAS multiframes. Loss of CAS multiframe alignment is also declared if basic frame alignment has been lost.

National Bit Extraction

The E1-FRMR extracts and assembles the submultiframe-aligned National bit codewords Sa4[1:4], Sa5[1:4], Sa6[1:4], Sa7[1:4] and Sa8[1:4]. The corresponding register values are updated upon generation of the CRC submultiframe interrupt.

This E1-FRMR also detects the V5.2 link ID signal, which is detected when 2 out of 3 Sa7 bits are zeros. Upon reception of this Link ID signal, the V52LINKV bit of the E1-FRMR Framing Status register is set to logic 1. This bit is cleared to logic 0 when 2 out of 3 Sa7 bits are ones.

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Alarm Integration

The OOF and the AIS defects are integrated, verifying that each condition has persisted for 104 ms (± 6 ms) before indicating the alarm condition. The alarm is removed when the condition has been absent for 104 ms (± 6 ms).

The AIS alarm algorithm accumulates the occurrences of AISD (AIS detection). The E1-FRMR counts the occurrences of AISD over a 4 ms interval and indicates a valid AIS is present when 13 or more AISD indications (of a possible 16) have been received. Each interval with a valid AIS presence indication increments an interval counter which declares AIS Alarm when 25 valid intervals have been accumulated. An interval with no valid AIS presence indication decrements the interval counter. The AIS Alarm declaration is removed when the counter reaches 0. This algorithm provides a 99.8% probability of declaring an AIS Alarm within 104 ms in the presence of a 10-3 mean bit error rate.

The Red alarm algorithm monitors occurrences of OOF over a 4 ms interval, indicating a valid OOF interval when one or more OOF indications occurred during the interval, and indicating a valid in frame (INF) interval when no OOF indication occurred for the entire interval. Each interval with a valid OOF indication increments an interval counter which declares Red Alarm when 25 valid intervals have been accumulated. An interval with valid INF indication decrements the interval counter; the Red Alarm declaration is removed when the counter reaches 0. This algorithm biases OOF occurrences, leading to declaration of Red alarm when intermittent loss of frame alignment occurs.

The E1-FRMR can also be disabled to allow reception of unframed data.

9.9 Receive Elastic Store (RX-ELST)

The Elastic Store (ELST) synchronizes backplane receive frames to the backplane receive clock and frame pulse (BRCLK[x], BRFP[x]) in the Clock Slave backplane receive modes or to the common backplane receive H-MVIP clock and frame pulse (CMV8MCLK, CMVFP, CMVFPC) in H-MVIP modes. The frame data is buffered in a two frame circular data buffer. Input data is written to the buffer using a write pointer and output data is read from the buffer using a read pointer.

When the elastic store is being used, if the average frequency of the incoming data is greater than the average frequency of the backplane clock, the write pointer will catch up to the read pointer and the buffer will be filled. Under this condition a controlled slip will occur when the read pointer crosses the next frame boundary. The subsequent backplane receive frame is deleted.

If the average frequency of the incoming data is less than the average frequency of the backplane clock, the read pointer will catch up to the write pointer and the buffer will be empty. Under this condition a controlled slip will occur when the read pointer crosses the next frame boundary. The previous backplane receive frame is repeated.

A slip operation is always performed on a frame boundary.

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When the backplane receive timing is recovered from the receive data the elastic store can be bypassed to eliminate the one frame delay. In this configuration (the Clock Master backplane receive modes), the elastic store is used to synchronize the backplane receive frames to the transmit line clock so that per-DS0 loopbacks may be enabled.

To allow for the extraction of signaling information in the data channels, superframe identification is also passed through the ELST.

For payload conditioning, the ELST may optionally insert a programmable idle code into all channels when the framer is out of frame synchronization. This code is set to all 1’s when the ELST is reset.

9.10 Signaling Extractor (SIGX)

The Signaling Extraction (SIGX) block provides channel associated signaling (CAS) extraction from an E1 signaling multi-frame or from ESF or SF T1 formats. It selectively debounces the bits, and serializes the results onto the BRSIG[x] or CASBRD outputs. Debouncing is performed on individual signaling bits. This BRSIG[x] (CASBRD) output is channel aligned with BRPCM[x] (MVBRD) output, and the signaling bits are repeated for the entire multiframe/superframe, allowing downstream logic to reinsert signaling into any frame, as determined by system timing. The signaling data stream contains the A,B,C,D bits in the lower 4 channel bit locations (bits 5, 6, 7 and 8) in T1 ESF or E1 framing formats; in T1 SF format the A and B bits are repeated in locations C and D (i.e. the signaling stream contains the bits ABAB for each channel).

The SIGX block contains three superframes worth of signal buffering to ensure that there is a greater than 95% probability that the signaling bits are frozen in the correct state for a 50% ones density out of frame condition, as specified in TR-TSY-000170 and BELL PUB 43801. With signaling debounce enabled, the per-channel signaling state must be in the same state for 2 superframes before appearing on the serial output stream.

The SIGX block provides one superframe or signaling-multiframe of signal freezing on the occurrence of slips. When a slip event occurs, the SIGX freezes the output signaling for the entire superframe in which the slip occurred; the signaling is unfrozen when the next slip-free superframe occurs.

The SIGX also provides control over timeslot signaling bit fixing, data inversion and signaling debounce on a per-timeslot basis.

The SIGX block also provides an interrupt to indicate a change of signaling state on a per channel basis.

9.11 Performance Monitor Counters (T1/E1-PMON)

The Performance Monitor Counters function is provided by the PMON block. The block accumulates CRC error events, Frame Synchronization bit error events, and Out Of Frame events, or optionally, Change of Frame Alignment (COFA) events with saturating counters over

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consecutive intervals as defined by the period of the supplied transfer clock signal (typically 1 second). When the transfer clock signal is applied, the PMON transfers the counter values into holding registers and resets the counters to begin accumulating events for the interval. The counters are reset in such a manner that error events occurring during the reset are not missed. If the holding registers are not read between successive transfer clocks, an OVR overrun register bit is asserted.

Generation of the transfer clock within a quadrant is performed by writing to any counter register location within the quadrant or by writing to the Revision/Chip ID/Quadrant PMON Update register. The holding register addresses are contiguous to facilitate faster polling operations.

9.12 T1 Automatic Performance Report Generation (APRM)

In compliance with the ANSI T1.231, T1.403 and T1.408 standards, a performance report is generated each second for T1 ESF applications. The report conforms to the HDLC protocol and is inserted into the ESF facility data link.

The performance report can only be transmitted if the TDPR is configured to insert the ESF Facility Data Link and the PREN bit of the TDPR Configuration register is logic 1. The performance report takes precedence over incompletely written packets, but it does not pre-empt packets already being transmitted.

See the Operation section for details on the performance report encoding.

9.13 T1 Alarm Integrator (ALMI)

The T1 Alarm Integration function is provided by the ALMI block. This block detects the presence of Yellow, Red, and AIS Carrier Fail Alarms (CFA) in SF, or ESF formats. The alarm detection and integration is compatible with the specifications defined in ANSI T1.403 and TR-TSY-000191.

The ALMI block declares the presence of Yellow alarm when the Yellow pattern has been received for 425 ms (± 50 ms); the Yellow alarm is removed when the Yellow pattern has been absent for 425 ms (± 50 ms). The presence of Red alarm is declared when an out of frame condition has been present for 2.55 sec (± 40 ms); the Red alarm is removed when the out of frame condition has been absent for 16.6 sec (± 500 ms). The presence of AIS alarm is declared when an out of frame condition and all-ones in the PCM data stream have been present for 1.5 sec (±100 ms); the AIS alarm is removed when the AIS condition has been absent for 16.8 sec (±500 ms).

CFA alarm detection algorithms operate in the presence of a 10-3 bit error rate.

The ALMI also indicates the presence or absence of the Yellow, Red, and AIS alarm signal conditions over 40 ms, 40 ms, and 60 ms intervals, respectively, allowing an external microprocessor to integrate the alarm conditions via software with any user-specific algorithms. Alarm indication is provided through internal register bits.

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9.14 HDLC Receiver (RDLC)

The RDLC is a microprocessor peripheral used to receive HDLC frames on the T1 4kHz ESF facility data link, the E1 Sa-bit data link, or in any arbitrary timeslot (T1 or E1).

The RDLC detects the change from flag characters to the first byte of data, removes stuffed zeros on the incoming data stream, receives packet data, and calculates the CRC-CCITT frame check sequence (FCS).

In the address matching mode, only those packets whose first data byte matches one of two programmable bytes or the universal address (all ones) are stored in the FIFO. The two least significant bits of the address comparison can be masked for LAPD SAPI matching.

Received data is placed into a 128-level FIFO buffer. An interrupt is generated when a programmable number of bytes are stored in the FIFO buffer. Other sources of interrupt are detection of the terminating flag sequence, abort sequence, or FIFO buffer overrun.

The Status Register contains bits that indicate the overrun or empty FIFO status, the interrupt status, and the occurrence of first flag or end of message bytes written into the FIFO. The Status Register also indicates the abort, flag, and end of message status of the data just read from the FIFO. On end of message, the Status Register indicates the FCS status and if the packet contained a non-integer number of bytes.

9.15 Bit Oriented Code Detector (RBOC)

The Bit Oriented Code detection function is provided by the RBOC block. This block detects the presence of 63 of the possible 64 bit oriented codes transmitted in the T1 Facility Data Link channel in ESF framing format, as defined in ANSI T1.403 and in TR-TSY-000194. The 64 (111111) i s simil ar to t he HDL C flag s equence and is used by the RBOC to indicate no valid code received.

Bit oriented codes are received on the Facility Data Link channel as a 16-bit sequence consisting of 8 ones, a zero, 6 code bits, and a trailing zero (111111110xxxxxx0). BOCs are validated when repeated at least 10 times. The RBOC can be enabled to declare a received code valid if it has been observed for 8 out of 10 times or for 4 out of 5 times, as specified by the AVC bit in the RBOC Configuration/Interrupt Enable register. The RBOC declares that the code is removed if two code sequences containing code values different from the detected code are received in a moving window of ten code periods.

Valid BOC are indicated through the RBOC Interrupt Status register. The BOC bits are set to all ones (111111) if n o val id code has been detected. An interrupt is generated to signal when a detected code has been validated, or optionally, when a valid code goes away (i.e. the BOC bits go to all ones).

code

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9.16 Receive Per-Channel Serial Controller (RPSC)

The RPSC allows data and signaling trunk conditioning to be applied on the backplane receive stream on a per-channel basis. It also allows per-channel control of data inversion, the extraction of clock and data on BRCLK[x] and BRPCM[x] (when the Clock Master: Nx64Kbit/s mode is active), and the detection or generation of pseudo-random patterns. The RPSC operates on the data after its passage through ELST, so that data and signaling conditioning may overwrite the ELST trouble code.

9.17 Pseudo Random Binary Sequence Generation and Detection (PRBS)

The Pseudo Random Binary Sequence Generator/Detector (PRBS) block is a software selectable PRBS generator and checker for 2

-1, 215-1 or 220-1 PRBS polynomials for use in the T1 and E1 links. PRBS patterns may be generated in either the transmit or receive directions, and detected in the opposite direction.

The PRBS block can perform an auto synchronization to the expected PRBS pattern and accumulates the total number of bit errors in two 24-bit counters. The error count accumulates over the interval defined by to the Quadrant PMON Update register. When an accumulation is forced, the holding register is updated, and the counter reset to begin accumulating for the next interval. The counter is reset in such a way that no events are missed. The data is then available in the Error Count registers until the next accumulation.

9.18 Backplane Receive System Interface (BRIF)

The Backplane Receive System Interface (BRIF) block provides system side serial clock and data access as well as H-MVIP access for up to 4 T1 or E1 receive streams. There are several master and slave clock modes for serial clock and data system side access to the T1 and E1 streams. When enabled for 8.192 Mbit/s H-MVIP, there are three separate signals for data and signaling. Information on programming the Backplane Receive System Interface can be found in the Operation section.

Three Clock Master modes provide a serial clock and data backplane receive interface with clocking provided by COMET-QUAD: Clock Master: Full T1/E1, Clock Master: Nx64Kbit/s, Clock Master: Clear Channel. Three Clock slave modes provide a serial clock and data backplane receive mode, an H-MVIP mode, and a mixed clock-and-data/H-MVIP mode. All Clock Slave modes accept externally sourced clocking. The modes are Clock Slave: Full T1/E1, Clock Slave: Full T1/E1 with CCS H-MVIP, and Clock Slave: H-MVIP.

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TRANSCEIVER / FRAMER

Figure 9: - Receive Clock Master: Full T1/E1

BRPCM[x], BRFP[x], BRSIG[x]

Timed to BRCLK[x]

BRPCM[1:4]

BRFP [1:4 ]

BRSIG[1:4]

BRCLK[1:4]

In Receive Clock Master: Full T1/E1 mode, the elastic store is bypassed and the backplane receive clock (BRCLK[x]) is, optionally, a jitter attenuated version of the 1.544 MHz or 2.048 MHz receive clock. The backplane receive data appears on BRPCM[x], the backplane receive signaling appears on BRSIG[x], and the backplane receive frame alignment is indicated by BRFP[x]. In this mode, T1 or E1 data passes through the COMET-QUAD unchanged during out of frame conditions, similar to an offline framer system. When the COMET-QUAD is the clock master in the backplane receive direction, the receive elastic store is used to buffer between the backplane receive and backplane transmit clocks to facilitate per-DS0 loopback.

Figure 10: - Receive Clock Master: Nx64Kbit/s

BRPCM[x], BRFP[x],

BRSIG[x] Timed to

gapped BRCLK[x]

BRPCM[1:4]

BRFP[1:4 ]

BRSIG[1:4 ]

BRCLK[1:4]

Backplane

Interface

BRIF

Backplane

Receive

System

Interface

BRIF

Receive

System

FRAM

Framer:

Slip Buffer RAM

FRM R

Framer:

Frame Alignment,

Alarm Extraction

FRAM

Framer:

Slip Buffer RAM

FRM R

Framer:

Frame Alignment,

Alarm Extraction

RECEIVER

RJAT

Digital Ji tter

Attenu ato r

RECEIVER

RJAT

Digita l Jitter

Attenu ato r

Receive Data[1:4]

Receive CLK[1:4]

Recei ve Data[1:4]

Receive CLK[1:4]

In Receive Clock Master: Nx64Kbit/s mode, BRCLK[x] is a gapped version of the optionally jitter attenuated 1.544 MHz or 2.048 MHz receive clock. BRCLK[x] is gapped on a per channel basis so that a subset of the 24 channels in the T1 frame or 32 channels in an E1 frame is extracted on BRPCM[x]. BRFP[x] indicates frame alignment but, in T1 mode, has no clock since it is gapped during the framing bit positions. Channel extraction is controlled by the RPSC block. The framing bit position is always gapped in T1 mode, so the number of BRCLK[x] pulses is controllable from 0 to 192 pulses per T1 frame or 0 to 256 pulses per E1 frame on a per-DS0 basis. In this mode, T1 or E1 streams pass through the COMET-QUAD unchanged during out of frame conditions. The parity functions are not usable in this mode. When the COMET-QUAD is the clock master in the backplane receive direction, the elastic store is used to buffer between the backplane receive and backplane transmit clocks to facilitate per-DS0 loopback.

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PM4354 COMET-QUAD

TRANSCEIVER / FRAMER

Figure 11: - Receive Clock Master: Clear Channel

BRPCM[x ]

Timed to gapped

BRCLK[x]

BRPCM[1:4]

BRCLK[1:4]

BRIF

Backplane

Receive

System

Interface

RECEIVER

RJAT

Digita l Jitter

Attenuator

Recei ve Data[1:4]

Receive CLK[1:4]

In Receive Clock Master: Clear Channel mode, the elastic store is bypassed and the backplane receive clock (BRCLK[x]) is optionally a jitter attenuated version of the 1.544 MHz or 2.048 MHz receive clock. The backplane receive data appears on BRPCM[x] with no frame alignment indication.

Figure 12: - Receive Clock Slave: Full T1/E1

ELS T

BRCLK[1:4]

BRFP [1:4 ]

BRPCM[1:4]

BRSIG[1:4 ]

BRPCM[x], BRSIG[x ],

Timed to BRCLK[x]

BRIF

Backplane

Receive

System

Interface

Elas tic

Store

FRA M

Framer:

Slip Buffer RAM

FRM R

Framer:

Frame Alignment,

Alarm Extraction

RECEIVER

RJAT

Digital Ji tter

Attenuator

Receive Data[1:4]

Receive CLK[1:4]

In Receive Clock Slave: Full T1/E1 mode, the elastic store is enabled to permit the input BRCLK[x] to specify the backplane receive-side timing. The backplane receive data on BRPCM[x] and signaling BRSIG[x] are bit aligned to the 1.544 MHz or 2.048 MHz backplane receive clock (BRCLK[x]) and are frame aligned to the backplane receive frame pulse (BRFP[x]). BRSIG[x] contains the signaling state (ABCD or ABAB) in the lower four bits of each channel.

Figure 13: - Receive Clock Slave: H-MVIP

ELS T

Elas tic

CMV8MCLK

CMVFPC

CMVFPB

MVBR D

CASBRD

Outpu ts Timed

to CMV8MCLK

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE 52

BRIF

Backplane

Receive

System

Interface

Store

FRA M

Framer:

Slip Buffer RAM

FRM R

Framer:

Frame Alignment,

Alarm Extraction

RECEIVER

RJAT

Digital Jitter

Attenu ato r

Receive Data[1:4]

Receive CLK[1:4]

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PM4354 COMET-QUAD

TRANSCEIVER / FRAMER

When Receive Clock Slave: H-MVIP mode is enabled a 8.192 Mbit/s H-MVIP backplane transmit interface multiplexes up to 128 channels from 4 T1s or E1s, up to 128 channel associated signaling (CAS) channels from 4 T1s or E1s and common channel signaling from up to 4 T1s or E1s. The H-MVIP interface uses common clocks, CMV8MCLK and CMVFPC, and frame pulse, CMVFPB, for synchronization.

Using the H-MVIP interface forces the T1 or E1 receiver to operate in synchronous mode, meaning that elastic stores are used.

The H-MVIP backplane receive data pins are multiplexed with serial data outputs to provide HMVIP access to 128 data channels.

The CASBRD H-MVIP signal provides access to the Channel Associated Signaling (CAS) for all of the 128 data channels. The CAS is time division multiplexed exactly the same way as the data channels and is synchronized with the H-MVIP data channels. Over a T1 or E1 multi-frame the four CAS bits per channel are repeated with each data byte. Four stuff bits are used to pad each CAS nibble (ABCD bits) out to a full byte in parallel with each data byte.

Figure 14: - Receive Clock Slave: Full T1/E1 with CCS H-MVIP

BRPCM[x], BRSIG[x],

Timed to BRCLK[x]

BRCLK[1:4]

BRFP [1:4 ]

BRPCM[1:4]

BRSIG[1:4]

CMV8MCLK

CMVFPC

CMVFPB

CCSBRD

CCSBRD T ime d

to CMV8MCLK

BRIF

Backplane

Receive

System

Interface

ELS T

Ela s tic

Store

CCS ELST

Ela s tic

Store

FRA M

Framer:

Slip Buffer RAM

FRM R

Framer:

Frame Alignment,

Alarm Extraction

RECEIVER

RJAT

Digital Jitter

Attenu ato r

Receive Data[1:4]

Receive CLK[1:4]

In Receive Clock Slave: Full T1/E1 with CCS H-MVIP mode, the elastic store is enabled to permit the input BRCLK[x] to specify the backplane receive-side timing. The backplane receive data on BRPCM[x] and signaling BRSIG[x] are bit aligned to the 1.544 MHz or 2.048 MHz backplane receive clock (BRCLK[x]) and are frame aligned to the backplane receive frame pulse (BRFP[x]). BRSIG[x] contains the signaling state (ABCD or ABAB) in the lower four bits of each channel.

The H-MVIP interface (CMV8MCLK, CMVFPC, CMVFPB, and CCSBRD) extracts Common Channel Signaling (CCS) from the 24

DS0 in T1 mode and up to 3 timeslots (15, 16, 31) in E1 mode. The H-MVIP interface uses common clocks, CMV8MCLK and CMVFPC, and frame pulse, CMVFPB, for synchronization.

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TRANSCEIVER / FRAMER

BRCLK[x] may optionally be configured as clock master. This is represented with the above figure but with BRCLK[x] being driven by the COMET-QUAD rather than being an input.

When CCS H-MVIP is enabled, BRCLK[1:4] must be configured to run at 2.048 MHz.

9.19 Backplane Transmit System Interface (BTIF)

The Backplane Transmit System Interface (BTIF) block provides system side serial clock and data access as well as H-MVIP access for up to 4 T1 or E1 transmit streams. There are several master and slave clocking modes for serial clock and data system side access to the T1 and E1 streams. When enabled for 8.192 Mbit/s H-MVIP there are three separate signals for data and signaling. Information on programming the Backplane Transmit System Interface for various modes can be found in the Operation section.

Three Clock Master modes provide a serial clock and data backplane transmit interface with per link clocking provided by COMET-QUAD: Clock Master: Full T1/E1, Clock Master: Nx64Kbit/s and Clock Master: Clear Channel. Four Clock slave modes provide two serial clock and data backplane transmit modes, a mixed clock-and-data/H-MVIP mode, and a pure H-MVIP mode all with externally sourced clocking: Clock Slave: Full T1/E1, Clock Slave: Full T1/E1 with CCS HMVIP, Clock Slave: Clear Channel and Clock Slave: H-MVIP.

In Clock Master modes the transmit clock can be sourced from either the common transmit clock, CTCLK, the received clock for that link, or one of the two recovered clocks.

Figure 15: - Transmit Clock Master: Full T1/E1

CTCLK

BTPCM[1:4]

BTSIG[1:4]

BTFP[1:4 ]

BTCLK[1:4]

BTPCM[x], BTSIG[x],

BTP[x]Timed to

BTCLK[x]

BTIF

Backplane

Trans mi t

System

Interface

T1 -XBAS /E1- TRAN

BasicTransmitter:

Frame Generation,

Alarm Insertion, Signaling Insertion, Trunk Conditioning

Line Coding

TJAT

Digital PLL

TRANSMITTER

Receive CLK[1:4]

Transm it CLK[1:4]

Trans mi t Data[1 :4]

In Transmit Clock Master: Full T1/E1 mode, the backplane transmit clock (BTCLK[x]) is a jitter attenuated version of the 1.544 MHz or 2.048 MHz receive clock. BTCLK[x] is pulsed for each bit in the 193 bit T1 frame or for each bit in the 256 bit E1 frame. The backplane transmit data is sampled from BTPCM[x], the backplane transmit signaling is sampled from BRSIG[x], and the backplane transmit frame alignment is indicated by BTFP[x].

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PM4354 COMET-QUAD

TRANSCEIVER / FRAMER

Figure 16: - Transmit Clock Master: Nx64Kbit/s

CTCLK

BTPCM[1:4]

BTSIG[1:4]

BTFP[1:4 ]

BTCLK[1:4]

BTPCM[x], BTSIG[x],

BTFP[x] Timed to

BTIF

Backplane

Tra ns mi t

Sys tem

Inte rface

T1-XBAS/ E1-TRAN

Bas icTra ns m itte r:

Frame Generation,

Alarm Ins er tion , Signaling Insertion, Trunk Conditioning

Line Coding

TJAT

Digital PLL

TRANSMITTER

Receive CLK[1:4]

Trans mit CL K[1:4]

Trans mi t Data[1 :4]

gapped BTCLK[x]

In Transmit Clock Master: Nx64Kbit/s mode, BTCLK[x] is gapped on a per-DS0 basis so that a subset of the 24 channels in a T1 frame or 32 timeslots in an E1 frame are inserted on BTPCM[x]. BTFP[x] indicates frame alignment but, in T1 mode, has no clock since it is gapped during the framing bit positions. Channel insertion is controlled by the IDLE_CHAN bits in the TPSC block’s Backplane Transmit Control Bytes. The framing bit position is always gapped, so the number of BTCLK[x] pulses is controllable from 0 to 192 pulses per T1 frame or 0 to 256 pulses per E1 frame on a per-DS0 basis. The parity functions are not usable in Nx64Kbit/s mode.

Figure 17: - Transmit Clock Master: Clear Channel

CTCLK

BTPCM[1:4]

BTCLK[1:4]

BTPCM[x] Timed

to BTCLK[x]

BTIF

Backplane

Trans mit

System

Inte rface

TJAT

Digital PLL

TRANSMITTER

Receive CLK[1:4]

Trans mit CL K[1:4]

Transm it Data[1 :4]

Transmit Clock Master: Clear Channel mode has no frame alignment therefore no frame alignment is indicated to the upstream device. BTCLK[x] is a continuous clock at 1.544 Mbit/s for T1 links or 2.048 Mbit/s for E1 links.

Figure 18: - Transmit Clock Slave: Full T1/E1

TRANSMITTER

BTCLK[1:4]

BTFP[1:4]

BTSIG[1:4]

BTPCM[1:4]

BTPCM[x], BTSIG[x]

Timed to BTCLK[x]

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE 55

BTIF

Backplan e

Trans mi t

System

Interface

T1-XBAS/E1-TRAN

BasicTransmitter:

Frame Generation,

Alar m Ins er tio n,

Signaling Insertion,

Trunk Conditioning

Line C oding

TJAT

Digital PLL

TJAT

FIFO

Trans mit CLK[1:4]

Transm it Data[1:4]

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PM4354 COMET-QUAD

TRANSCEIVER / FRAMER

In Transmit Clock Slave: Full T1/E1 mode, the backplane transmit interface is clocked by the backplane transmit clock (BTCLK[x]). The transmitter is either frame-aligned or superframealigned to the backplane transmit frame pulse (BTFP[x]). BTFP[x] is configurable to indicate the frame alignment or the superframe alignment of BTPCM[x]. BTSIG[x] contain the signaling data to be inserted into Transmit Data[x], with the four least significant bits of each channel on BTSIG[x] representing the signaling state (ABCD or ABAB). BTCLK[x] can be enabled to be either a 1.544 MHz clock for T1 links or a 2.048 MHz clock for T1 and E1 links.

Figure 19: - Transmit Clock Slave: Clear Channel

BTPCM[x] Timed

to BTCLK[x]

BTCLK[1:4]

BTPCM[1:4]

BTIF

Backplane

Trans mit

System

Inte rface

TJAT

Digital PLL

TJAT

FIFO

TRANSMITTER

Trans mit CL K[1:4]

Transm it Data[1 :4]

In Transmit Clock Slave: Clear Channel mode, the backplane transmit interface is clocked by the externally provided backplane transmit clock (BTCLK[x]). BTCLK[x] must be a 1.544 MHz clock for T1 links or a 2.048 MHz clock for E1 links. The Transmit Clock[x] is a jitter attenuated version of BTCLK[x].

Figure 20: - Transmit Clock Slave: H-MVIP

TRANSMITTER

CMV8MCLK

CMVFPC

CMVFPB

MVBTD

CCSBTD

CASBTD

Inputs Timed to CMV8MCLK

BTIF

Backplane

Tra ns mi t

Sys tem

Interface

T1-XBAS/ E1-TRAN

BasicTransmitter:

Frame Generation,

Alarm Insertion, Signaling Insertion, Trunk Conditioning

Line Coding

TJAT

Digital PLL

TJAT

FIFO

Trans mit C LK[1:4]

Trans mi t Data[1 :4]

When Transmit Clock Slave: H-MVIP mode is enabled, a 8.192 Mbit/s H-MVIP backplane transmit interface multiplexes up to 128 channels from 4 T1’s or E1’s, up to 128 Channel Associated Signaling (CAS) channels from 4 T1’s or E1’s and Common Channel Signaling (CCS) from up to 4 T1’s or E1’s. The H-MVIP interface uses common clocks, CMV8MCLK and CMVFPC, and frame pulse, CMVFPB, for synchronization.

The H-MVIP data signal, MVBTD, provides H-MVIP access to 128 data channels.

A separate H-MVIP signal, CASBTD, provides access to the Channel Associated Signaling (CAS) for 128 channels. The CAS H-MVIP signal is time division multiplexed exactly the same way as

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TRANSCEIVER / FRAMER

the data channels and should be synchronized with the H-MVIP data channels. Over a T1 or E1 multi-frame the four CAS bits per channel are repeated with each data byte. Four stuff bits are used to pad each CAS nibble (ABCD bits) out to a full byte in parallel with each data byte.

The third H-MVIP signal, CCSBTD, is used to time division multiplex the Common Channel Signaling (CCS) for all 4 T1’s and E1’s plus V5.1 and V5.2 channels in E1 mode.

Figure 21: - Transmit Clock Slave: Full T1/E1 with CCS H-MVIP

BTPCM[x], BTSIG[x]

Timed to BTCLK[x]

BTCLK[1:4]

BTFP[1:4]

BTSIG[1:4]

BTPCM[1:4]

CMV8MCLK

CMVFPC

CMVFPB

CCSBTD

CCSB TDTimed to CMV8MCLK

BTIF

Backplane

Trans mit

System

Inte rface

CCS EL ST

Elas tic

Store

T1-XBAS/E1-TRAN

BasicTransmitter:

Frame Generation,

Alarm Insertion, Signaling Insertion, Trunk Conditioning

Line Coding

TRANSMITTER

TJAT

Digital PLL

TJAT

FIFO

Trans mit C LK[1:4]

Trans mi t Data[1 :4]

Transmit Clock Slave: Full T1/E1 with CCS H-MVIP mode is the same as Transmit Clock Slave: Full T1/E1 mode except that Common Channel Signaling (CCS) is inserted into the transmit stream via an H-MVIP interface. The CCSBTD H-MVIP signal is used to time division multiplex the Common Channel Signaling (CCS) for all 4 T1’s and E1’s plus V5.1 and V5.2 channels in E1 mode. The H-MVIP interface use common clocks, CMV8MCLK and CMVFPC, and frame pulse, CMVFPB, for synchronization.

BTCLK[x] may optionally be configured as clock master. This is represented with the above figure but with BTCLK[x] being driven by the COMET-QUAD rather than being an input.

9.20 Transmit Per-Channel Serial Controller (TPSC)

The Transmit Per-Channel Serial Controller allows data and signaling trunk conditioning or idle code to be applied on the transmit DS-1 stream on a per-channel basis. It also allows per-channel control of zero code suppression, data inversion, channel loopback (from the backplane receive stream), channel insertion, and the detection or generation of pseudo-random or repetitive patterns.

The TPSC interfaces directly to the E1-TRAN and T1-XBAS block and provides serial streams for signaling control, idle code data and backplane transmit data control.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE 57

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PM4354 COMET-QUAD

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9.21 Transmit Elastic Store (TX-ELST)

The Transmit Elastic Store (TX-ELST) provides the ability to decouple the line timing from the backplane timing. The TX-ELST is required whenever the backplane and lineside clocks are not traceable to a common source.

When the elastic store is being used, if the average frequency of the backplane data is greater than the average frequency of the line clock, the buffer will fill. Under this condition a controlled slip will occur upon the next frame boundary. The following frame of PCM data will be deleted.

If the average frequency of the backplane data is less than the average frequency of the line clock, the buffer will empty. Under this condition a controlled slip will occur upon the next frame boundary. The last frame will be repeated.

A slip operation is always performed on a frame boundary. The TX-ELST is upstream of the frame overhead insertion; therefore, frame slips do not corrupt the frame alignment signal.

When the line timing is derived from CTCLK or BTCLK is an output, the elastic store is bypassed to eliminate the one frame delay.

9.22 T1 Basic Transmitter (T1-XBAS)

The T1 Basic Transmitter (T1-XBAS) block generates the 1.544 Mbit/s T1 data stream according to SF or ESF frame formats.

In concert with the Transmit Per-Channel Serial Controller (TPSC), the T1-XBAS block, provides per-channel control of idle code substitution, data inversion (either all 8 bits, sign bit magnitude or magnitude only), and zero code suppression. Three types of zero code suppression (GTE, Bell and "jammed bit 8") are supported and selected on a per-channel basis to provide minimum ones density control. An internal signaling control stream provides per-channel control of robbed bit signaling and selection of the signaling source. All channels can be forced into a trunk conditioning state (idle code substitution and signaling conditioning) by use of the Master Trunk Conditioning bit in the Configuration Register.

A data link is provided for ESF mode. The data link sources include bit oriented codes and HDLC messages. Support is provided for the transmission of framed or unframed Inband Code sequences and transmission of AIS or Yellow alarm signals for all formats.

The transmitter can be disabled for framing via the disable bit in the Transmit Functions Enable register. When transmitting ESF formatted data, the framing bit, datalink bit, or the CRC-6 bit from the backplane transmit stream can be by-passed to the output PCM stream. Finally, the transmitter can be by-passed completely to provide an unframed operating mode.

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PM4354 COMET-QUAD

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9.23 E1 Transmitter (E1-TRAN)

The E1 Transmitter (E1-TRAN) generates a 2048 kbit/s data stream according to ITU-T recommendations, providing individual enables for frame generation, CRC multiframe generation, and channel associated signaling (CAS) multiframe generation.

In concert with Transmit Per-Channel Serial Controller (TPSC), the E1-TRAN block provides pertimeslot control of idle code substitution, data inversion, digital milliwatt substitution, selection of the signaling source and CAS data. All timeslots can be forced into a trunk conditioning state (idle code substitution and signaling substitution) by use of the master trunk conditioning bit in the Configuration Register.

Common Channel Signaling (CCS) is supported in timeslot 16 through the Transmit Channel Insertion (TXCI) block. Support is provided for the transmission of AIS and TS16 AIS, and the transmission of remote alarm (RAI) and remote multiframe alarm signals.

The National Use bits (Sa-bits) can be sourced from the E1-TRAN National Bits Codeword registers as 4-bit codewords aligned to the submultiframe. Alternatively, the Sa-bits may individually carry data links sourced from the internal HDLC controller, or may be passed transparently from the BTPCM[x] input.

9.24 T1 Inband Loopback Code Generator (XIBC)

The T1 Inband Loopback Code Generator (XIBC) block generates a stream of inband loopback codes (IBC) to be inserted into a T1 data stream. The IBC stream consists of continuous repetitions of a specific code and can be either framed or unframed. When the XIBC is enabled to generate framed IBC, the framing bit overwrites the inband code pattern. The contents of the code and its length are programmable from 3 to 8 bits. The XIBC interfaces directly to the T1XBAS Basic Transmitter block.

9.25 Pulse Density Enforcer (XPDE)

The Pulse Density Enforcer function is provided by the XPDE block. Pulse density enforcement is enabled by a register bit within the XPDE.

This block monitors the digital output of the transmitter and detects when the stream is about to violate the ANSI T1.403 12.5% pulse density rule over a moving 192-bit window. If a density violation is detected, the block can be enabled to insert a logic 1 into the digital stream to ensure the resultant output no longer violates the pulse density requirement. When the XPDE is disabled from inserting logic 1s, the digital stream from the transmitter is passed through unaltered.

9.26 T1 Signaling Aligner (SIGA)

When enabled, the Signaling Aligner is positioned in the backplane transmit path before the T1XBAS. Its purpose is to ensure that, if the signaling on BTSIG[x] is changed in the middle of a superframe, the T1-XBAS completes transmitting the signalling bits (the A,B,C, and D bits in ESF

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mode, the A and B bits in SF mode) for the current superframe before switching to the new values. This permits signaling integrity to be preserved independent of the superframe alignment of the T1-XBAS or the signaling data source.

9.27 Bit Oriented Code Generator (XBOC)

The Bit Oriented Code Generator function is provided by the XBOC block. This block transmits 63 of the possible 64 bit oriented codes in the Facility Data Link (FDL) channel in ESF framing format, as defined in ANSI T1.403-1989. The 64th code (111111) is s imila r to the HDLC F lag sequence and is used in the XBOC to disable transmission of any bit oriented codes. When transmission is disabled the FDL channel is set to all ones.

Bit oriented codes are transmitted on the T1 Facility Data Link channel as a 16-bit sequence consisting of 8 ones, a zero, 6 code bits, and a trailing zero (111111110xxxxxx0) which is repeated as long as the code is not 111111. W hen driving the T1 facility data link the transmitted bit oriented codes have priority over any data transmitted except for ESF Yellow Alarm. The code to be transmitted is programmed by writing to the XBOC code registers when it is held until the last code has been transmitted at least 10 times. An interrupt or polling mechanism is used to determine when the most recent code written the XBOC register is being transmitted and a new code can be accepted.

9.28 HDLC Transmitter (TDPR)

The HDLC Transmitter (TDPR) provides a serial data link in the T1 4 kHz ESF facility data link, E1 Sa-bit data link, or in any arbitrary timeslot (T1 or E1). The TDPR is used under microprocessor control to transmit HDLC data frames. It performs all of the data serialization, CRC generation, zero-bit stuffing, as well as flag, and abort sequence insertion. Upon completion of the message, a CRC-CCITT frame check sequence (FCS) may be appended, followed by flags. If the TDPR transmit data FIFO underflows, an abort sequence is automatically transmitted.

When enabled, the TDPR continuously transmits the flag sequence (01111110) u ntil d ata i s ready to be transmitted. Data bytes to be transmitted are written into the Transmit Data Register. The TDPR performs a parallel-to-serial conversion of each data byte before transmitting it.

The default procedure provides automatic transmission of data once a complete packet is written. All complete packets of data will be transmitted. After the last data byte of a packet, the CRC word (if CRC insertion has been enabled) and a flag, or just a flag (if CRC insertion has not been enabled) is transmitted. The TDPR then returns to the transmission of flag characters until the next packet is available for transmission. While working in this mode, the user must only be careful to avoid overfilling the FIFO; underruns cannot occur unless the packet is greater than 128 bytes long. The TDPR will force transmission if the FIFO is filled up regardless of whether or not the packet has been completely written into the FIFO.

The second procedure transmits data only when the FIFO depth has reached a user configured upper threshold. The TDPR will continue to transmit data until the FIFO depth has fallen below the upper threshold and the transmission of the last packet with data above the upper threshold

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has completed. In this mode, the user must be careful to avoid overruns and underruns. An interrupt can be generated once the FIFO depth has fallen below a user configured lower threshold as an indicator for the user to write more data.

Interrupts can also be generated if the FIFO underflows while transmitting a packet, when the FIFO falls below a lower threshold, when the FIFO is full, or if the FIFO is overrun.

If there are more than five consecutive ones in the raw transmit data or in the CRC data, a zero is stuffed into the serial data output. This prevents the unintentional transmission of flag or abort sequences.

Abort characters can be continuously transmitted at any time by setting a control bit. During packet transmission, an underrun situation can occur if data is not written to the TDPR Transmit Data register before the previous byte has been depleted. In this case, an abort sequence is transmitted, and the controlling processor is notified via the UDRI interrupt.

Before enabling TDPR transmission, the XBOC must first be disabled by programming the XBOC Code register to an all-ones code.

9.29 Transmit Jitter Attenuator (TJAT)

The Transmit Jitter Attenuation function is provided by a digital phase lock loop and 80-bit deep FIFO. The TJAT receives jittery, dual-rail data in NRZ format on two separate inputs, which allows bipolar violations to pass through the block uncorrected. The incoming data streams are stored in a FIFO timed to the transmit clock (either CTCLK or the recovered clock). The respective input data emerges from the FIFO timed to the jitter attenuated clock (Transmit clock) referenced to either CTCLK, BTCLK[x], or the recovered clock.

The jitter attenuator generates the jitter-free 1.544 MHz or 2.048 MHz Transmit clock output transmit clock by adjusting Transmit clock's phase in 1/96 UI increments to minimize the phase difference between the generated Transmit clock and input data clock to TJAT (either CTCLK or the recovered clock). Jitter fluctuations in the phase of the input data clock are attenuated by the phase-locked loop within TJAT so that the frequency of Transmit clock is equal to the average frequency of the input data clock. For T1 applications, to best fit the jitter attenuation transfer function recommended by TR 62411, phase fluctuations with a jitter frequency above 5.7 Hz are attenuated by 6 dB per octave of jitter frequency. Wandering phase fluctuations with frequencies below 5.7 Hz are tracked by the generated Transmit clock. In E1 applications, the corner frequency is 7.6 Hz. To provide a smooth flow of data out of TJAT, Transmit clock is used to read data out of the FIFO.

If the FIFO read pointer (timed to Transmit clock) comes within one bit of the write pointer (timed to the input data clock, CTCLK or RSYNC), TJAT will track the jitter of the input clock. This permits the phase jitter to pass through unattenuated, inhibiting the loss of data.

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PM4354 COMET-QUAD

TRANSCEIVER / FRAMER

Jitter Characteristics

The TJAT Block provides excellent jitter tolerance and jitter attenuation while generating minimal residual jitter. It can accommodate up to 61 UIpp of input jitter at jitter frequencies above 5.7 Hz (7.6 Hz for E1). For jitter frequencies below 5.7 Hz (7.6 Hz for E1), more correctly called wander, the tolerance increases 20 dB per decade. In most applications the TJAT Block will limit jitter tolerance at lower jitter frequencies only. For high frequency jitter, above 10 kHz for example, other factors such as clock and data recovery circuitry may limit jitter tolerance and must be considered. For low frequency wander, below 10 Hz for example, other factors such as slip buffer hysteresis may limit wander tolerance and must be considered. The TJAT block meets the stringent low frequency jitter tolerance requirements of AT&T TR 62411 and thus allows compliance with this standard and the other less stringent jitter tolerance standards cited in the references.

The corner frequency in the jitter transfer response can be altered through programming.

TJAT exhibits negligible jitter gain for jitter frequencies below 5.7 Hz (7.6 Hz for E1), and attenuates jitter at frequencies above 5.7 Hz (7.6 Hz for E1) by 20 dB per decade. In most applications, the TJAT block will determine jitter attenuation for higher jitter frequencies only. Wander, below 10 Hz for example, will essentially be passed unattenuated through TJAT. Jitter, above 10 Hz for example, will be attenuated as specified, however, outgoing jitter may be dominated by the generated residual jitter in cases where incoming jitter is insignificant. This generated residual jitter is directly related to the use of a 1/96 UI phase adjustment quantum. TJAT meets the jitter attenuation requirements of AT&T TR 62411. The block allows the implied jitter attenuation requirements for a TE or NT1 given in ANSI Standard T1.408, and the implied jitter attenuation requirements for a type II customer interface given in ANSI T1.403 to be met.

Jitter Tolerance

Jitter tolerance is the maximum input phase jitter at a given jitter frequency that a device can accept without exceeding its linear operating range, or corrupting data. For TJAT, the input jitter tolerance is 61 Unit Intervals peak-to-peak (UIpp) with a worst case frequency offset of 354 Hz. It is 80 UIpp with no frequency offset. The frequency offset is the difference between the frequency of XCLK and that of the input data clock.

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Figure 22: - TJAT Jitter Tolerance

PM4354 COMET-QUAD

TRANSCEIVER / FRAMER

100

JITTER

AMPLITUDE,

UI pp

1.0

0.1

0.01

JAT MIN.TOLER ANCE

acceptable

unacceptable

100

1k 10k

0.4

100k

JITTER FREQUENCY, Hz

The accuracy of the XCLK frequency and that of the TJAT PLL reference input clock used to generate the jitter-free Transmit clock output have an effect on the minimum jitter tolerance. Given that the TJAT PLL reference clock accuracy can be ±200 Hz and that the XCLK input accuracy can be ±100 ppm, the minimum jitter tolerance for various differences between the frequency of PLL reference clock and XCLK are shown in Figure 23.

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Figure 23: - TJAT Minimum Jitter Tolerance vs. XCLK Accuracy

PM4354 COMET-QUAD

TRANSCEIVER / FRAMER

JAT MIN. JITTER TOLERANCE,

UI pp

MAX. FREQUENCY OFFSET

100

XCLK ACCURACY

Jitter Transfer

For T1 applications, the output jitter for jitter frequencies from 0 to 5.7 Hz (7.6 Hz for E1) is no more than 0.1 dB greater than the input jitter, excluding residual jitter. Jitter frequencies above

5.7 Hz (7.6 Hz for E1) are attenuated at a level of 6 dB per octave, as shown in Figure 24. The figure is valid for the case where the N1 = 2FH in the TJAT Jitter Attenuator Divider N1 Control register and N2 = 2FH in the TJAT Divider N2 Control register.

200

250

300 354

100

,± ppm

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Figure 24: - TJAT Jitter Transfer

PM4354 COMET-QUAD

TRANSCEIVER / FRAMER

-10

JITTER

GAIN

-20

-30

62411 min

62411 max

JAT response

43802 max

-40

-50

10 100 1k 10k

5.7

JITTER FREQUENCY

In the non-attenuating mode, when the FIFO is within one UI of overrunning or under running, the tracking range is 1.48 MHz to 1.608 MHz.

The guaranteed linear operating range for the jittered input clock is 1.544 MHz ± 200 Hz with worst case jitter (61 UIpp), and maximum system clock frequency offset (± 100 ppm). The nominal range is 1.544 MHz ± 963 Hz with no jitter or system clock frequency offset.

In the non-attenuating mode, when the FIFO is within one UI of overrunning or under running, the tracking range is 2.13 MHz to 1.97 MHz.

The guaranteed linear operating range for the jittered input clock is 2.048 MHz ± 300 Hz with worst case jitter (61 UIpp), and maximum system clock frequency offset (± 100 ppm). The nominal range is 2.048 MHz ± 1277 Hz with no jitter or system clock frequency offset.

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PM4354 COMET-QUAD

TRANSCEIVER / FRAMER

Jitter Generation

In the absence of input jitter, the output jitter shall be less than 0.025 UIpp. This complies with the AT&T TR 62411 requirement of less than 0.025 UIpp of jitter generation.

9.30 Line Transmitter

The line transmitter generates Alternate Mark Inversion (AMI) transmit pulses suitable for use in the DSX-1 (short haul T1), short haul E1, long haul T1 and long haul E1 environments. The voltage pulses are produced by applying a current to a known termination (termination resistor plus line impedance). The use of current (instead of a voltage driver) simplifies transmit Input Return Loss (IRL), transmit short circuit protection (none needed) and transmit tri-stating.

The output pulse shape is synthesized digitally with current digital-to-analog (DAC) converters, which produce 24 samples per symbol. The current DAC’s produce differential bipolar outputs that directly drive the TXTIP1[x], TXTIP2[x] TXRING1[x], and TXRING2[x] pins. The current output is applied to a terminating resistor and line-coupling transformer in a differential manner, which when viewed from the line side of the transformer produce the output pulses at the required levels and insures a small positive to negative pulse imbalance.

The pulse shape is user programmable. For T1 short haul, the cable length between the COMETQUAD and the cross-connect (where the pulse template specifications are given) greatly affects the resulting pulse shapes. Hence, the data applied to the converter must account for different cable lengths. For CEPT E1 applications the pulse template is specified at the transmitter, thus only one setting is required. For T1 long haul with a LBO of 7.5 dB the previous bits effect what the transmitter must drive to compensate for inter-symbol interference; for LBO’s of 15 dB or

22.5 dB the previous 3 or 4 bits effect what the transmitter must send out.

Refer to the Operation section for details on creating the synthesized pulse shape.

9.31 Timing Options (TOPS)

The Timing Options block provides a means of selecting the source of the internal input clock to the TJAT block, and the reference clock for the TJAT digital PLL.

9.32 JTAG Test Access Port

The JTAG Test Access Port block provides JTAG support for boundary scan. The standard JTAG EXTEST, SAMPLE, BYPASS, IDCODE and STCTEST instructions are supported.

9.33 Microprocessor Interface

The Microprocessor Interface Block provides normal and test mode registers, the interrupt logic, and the logic required to connect to the Microprocessor Interface. The normal mode registers are

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PM4354 COMET-QUAD

TRANSCEIVER / FRAMER

required for normal operation, and test mode registers are used to enhance the testability of the COMET-QUAD.

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PM4354 COMET-QUAD

TRANSCEIVER / FRAMER

10 NORMAL MODE REGISTER DESCRIPTION

Normal mode registers are used to configure and monitor the operation of the COMET-QUAD.

The Register Memory Map in Table 4 below shows where the normal mode registers are accessed. The registers are organized so that backward software compatibility with existing PMC devices is optimized. The COMET-QUAD contains 1 set of master configuration, H-MVIP, and CSU registers and 4 sets of T1/E1 Framer registers. Where only 1 set is present, the registers apply to the entire device. Where 4 sets are present, the registers apply to a single quadrant of the COMET-QUAD. By convention, where 4 sets of registers are present, address space 000H – 0FFH applies to quadrant #1, 100H – 1FFH applies to quadrant #2, 200H – 2FFH applies to quadrant #3, and 300H – 3FFH applies to quadrant #4.

On reset the COMET-QUAD defaults to T1 mode. For proper operation some register configuration is expected. System side access defaults to the serial clock and data signals. By default interrupts will not be enabled, and automatic alarm generation is disabled.

Notes on Normal Mode Register Bits:

1. Writing values into unused register bits has no effect. Reading back unused bits can produce either a logic 1 or a logic 0; hence, unused register bits should be masked off by software when read.

2. All configuration bits that can be written into can also be read back. This allows the processor controlling the COMET-QUAD to determine the programming state of the chip.

3. Writeable normal mode register bits are cleared to zero upon reset unless otherwise noted.

4. Writing into read-only normal mode register bit locations does not affect COMET-QUAD operation unless otherwise noted.

5. Certain register bits are reserved. These bits are associated with functions that are unused in this application. To ensure that the COMET-QUAD operates as intended, reserved register bits must only be written with their default values unless otherwise stated. Similarly, writing to reserved registers should be avoided unless otherwise stated.

10.1 Normal Mode Register Memory Map

Table 4 - Normal Mode Register Memory Map

Addr Addr Addr Addr Register

000H 100H 200H 300H Global Configuration

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TRANSCEIVER / FRAMER

Addr Addr Addr Addr Register

001H 101H 201H 301H Clock Monitor

002H 102H 202H 302H Receive Options

003H 103H 203H 303H Receive Line Interface Configuration

004H 104H 204H 304H Transmit Line Interface Configuration

005H 105H 205H 305H Transmit Framing and Bypass Options

006H 106H 206H 306H Transmit Timing Options

007H 107H 207H 307H Interrupt Source #1

008H 108H 208H 308H Interrupt Source #2

009H 109H 209H 309H Interrupt Source #3

00AH 10AH 20AH 30AH Master Diagnostics

00BH Master Test

10BH 20BH 30BH Reserved

00CH 10CH 20CH 30CH Reserved

00DH 10DH 20DH 30DH Revision/Chip ID/Quadrant PMON Update

00EH Reset

10EH 20EH 30EH Reserved

00FH 10FH 20FH 30FH PRBS Positioning/Control and HDLC Control

010H 110H 210H 310H CDRC Configuration

011H 111H 211H 311H CDRC Interrupt Enable

012H 112H 212H 312H CDRC Interrupt Status

013H 113H 213H 313H CDRC Alternate Loss of Signal

014H 114H 214H 314H RJAT Interrupt Status

015H 115H 215H 315H RJAT Reference Clock Divisor (N1) Control

016H 116H 216H 316H RJAT Output Clock Divisor (N2) Control

017H 017H 217H 317H RJAT Configuration

018H 118H 218H 318H TJAT Interrupt Status

019H 119H 219H 319H TJAT Reference Clock Divisor (N1) Control

01AH 11AH 21AH 31AH TJAT Output Clock Divisor (N2) Control

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TRANSCEIVER / FRAMER

Addr Addr Addr Addr Register

01BH 11BH 21BH 31BH TJAT Configuration

01CH 11CH 21CH 31CH RX-ELST Configuration

01DH 11DH 21DH 31DH RX-ELST Interrupt Enable/Status

01EH 11EH 21EH 31EH RX-ELST Idle Code

01FH 11FH 21FH 31FH RX-ELST Reserved

020H 120H 220H 320H TX-ELST Configuration

021H 121H 221H 321H TX-ELST Interrupt Enable/Status

022H023H

024H027H

122H123H

124H127H

222H223H

224H227H

322H323H

324H327H

TX-ELST Reserved

Reserved

028H 128H 228H 328H RXCE Receive Data Link Control

029H 129H 229H 329H RXCE Receive Data Link Bit Select

02AH02FH

12AH12FH

22AH22FH

032AH

-32FH

RXCE Reserved

030H 130H 230H 330H BRIF Receive Backplane Configuration

031H 131H 231H 331H BRIF Receive Backplane Frame Pulse Configuration

032H 132H 232H 332H BRIF Receive Backplane Parity/F-Bit Configuration

033H 133H 233H 333H BRIF Receive Backplane Timeslot Offset

034H 134H 234H 334H BRIF Receive Backplane Bit Offset

035H037H

135H137H

235H237H

335H337H

BRIF Receive Backplane Reserved

038H 138H 238H 338H TXCI Transmit Data Link Control

039H 139H 239H 339H TXCI Transmit Data Link Bit Select

03AH03FH

13AH13FH

23AH23FH

033AH

-33FH

TXCI Reserved

040H 140H 240H 340H BTIF Transmit Backplane Configuration

041H 141H 241H 341H BTIF Transmit Backplane Frame Pulse Configuration

042H 142H 242H 342H BTIF Transmit Backplane Parity Configuration and Status

043H 143H 243H 343H BTIF Transmit Backplane Timeslot Offset

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PM4354 COMET-QUAD

TRANSCEIVER / FRAMER

Addr Addr Addr Addr Register

044H 144H 244H 344H BTIF Transmit Backplane Bit Offset Register

045H047H

145H147H

245H247H

345H347H

BTIF Transmit Backplane Reserved

048H 148H 248H 348H T1-FRMR Configuration

049H 149H 249H 349H T1-FRMR Interrupt Enable

04AH 14AH 24AH 34AH T1-FRMR Interrupt Status

04BH 14BH 24BH 34BH Reserved

04CH 14CH 24CH 34CH IBCD Configuration

04DH 14DH 24DH 34DH IBCD Interrupt Enable/Status

04EH 14EH 24EH 34EH IBCD Activate Code

04FH 14FH 24FH 34FH IBCD Deactivate Code

050H 150H 250H 350H SIGX Configuration/Change of Signaling State

051H 151H 251H 351H SIGX µP Access Status/Change of Signaling State

052H 152H 252H 352H SIGX Channel Indirect Address/Control/ Change of Signaling

State

053H 153H 253H 353H SIGX Channel Indirect Data Buffer/Change of Signaling

State

054H 154H 254H 354H T1 XBAS Configuration

055H 155H 255H 355H T1 XBAS Alarm Transmit

056H 156H 256H 356H T1 XIBC Control

057H 157H 257H 357H T1 XIBC Loopback Code

058H 158H 258H 358H PMON Interrupt Enable/Status

059H 159H 259H 359H PMON Framing Bit Error Count

05AH 15AH 25AH 35AH PMON OOF/COFA/Far End Block Error Count (LSB)

05BH 15BH 25BH 35BH PMON OOF/COFA/Far End Block Error Count (MSB)

05CH 15CH 25CH 35CH PMON Bit Error/CRCE Count (LSB)

05DH 15DH 25DH 35DH PMON Bit Error/CRCE Count (MSB)

05EH 15EH 25EH 35EH PMON LCV Count (LSB)

05FH 15FH 25FH 35FH PMON LCV Count (MSB)

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TRANSCEIVER / FRAMER

Addr Addr Addr Addr Register

060H 160H 260H 360H T1 ALMI Configuration

061H 161H 261H 361H T1 ALMI Interrupt Enable

062H 162H 262H 362H T1 ALMI Interrupt Status

063H 163H 263H 363H T1 ALMI Alarm Detection Status

064H 164H 264H 364H T1 PDVD Reserved

065H 165H 265H 365H T1 PDVD Interrupt Enable/Status

066H 166H 266H 366H T1 XBOC Control

067H 167H 267H 367H T1 XBOC Code

068H 168H 268H 368H T1 XPDE Reserved

069H 169H 269H 369H T1 XPDE Interrupt Enable/Status

06AH 16AH 26AH 36AH T1 RBOC Enable

06BH 16BH 26BH 36BH T1 RBOC Code Status

06CH 16CH 26CH 36CH TPSC Configuration

06DH 16DH 26DH 36DH TPSC µP Access Status

06EH 16EH 26EH 36EH TPSC Channel Indirect Address/Control

06FH 16FH 26FH 36FH TPSC Channel Indirect Data Buffer

070H 170H 270H 370H RPSC Configuration

071H 171H 271H 371H RPSC µP Access Status

072H 172H 272H 372H RPSC Channel Indirect Address/Control

073H 173H 273H 373H RPSC Channel Indirect Data Buffer

074H077H

174H177H

274H277H

374H377H

Reserved

078H 178H 278H 378H T1 APRM Configuration/Control

079H 179H 279H 379H T1 APRM Reserved

07AH 17AH 27AH 37AH T1 APRM Interrupt Status

07BH 17BH 27BH 37BH T1 APRM One Second Content Octet 2

07CH 17CH 27CH 37CH T1 APRM One Second Content Octet 3

07DH 17DH 27DH 37DH T1 APRM One Second Content Octet 4

07EH 17EH 27EH 37EH T1 APRM One Second Content MSB (Octet 5)

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TRANSCEIVER / FRAMER

Addr Addr Addr Addr Register

07FH 17FH 27FH 37FH T1 APRM One Second Content LSB (Octet 6)

080H 180H 280H 380H E1-TRAN Configuration

081H 181H 281H 381H E1-TRAN Transmit Alarm/Diagnostic Control

082H 182H 282H 382H E1-TRAN International Control

083H 183H 283H 383H E1-TRAN Extra Bits Control

084H 184H 284H 384H E1-TRAN Interrupt Enable

085H 185H 285H 385H E1-TRAN Interrupt Status

086H 186H 286H 386H E1-TRAN National Bit Codeword Select

087H 187H 287H 387H E1-TRAN National Bit Codeword

088H08BH

08CH08DH

08EH08FH

188H18BH

18CH18DH

18EH18FH

288H28BH

28CH28DH

28EH28FH

388H38BH

38CH38DH

38EH38FH

Reserved

T1-FRMR Reserved

Reserved

090H 190H 290H 390H E1-FRMR Frame Alignment Options

091H 191H 291H 391H E1-FRMR Maintenance Mode Options

092H 192H 292H 392H E1-FRMR Framing Status Interrupt Enable

093H 193H 293H 393H E1-FRMR Maintenance/Alarm Status Interrupt Enable

094H 194H 294H 394H E1-FRMR Framing Status Interrupt Indication

095H 195H 295H 395H E1-FRMR Maintenance/Alarm Status Interrupt Indication

096H 196H 296H 396H E1-FRMR Framing Status

097H 197H 297H 397H E1-FRMR Maintenance/Alarm Status

098H 198H 298H 398H E1-FRMR International/National Bits

099H 199H 299H 399H E1-FRMR CRC Error Count - LSB

09AH 19AH 29AH 39AH E1-FRMR CRC Error Count - MSB

09BH 19BH 29BH 39BH E1-FRMR National Bit Codeword Interrupt Enables

09CH 19CH 29CH 39CH E1-FRMR National Bit Codeword Interrupts

09DH 19DH 29DH 39DH E1-FRMR National Bit Codewords

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Addr Addr Addr Addr Register

09EH 19EH 29EH 39EH E1-FRMR Frame Pulse/Alarm Interrupt Enables

09FH 19FH 29FH 39FH E1-FRMR Frame Pulse/Alarm Interrupt

0A0H0A7H

1A0H1A7H

2A0H2A7H

3A0H3A7H

Reserved

0A8H 1A8H 2A8H 3A8H TDPR Configuration

0A9H 1A9H 2A9H 3A9H TDPR Upper Transmit Threshold

0AAH 1AAH 2AAH 3AAH TDPR Lower Transmit Threshold

0ABH 1ABH 2ABH 3ABH TDPR Interrupt Enable

0ACH 1ACH 2ACH 3ACH TDPR Interrupt Status/UDR Clear

0ADH 1ADH 2ADH 3ADH TDPR Transmit Data

0AEH0AFH

0AEH1AFH

2AEH2AFH

3AEH3AFH

Reserved

0B0H 1B0H 2B0H 3B0H RX-ELST CCS Configuration

0B1H 1B1H 2B1H 3B1H RX-ELST CCS Interrupt Enable/Status

0B2H 1B2H 2B2H 3B2H RX-ELST CCS Idle Code

0B3H 1B3H 2B3H 3B3H RX-ELST CCS Reserved

0B4H 1B4H 2B4H 3B4H TX-ELST CCS Configuration

0B5H 1B5H 2B5H 3B5H TX-ELST CCS Interrupt Enable/Status

0B6H0B7H

1B6H1B7H

2B6H2B7H

3B6H3B7H

TX-ELST CCS Reserved

0B8H Receive H-MVIP/CCS Enable

1B8H 2B8H 3B8H Reserved

0B9H 1B9H 2B9H 3B9H Transmit H-MVIP/CCS Enable and Configuration

0BAH 1BAH 2BAH 3BAH Reserved

0BBH RSYNC Select

1BBH 2BBH 3BBH Reserved

0BCH COMET-QUAD Master Interrupt Source

1BCH 2BCH 3BCH Reserved

0BDH0BFH

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1BDH1BFH

2BDH2BFH

3BDH3BFH

Reserved

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PM4354 COMET-QUAD

TRANSCEIVER / FRAMER

Addr Addr Addr Addr Register

0C0H 1C0H 2C0H 3C0H RDLC Configuration

0C1H 1C1H 2C1H 3C1H RDLC Interrupt Control

0C2H 1C2H 2C2H 3C2H RDLC Status

0C3H 1C3H 2C3H 3C3H RDLC Data

0C4H 1C4H 2C4H 3C4H RDLC Primary Address Match

0C5H 1C5H 2C5H 3C5H RDLC Secondary Address Match

0C6H0D5H

1C6H1D5H

2C6H2D5H

3C6H3D5H

Reserved

0D6H CSU Configuration

1D6H 2D6H 3D6H Reserved

0D7H CSU Reserved

1D7H 2D7H 3D7H Reserved

0D8H 1D8H 2D8H 3D8H RLPS Equalization Indirect Data Register

0D9H 1D9H 2D9H 3D9H RLPS Equalization Indirect Data Register

0DAH 1DAH 2DAH 3DAH RLPS Equalization Indirect Data Register

0DBH 1DBH 2DBH 3DBH RLPS Equalization Indirect Data Register

0DCH 1DCH 2DCH 3DCH RLPS Equalizer Loop Voltage Reference

0DDH0DFH

1DDH1DFH

2DDH2DFH

3DDH3DFH

RLPS Reserved

0E0H 1E0H 2E0H 3E0H PRBS Generator/Checker Control

0E1H 1E1H 2E1H 3E1H PRBS Checker Interrupt Enable/Status

0E2H 1E2H 2E2H 3E2H PRBS Pattern Select

0E3H 1E3H 2E3H 3E3H PRBS Reserved

0E4H 1E4H 2E4H 3E4H PRBS Error Count #1

0E5H 1E5H 2E5H 3E5H PRBS Error Count #2

0E6H 1E6H 2E6H 3E6H PRBS Error Count #3

0E7H0EFH

1E7H1EFH

2E7H2EFH

3E7H3EFH

Reserved

0F0H 1F0H 2F0H 3F0H XLPG Line Driver Configuration

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TRANSCEIVER / FRAMER

Addr Addr Addr Addr Register

0F1H 1F1H 2F1H 3F1H Reserved

0F2H 1F2H 2F2H 3F2H XLPG Pulse Waveform Storage Write Address

0F3H 1F3H 2F3H 3F3H XLPG Pulse Waveform Storage Data

0F4H 1F4H 2F4H 3F4H XLPG Configuration #1

0F5H 1F5H 2F5H 3F5H XLPG Configuration #2

0F6H 1F6H 2F6H 3F6H XLPG Initialization

0F7H 1F7H 2F7H 3F7H XLPG Reserved

0F8H 1F8H 2F8H 3F8H RLPS Configuration and Status

0F9H 1F9H 2F9H 3F9H RLPS ALOS Detection/Clearance Threshold

0FAH 1FAH 2FAH 3FAH RLPS ALOS Detection Period

0FBH 1FBH 2FBH 3FBH RLPS ALOS Clearance Period

0FCH 1FCH 2FCH 3FCH RLPS Equalization Indirect Address

0FDH 1FDH 2FDH 3FDH RLPS Equalization Read/WriteB Select

0FEH 1FEH 2FEH 3FEH RLPS Equalizer Loop Status and Control

0FFH 1FFH 2FFH 3FFH RLPS Equalizer Configuration

400H-7FFH Reserved for Test

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PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1

PM4354 COMET-QUAD

TRANSCEIVER / FRAMER

Bit Type Function Default

Bit 7 R/W PIO_OE 0

Bit 6 R/W PIO 0

Bit 5 R/W IBCD_IDLE 0

Bit 4 R/W RSYNC_ALOSB 0

Bit 3 R/W OOSMFAIS 0

Bit 2 R/W TRKEN 0

Bit 1 R/W RXMTKC 0

Bit 0 R/W E1/T1B 0

PIO_OE:

The programmable I/O output enable, PIO_OE, bit controls the PIO pin. When PIO_OE is logic 1, the PIO pin is configured as an output and driven by the COMET-QUAD. When PIO_OE is logic 0, the PIO pin is configured as an input. Upon reset, the PIO pin is configured as an input. PIO_OE is only defined for Register 000H. In Registers 100H, 200H, and 300H the bit is unused, and the Default value is ‘X’.

PIO:

The programmable I/O, PIO, bit controls/reflects the state of the PIO pin. W hen the PIO pin is configured as an output, the PIO bit controls the state of the PIO pin. When the PIO pin is configured as an input, the PIO bit reflects the state of the PIO pin. Upon reset, the PIO pin is an input. PIO is only defined for Register 000H. In Registers 100H, 200H, and 300H the bit is unused, and the Default value is ‘X’.

OOSMFAIS:

In E1 mode, this bit controls the quadrant receive backplane signaling trunk conditioning in an out of signaling multiframe condition. If OOSMFAIS is set to a logic 0, an OOSMF indication from the E1-FRMR does not affect the BRSIG[x] or CASBRD output of the quadrant. When OOSMFAIS is a logic 1, an OOSMF indication from the E1-FRMR will cause the BRSIG[x] or CASBRD output of the quadrant to be set to all 1's.

RSYNC_ALOSB:

The RSYNC_ALOSB bit controls the source of the loss of signal condition used to control the behaviour of the receive reference presented on the RSYNC. If RSYNC_ALOSB is a logic 0, analog loss of signal is used. If RSYNC_ALOSB is a logic 1, digital loss of signal is used.

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PM4354 COMET-QUAD

TRANSCEIVER / FRAMER

When the COMET-QUAD quadrant is in a loss of signal state, the RSYNC output is derived from XCLK. When the COMET-QUAD quadrant is not in a loss of signal state, the RSYNC output is derived from the receive recovered clock of the selected quadrant.

The quadrant becoming the source of RSYNC is configured in the RSYNC Select register.

IBCD_IDLE:

When the IBCD_IDLE bit is set to logic 1, the data to the inband code detector (IBCD) block is gapped during the framing bit. This allows the IBCD to be used to detect an idle code that is inserted only in the payload of the receive DS1 PCM stream. The IBCD must still be programmed to detect the desired pattern, and otherwise operates unchanged. The IBCD_IDLE bit is only valid in T1 mode.

TRKEN:

The TRKEN bit enables quadrant receive trunk conditioning upon an out of frame condition. If TRKEN is logic 1, the contents of the RX-ELST Idle Code register are inserted into all data timeslots (including TS0 and TS16) of BRPCM[x] or MVBRD of the quadrant if the framer is out-of-basic frame (i.e. the OOF status bit is logic 1). The TRKEN bit only has effect if RXELSTBYP bit is logic 0. If TRKEN is a logic 0, receive trunk conditioning can still be performed on a per-timeslot basis via the RPSC Data Trunk Conditioning and Signaling Trunk Conditioning registers.

RXMTKC:

The RXMTKC bit allows quadrant trunk conditioning to be applied to the received data and signaling streams, BRPCM[x] or MVBRD, and BRSIG[x] or CASBRD, of the quadrant. When RXMTKC is set to logic 1, the data on BRPCM[x] or MVBRD for each channel of the quadrant is replaced with the data contained in the data trunk conditioning registers within RPSC; similarly, the signaling on BRSIG[x] or CASBRD for each channel of the quadrant is replaced with the signaling contained in the signaling trunk conditioning registers. When RXMTKC is set to logic 0, the data and signaling streams are modified on a per-channel basis in accordance with the control bits contained in the per-channel control registers within the RPSC.

E1/T1B:

The global E1/T1B bit selects the operating mode of all four of the COMET-QUAD quadrants. If E1/T1B is logic 1, the 2.048 Mbit/s E1 mode is selected for all four quadrants. If E1/T1B is logic 0, the 1.544 Mbit/s T1 mode is selected for all four quadrants.

E1/T1B is only defined for Register 000H. In Registers 100H, 200H, and 300H the bit is unused, and the Default value is ‘X’.

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PM4354 COMET-QUAD

TRANSCEIVER / FRAMER

Bit Type Function Default

Bit 7 Unused X

Bit 6 Unused X

Bit 5 Unused X

Bit 4 R XCLKA X

Bit 3 R BTCLKA X

Bit 2 R CTCLKA X

Bit 1 R BRCLKA X

Bit 0 Unused X

When a monitored clock signal makes a low to high transition, the corresponding register bit is set high. The bit will remain high until this register is read, at which point all the bits in this register are cleared. A lack of transitions is indicated by the corresponding register bit reading low. This register should be read at periodic intervals to detect clock failures.

XCLKA:

The XCLK active (XCLKA) bit detects for low to high transitions on the XCLK input. XCLKA is set high on a rising edge of XCLK, and is set low when this register is read.

Note: XCLKA is only defined for register 301H, although it applies to the XCLK source used by four quadrants. In Registers 001H, 101H, and 201H, the bit is unused and the Default value is ‘X’.

BTCLKA:

The BTCLK active (BTCLKA) bit detects low to high transitions on the BTCLK input. BTCLKA is set high on a rising edge of BTCLK, and is set low when this register is read.

CTCLKA:

The CTCLK active (CTCLKA) bit detects low to high transitions on the CTCLK input. CTCLKA is set high on a rising edge of CTCLK, and is set low when this register is read.

BRCLKA:

The BRCLK active (BRCLKA) bit detects low to high transitions on the BRCLK input. BRCLKA is set high on a rising edge of BRCLK, and is set low when this register is read.

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PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1

PM4354 COMET-QUAD

TRANSCEIVER / FRAMER

Bit Type Function Default

Bit 7 R/W RJATBYP 1

Bit 6 R/W UNF 0

Bit 5 R/W RXELSTBYP 0

Bit 4 R/W RSYNC_MEM 0

Bit 3 R/W RSYNCSEL 0

Bit 2 R/W WORDERR 0

Bit 1 R/W CNTNFAS 0

Bit 0 R/W CCOFA 0

This register allows software to configure the receive functions of each framer.

RJATBYP:

The RJATBYP bit disables jitter attenuation in the receive direction. When receive jitter attenuation is not being used, setting RJATBYP to logic 1 will reduce the latency through the receiver section by typically 40 bits. When RJATBYP is set to logic 0, the quadrant’s BRCLK[x] output (if BRCLK[x] is configured to be an output by setting the CMODE bit of the BRIF Configuration register to logic 0), is jitter attenuated. When the RJAT is bypassed, the quadrant’s BRCLK[x] is not jitter attenuated. The RSYNC output is jitter attenuated by the RJAT, regardless of the state of RJATBYP.

Note: In T1 mode, when the framer is enabled (i.e., the UNF bit in the Receive Options register is logic 0), this bit must be programmed to logic 0.

UNF:

The UNF bit allows the framer to operate with unframed DS-1 or E1 data. When UNF is set to logic 1, the framer is disabled (both the T1-FRMR and E1-FRMR are held reset) and the recovered data passes through the receiver section of the framer without frame or channel alignment. While UNF is set to logic 1, the Alarm Integrator continues to operate and detects and integrates AIS alarm. When UNF is set to logic 0, the framer operates normally, searching for frame alignment on the incoming data.

When UNF is a logic 1, the BRFP[x] pin (if configured as an output) is held low.

RXELSTBYP:

The RXELSTBYP bit allows the Receive Elastic Store (RX-ELST) to be bypassed, eliminating the one frame delay incurred through the RX-ELST. When set to logic 1, the received data

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PM4354 COMET-QUAD

TRANSCEIVER / FRAMER

and clock inputs to RX-ELST are internally routed directly to the RX-ELST output. If RXELSTBYP is logic 1, the CMODE bit of the BRIF Configuration register must be logic 0 and the FPMODE bit of the BRIF Frame Pulse Configuration register must be logic 0.

In Receive Clock Slave: H-MVIP mode, RXELSTBYP must be programmed to logic 0.

RSYNC_MEM:

The RSYNC_MEM bit controls the quadrant’s RSYNC output under a loss of signal condition (as determined by the RSYNC_ALOSB register bit). When RSYNC_MEM is a logic 1, the quadrant’s RSYNC output is held high during a loss of signal condition. When RSYNC_MEM is a logic 0, the quadrant’s RSYNC output is derived from XCLK during a loss of signal condition.

RSYNCSEL:

The RSYNCSEL bit selects the frequency of the receive reference presented on the quadrant’s RSYNC output. If RSYNCSEL is a logic 1, the quadrant’s RSYNC will be an 8 kHz clock. If RSYNCSEL is a logic 0, the quadrant’s RSYNC will be an 1.544 MHz (T1) or

2.048 MHz (E1) clock.

WORDERR:

In E1 mode, the WORDERR bit determines how frame alignment signal (FAS) errors are reported. When WORDERR is logic 1, one or more errors in the seven bit FAS word results in a single framing error count. When WORDERR is logic 0, each error in a FAS word results in a single framing error count.

CNTNFAS:

In E1 mode, when the CNTNFAS bit is a logic 1, a zero in bit 2 of timeslot 0 of non-frame alignment signal (NFAS) frames results in an increment of the framing error count. If WORDERR is also a logic 1, the word is defined as the eight bits consisting of the seven-bit FAS pattern and bit 2 of timeslot 0 of the next NFAS frame. When the CNTNFAS bit is a logic 0, only errors in the FAS affect the framing error count.

CCOFA

The CCOFA bit determines whether the PMON counts Change-Of-Frame Alignment (COFA) events or out of frame (OOF) events. When CCOFA is set to logic 1, COFA events are counted by PMON. When CCOFA is set to logic 0, OOF events are counted by PMON. The CCOFA bit is only valid in T1 mode.

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PM4354 COMET-QUAD

TRANSCEIVER / FRAMER

Bit Type Function Default

Bit 7 R/W AUTOYELLOW 0

Bit 6 R/W AUTORED 0

Bit 5 R/W AUTOOOF 0

Bit 4 R/W AUTOAIS 0

Bit 3 R/W Reserved 0

Bit 2 R/W BPV 0

Bit 1 R/W Reserved 0

Bit 0 R/W Reserved 0

Reserved:

These bits must be a logic 0 for normal operation.

AUTOYELLOW:

In T1 mode, when the AUTOYELLOW bit is set to logic 1, whenever the alarm integrator declares a Red alarm in the receive direction, Yellow alarm will be transmitted to the far end. When AUTOYELLOW is set to logic 0, Yellow alarm will only be transmitted when the XYEL bit is set in the T1-XBAS Alarm Transmit Register. Note that the Red alarm is not deasserted on detection of AIS.

In E1 mode, when the AUTOYELLOW bit is set to logic 1, the RAI bit in the transmit stream is set to a logic 1 for the duration of a loss of frame alignment or AIS. The G706ANNBRAI bit of the Transmit Framing and Bypass Options register optionally also allows for the transmission of RAI when CRC-to-non-CRC interworking has been established. When AUTOYELLOW is set to logic 0, RAI will only be transmitted when the RAI bit is set in the E1-TRAN Transmit Alarm/Diagnostic Control register.

AUTORED:

The AUTORED bit allows quadrant trunk conditioning to be applied to the receive data and signaling streams, BRPCM[x] or MVBRD, and BRSIG[x] or CASBRD, immediately upon declaration of Red carrier failure alarm. When AUTORED is set to logic 1, the data on BRPCM[x] or MVBRD for each channel of the quadrant is replaced with the data contained in the Data Trunk Conditioning registers within RPSC and the signaling on BRSIG[x] or CASBRD for each channel of the quadrant is replaced with the signaling contained in the Signaling Trunk Conditioning registers within the RPSC while Red CFA is declared. When AUTORED is set to logic 0, the receive data and signaling is not automatically conditioned when Red CFA is declared.

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PM4354 COMET-QUAD

TRANSCEIVER / FRAMER

AUTOOOF:

The AUTOOOF bit allows quadrant trunk conditioning to be applied to the receive data stream, BRPCM[x] or MVBRD of the quadrant, immediately upon declaration of out of frame (OOF). When AUTOOOF is set to logic 1, while OOF is declared, the data on BRPCM[x] or MVBRD for each channel of the quadrant is replaced with the data contained in the data trunk conditioning registers within RPSC. When AUTOOOF is set to logic 0, the receive data stream, BRPCM[x] or MVBRD of the quadrant, is not automatically conditioned by RPSC when OOF is declared. However, if the RX-ELST is not bypassed, the RX-ELST trouble code will still be inserted in channel data while OOF is declared if the TRKEN register bit is logic 1. RPSC data and signaling trunk conditioning overwrites the RX-ELST trouble code.

AUTOAIS:

If the AUTOAIS bit is logic 1, AIS is inserted in the receive path and the channel associated signaling is frozen for the duration of a loss of signal condition. (The loss of signal criteria is configured via the LOS[1:0] bits of the CDRC Configuration register.) If AUTOAIS is logic 0, AIS may be inserted manually via the RAIS register bit.

BPV:

In T1 mode, the BPV bit enables only bipolar violations to indicate line code violations and be accumulated in the PMON LCV Count Registers. When BPV is set to logic 1, BPVs (which are not part of a valid B8ZS signature if B8ZS line coding is used) generate an LCV indication and increment the PMON LCV counter. When BPV is set to logic 0, both BPVs (which are not part of a valid B8ZS signature if B8ZS line coding is used) and excessive zeros (EXZ) generate an LCV indication and increment the PMON LCV counter. Excessive zeros is a sequence of zeros greater than fifteen bits long for an AMI-coded signal and greater than seven bits long for a B8ZS-coded signal.

In E1 mode, the BPV bit enables only bipolar violations to indicate line code violations and be accumulated in the PMON LCV Count registers. (The O162 bit in the CDRC Configuration register provides two E1 LCV definitions.) When BPV is set to logic 1, BPVs (which are not part of a valid HDB3 signature if HDB3 line coding is used) generate an LCV indication and increment the PMON LCV counter. When BPV is set to logic 0, both BPVs (which are not part of a valid HDB3 signature if HDB3 line coding is used) and excessive zeros (EXZ) generate an LCV indication and increment the PMON LCV counter. Excessive zeros is a sequence of zeros greater than four bits long.

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PM4354 COMET-QUAD

TRANSCEIVER / FRAMER

Bit Type Function Default

Bit 7 R/W TJATBYP 0

Bit 6 R/W TAISEN 0

Bit 5 R/W TAUXP 0

Bit 4 R/W Reserved 0

Bit 3 R/W Reserved 0

Bit 2 Unused X

Bit 1 R/W Reserved 0

Bit 0 Unused X

Reserved:

These bits must be a logic 0 for normal operation.

TJATBYP:

The TJATBYP bit enables the transmit jitter attenuator's FIFO to be removed from the transmit data path. When transmit jitter attenuation is not being used, setting TJATBYP to logic 1 will reduce the latency through the transmitter section by typically 40 bits. Since the transmit jitter attenuator’s PLL is never bypassed, the PLLREF[1:0] bits of the Transmit Timing Options register must be configured to reference the transmit line clock regardless of the value of the TJATBYP bit.

TAISEN:

The TAISEN bit enables the interface to generate an unframed all-ones AIS alarm on the TXTIP[x] and TXRING[x]. When TAISEN is set to logic 1 the bipolar TXTIP[x] and TXRING[x] outputs are forced to pulse alternately, creating an all-ones signal. The transition to transmitting AIS on the TXTIP[x] and TXRING[x] outputs is done in such a way as to not introduce any bipolar violations.

The diagnostic loopback point is upstream of this AIS insertion point.

TAUXP:

The TAUXP bit enables the interface to generate an unframed alternating zeros and ones (i.e.

010101...) auxiliary pattern (AUXP) on the TXTIP[x] and TXRING[x]. When TAUXP is set to logic 1 the bipolar TXTIP[x] and TXRING[x] outputs are forced to pulse alternately every other cycle. The transition to transmitting AUXP on the TXTIP[x] and TXRING[x] outputs is done in such a way as to not introduce any bipolar violations. The diagnostic loopback point is upstream of this AUXP insertion point.

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PM4354 COMET-QUAD

TRANSCEIVER / FRAMER

Bit Type Function Default

Bit 7 R/W PATHCRC 0

Bit 6 R/W G706ANNBRAI 0

Bit 5 R/W SIGAEN 0

Bit 4 R/W OOCMFE0 0

Bit 3 R/W FDIS 0

Bit 2 R/W FBITBYP 0

Bit 1 R/W CRCBYP 0

Bit 0 R/W FDLBYP 0

This register allows software to configure the bypass and framing options of the transmitter, the use of the Signaling Alignment block, and controls the quadrant transmit framing disable.

PATHCRC:

This bit only has effect in E1 mode.

When in E1 mode, the PATHCRC bit allows upstream block errors to be preserved in the transmit CRC bits. If PATHCRC is a logic 1, the CRC-4 bits are modified to reflect any bit values in BTPCM[x], MVBTD or CCSBTD of the quadrant which have changed prior to transmission. When PATHCRC is set to logic 0, a new CRC-4 value overwrites the incoming CRC-4 word. For the PATHCRC bit to be effective, the FPTYP bit of the Transmit Backplane Frame Pulse Configuration register must be a logic 1; otherwise, the identification of the incoming CRC-4 bits would be impossible. The PATHCRC bit only takes effect if the GENCRC bit of the E1-TRAN Configuration register is a logic 1 and either the INDIS or FDIS bit in the same register are set to logic 1.

G706ANNBRAI:

When in E1 mode, the G.706 Annex B RAI bit, G706ANNBRAI, selects between two modes of operation concerning the transmission of RAI when the quadrant is out of CRC-4 multiframe. When G706ANNBRAI is logic 1, the behaviour of RAI follows Annex B of G.706, i.e., RAI is transmitted only when out of basic frame, not when CRC-4-to-non-CRC-4 interworking is declared, nor when the offline framer is out of frame. When G706ANNBRAI is logic 0, the behaviour of RAI follows ETSI standards, i.e., RAI is transmitted when out of basic frame, when CRC-4-to-non-CRC-4 interworking is declared, and when the offline framer is out of frame.

This bit only has effect in E1 mode.

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Datasheet PM4354-PI Datasheet (PMC)

Specifications and Main Features

Frequently Asked Questions

User Manual

CONTENTS

LIST OF FIGURES

LIST OF TABLES

9.3 Clock and Data Recovery (CDRC)

9.4 Receive Jitter Attenuator (RJAT)

9.5 T1 Inband Loopback Code Detector (IBCD)

9.6 T1 Pulse Density Violation Detector (PDVD)

9.7 T1 Framer (T1-FRMR)

9.8 E1 Framer (E1-FRMR)

9.9 Receive Elastic Store (RX-ELST)

10 NORMAL MODE REGISTER DESCRIPTION