Datasheet PM4351-NI, PM4351-RI, PM7366 Datasheet (PMC)

STANDARD PRODUCT

DATA SHEET PMC-1970624 ISSUE 10 COMBINED E1/T1 TRANSCEIVER

PM4351 COMET

PM4351

COMET

COMBINED E1/T1

TRANSCEIVER/FRAMER

DATA SHEET

ISSUE10: NOVEMBER 2000

PMC-Sierra, Inc. 105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 .415.6000

STANDARD PRODUCT

DATA SHEET PMC-1970624 ISSUE 10 COMBINED E1/T1 TRANSCEIVER

PM4351 COMET

PMC-Sierra, Inc. 105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 .415.6000

STANDARD PRODUCT

DATA SHEET PMC-1970624 ISSUE 10 COMBINED E1/T1 TRANSCEIVER

PM4351 COMET

LIST OF REGISTERS

Register 000H: Global Configuration................................................................ 76

Register 001H: Clock Monitor........................................................................... 78

Register 002H: Receive Options....................................................................... 80

Register 003H: Receive Line Interface Configuration....................................... 82

Register 004H: Transmit Line Interface Configuration...................................... 85

Register 005H: Transmit Framing and Bypass Options.................................... 87

Register 006H: Transmit Timing Options.......................................................... 90

Register 007H: Interrupt Source #1.................................................................. 95

Register 008H: Interrupt Source #2.................................................................. 96

Register 009H: Interrupt Source #3.................................................................. 97

Register 00AH: Master Diagnostics.................................................................. 98

Register 00BH: Master Test............................................................................ 100

Register 00CH: Analog Diagnostics................................................................ 102

Register 00DH: Revision/Chip ID/Global PMON Update................................ 103

Register 00EH: Reset..................................................................................... 104

Register 00FH: PRGD Positioning/Control and HDLC Control....................... 105

Register 010H: CDRC Configuration.............................................................. 108

Register 011H: CDRC Interrupt Control...........................................................110

Register 012H: CDRC Interrupt Status............................................................111

Register 013H: Alternate Loss of Signal Status...............................................113

Register 014H: RJAT Interrupt Status..............................................................114

Register 015H: RJAT Divider N1 Control.........................................................115

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DATA SHEET PMC-1970624 ISSUE 10 COMBINED E1/T1 TRANSCEIVER

PM4351 COMET

Register 016H: RJAT Divider N2 Control.........................................................116

Register 017H: RJAT Configuration.................................................................117

Register 018H: TJAT Interrupt Status..............................................................119

Register 019H: TJAT Jitter Attenuator Divider N1 Control.............................. 120

Register 01AH: TJAT Divider N2 Control........................................................ 121

Register 01BH: TJAT Configuration................................................................ 123

Register 01CH: RX-ELST Configuration ......................................................... 125

Register 01DH: RX-ELST Interrupt Enable/Status.......................................... 126

Register 01EH: RX-ELST Idle Code............................................................... 127

Register 020H: TX-ELST Configuration.......................................................... 128

Register 021H: TX-ELST Interrupt Enable/Status........................................... 129

Register 028H: RXCE Receive Data Link 1 Control....................................... 130

Register 029H: RXCE Receive Data Link 1 Bit Select.................................... 132

Register 02AH: RXCE Receive Data Link 2 Control....................................... 133

Register 02BH: RXCE Receive Data Link 2 Bit Select................................... 134

Register 02CH: RXCE Receive Data Link 3 Control....................................... 135

Register 02DH: RXCE Receive Data Link 3 Bit Select................................... 136

Register 030H: BRIF Configuration................................................................ 137

Register 031H: BRIF Frame Pulse Configuration........................................... 140

Register 032H: BRIF Parity/F-bit Configuration.............................................. 144

Register 033H: BRIF Time Slot Offset............................................................ 146

Register 034H: BRIF Bit Offset....................................................................... 147

Register 038H: TXCI Transmit Data Link 1 Control ........................................ 149

Register 039H: TXCI Transmit Data Link 1 Bit Select..................................... 151

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DATA SHEET PMC-1970624 ISSUE 10 COMBINED E1/T1 TRANSCEIVER

PM4351 COMET

Register 03AH: TXCI Transmit Data Link 2 Control........................................ 152

Register 03BH: TXCI Transmit Data Link 2 Bit Select.................................... 153

Register 03CH: TXCI Transmit Data Link 3 Control........................................ 154

Register 03DH: TXCI Transmit Data Link 3 Bit Select.................................... 155

Register 040H: BTIF Configuration................................................................. 156

Register 041H: BTIF Frame Pulse Configuration........................................... 159

Register 042H: BTIF Parity Configuration and Status..................................... 161

Register 043H: BTIF Time Slot Offset ............................................................ 163

Register 044H: BTIF Bit Offset....................................................................... 164

Register 048H: T1 FRMR Configuration......................................................... 166

Register 049H: T1 FRMR Interrupt Enable..................................................... 168

Register 04AH: T1 FRMR Interrupt Status...................................................... 170

Register 04CH: IBCD Configuration ............................................................... 172

Register 04DH: IBCD Interrupt Enable/Status................................................ 173

Register 04EH: IBCD Activate Code............................................................... 175

Register 04FH: IBCD Deactivate Code........................................................... 176

Register 050H: SIGX Configuration Register (COSS = 0)............................. 177

Register 050H: SIGX Change of Signaling State Register (COSS = 1).......... 179

Register 051H: SIGX Timeslot Indirect Status (COSS = 0)............................ 180

Register 051H: SIGX Change Of Signaling State Change (COSS=1)............ 181

Register 052H: SIGX Timeslot Indirect Address/Control (COSS = 0)............. 182

Register 052H: SIGX Change of Signaling State Register (COSS = 1).......... 183

Register 053H: SIGX Timeslot Indirect Data Buffer (COSS = 0) .................... 184

Register 053H: SIGX Change of Signaling State (COSS = 1)........................ 185

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STANDARD PRODUCT

DATA SHEET PMC-1970624 ISSUE 10 COMBINED E1/T1 TRANSCEIVER

PM4351 COMET

Register 054H: T1 XBAS Configuration.......................................................... 191

Register 055H: T1 XBAS Alarm Transmit....................................................... 193

Register 056H: T1 XIBC Control..................................................................... 194

Register 057H: T1 XIBC Loopback Code....................................................... 196

Register 058H: PMON Interrupt Enable/Status............................................... 197

Register 059H: PMON Framing Bit Error Count............................................. 199

Register 05AH: PMON OOF/COFA/Far End Block Error Count LSB ............. 200

Register 05BH: PMON OOF/COFA/Far End Block Error Count MSB ............ 201

Register 05CH: PMON Bit Error/CRC Error Count LSB ................................. 202

Register 05DH: PMON Bit Error/CRC Error Count MSB ................................ 203

Register 05EH: PMON LCV Count (LSB)....................................................... 204

Register 05FH: PMON LCV Count (MSB) ...................................................... 205

Register 060H: T1 ALMI Configuration ........................................................... 206

Register 061H: T1 ALMI Interrupt Enable....................................................... 208

Register 062H: T1 ALMI Interrupt Status........................................................ 209

Register 063H: T1 ALMI Alarm Detection Status............................................ 210

Register 065H: T1 PDVD Interrupt Enable/Status.......................................... 212

Register 067H: T1 XBOC Code...................................................................... 214

Register 069H: T1 XPDE Interrupt Enable/Status .......................................... 215

Register 06AH: T1 RBOC Enable................................................................... 217

Register 06BH: T1 RBOC Code Status .......................................................... 218

Register 06CH: TPSC Configuration .............................................................. 219

Register 06DH: TPSC µP Access Status........................................................ 220

Register 06EH: TPSC Channel Indirect Address/Control ............................... 221

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DATA SHEET PMC-1970624 ISSUE 10 COMBINED E1/T1 TRANSCEIVER

PM4351 COMET

Register 06FH: TPSC Channel Indirect Data Buffer....................................... 222

Register 070H: RPSC Configuration............................................................... 231

Register 071H: RPSC µP Access Status........................................................ 232

Register 072H: RPSC Channel Indirect Address/Control ............................... 233

Register 073H: RPSC Channel Indirect Data Buffer....................................... 234

Register 078H: T1 APRM Configuration/Control............................................. 239

Register 079H: T1 APRM Manual Load.......................................................... 241

Register 07AH: T1 APRM Interrupt Status...................................................... 242

Register 07BH: T1 APRM One Second Content Octet 2................................ 243

Register 07CH: T1 APRM One Second Content Octet 3................................ 244

Register 07DH: T1 APRM One Second Content Octet 4................................ 245

Register 07EH: T1 APRM One Second Content MSB (Octet 5)..................... 246

Register 07FH: T1 APRM One Second Content LSB (Octet 6)..................... 248

Register 080H: E1 TRAN Configuration ......................................................... 250

Register 081H: E1 TRAN Transmit Alarm/Diagnostic Control......................... 253

Register 082H: E1 TRAN International/National Control................................ 255

Register 083H: E1 TRAN Extra Bits Control................................................... 256

Register 084H: E1 TRAN Interrupt Enable..................................................... 257

Register 085H: E1 TRAN Interrupt Status...................................................... 259

Register 086H: E1 TRAN National Bits Codeword Select.............................. 261

Register 087H: E1 TRAN National Bits Codeword......................................... 263

Register 090H: E1 FRMR Frame Alignment Options...................................... 265

Register 091H: E1 FRMR Maintenance Mode Options .................................. 267

Register 092H: E1 FRMR Framing Status Interrupt Enable............................ 269

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PM4351 COMET

Register 093H: E1 FRMR Maintenance/Alarm Status Interrupt Enable.......... 270

Register 094H: E1 FRMR Framing Status Interrupt Indication ....................... 271

Register 095H: E1 FRMR Maintenance/Alarm Status Interrupt Indication...... 272

Register 096H: E1 FRMR Framing Status...................................................... 273

Register 097H: E1 FRMR Maintenance/Alarm Status.................................... 275

Register 098H: E1 FRMR Timeslot 0 International/National Bits.................... 277

Register 099H: E1 FRMR CRC Error Counter - LSB...................................... 279

Register 09AH: E1 FRMR CRC Error Counter – MSB/Timeslot 16 Extra Bits 280

Register 09BH: E1 FRMR National Bit Codeword Interrupt Enables.............. 283

Register 09CH: E1 FRMR National Bit Codeword Interrupts.......................... 285

Register 09DH: E1 FRMR National Bit Codeword.......................................... 286

Register 09EH: E1 FRMR Frame Pulse/Alarm/V5.2 Link ID Interrupt Enables287

Register 09FH: E1 FRMR Frame Pulse/Alarm Interrupts............................... 289

Register 0A8H (#1), 0B0H (#2), 0B8H (#3): TDPR Configuration .................. 291

Register 0A9H (#1), 0B1H (#2), 0B9H (#3): TDPR Upper Transmit Threshold293 Register 0AAH (#1), 0B2H (#2), 0BAH (#3): TDPR Lower Interrupt Threshold294

Register 0ABH (#1), 0B3H (#2), 0BBH (#3): TDPR Interrupt Enable............. 295

Register 0ACH (#1), 0B4H (#2), 0BCH (#3): TDPR Interrupt Status.............. 296

Register 0ADH (#1), 0B5H (#2), 0BDH (#3): TDPR Transmit Data ................ 298

Registers 0C0H (#1), 0C8H (#2), 0D0H (#3): RDLC Configuration................ 299

Registers 0C1H (#1), 0C9H (#2), 0D1H (#3): RDLC Interrupt Control ........... 301

Registers 0C2H (#1), 0CAH (#2), 0D2H (#3): RDLC Status........................... 302

Registers 0C3H (#1), 0CBH (#2), 0D3H (#3): RDLC Data ............................. 305

Registers 0C4H (#1), 0CCH (#2), 0D4H (#3): RDLC Primary Address Match 306

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STANDARD PRODUCT

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PM4351 COMET

Registers 0C5H (#1), 0CDH (#2), 0D5H (#3): RDLC Secondary Address Match

............................................................................................................. 307

Register 0D6H: CSU Configuration ................................................................ 308

Register 0D8H: RLPS Equalization Indirect Data........................................... 310

Register 0D9H: RLPS Equalization Indirect Data............................................311

Register 0DAH: RLPS Equalization Indirect Data........................................... 312

Register 0DBH: RLPS Equalization Indirect Data........................................... 313

Register 0DCH: RLPS Equalizer Voltage Reference...................................... 314

Register 0E0H: PRGD Control........................................................................ 315

Register 0E1H: PRGD Interrupt Enable/Status............................................... 317

Register 0E2H: PRGD Shift Register Length.................................................. 319

Register 0E3H: PRGD Tap ............................................................................. 320

Register 0E4H: PRGD Error Insertion ............................................................ 321

Register 0E8H: PRGD Pattern Insertion #1.................................................... 322

Register 0E9H: PRGD Pattern Insertion #2.................................................... 323

Register 0EAH: PRGD Pattern Insertion #3 ................................................... 324

Register 0EBH: PRGD Pattern Insertion #4 ................................................... 325

Register 0ECH: PRGD Pattern Detector #1 ................................................... 326

Register 0EDH: PRGD Pattern Detector #2 ................................................... 327

Register 0EEH: PRGD Pattern Detector #3.................................................... 328

Register 0EFH: PRGD Pattern Detector #4.................................................... 329

Register 0F0H: XLPG Line Driver Configuration.............................................330

Register 0F1H: XLPG Control/Status.............................................................. 332

Register 0F2H: XLPG Pulse Waveform Storage Write Address..................... 333

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PM4351 COMET

Register 0F3H: XLPG Pulse Waveform Storage Data.................................... 334

Register 0F4H: XLPG Analog Test Negative Control...................................... 335

Register 0F5H: XLPG Analog Test Positive Control........................................ 336

Register 0F6H: XLPG Fuse Data Select......................................................... 337

Register 0F8H: RLPS Configuration and Status............................................. 338

Register 0F9H: RLPS ALOS Detection/Clearance Threshold......................... 340

Register 0FAH: RLPS ALOS Detection Period............................................... 342

Register 0FBH: RLPS ALOS Clearance Period.............................................. 343

Register 0FCH: RLPS Equalization Indirect Address...................................... 344

Register 0FDH: RLPS Equalization Read/WriteB Select................................ 345

Register 0FEH: RLPS Equalizer Loop Status and Control.............................. 346

Register 0FFH: RLPS Equalizer Configuration............................................... 347

Register 00BH: COMET Master Test .............................................................. 350

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PM4351 COMET

LIST OF FIGURES

Figure 1 - Wireless Base Station Application ................................................11

Figure 2 - V5.1 Interface Application............................................................ 12

Figure 3 PM4351-RI COMET Pin Diagram.................................................. 17

Figure 4 PM4351-NI COMET Pin Diagram.................................................. 18

Figure 5 - External Analog Interface Circuits................................................ 33

Figure 6 - T1 Jitter Tolerance ....................................................................... 37

Figure 7 - Compliance with ITU-T Specification G.823 for E1 Input Jitter .... 38

Figure 8 - CRC Multiframe Alignment Algorithm........................................... 43

Figure 9 - TJAT Jitter Tolerance ................................................................... 59

Figure 10 - TJAT Minimum Jitter Tolerance vs. XCLK Accuracy .................... 60

Figure 11 - TJAT Jitter Transfer...................................................................... 61

Figure 12 - Transmit Timing Options.............................................................. 94

Figure 13 - Transmit Backplane: CMS=0, FE=1, DE=1, BTFP is Input........... 356

Figure 14 - Transmit Backplane: CMS=0, FE=1, DE=0, BTFP is Input........... 356

Figure 15 - Transmit Backplane: CMS=1, FE=1, DE=1, BTFP is Input........... 356

Figure 16 - Transmit Backplane: CMS=1, FE=0, DE=1, BTFP is Input.......... 356

Figure 17 - Transmit Backplane: CMS=0, FE=1, DE=1, BTFP is Output........ 357

Figure 18 - Transmit Backplane: CMS=0, FE=1, DE=0, BTFP is Output........ 357

Figure 19 - Transmit Backplane at 1.544 Mbit/s (T1 mode)......................... 357

Figure 20 - Transmit Backplane at 2.048 Mbit/s (T1 mode)......................... 358

Figure 21 - Transmit Backplane at 2.048 Mbit/s (E1 mode)......................... 359

Figure 22 - Transmit Backplane at 4.096 Mbit/s (T1 mode)......................... 359

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PM4351 COMET

Figure 23 - Transmit Backplane at 4.096 Mbit/s (E1 mode)......................... 360

Figure 24 - Transmit Backplane at 8.192 Mbit/s (T1 mode)......................... 360

Figure 25 - Transmit Backplane at 8.192 Mbit/s (E1 mode)......................... 361

Figure 26 - Concentration Highway Interface Timing, Example 1 ................ 361

Figure 27 - Concentration Highway Interface Timing, Example 2 ................ 361

Figure 28 - Receive Backplane at 1.544 Mbit/s (T1 Mode).......................... 362

Figure 29 - Receive Backplane at 2.048 Mbit/s (T1 Mode).......................... 363

Figure 30 - Receive Backplane at 2.048 Mbit/s (E1 Mode).......................... 363

Figure 31 - Receive Backplane at 4.096 Mbit/s (T1 Mode)......................... 364

Figure 32 - Receive Backplane at 4.096 Mbit/s (E1 Mode)......................... 364

Figure 33 - Receive Backplane at 8.192 Mbit/s (T1 Mode)......................... 365

Figure 34 - Receive Backplane at 8.192 Mbit/s (E1 Mode)......................... 365

Figure 35 - Concentration Highway Interface Timing, Example 1 ............... 366

Figure 36 - Concentration Highway Interface Timing, Example 2 ............... 366

Figure 37 - Typical Data Frame.................................................................... 377

Figure 38 - Pattern Generator Structure....................................................... 414

Figure 39 - Line Loopback........................................................................... 418

Figure 40 - Payload Loopback..................................................................... 419

Figure 41 - Diagnostic Digital Loopback....................................................... 420

Figure 42 - LCV Count vs. BER (E1 mode).................................................. 424

Figure 43 - FER Count vs. BER (E1 mode) ................................................. 424

Figure 44 - CRCE Count vs. BER (E1 mode).............................................. 425

Figure 45 - LCV Count vs. BER (T1 mode).................................................. 426

Figure 46 - FER Count vs. BER (T1 ESF mode).......................................... 426

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PM4351 COMET

Figure 47 - CRCE Count vs. BER (T1 ESF mode)....................................... 427

Figure 48 - CRCE Count vs. BER (T1 SF mode)......................................... 427

Figure 49 - Boundary Scan Architecture ...................................................... 428

Figure 50 - TAP Controller Finite State Machine.......................................... 430

Figure 51 - Input Observation Cell (IN_CELL) ............................................. 435

Figure 52 - Output Cell (OUT_CELL)........................................................... 436

Figure 53 - Bidirectional Cell (IO_CELL)...................................................... 436

Figure 54 - Layout of Output Enable and Bidirectional Cells........................ 437

Figure 55 - Microprocessor Read Access Timing......................................... 443

Figure 56 - Microprocessor Write Access Timing......................................... 445

Figure 57 - Backplane Transmit Input Timing Diagram................................ 447

Figure 58 - Backplane Transmit Output Timing Diagram ............................. 448

Figure 59 - Backplane Receive Input Timing Diagram................................. 450

Figure 60 - Backplane Receive Output Timing Diagram.............................. 451

Figure 61 - Digital Receive Interface Timing Diagram.................................. 453

Figure 62 - Digital Transmit Interface Timing Diagram................................. 454

Figure 63 - JTAG Port Interface Timing........................................................ 456

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PM4351 COMET

LIST OF TABLES

Table 1 - Backplane Transmit Interface (4 pins)......................................... 19

Table 2 - Backplane Receive Interface (4 pins).......................................... 21

Table 3 - Transmit Line Interface (6 pins) ................................................... 23

Table 4 - Receive Line Interface (4 pins).................................................... 24

Table 5 - Timing Options Control (5 pins) ................................................... 24

Table 6 - Analog Support Circuitry (4 pins)................................................. 25

Table 7 - JTAG (IEEE 1149.1) Boundary Scan Test Interface (5 pins)........ 26

Table 8 - Microprocessor Interface (23 pins).............................................. 26

Table 9 - Power and Ground (25 pins)........................................................ 28

Table 10 - PM4351-RI Pin Summary............................................................ 30

Table 11 PM4351-NI Pin Summary.............................................................. 30

Table 12 - External Component Descriptions............................................... 34

Table 13 - Typical Input Return Loss at Receiver ......................................... 35

Table 14 - Termination Resistors, Transformer Ratios and TRL................... 35

Table 15 - E1-FRMR Framing States............................................................ 44

Table 16 - Normal Mode Register Memory Map........................................... 66

Table 17 - TJAT FIFO Output Clock Source................................................ 90

Table 18 - TJAT PLL Source......................................................................... 91

Table 19 - Transmit Timing Options Summary.............................................. 91

Table 20 - Loss of Signal Thresholds.......................................................... 109

Table 21 - Receive Backplane NXDS0 Mode Selection ............................. 137

Table 22 - Receive Backplane Rate............................................................ 139

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Table 23 - E1 Receive Backplane Frame Pulse Configurations................. 142

Table 24 - Receive Backplane Tri-state Control.......................................... 145

Table 25 - Receive Backplane Bit Offset for CMS = 0................................ 148

Table 26 - Receive Backplane Bit Offset for CMS = 1................................ 148

Table 27 - Transmit Backplane NXDS0 Mode Selection............................. 156

Table 28 - Transmit Backplane Rate........................................................... 158

Table 29 - Transmit Backplane Bit Offset for CMS = 0............................... 165

Table 30 - Transmit Backplane Bit Offset for CMS = 1............................... 165

Table 31 - T1 Framing Modes..................................................................... 167

Table 32 - Loopback Code Configurations ................................................. 172

Table 33 - SIGX Indirect Register Map....................................................... 185

Table 34 - SIGX Indirect Registers 10H - 1FH: Current Timeslot/Channel

Signaling Data ................................................................................................ 187

Table 35 - SIGX Indirect Registers 20H - 3FH: Delayed Timeslot/Channel

Signaling Data ................................................................................................ 188

Table 36 - Indirect Registers 40H - 5FH: Per-Timeslot Configuration......... 188

Table 37 - SIGX Per-Channel T1 Data Conditioning................................... 189

Table 38 - SIGX Per-Channel E1 Data Conditioning.................................. 189

Table 39 - T1 Framing Formats.................................................................. 192

Table 40 - T1 Zero Code Suppression Formats.......................................... 192

Table 41 - Transmit In-band Code Length.................................................. 194

Table 42 - T1 Framing Modes..................................................................... 207

Table 43 - TPSC Indirect Register Map...................................................... 222

Table 44 - TPSC Indirect Registers 20H-3FH: PCM Data Control byte...... 224

Table 45 - TPSC Transmit Data Conditioning............................................. 225

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Table 46 - Transmit Test Pattern Modes..................................................... 225

Table 47 - Transmit Zero Code Suppression Formats................................ 226

Table 48 - TPSC Indirect Registers 40H-5FH: IDLE Code byte.................. 227

Table 49 - TPSC Indirect Registers 60H-7FH: Signaling/E1 Control byte... 227

Table 50 - Transmit Per-timeslot Data Manipulation................................... 228

Table 51 - A-Law Digital Milliwatt Pattern.................................................... 228

Table 52 - µ-Law Digital Milliwatt Pattern.................................................... 229

Table 53 - RPSC Indirect Register Map ...................................................... 234

Table 54 - RPSC Indirect Registers 20H-3FH: PCM Data Control byte...... 236

Table 55 - Receive Test Pattern Modes...................................................... 236

Table 56 - RPSC Indirect Registers 40H-5FH: Data Trunk Conditioning Code byte 238

Table 57 - RPSC Indirect Registers 61H-7FH: Signaling Trunk Conditioning byte 238

Table 58 - NmNi Settings............................................................................ 249

Table 59 - E1 Signaling Insertion Mode...................................................... 250

Table 60 - E1 Timeslot 0 Bit 1 Insertion Control Summary......................... 252

Table 61 - National Bits Codeword Select .................................................. 262

Table 62 - Timeslot 0 Bit Position Allocation............................................... 278

Table 63 - Signaling Multiframe Timeslot 16, Frame 0 Bit Positions........... 282

Table 64 - E1 FRMR Codeword Select....................................................... 284

Table 65 - Receive Packet Byte Status....................................................... 302

Table 66 - Clock Synthesis Mode ............................................................... 308

Table 67 - Pattern Detector Register Configurations.................................. 315

Table 68 - Error Insertion Rates.................................................................. 321

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Table 69 - Transmit Output Amplitude........................................................ 331

Table 70 - ALOS Detection/Clearance Thresholds..................................... 340

Table 71 - Equalization Feedback Frequencies.......................................... 347

Table 72 - Valid Period................................................................................ 348

Table 73 - Observing Inputs in Test Mode 0 ............................................... 351

Table 74 - Controlling Outputs in Test Mode 0............................................ 352

Table 75 - Boundary Scan Register............................................................ 354

Table 76 - Default Settings ......................................................................... 367

Table 77 - ESF Frame Format.................................................................... 368

Table 78 - SLC®96 Frame Format ............................................................. 369

Table 79 - SF Frame Format ...................................................................... 370

Table 80 - T1DM Frame Format................................................................. 370

Table 81 - E1 Frame Format....................................................................... 371

Table 82 - PMON Polling Sequence........................................................... 372

Table 83 - ESF FDL Processing ................................................................. 373

Table 84 - Performance Report Message Structure and Contents............. 380

Table 85 - Performance Report Message Structure Notes......................... 380

Table 86 - Performance Report Message Contents.................................... 381

Table 87 - Transmit Waveform Values for T1 Long Haul (LBO 0 dB):........ 382

Table 88 - Transmit Waveform Values for T1 Long Haul (LBO 7.5 dB):..... 383

Table 89 - Transmit Waveform Values for T1 Long Haul (LBO 15 dB):...... 384

Table 90 - Transmit Waveform Values for T1 Long Haul (LBO 22.5 dB): ... 385

Table 91 - Transmit Waveform Values for T1 Short Haul (0 - 110 ft.):........ 386

Table 92 - Transmit Waveform Values for T1 Short Haul (110 – 220 ft.):.... 387

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Table 93 - Transmit Waveform Values for T1 Short Haul (220 – 330 ft.): ... 388 Table 94 - Transmit Waveform Values for T1 Short Haul (330 – 440 ft.): ... 389 Table 95 - Transmit Waveform Values for T1 Short Haul (440 – 550 ft.): ... 390 Table 96 - Transmit Waveform Values for T1 Short Haul (550 – 660 ft.): ... 391 Table 97 - TR62411 Transmit Waveform Values for T1 Long Haul (LBO 0 dB):

392

Table 98 - TR62411 Transmit Waveform Values for T1 Short Haul (0 - 110 ft.):

393

Table 99 - TR62411 Transmit Waveform Values for T1 Short Haul (110 – 220 ft.): 394

Table 100 - TR62411 Transmit Waveform Values for T1 Short Haul (220 – 330 ft.): 395

Table 101 - TR62411 Transmit Waveform Values for T1 Short Haul (330 – 440 ft.): 396

Table 102 - TR62411 Transmit Waveform Values for T1 Short Haul (440 – 550 ft.): 397

Table 103 - TR62411 Transmit Waveform Values for T1 Short Haul (550 – 660 ft.): 398

Table 104 - Transmit Waveform Values for E1 120 Ohm:............................. 399

Table 105 - Transmit Waveform Values for E1 75 Ohm:............................... 400

Table 106 - RLPS Register Programming....................................................... 401

Table 107 - RLPS Equalizer RAM Table (T1 mode) ..................................... 402

Table 108 - RLPS Equalizer RAM Table (E1 mode) ..................................... 407

Table 109 - RLPS Equalizer Lookup Table for T1 Performance Monitor Mode412

Table 110 - Pseudo-Random Pattern Generation (PS bit = 0) ..................... 415

Table 111 - Repetitive Pattern Generation (PS bit = 1).................................416

Table 112 - PMON Counter Saturation Limits (E1 mode)............................. 423

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Table 113 - PMON Counter Saturation Limits (T1 mode)............................. 423

Table 114 - Boundary Scan Register............................................................ 433

Table 115 - D.C. Characteristics................................................................... 439

Table 116 - Microprocessor Read Access (Figure 55).................................. 442

Table 117 - Microprocessor Write Access (Figure 56).................................. 444

Table 118 - Transmit Backplane Interface.................................................... 446

Table 119 - Receive Backplane Interface..................................................... 448

Table 120 - Receive Digital Interface............................................................ 452

Table 121 - Transmit Digital Interface........................................................... 453

Table 122 - JTAG Port Interface................................................................... 455

Table 123 - Ordering Information.................................................................. 458

Table 124 - Thermal Information................................................................... 458

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STANDARD PRODUCT

DATA SHEET PMC-1970624 ISSUE 10 COMBINED E1/T1 TRANSCEIVER

PM4351 COMET

1 FEATURES

• Monolithic device which integrates software selectable full-featured T1 and

E1 framers and T1 and E1 short haul and long haul line interfaces.

• Meets or exceeds T1 and E1 shorthaul and longhaul network access

specifications including AN SI T1.102, T1.403, T1.408, AT&T TR 62411, ITU-T G.703, G.704 as well as ETSI 300-011, CTR-4, CTR-12 and CTR-13.

• Provides encoding and decoding of B8ZS, HDB3 and AMI line codes.

• Provides receive equalization, clock recovery and line performance

monitoring.

• Provides transmit jitter attenuation and digitally programmable long haul and

short haul line build out.

• Provides on-board programmable binary sequence generators and detectors

for error testing including support for patterns recommended in ITU-T O.151.

• Provides three full-featured HDLC controllers, each with 128-byte transmit

and receive FIFO buffers.

• Automatically generates and transmits DS-1 performance report messages to

ANSI T1.231 and ANSI T1.408 specifications.

• Compatible with Mitel ST®-bus, A T&T CHI® and MVIP PCM backplanes,

supporting rates of 1.544 Mbit/s, 2.048 Mbit/s, 4.096 Mbit/s, and 8.192 Mbit/s. Up to four COMET devices may be byte-interleaved on a single backplane with no external circuitry.

• Supports NxDS0 fractional bandwidth backplane.

• Provides an 8-bit microprocessor bus interface for configuration, control, and

status monitoring.

• Uses line rate system clock.

• Provides a IEEE P1149.1 (JTAG) compliant test access port (TAP) and

controller for boundary scan test.

• Implemented in a low power 5 V tolerant +3.3 V CMOS technology.

PROPRIETARY AND CONFIDENTIAL

1

STANDARD PRODUCT

DATA SHEET PMC-1970624 ISSUE 10 COMBINED E1/T1 TRANSCEIVER

PM4351 COMET

• Available in a high density 80-pin MQFP (14 mm by 14 mm) package or an

81-ball CABGA (9 mm by 9 mm) package.

• Provides a -40°C to +85°C Industrial temperature operating range.

1.1 Receiver section:

• Guaranteed T1 signal reception for distances with up to 36 dB of cable

attenuation under production test conditions (772 kHz, VDD = 3.069V and 25°C) using PIC 22 gauge cable emulation.

• Guaranteed E1 signal reception for distances with up to 36 dB of cable

attenuation under production test conditions (1.024 MHz, VDD = 3.069V and 25°C) using PIC 22 gauge cable emulation.

• Recovers clock and data using a digital phase locked loop for high jitter

tolerance.

• Provides an alternative digital interface for applications without line interface

units.

• Frames to ITU-T G.704 basic and CRC-4 multiframe formatted E1 signals.

The framing procedures are consistent ITU-T G.706 specifications.

• Frames to DSX/DS-1 signals in D4, SF, ESF and SLC®96 formats.

• Frames to TTC JT-G704 multiframe formatted J1 signals. Supports the

alternate CRC-6 calculation for Japanese applications.

• Frames in the presence of and detects the “Japanese Yellow” alarm.

• Tolerates more than 0.3 UI peak-to-peak, high frequency jitter as required by

AT&T TR 62411 and Bellcore TR-TSY-000170.

• Detects violations of the ANSI T1.403 12.5% pulse density rule over a moving

192-bit window.

• Provides loss of signal detection as per ITU-T G.775 and ANSI T1.231. Red,

Yellow, and AIS alarm detection and integration are according to ANSI T1.231 specifications.

• Provides programmable in-band loopback activate and deactivate code

detection.

PROPRIETARY AND CONFIDENTIAL

2

STANDARD PRODUCT

DATA SHEET PMC-1970624 ISSUE 10 COMBINED E1/T1 TRANSCEIVER

PM4351 COMET

• Supports line and path performance monitoring according to AT&T and ANSI

specifications. Accumulators are provided for counting ESF CRC-6 errors, framing bit errors, line code violations and loss of frame or change of frame alignment events.

• Provides ESF bit-oriented code detection and an HDLC/LAPD interface for

terminating the ESF facility data link.

• Supports polled or interrupt-driven servicing of the HDLC interface.

• Extracts the data link in ESF and T1DM (DDS) modes. Optionally extracts a

datalink in the E1 national use bits.

• Extracts 4-bit codewords from the E1 national use bits as specified in

ETS 300 233

• Extracts up to three HDLC links from arbitrary time slots to support the D-

channel for ISDN Primary Rate Interfaces and the C-channels for V5.1/V5.2 interfaces.

• Detects the V5.2 link identification signal.

• Provides a two-frame elastic store buffer for backplane rate adaptation that

performs controlled slips and indicates slip occurrence and direction.

• Provides DS-1 robbed bit signaling extraction, with optional data inversion,

programmable idle code substitution, digital milliwatt code substitution, bit fixing, and two superframes of signaling debounce on a per-channel basis.

• Frames to the E1 signaling multiframe alignment when enabled and extracts

channel associated signaling. Alternatively, a common channel signaling data link may be extracted from timeslot 16.

• Can be programmed to generate an interrupt on change of signaling state.

• Provides trunk conditioning which forces programmable trouble code

substitution and signaling conditioning on all channels or on selected channels.

• Provides diagnostic, line loopbacks and per-DS0 line loopback.

• Provides an integral pattern detector that may be programmed to detect

common pseudo-random sequences. The programmed sequence may be detected in the entire frame, or on an NxDS0 basis.

PROPRIETARY AND CONFIDENTIAL

3

STANDARD PRODUCT

DATA SHEET PMC-1970624 ISSUE 10 COMBINED E1/T1 TRANSCEIVER

PM4351 COMET

• Provides an integral pattern generator that may be programmed to generate

common pseudo-random or repetitive sequences towards the backplane.

• Provides tristateable single-rail PCM and signaling data outputs for

1.544 Mbit/s, 2.048 Mbit/s, 4.096 Mbit/s or 8.192 Mbit/s backplane buses.

1.2 Transmitter section:

• Supports transfer of transmitted single rail PCM and signaling data from

1.544 Mbit/s, 2.048 Mbit/s, 4.096 Mbit/s or 8.192 Mbit/s backplane buses.

• Generates DSX-1 shorthaul and DS-1 longhaul pulses with programmable

pulse shape compatible with AT&T, ANSI and ITU requirements.

• Generates E1 pulses compliant to G.703 recommendations.

• Provides a digitally programmable pulse shape extending up to 5 transmitted

bit periods for custom long haul pulse shaping applications.

• Provides line outputs which are current limited and may be tristated for

protection or in redundant applications.

• Provides an alternative digital interface for external line interface units.

• Provides a digital phase locked loop for generation of a low jitter transmit

clock complying with all jitter attenuation, jitter transfer and residual jitter specifications of AT&T TR 62411 and ETSI TBR 12 and TBR 13.

• Provides a FIFO buffer for jitter attenuation and rate conversion in the

transmit path.

• Provides a two-frame payload slip buffer to allow independent backplane and

line timing.

• Provides an integral pattern generator that may be programmed to generate

common pseudo-random or repetitive sequences. The programmed sequence may be inserted in the entire frame, or on an NxDS0 basis.

• Provides an integral pattern detector that may be programmed to detect

common pseudo-random or repetitive sequences from the backplane.

• Transmits G.704 basic and CRC-4 multiframe formatted E1 signals or D4, SF

or ESF formatted DSX/DS-1 signals.

PROPRIETARY AND CONFIDENTIAL

4

STANDARD PRODUCT

DATA SHEET PMC-1970624 ISSUE 10 COMBINED E1/T1 TRANSCEIVER

PM4351 COMET

• Transmits TTC JT-G704 multiframe formatted J1 signals. Supports the

alternate ESF CRC-6 calculation for Japanese applications.

• Transmits the “Japanese Yellow” alarm.

• Supports unframed mode and framing bit, CRC, or data link by-pass.

• Provides signaling insertion, programmable idle code substitution, digital

milliwatt code substitution, and data inversion on a per channel basis.

• Provides trunk conditioning which forces programmable trouble code

substitution and signaling conditioning on all channels or on selected channels.

• Provides minimum ones density through Bell (bit 7), GTE or DDS zero code

suppression on a per channel basis.

• Detects violations of the ANSI T1.403 12.5% pulse density rule over a moving

192-bit window and optionally stuffs ones to maintain minimum ones density.

• Allows insertion of framed or unframed in-band loopback code sequences.

• Allows insertion of a data link in ESF or T1DM (DDS) DS-1 modes.

Optionally inserts a datalink in the E1 national use bits.

• Supports 4-bit codeword insertion in the E1 national use bits as specified in

ETS 300 233

• Inserts up to three HDLC links into arbitrary time slots to support the D-

channel for ISDN Primary Rate Interfaces and the C-channels for V5.1/V5.2 interfaces.

• Supports transmission of the alarm indication signal (AIS) and the Yellow

alarm signal. Supports “Japanese Yellow” alarm generation.

• Provides ESF bit-oriented code generation.

PROPRIETARY AND CONFIDENTIAL

5

STANDARD PRODUCT

DATA SHEET PMC-1970624 ISSUE 10 COMBINED E1/T1 TRANSCEIVER

PM4351 COMET

2 APPLICATIONS

• T1/E1 Wireless Digital Loop Carriers (DLC's) and Cellular Base Stations

• T1/E1 Internet Access Equipment

• T1/E1 Channel Service Units (CSU)

• T1/E1 Frame Relay Interfaces

• T1/E1 ATM Interfaces

• T1/E1 Multiplexers (CPE MUX)

• Digital Private Branch Exchanges (PBX)

• Digital Access Cross-Connect Systems (DACS) and Electronic DSX Cross-

Connect Systems (EDSX)

• ISDN Primary Rate Interfaces (PRI)

• Test Equipment

PROPRIETARY AND CONFIDENTIAL

6

STANDARD PRODUCT

DATA SHEET PMC-1970624 ISSUE 10 COMBINED E1/T1 TRANSCEIVER

PM4351 COMET

3 REFERENCES

1. ANSI - T1.101-1987 - American National Standard for Telecommunications -

Digital Hierarchy - Timing Synchronization.

2. ANSI - T1.102-1993 - American National Standard for Telecommunications -

Digital Hierarchy - Electrical Interfaces.

3. ANSI - T1.107-1995 - American National Standard for Telecommunications -

Digital Hierarchy - Formats Specification.

4. ANSI - T1.231-1993 - American National Standard for Telecommunications -

Layer 1 In-Service Digital Transmission Performance Monitoring

5. ANSI - T1.403-1995 - American National Standard for Telecommunications -

Carrier to Customer Installation - DS-1 Metallic Interface Specification.

6. ANSI - T1.408-1990 - American National Standard for Telecommunications -

Integrated Services Digital Network (ISDN) Primary Rate - Customer Installation Metallic Interfaces Layer 1 Specification.

7. AT&T - PUB 43802 – Digital Multiplexes Requirements and Objectives,

July 1982.

8. AT&T - PUB 54016 - Requirements For Interfacing Digital Terminal

Equipment To Services Employing The Extended Superframe Format, October 1984.

9. AT&T - TR 62411 - Accunet T1.5 - Service Description and Interface

Specification, December 1990.

10. AT&T - TR 62411 - Accunet T1.5 - Service Description and Interface

Specification, Addendum 1, March 1991.

11. AT&T - TR 62411 - Accunet T1.5 - Service Description and Interface

Specification, Addendum 2, October 1992.

12. AT&T - Interface Specification - Concentration Highway Interface -

November 1990.

13. Bellcore – Digital Cross-Connect System Requirements and Objectives,

TR-TSY-000170, Issue 1, November 1985.

14. Bellcore – Extended Superframe format (ESF),TR-TSY-000194, Issue 1,

December 1987

PROPRIETARY AND CONFIDENTIAL

7

STANDARD PRODUCT

DATA SHEET PMC-1970624 ISSUE 10 COMBINED E1/T1 TRANSCEIVER

PM4351 COMET

15. ETSI - ETS 300 011 – Integrated Services Digital Network (ISDN); Primary

Rate User-Network Interface Layer 1 Specification and Test Principles, April 1992.

16. ETSI - ETS 300 011 A1 – Integrated Services Digital Network (ISDN); Primary

Rate User-Network Interface Layer 1 Specification and Test Principles, December 1992.

17. ETSI - ETS 300 011 A2 – Integrated Services Digital Network (ISDN); Primary

Rate User-Network Interface Layer 1 Specification and Test Principles, March 1996.

18. ETSI - ETS 300 166 – Transmission and Multiplexing (TM); Physical and

Electrical Characteristics of Hierarchical Digital Interfaces for Equipment Using the 2 048 kbit/s - based Plesiochronous or Synchronous Digital Hierarchies, August 1993.

19. ETSI - ETS 300 233 – Integrated Services Digital Network (ISDN); Access

Digital Section for ISDN Primary Rate, May 1994.

20. ETSI - ETS 300 324-1 - Signaling Protocols and Switching (SPS); V

interfaces at the Digital Local Exchange (LE) V5.1 Interface for the Support of Access Network (AN) Part 1: V5.1 Interface Specification, February 1994.

21. ETSI - ETS 300 347-1 - Signaling Protocols and Switching (SPS); V

Interfaces at the Digital Local Exchange (LE) V5.2 Interface for the Support of Access Network (AN) Part 1: V5.2 Interface Specification, September 1994.

22. ETSI - CTR 4 - Integrated Services Digital Network (ISDN); Attachment

requirements for terminal equipment to connect to an ISDN using ISDN primary rate access, November 1995.

23. ETSI - CTR 12 - Business Telecommunications (BT); Open Network Provision

(ONP) technical requirements; 2 048 kbit/s digital unstructured leased lines (D2048U) Attachment requirements for terminal equipment interface, December 1993.

24. ETSI - CTR 13 - Business Telecommunications (BTC); 2 048 kbit/s digital

structured leased lines (D2048S); Attachment requirements for terminal equipment interface, January 1996.

25. FCC Rules - Part 68.308 - Signal Power Limitations

26. ITU-T - Recommendation G.703 - Physical/Electrical Characteristics of

Hierarchical Digital Interface, Geneva, 1991.

PROPRIETARY AND CONFIDENTIAL

8

STANDARD PRODUCT

DATA SHEET PMC-1970624 ISSUE 10 COMBINED E1/T1 TRANSCEIVER

PM4351 COMET

27. ITU-T - Recommendation G.704 - Synchronous Frame Structures Used at

Primary Hierarchical Levels, July 1995.

28. ITU-T - Recommendation G.706 - Frame Alignment and CRC Procedures

Relating to G.704 Frame Structures, 1991.

29. ITU-T - Recommendation G.732 – Characteristics of Primary PCM Multiplex

Equipment Operating at 2048 kbit/s, 1993.

30. ITU-T - Recommendation G.711 – Pulse Code Modulation (PCM) of Voice

Frequencies, 1993.

31. ITU-T - Recommendation G.775 - Loss of Signal (LOS), November 1994.

32. ITU-T Recommendation G.802, - Interworking Between Networks Based on

Different Digital Hierarchies and Speech Encoding Laws, 1993.

33. ITU-T Recommendation G.823, - The Control of Jitter and Wander Within

Digital Networks Which are Based on the 2048 kbit/s Hierarchy, 1993.

34. ITU-T Recommendation G.964, - V-Interfaces at the Digital Local Exchange

(LE) - V5.1 Interface (Based on 2048 kbit/s) for the Support of Access Network (AN), June 1994.

35. ITU-T Recommendation G.965, - V-Interfaces at the Digital Local Exchange

(LE) - V5.2 Interface (Based on 2048 kbit/s) for the Support of Access Network (AN), March 1995.

36. ITU-T - Recommendation I.431 - Primary Rate User-Network Interface –

Layer 1 Specification, 1993.

37. ITU-T Recommendation O.151, - Error Performance Measuring Equipment

For Digital Systems at the Primary Bit Rate and Above, 1988.

38. ITU-T Recommendation O.152 - Error Performance Measuring Equipment for

Bit Rates of 64 kbit/s and N X 64 kbit/s, October 1992

39. ITU-T Recommendation O.153 - Basic Parameters for the Measurement of

Error Performance at Bit Rates below the Primary Rate, October 1992.

40. TTC Standard JT-G703 - Physical/Electrical Characteristics of Hierarchical

Digital Interfaces, 1995.

41. TTC Standard JT-G704 - Frame Structures on Primary and Secondary

Hierarchical Digital Interfaces, 1995.

PROPRIETARY AND CONFIDENTIAL

9

STANDARD PRODUCT

DATA SHEET PMC-1970624 ISSUE 10 COMBINED E1/T1 TRANSCEIVER

PM4351 COMET

42. TTC Standard JT-G706 - Frame Synchronization and CRC Procedure

43. TTC Standard JT-I431 - ISDN Primary Rate User-Network Interface Layer 1 -

Specification, 1995.

44. Nippon Telegraph and Telephone Corporation - Technical Reference for High-

Speed Digital Leased Circuit Services, Third Edition, 1990.

45. GO-MVIP - Multi-Vendor Integration Protocol, MVIP-90 Release 1.1, 1994.

PROPRIETARY AND CONFIDENTIAL

10

STANDARD PRODUCT

DATA SHEET PMC-1970624 ISSUE 10 COMBINED E1/T1 TRANSCEIVER

PM4351 COMET

4 APPLICATION EXAMPLE

Figure 1 - Wireless Base Station Application

PM8313

D3MX

or

PM5342

SPECTRA

DS3

or

Fibre Optics

TOCTL/TQUAD/

Basestation

Switch

Fabric

TOCTL/TQUAD/

Base Station

Controller

Public

Switched

Telephone

Network

EQUAD

QDSX

T1/E1/J1

Longhaul/

Shorthaul

LIU

Software

Selectable

T1/E1/J1

Framer

MVIP

Tx/Rx

RF

Subsystem

PM4351 COMET

T1/E1/J1

Longhaul/

Shorthaul

LIU

Software

Selectable

T1/E1/J1

Framer

MVIP

Intel or Motorola

Low Power

3.3v Power Supply

µµµµ

P

PM4351 COMET

CDMA/TDMA/GSM

Base Transceiver Station

●●●●

COMET provides a complete physical layer solution fo r Basestation designs, while the PM4314 QDSX, the PM6344 EQUAD, the and PM4388 TOCTL provide high density multi-channel solutions for the Basestation Controller

PROPRIETARY AND CONFIDENTIAL

11

STANDARD PRODUCT

DATA SHEET PMC-1970624 ISSUE 10 COMBINED E1/T1 TRANSCEIVER

PM4351 COMET

Figure 2 - V5.1 Interface Application

PM4314

PM6344

QDSX

PM5342

SPECTRA

155

STM-1

Switch Fabric

PM5362

TUPP+

PM7364

FREEDM

Central Offi ce S wi tch

EQUAD

PM6344 EQUAD

Processor

PM4314

QDSX

PM4314

QDSX

PM4314

QDSX

V5.1

Interface

LIU Framer

PM4351 COMET

Intel or Motorola

HDLC

µµµµ

P

Line Card Line Card Line Card

●●●●

Line Card

Low Power

3.3v Power Supply

Subscribers

●●●●

Pedestal-Mount

Digital Loo p C ar r ier

COMET used in conjunction with PM6344 EQUAD and PM7366 FREEDM-8 to provide a complete V5.1 solution for both the Access Network and the Central Office

PROPRIETARY AND CONFIDENTIAL

12

STANDARD PRODUCT

PM4351 COMET

DATA SHEET PMC-1970624 ISSUE 10 COMBINED E1/T1 TRANSCEIVER

5 BLOCK DIAGRAM

D[7:0]

A[8:0]

RDB

WRB

CSB

ALE

RSTB

INTB

TDO

TDI TCK TMS

TRSTB

MPIF

Micro-

Processor

Interface

JTAG

Test Access

Port

Bit Oriented

XBOC

Code

Generator

TDPR#3

HDLC

Transmitter

TDPR#2

HDLC

Transmitter

TDPR#1

HDLC

Transmitter

] 1

: 2

[ P

T

I

A

T

P

X

D

F

T

XLPG

Transmit

LIU

TJAT

Tran s mit

Digital Jitter

Attenuator

T1-XBAS/

E1-TRAN

BasicTransmitter:

Frame Generation,

Alarm Insertion, Signaling Insertion, Trunk Conditioning

] 1

: 2

[ G N

I R X T

TX-

ELST

Elastic

Store

BTIF

Backplane

Tran sm it Interface

F

O

E

K

R

L

V

C

T

XIBC

Inband

Loopback

Code

Generator

PRGD

1/2 Pattern Gene rato r/

Detector

I K L C T

Clock Synthesis and Distribution

XPDE

Pulse

Density

Enforcer

TPSC

Per-DS0

Serial

Controller

K L C V /

K L C X

CSD

TOPS

Timing Options

PRGD

1/2 Pattern Generator /

Detector

C N Y S R

FRAM

Framing

RAM

RPSC

Per-DS0

Serial

Controller

F E R V R

ELST

Elastic

Store

P

I T X R

RLPS

Receive

LIU

CDRC

Clock and

Data

Recovery

RJAT

Receive

Digital Jitter

Attenuator

IBCD

Inband

Loopback

Code

Detector

FRMR

Frame

Alignment,

Alarm

Extraction

RX-

BRIF

Backplane

Receive

Interface

G N

I R X R

PMON

Performance

Monitor

Counters

ALMI

Alarm

Integrator

Signaling

Extrac tor

E1/T1-

SIGX

T A D R

I K L C R

PDVD

Density Violation Detector

RBOC

Bit Oriented

Detector

RDLC#3

Receiver

RDLC#2

Receiver

RDLC#1

HDLC

Receiver

Pulse

Code

HDLC

PROPRIETARY AND CONFIDENTIAL

G

P

K

M

I

L

F

S

C

T

C

T

P

B

T

B

T

B

K

P

G

M

I

L

F

C

S

C

R

P

R

B

R

B

13

STANDARD PRODUCT

DATA SHEET PMC-1970624 ISSUE 10 COMBINED E1/T1 TRANSCEIVER

PM4351 COMET

6 DESCRIPTION

The PM4351 Combined E1/T1 Transceiver (COMET) is a feature-rich monolithic integrated circuit suitable for use in long haul and short haul T1 and E1 systems with a minimum of external circuitry. The COMET is software configurable, allowing feature selection without changes to external wiring.

Analog circuitry is provided to allow direct reception of long haul E1 and T1 compatible signals with up to 36 dB cable loss (at 1.024 MHz in E1 mode) or up to 36 dB cable loss (at 772 kHz in T1 mode) using a minimum of external components. Typically, only line protection, a transformer and a line termination resistor are required. Digital line inputs are provided for applications not requiring a physical T1 or E1 interface.

The COMET recovers clock and data from the line and frames to incoming data. In T1 mode, it can frame to several DS-1 signal formats: SF, ESF, T1DM (DDS) and SLC®96. In E1 mode, the COMET frames to basic G.704 E1 signals and CRC-4 multiframe alignment signals, and automatically performs the G.706 interworking procedure. AMI, HDB3 and B8ZS line codes are supported.

The COMET supports detection of various alarm conditions such as loss of signal, pulse density violation, Red alarm, Yellow alarm, and AIS alarm in T1 mode and loss of signal, loss of frame, loss of signaling multiframe and loss of CRC multiframe in E1 mode. The COMET also supports reception of remote alarm signal, remote multiframe alarm signal, alarm indication signal, and time slot 16 alarm indication signal in E1 mode. The presence of Yellow and AIS patterns in T1 mode and remote alarm and AIS patterns in E1 mode is detected and indicated. In T1 mode, the COMET integrates Yellow, Red, and AIS alarms as per industry specifications. In E1 mode, the COMET integrates Red and AIS alarms.

Performance m onitoring with accumulation of CRC-6 errors, framing bit errors, line code violations, and loss of frame events is provided in T1 mode. In E1 mode, CRC-4 errors, far end block errors, framing bit errors, and line code violation are monitored and accumulated.

The COMET provides three receive HDLC controllers for the detection and termination of messages on the ESF facility data link (T1) or national use bits (E1) and in any arbitrary time slot (T1 or E1). In T1 mode, the COMET also detects the presence of in-band loop back codes and ESF bit oriented codes. Detection and optional debouncing of the 4-bit Sa-bit codewords defined in ITUT G.704 and ETSI 300-233 is supported. An interrupt may be generated on any change of state of the Sa codewords.

PROPRIETARY AND CONFIDENTIAL

14

STANDARD PRODUCT

DATA SHEET PMC-1970624 ISSUE 10 COMBINED E1/T1 TRANSCEIVER

PM4351 COMET

Dual (transmit and receive) elastic stores for slip buffering and rate adaptation to backplane timing are provided, as is a signaling extractor that supports signaling debounce, signaling freezing, idle code substitution, digital milliwatt tone substitution, data inversion, and signaling bit fixing on a per-channel basis. Receive side data and signaling trunk conditioning is also provided.

In T1 mode, the COMET generates framing for SF, ESF and T1DM (DDS) formats. In E1 mode, the COMET generates framing for a basic G.704 E1 signal. The signaling multiframe alignment structure and the CRC multiframe structure may be optionally inserted. Framing can be optionally disabled.

Internal analog circuitry allows direct transmission of long haul and short haul T1 and E1 compatible signals using a minimum of external components. Typically, only line protection, a transformer and an optional line termination resistor are required. Digitally programmable pulse shaping allows transmission of DSX-1 compatible signals up to 655 feet from the cross-connect, E1 short haul pulses into 120 ohm twisted pair or 75 ohm coaxial cable, E1 long haul pulses into 120 ohm twisted pair as well as long haul DS-1 pulses into 100 ohm twisted pair with integrated support for LBO filtering as required by the FCC rules. In addition, the programmable pulse shape extending over 5-bit periods allows customization of short haul and long haul line interface circuits to application requirements. Digital line inputs and outputs are provided for applications not requiring a physical T1 or E1 interface.

In the transmit path, the COMET supports signaling insertion, idle code substitution, digital milliwatt tone substitution, data inversion, and zero code suppression on a per-channel basis. Zero code suppression may be configured to Bell (bit 7), GTE, or DDS standards, and can also be disabled. Transmit side data and signaling trunk conditioning is also provided. Signaling bit transparency from the backplane may be enabled.

The COMET provides three transmit HDLC controllers. These controllers may be used for the transmission of messages on the ESF data link (T1) or national use bits (E1) and in any time slot. In T1 mode, the COMET can be configured to generate in-band loop back codes and ESF bit oriented codes. In E1 mode, transmission of the 4-bit Sa codewords defined in ITU-T G.704 and ETSI 300233 is supported.

The COMET provides optional jitter attenuation in both the transmit and receive directions.

The COMET provides both a parallel microprocesso r interface for controlling the operation of the device and serial PCM interfaces that allow backplane rates from 1.544 Mbit/s to 8.192 Mbit/s to be directly supported. Up to four COMET devices can be multiplexed on a byte-interleaved basis on a common bus with

PROPRIETARY AND CONFIDENTIAL

15

STANDARD PRODUCT

DATA SHEET PMC-1970624 ISSUE 10 COMBINED E1/T1 TRANSCEIVER

PM4351 COMET

no additional arbitration logic. The COMET supports the Mitel ST® bus, AT&T

®

and MVIP standards.

CHI

PROPRIETARY AND CONFIDENTIAL

16

STANDARD PRODUCT

PM4351 COMET

DATA SHEET PMC-1970624 ISSUE 10 COMBINED E1/T1 TRANSCEIVER

7 PIN DIAGRAMS

The COMET is packaged in an 80-pin metric plastic quad flat pack (MQFP) package having a body size of 14 mm by 14 mm and a pin pitch of 0.65 mm.

Figure 3 PM4351-RI COMET Pin Diagram

TAVD1 TAVS1

XCLK

TCLKI

TCLKO

TDAT

TFP VDDO2 VSSO2

BTCLK

BTPCM

BTSIG

BTFP

VDDI2

VSSI2

TCK

TMS

TDI

TDO

TRSTB

2 G

2

3

F

3

N

P

I R X T

0 8

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20

1 2

B S C

E

S

D

I

V

T

R

V

X

A

V

A

T

8

9

7

6

7

PM4351-RI

2

4

5

3

2

B

T

D

R

S

N

R

I

W

R

1 G

1

2

2 S V A T

5 7

4

N

P

D

I T

V

X

A

T

T 4

3

7

S

I

D

R

V

X

A

T

2

1

7

D

S

V

B

A

T

A T

Q

A

Q

9

0

8

7

6

7

6

(TOP VIE W)

6

7

8

9

0

1

4

2

]

0

3

1

2

[

D

3

]

3 O D D V

]

3

4

5

6

[

O

D

S S V

G

2

2 S

D

V

A

R

6

5

6

5

6

3

]

7

0

[

[ A

D

1

N

P

I

S

D

I

R

T

V

X

A

R

3

4

2

1

6

60

RVREF PIO

59

TRIMF

58 57

RDAT RCLKI

56

RSYNC

55 54

BRCLK VDDO1

53

VSSO1

52 51

BRPCM BRSIG

50

BRFP

49 48

VDDI1 VSSI1

47

BIAS

46 45

ALE A[8]

44

A[7]

43 42

A[6] A[5]

41

7

8

9

0

3

4

]

1

2

3

4

[

A

PROPRIETARY AND CONFIDENTIAL

17

STANDARD PRODUCT

DATA SHEET PMC-1970624 ISSUE 10 COMBINED E1/T1 TRANSCEIVER

PM4351 COMET

The COMET is also available in an 81 pin Chip Array Ball Grid Array (CABGA) package having a body size of 9 mm by 9 mm and a pin pitch of 0.8 mm.

Figure 4 PM4351-NI COMET Pin Diagram

(Bottom View)

987654321

A RAVD1 RXRING RAVD2 QAVD TAVD4 TVREF T AVS2 TXTIP2 TAVD1 A

B PIO RAVS1 RAVS2 ATB TAVD3 TAVD2 TAVS3 TAVS1 TCLKI B

C RSYNC TRIMF RXTIP T AVS4 TXRING1TXRING2XCLK/

VCLK

D RCLKI BRCLK RVREF QAVS TXTIP1 VSSO1 BTCLK VDDO1 TFP D

E BRPCM RDAT VSSO2 VDDO2 NC BTFP BTSIG TMS BTPCM E

F VSSI2 VDDI2 BRSIG BRFP D[5] D[3] TRSTB VDDI1 TCK F

G ALE BIAS A[7] A[4] D[4] VDDO3 RDB TDI VSSI1 G

H A[8] A[6] A[2] D[6] A[1] D[2] D[0] RSTB TDO H

J A[5] A[3] D[7] A[0] VSSO3 D[1] INTB WRB CSB J

987654321

TDAT TCLKO C

PROPRIETARY AND CONFIDENTIAL

18

STANDARD PRODUCT

DATA SHEET PMC-1970624 ISSUE 10 COMBINED E1/T1 TRANSCEIVER

PM4351 COMET

8 PIN DESCRIPTION

Table 1 - Backplane Transmit Interface (4 pins)

Pin No.Pin Name Type

-RI -NI

BTCLK I/O 10 D3 Backplane Transmit Cloc k (BTCLK). In synchronous bac kplane applications,

Function

the BTCLK input may be a 1. 544 MHz, 2.048 MHz, 3.088 MHz, 4.096 MHz,

8.192 MHz or 16.384 MHz clock with optional gapping for adaptat i on from nonuniform system clocks.

BTCLK can be configured as a li ne-rat e output, in which case it is ref erenced to TCLKI or the receive recovered clock (loop timed). In T1 NxDS0 mode, BTCLK is gapped during the fram i ng bi t position and optionally for between 1 and 23 DS0 channels in the backpl ane data s tream. In E1 NxDS0 mode, BTCLK is gapped optionally for between 1 and 31 time slots in the backplane data stream.

When BTCLK is configured as an input, byte-interl eaved backplanes are supported.

BTCLK may be configured t o be active on either its rising or fal l i ng edge. BTPCM and BTSIG are sampl ed on t he active edge of BTCLK. Depending on its configuration, BTFP is ei ther sampled or updated on the selec ted active edge of BTCLK.

After a reset, BTCLK is configured as an input.

PROPRIETARY AND CONFIDENTIAL

19

STANDARD PRODUCT

DATA SHEET PMC-1970624 ISSUE 10 COMBINED E1/T1 TRANSCEIVER

PM4351 COMET

Pin No.Pin Name Type

Function

-RI -NI

BTFP I/O 13 E4 B ackplane Transmit Frame Pulse (BTFP). When BTFP is configured as an

input, it is used to f rame align the transmitter to the system backplane. T1 mode: If only frame alignment is required, a pulse at leas t one BTCLK cycle wide

must be provided on BTFP at mul tiples of 193 bit periods. If superframe alignment is required, t ransmit superframe al i gnment must be enabled, and BTFP must be brought high for at least one BTCLK cycle to mark bit 1 of frame 1 of every 12-frame or 24-frame s uperframe.

E1 mode: If basic frame al i gnment only is required, a pulse at least one BTCLK cycle

wide must be provided on BTFP at mult ipl es of 256 bit periods. If multiframe alignment is required, t ransmit multiframe alignment m ust be enabled, and BTFP must be brought high to mark bit 1 of frame 1 of every 16-f rame signaling multif rame and brought low following bit 1 of frame 1 of every 16frame CRC multif rame. This mode allows both mul tiframe alignments to be independently controlled using the s i ngl e B TFP s i gnal . Note that if the signaling and CRC multiframe alignments are coincident, BTFP must pulse high for one BTCLK cycle every 16 frames.

When BTFP is conf i gured as an output (only valid when the transmit backplane clock rate is no greater t han 2.048 MHz), transmit frame alignment is derived internally and BTFP is updated on the confi gured active edge of BTCLK. BTFP pulses high for one cycle to indi cate the first bit of each frame or multiframe, as optioned.

BTPCM Input 11 E1 Backplane Transmit PCM Data (BTPCM). The non-return to zero, digital data

BTSIG Input 12 E3 Backplane Transmit Signaling (BTSIG). The BTSIG i nput signal contains the

PROPRIETARY AND CONFIDENTIAL

After a reset, BTFP is confi gured as an input.

stream to be transmitted is input on this pin. BTPCM may present a

1.544 Mbit/s, 2.048 Mbit/s or sub-rate NxDS0 data stream or may pres ent a byte-interleaved 4.096 Mbit/s or 8.192 Mbit/s multiplexed data stream.

The bit alignment of BTP CM relati ve to BTFP is configurable. Two mappings of a DS-1 into a 2.048 Mbit/s f ormat are defined: every fourth ti meslot unused and 24 contiguous times l ots .

The BTPCM signal is sam pl ed on t he configured active edge of BTCLK.

signaling bits for each channel i n the transmit data fram e, repeated for the entire superframe. Eac h channel's signaling bits are in bit l ocations 5, 6, 7 and 8 of the channel and are channel-aligned with the BT PCM data stream.

The BTSIG signal is sampled on the configured active edge of BTCLK.

20

STANDARD PRODUCT

DATA SHEET PMC-1970624 ISSUE 10 COMBINED E1/T1 TRANSCEIVER

PM4351 COMET

Table 2 - Backplane Receive Interface (4 pins)

Pin No.Pin Name Type

Function

-RI -NI

BRCLK I/O 54 D8 Backplane Receive Clock (BRCLK). W hen BRCLK is configured as an input

and the elastic store i s enabled, BRCLK may be either a 1.544 MHz,

2.048 MHz, 3.088 MHz, 4.096 MHz, 8.192 MHz or 16.384 MHz clock with optional gapping for adaptation to non-uniform backplane data streams.

When BRCLK is configured as a output, it c an be ei ther a 1.544 MHz or

2.048 MHz clock derived from t he recovered line rate timing (available on RSYNC), with optional jitter attenuation. In T1 NxDS0 mode, BRCLK is gapped during the framing bit posi tion and optionally for between 1 and 23 DS0 channels in the backplane data stream. In E1 NxDS0 mode, BRCLK is gapped optionally for between 1 and 31 time slots i n the backplane data stream.

Either the rising or falli ng edge of BRCLK may be configured as the active edge. BRPCM and BRSIG are updated on the acti ve edge of BRCLK. When BRFP is configured as an input, i t is sampled on the act i ve edge of BRCLK. When BRFP is confi gured as an output, it is updated on t he active edge of BRCLK.

After a reset, BRCLK is configured as an input.

PROPRIETARY AND CONFIDENTIAL

21

STANDARD PRODUCT

DATA SHEET PMC-1970624 ISSUE 10 COMBINED E1/T1 TRANSCEIVER

PM4351 COMET

Pin No.Pin Name Type

Function

-RI -NI

BRFP I/O 49 F6 Backplane Receive Frame Puls e (BRFP). When BRFP is c onf i gured as an

output, it indicates t he frame alignment of BRP CM and BRS IG. BRFP is generated on the active edge of BRCLK.

T1 mode: If basic frame ali gnment is desired, BRFP pulses high for one BRCLK cycle

during bit 1 of each 193-bit fram e. Optionally, BRFP may pulse high every second frame to ease t he i dent i fication of data link bits. I f superframe alignment is desired, B RFP pulses high for one BRCLK cycle during bit 1 of frame 1 of every 12-frame or 24-frame superframe. Optional l y, BRFP may pulse high every second superframe to ease the conversion between SF and ESF.

E1 mode: If basic frame ali gnment is desired, BRFP pulses high for one BRCLK cycle

during bit 1 of each 256-bit fram e. Optionally, BRFP may pulse high every second frame to ease t he i dentification of NFAS frames. If multiframe alignment is desired, B RFP transitions high to mark bit 1 of frame 1 of every 16-frame signaling mul tiframe and transitions low following bit 1 of frame 1 of every 16-frame CRC multiframe. Note that if the signaling and CRC multiframe ali gnments are coincident, BRFP puls es high for one BRCLK cycle every 16 frames.

BRPCM Output

with Tristate

When BRFP is confi gured as an input, it is used to frame align the receive data to the backplane frame al i gnment. When f rame alignment is required, a pul se at least one BRCLK cycle wide m ust be provided on BRFP a maximum of once every frame (193 bit periods in T1 mode or 256 bit periods in E1 mode). BRFP is sampled on the active edge of BRCLK.

After a reset, BRFP is configured as an input.

51 E9 B ackplane Receive PCM Data (BRPCM). BRPCM contains the recovered data

stream passed through the elastic store, signali ng extrac tor and per-DS0 serial controller. When the receive elasti c store is not bypassed, the B RPCM stream is aligned to the backplane i nput timing. When BRCLK is either 4.096 MHz,

8.192 MHz or 16.384 MHz, BRPCM can be tristated and is onl y active during programmable tim eslots. This allows byte interleaving of PCM data streams from up to 4 COMET devices with no external logic.

After a reset, BRPCM is high impedance. BRPCM is updated on the active edge of BRCLK.

PROPRIETARY AND CONFIDENTIAL

22

STANDARD PRODUCT

DATA SHEET PMC-1970624 ISSUE 10 COMBINED E1/T1 TRANSCEIVER

PM4351 COMET

Pin No.Pin Name Type

Function

-RI -NI

BRSIG Output

with Tristate

50 F7 Backplane Receive Si gnal i ng (BRSIG). BRSIG contains t he extracted

signaling bits for each channel i n the frame, repeated for the enti re superframe. Each channel's signali ng bi ts are val i d i n bi t locations 5, 6, 7 and 8 of t he channel and are channel-aligned with the BRPCM data stream. When the RXELST is not by-passed, the BRSI G stream is aligned to the backplane input timing. When BRCLK is either 4.096 MHz, 8. 192 MHz or 16.384 MHz, B RSIG can be tristated and is only active during programmable timeslots to allow byte interleaving of signaling data streams from up to 4 COMET devices with no external logic.

After a reset, BRSIG is hi gh i mpedance. BRSIG is updated on the acti ve edge of BRCLK.

Table 3 - Transmit Line Interface (6 pins)

TXTIP1 TXTIP2

Analog Output

Pin No.Pin Name Type

-RI -NI

7379D5A2Transmit Analog Positive Pulse (TXTIP1 and TXTIP2). When the t ransmit

Function

analog line interface is enabled, t he TXTIP1 and TXTIP2 analog outputs drive the transmit line pul se signal through an external matching transformer. Both TXTIP1 and TXTIP2 are normally connected to the positive lead of the transformer primary. Two outputs are provided for better signal integrity and should be shorted together on the board.

TXRING1 TXRING2

Analog Output

TDAT Digital

Output

After a reset, TXTIP1 and TXTIP2 are high impedance. The HIGHZ bit of the XLPG Line Driver Configuration register (address 0F0H) must be programmed to logic 0 to remove the high i mpedance state.

7280C5C4Transmit Analog Negative Pulse (TXRING1 and TXRING2). When the transmit

analog line interface is enabled, the TXRING1 and TXRING2 analog outputs drive the transmit line pul se signal through an external matching transformer. Both TXRING1 and TXRING2 are normally connected to the negative lead of the transformer primary. Two outputs are provided for better signal integrity and should be shorted together on the board.

After a reset, TXRING1 and TXRING2 are high impedance. The HIGHZ bit of the XLPG Line Driver Configuration register (address 0F0H) must be programmed to logic 0 t o remove the high impedance stat e.

6 C2 Transmit Digital PCM Data (TDAT). When the transmi t digital line interface is

enabled, the TDAT output provides the line side NRZ PCM transmit data. This mode may be used in applic ations not requiring a physical T1/E1 in t erface (e.g. interfacing to HDSL transceivers). TDAT is updated on the either the rising or falling (default) edge of TCLKO.

PROPRIETARY AND CONFIDENTIAL

23

STANDARD PRODUCT

DATA SHEET PMC-1970624 ISSUE 10 COMBINED E1/T1 TRANSCEIVER

PM4351 COMET

TFP Digital

Output

Pin No.Pin Name Type

-RI -NI

7 D1 Transmit Digital Frame Pulse (TFP). When the transmit digital line interf ace is

Function

enabled, the TFP output indicates frame alignment of the line s i de t ransmitted PCM stream (TDAT). This mode may be used in applicati ons not requiring a physical T1/E1 interface (e.g. i nterfacing to HDSL transceivers). TFP is updated on the either the rising or falling (default) edge of TCLKO.

Table 4 - Receive Line Interface (4 pins)

Pin No.Pin Name Type

-RI -NI

RXTIP Analog

Input

RXRING Analog

Input

RDAT I nput 57 E8 Receive Digital Line Data (RDAT). When the digi tal receive interface is

63 C7 Receive Analog Positive Pulse (RXTIP). When the analog receive line

64 A8 Rec ei ve Analog Negative Pulse (RXRING). When the analog receive line

Function

interface is enabled, RXTIP sampl es the received line pulse signal f rom an external isolation transform er. RXTIP is normally connect ed di rectly to the positive lead of the receive transformer secondary.

interface is enabled, RXRING samples the received line pulse s i gnal from an external isolation transformer. RXRING is normally connected directly to the negative lead of the receive transformer secondary.

enabled, the RDAT input samples the line side recovered NRZ PCM data stream. This mode may be used in applications not requi ri ng a physical T1/E1 interface (e.g. interf acing to HDSL transceivers). In digital mode, clock and data recovery is disabled. RDAT is sampled on the rising (default) or falling edge of RCLKI.

RCLKI Input 56 D9 Receive Digital Line Clock (RCLKI). When the digital receive li ne i n t erface is

Table 5 - Timing Options Control (5 pins)

PIO I/O 59 B9 Program mable I/O. PIO is an i nput/output pin controlled by a COMET register

PROPRIETARY AND CONFIDENTIAL

Pin No.Pin Name Type

-RI -NI

enabled, the externally recovered line rate clock must be provided on RCLKI. This mode may be used in appl i cations not requiring a physical T1/E 1 i nterface (e.g. interfacing to HDS L transce i vers ). RCLKI samples the receive PCM stream (RDAT) on its rising (default) or falling edge.

Function

bit. As an output, the PIO bit can, under software control, be used to configure external circuitry dependent upon the m ode of the COMET device. As an input, the state of the PIO pin can be read via a register bit.

24

STANDARD PRODUCT

DATA SHEET PMC-1970624 ISSUE 10 COMBINED E1/T1 TRANSCEIVER

PM4351 COMET

Pin No.Pin Name Type

Function

-RI -NI

TCLKO Output 5 C1 Transmit Cl ock Output (TCLKO). TCLKO is a clock at the transmit line rate

and may be used by external circuits as a transmit clock reference. When t h e digital transmit line interface is enabled, TDAT and TFP are updated on the either the rising or falling (defaul t) edge of TCLKO.

RSYNC Output 55 C9 Recovered Clock Synchronization Si gnal (RSYNC). This output signal is the

dejittered recovered receiver line rate clock (1.544 or 2.048 MHz) or, optionally, the recovered clock sync hronously divided by 193 (T1 mode) or 256 (E1 mode) to create a 8 kHz timi ng reference signal. When 8 kHz, the RSYNC phase is independent of frame alignment and is not affected by framing events.

When the COMET is in a los s of signal state, RSYNC i s derived from the XCLK input or, optionally, is held high.

TCLKI Input 4 B1 Transmit Clock Reference (TCLKI). TCLKI m ay be used as a reference for the

transmit line rat e generat ion. TCLKI may be any multip l e of 8 kHz (N x 8 kHz, where 1≤N≤256) so long as TCLKI has minim al j i tter when divided down to 8 kHz. When the TCLKI frequency differs from the t ransmit line rate, the transmit jitt er attenuation block (TJAT) must be enabled to attenuat e j i t ter on the transmit cl ock in accordance with AT&T TR-62411 and ETS 300 011. When the TCLKI frequency is the same as the transmit l i ne rate, TCLKI is optionally jitter attenuated by the TJAT in accordance with AT&T TR-62411 and ETS 300

011. When TCLKI jitter attenuation is enabled, the TCLKI frequency should be programmed into the TJAT Jitter Attenuation Divider N1 Control register.

The COMET may be configured to ignore the TCLKI input and utilize BTCLK or the receive recovered clock i nstead.

XCLK /

Input 3 C3 Crystal Clock Input (XCLK). This signal provides a stable, global t i ming

reference for the COMET internal circ uitry via an internal clock synthesizer. XCLK is a nominally jitter-free 50% duty cycle clock at 1.544 MHz in T1 mode and 2.048 MHz in E1 mode.

In T1 mode, a 2.048 MHz clock may be used as a reference. When used in this way, however, the intrinsic jitter s pecifications to AT&T TR62411 may not be met.

VCLK

Vector Clock (VCLK). The VCLK signal is used duri ng COMET production test to verify internal functi onal i ty.

Table 6 - Analog Support Circuitry (4 pins)

ATB Analog

I/O

Pin No.Pin Name Type

-RI -NI

68 B6 Anal og Test Bus (ATB). Reserved for COMET production test. This pin must

Function

be connected to an analog ground for normal operation.

PROPRIETARY AND CONFIDENTIAL

25

STANDARD PRODUCT

DATA SHEET PMC-1970624 ISSUE 10 COMBINED E1/T1 TRANSCEIVER

PM4351 COMET

Pin No.Pin Name Type

-RI -NI

TVREF Analog

I/O

RVREF Analog

I/O

TRIMF Input 58 C8 Trim Fuse. This pi n i s reserved for production purposes. The TRIMF signal is

76 A4 Transmi t Voltage Reference (TVREF). This pin is reserved for a precisi on

60 D7 Receive Voltage Reference (RVREF). This pin is reserved for a prec i sion

Function

analog voltage or current reference.

analog voltage or current reference. This pin m ust be connected to an external RC network consisting of a 100 kohm resistor connect ed i n parallel with a 10 nF capacitor to analog ground.

used during COMET production test to c ont rol the trimming of f uses. This pin must be tied low for normal operation.

Table 7 - JTAG (IEEE 1149.1) Boundary Scan Test Interface (5 pins)

Pin No.Pin Name Type

-RI -NI

TCK Input 16 F1 Test Clock (TCK). The test clock (TCK) signal provides timing for test

TMS Input 17 E2 Test Mode Select (TMS). The test mode select (TMS) signal cont rol s the test

Function

operations that are carried out us i ng the IEEE P1149.1 test access port.

operations that are carried out usi ng the IEEE P1149.1 test access port. TMS is sampled on the risi ng edge of TCK. TMS has an integral pull-up resistor.

TDI I nput 18 G2 Test Data Input (TDI). The test data input (TDI) signal c arri es test data into the

COMET via the IEEE P1149.1 test access port. TDI is sampled on the rising edge of TCK. TDI has an integral pull-up resist or.

TDO Output

with Tristate

TRSTB Input 20 F3 Active Low Test Reset (TRSTB). The test reset (TRSTB) signal provides an

19 H1 Test Data Output (TDO). The test data output (TDO) signal carries test data

out of the COMET via the IEEE P1149.1 test access port. TDO is updated on the falling edge of TCK. TDO is a tristate out put which i s tristated except when scanning of data is in progress.

asynchronous COMET test access port reset via the IEEE P1149.1 test access port. TRSTB is a Schm i tt triggered input with an integral pull-up resi stor.

The JTAG TAP controller must be initialized when the COMET is powered up. If the JTAG port is not used, TRSTB should be connected to the RSTB input.

Table 8 - Microprocessor Interface (23 pins)

Pin No.Pin Name Type

-RI -NI

CSB Input 21 J1 Active Low Chip Select (CS B). CSB must be low to enable COMET register

Function

accesses. CSB must go high at least once after power up to clear internal test modes. If CSB i s not used, it should be tied to an inverted version of RSTB, in which case, RDB and WRB determine register ac cesses.

PROPRIETARY AND CONFIDENTIAL

26

STANDARD PRODUCT

DATA SHEET PMC-1970624 ISSUE 10 COMBINED E1/T1 TRANSCEIVER

PM4351 COMET

Pin No.Pin Name Type

Function

-RI -NI

RDB Input 23 G3 Active Low Read Enable (RDB). RDB i s pulsed low to enable a COMET

register read access. The COMET drives the D[7:0] bus with the contents of the addressed register while RDB and CSB are bot h l ow.

WRB Input 24 J2 Active Low Write Strobe (WRB). WRB i s pulsed low to enable a COMET

register write access. The D[7: 0] bus contents are clocked int o the addressed normal mode register on t he ri sing edge of WRB while CSB i s low.

ALE Input 45 G9 Address Latch Enable (ALE). This signal l atches the address bus contents,

A[8:0], when low, allowing the COMET to be interfaced to a multiplexed

address/data bus. When ALE is high, the address latches are trans parent. D[0] D[1] D[2] D[3] D[4] D[5] D[6] D[7]

I/O 26

27 28 29 32 33 34 35

H3

Bi-directional Data Bus (D[7: 0]). This bus is used during read and write

accesses to internal COMET registers.

J4 H4 F4 G5 F5 H6

J7

A[0] A[1] A[2] A[3] A[4] A[5] A[6] A[7] A[8]

Input 36

37 38 39 40 41 42 43 44

J6

Address bus (A[8:0] ). This bus selects speci fic registers during COMET register accesses.

H5 H7

J8 G6

J9 H8 G7 H9

RSTB Input 22 H2 Active Low Reset (RSTB). When forced low, RSTB will asynchronously reset

the COMET. RSTB is a Schmitt-trigger input with integral pul l -up. When resetting the device, RSTB must be asserted f or a minimum of 100 ns to ensure that the COMET is compl etely reset.

INTB OD

Output

25 J3 Act i ve Low Open-drain Int errupt (INTB). INTB drives low when an unmasked

interrupt event is detect ed on any of the internal interrupt source s. Note that INTB will remain low until all active, unmasked interrupt sources are acknowledged at their source at which time, INTB will tristate.

PROPRIETARY AND CONFIDENTIAL

27

STANDARD PRODUCT

DATA SHEET PMC-1970624 ISSUE 10 COMBINED E1/T1 TRANSCEIVER

PM4351 COMET

Table 9 - Power and Ground (25 pins)

Pin No.Pin Name Type

Function

-RI -NI

VDDO1 VDDO2 VDDO3 VSSO1 VSSO2 VSSO3 VDDI1 VDDI2 VSSI1 VSSI2

Power 53

Ground 52

30

31

D2

Output Power Pins (VDDO[3:1]). The output power pins should be connected

8

to a well-decoupled +3.3 V DC supply in common with VDDI.

E6 G4 D4

Output Ground Pins (VSSO[3:1]). The output ground pins should be

9

connected to GND in common with VSSI.

E7

J5

Power 4814F2F8Internal Power Pins (VDDI[2: 1]). The internal power pins should be connected

to a well-decoupled +3.3 V DC supply in common with VDDO.

Ground 4715G1F9Internal Ground Pins (VSSI [2:1]). The internal ground pins shoul d be

connected to GND in common with VSSO.

BIAS Input 46 G8 +5 V Bias (B I AS). The BIAS input facilitates 5 V t olerance on the inputs. BIAS

must be connected t o a well-dec oupl ed +5 V rai l i f 5 V tolerant inputs are required. If 5 V tolerant inputs are not required, BIAS mus t be connected to a well-decoupled 3.3 V DC supply together with the power pins VDDO[3:1] and VDDI[3:1].

TAVD1 Analog

Power

1 A1 Transmit Analog Power (TAVD1). TAVD1 provides power for the transm i t LIU

reference circuitry. TAVD1 should be connected to analog +3.3 V. TAVD2 TAVD3

Analog Power

TAVD4 Analog

Power

TAVS1 Analog

Ground TAVS2 TAVS3

Analog

Ground

TAVS4 Analog

Ground RAVD1 Analog

Power RAVD2 Analog

Power RAVS1 Analog

Ground

7477B4B5Transmit Analog Power (TAVD2, TAVD3). TAVD2 and TAVD3 supply power for

the transmit LIU out put drivers. TAVD2 and TAVD3 should be connected to analog +3.3 V.

71 A5 Transm i t Analog Power (TAVD4). TAVD4 supplies power for the transmit cl ock

synthesis unit. TAVD4 should be connected to analog +3.3 V.

2 B2 Transmit Analog Ground (TAVS1). TAVS1 provides ground for the transmit LIU

reference circuitry. TAVS1 should be connected to analog GND.

7578A3B3Transmit Analog Ground (TAVS2A, TAVD2B). TAVS2A and TAVS2B supply

ground for the transmit LI U output drivers. TAVS2A and TAVS2B should be connected to analog GND.

70 C6 Transmit Analog Ground (TAVS4). TAVS supplies ground for the transmit clock

synthesis unit. TAVS4 should be connected to analog GND.

61 A9 Rec ei ve Analog Power (RAVD1). RAVD1 supplies power for the recei ve LI U

input equalizer. RAVD1 should be connected to analog +3.3 V.

65 A7 Rec ei ve Analog Power (RAVD2). RAVD2 supplies power for the recei ve LI U

peak detect and slicer. RAVD2 should be connected to analog +3.3 V.

62 B8 Rec ei ve Analog Ground (RAVS1). RAVS1 supplies power for the receive LIU

input equalizer. RAVS1 should be connected t o anal og GND.

PROPRIETARY AND CONFIDENTIAL

28

STANDARD PRODUCT

DATA SHEET PMC-1970624 ISSUE 10 COMBINED E1/T1 TRANSCEIVER

PM4351 COMET

RAVS2 Analog

Ground QAVD Analog

Power QAVS Analog

Ground

Pin No.Pin Name Type

Function

-RI -NI

66 B7 Rec ei ve Analog Ground (RAVS2). RAVS2 supplies power for the receive LIU

peak detect and slicer. RAVS2 should be connected to analog GND.

67 A6 Quiet Analog Power (QAVD). QAVD supplies power for the core analog

circuitry. QAVD should be connected to analog +3.3 V.

69 D6 Quiet Analog Ground (QAVS). QAVS supplies ground for the core analog

circuitry. QAVS should be connected t o anal og GND.

PROPRIETARY AND CONFIDENTIAL

29

STANDARD PRODUCT

DATA SHEET PMC-1970624 ISSUE 10 COMBINED E1/T1 TRANSCEIVER

PM4351 COMET

Table 10 - PM4351-RI Pin Summary

Function Pins

Backplane Transmit Interface 4 pins Backplane Receive Interface 4 pins Transmit Line Interface 6 pins Receive Line Interface 4 pins Timing Options Control 5 pins Analog Support Circuitry 4 pins JTAG (IEEE 1149.1) Boundary Scan Test Interface 5 pins Microprocessor Interface 23 pins Power and Ground 25 pins Total Functions Pins 80 pins Total 80 pins

Table 11 PM4351-NI Pin Summary

Function Pins

Backplane Transmit Interface 4 pins Backplane Receive Interface 4 pins Transmit Line Interface 6 pins Receive Line Interface 4 pins Timing Options Control 5 pins Analog Support Circuitry 4 pins JTAG (IEEE 1149.1) Boundary Scan Test Interface 5 pins Microprocessor Interface 23 pins Power and Ground 25 pins Total Functions Pins 80 pins Unused Pins 1 pin Total 81 pins

Notes on Pin Description:

PROPRIETARY AND CONFIDENTIAL

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STANDARD PRODUCT

DATA SHEET PMC-1970624 ISSUE 10 COMBINED E1/T1 TRANSCEIVER

PM4351 COMET

1. All COMET digital inputs and bi-directional pins present minimum capacitive loading and operate at TTL logic levels.

2. All COMET digital outputs and bi-directional pins have at least 2 mA drive capability. The BTCLK and BRCLK outputs, have 6 mA drive capability. The transmit analog outputs (TXTIP and TXRING) have built-in short circuit current limiting.

3. Inputs RSTB, TMS, TDI and TRSTB have internal pull-up resistors.

4. The VSSI and VSSO ground pins are not internally connected together. Failure to connect these pins externally may cause malfunction or damage the COMET.

5. The VDDI and VDDO power pins are not internally connected together. Failure to connect these pins externally may cause malfunction or damage the COMET.

6. The recommended power supply sequencing is as follows: a) During power-up, the voltage on the BIAS pin must be kept equal to or

greater than the voltage on the VDDO3, VDDO2, VDDO1, VDDI2 and VDDI1 pins, to avoid damage to the device.

b) VDDI power must be supplied either before VDDO or simultaneously with VDDO. Connection of VDDI and VDDO to a common VDD power plane is recommended.

c) The VDDI power must be applied before input pins are driven or the input current per pin be limited to less than the maximum DC input current specification (20 mA).

d) Analog power supplies (TAVD1, TAVD2, TAVD3, TAVD4, RAVD1, RAVD2, QAVD) must be applied after both VDDI and VDDO have been applied or they must be current limited to the maximum latch-up current specification (100 mA). In operation, the differential voltage measured between AVD supplies and VDDI must be less than 0.5 V. The relative power sequencing of the multiple AVD power supplies is not important.

e) Power down the device in the reverse sequence.

PROPRIETARY AND CONFIDENTIAL

31

STANDARD PRODUCT

DATA SHEET PMC-1970624 ISSUE 10 COMBINED E1/T1 TRANSCEIVER

PM4351 COMET

9 FUNCTIONAL DESCRIPTION

9.1 Receive Interface

Two basic receive options are available: the receive stream is presented as a TTL-compatible unipolar signal with an associated clock, or the receive data is reconstructed from unequalized pulses from a center tapped signal transformer. See Figure 5 for the recommended external analog circuitry.

When the digital receive interface is enabled, the RDAT signal is expected to carry a decoded serial bit stream. RDAT can be sampled on either the rising or falling RCLKI edge. The polarity of RDAT can also be inverted.

The analog receive interface is configurable to operate in both E1 and T1 shorthaul and long-haul applications. Short-haul T1 is defined as transmission over less than 655 ft of cable. Short-haul E1 is defined as transmission on any cable that attenuates the signal by less than 6 dB.

For long-haul signals, unequalized long- or short-haul bipolar alternate mark inversion (AMI) signals are received as the differential voltage between the RXTIP and RXRING inputs.

For short-haul, the slicing threshold is set to a fraction of the input signal’s peak amplitude, and adapts to changes in this amplitude. The slicing threshold is 67% and 50% for DSX-1 and E1 applications, respectively. Abnormally low input signals are detected when the input level is below 140 mV for E1 and 105 mV for T1.

PROPRIETARY AND CONFIDENTIAL

32

STANDARD PRODUCT

DATA SHEET PMC-1970624 ISSUE 10 COMBINED E1/T1 TRANSCEIVER

PM4351 COMET

Figure 5 - External Analog Interface Circuits

TXTIP1 TXTIP2

TVREF

TXRING1 TXRING2

ATB

RXTIP

RXRING

TXTIP1 TXTIP2

TVREF

TXRING1 TXRING2

ATB

RXTIP

RXRING

Figure 5 gives the recommended external protection circuitry for two cases:

PROPRIETARY AND CONFIDENTIAL

33

STANDARD PRODUCT

DATA SHEET PMC-1970624 ISSUE 10 COMBINED E1/T1 TRANSCEIVER

PM4351 COMET

1) for systems requiring phantom feed or inter-building line protection

2) for systems with no DC current requirements or intra-building line protection.

See Table 12 for the descriptions of components for Figure 5. See Table 14 for the descriptions of values for the transformer turns ratio, n, Rt1 and Rt2 for Figure 5.

Figure 5 assumes primary protectors (like carbon blocks) are also present. The protection resistors (PTCs) of 1Ω (but can be up to about 2Ω) are optional, but if not included then 1 to 2Ω resistor with a series fuse should be used instead.

Note that the crowbar devices (Z1 – Z4) are not required if the transformer’s isolation rating is not exceeded.

Table 12 - External Component Descriptions

Component Description Part # Source

Rt1 & Rt2

Typically 12.7Ω=±1% Resistors (see Table 14)

Rterm

18.2Ω=±1% Resistor for T1 & 120Ω E1

13Ω=±1% Resistor for 75Ω= E1 (assuming a 1:2.42 transformer)

C0 & C1

PTC1 – PTC4

4.7µF±10% Capacitors 1Ω Positive Temperature Coefficient

TC250-180 Raychem

R

TVS1 & TVS2 6V Bi-directional Transient Voltage

LC01-6 Semtech

Suppressor Diode

TVS2 & TVS3 6V Bi-directional Transient Voltage

LC03-6 Semtech

Suppressor Diode

D1 Surge Protector Diode Array SRDA3.3-4 Semtech

Z1 – Z4 Bi-directional Transient Surge

SGT27B13 Harris

Suppressors

T1 & T2 Generally 1:2.42CT Transformers

(see Table 14)

50436 (single)

T1137 (dual)

TG23-1505NS

(single)

TG23-1505N1

(dual)

Midcom

Pulse

Halo Halo

PROPRIETARY AND CONFIDENTIAL

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STANDARD PRODUCT

DATA SHEET PMC-1970624 ISSUE 10 COMBINED E1/T1 TRANSCEIVER

PM4351 COMET

T3 & T4 Generally 1:2.42CT Transformers

with centre taps floating (see Table

14)

50436 (single)

T1137 (dual)

TG23-1505NS

(single)

TG23-1505N1

(dual)

Table 13 - Typical Input Return Loss at Receiver

Case n Rterm Typical IRL T1: Zo=100Ω E1: Zo=120Ω

E1: Zo=75Ω

1:2.42 1:2.42 1:2.42

18.2Ω=±1%

13.0Ω=±1%

30.2dB

24.4dB

43.3dB

Table 14 - Termination Resistors, Transformer Ratios and TRL

Case n Rt1 Rt2 Typical TRL

Midcom

Pulse

Halo Halo

SH T1: Zo=100Ω SH T1: Zo=100Ω

SH E1: Zo=120Ω

SH E1: Zo=75Ω

1

LH T1 LBO=0dB:= Zo=100Ω

LH T1 LBO=-7.5dB: Zo=100Ω

LH T1 LBO=-15dB: Zo=100Ω

LH T1 LBO=-22.5dB:= Zo=100Ω

1:2.42

12.7Ω=±1% 12.7Ω=±1%

1:2.42 0dB 1:2.42 1:2.42

1:2.42

1:2.42 1:2.42 1:2.42 1:2.42

12.7Ω=±1% 12.7Ω=±1%

12.7Ω=±1%

1

8.06Ω=±1%

12.7Ω=±1% 12.7Ω=±1%

Notes:

1) Headroom power is about 30% higher in this case.

9.2 Clock and Data Recovery (CDRC)

The Clock and Data Recovery function is provided by the Clock and Data Recovery (CDRC) block. The CDRC provides clock and PCM data recovery,

12.7Ω=±1%

8.06Ω=±1%

14.1dB

19.4dB

9.6dB

18.8dB

14.1dB

PROPRIETARY AND CONFIDENTIAL

35

STANDARD PRODUCT

DATA SHEET PMC-1970624 ISSUE 10 COMBINED E1/T1 TRANSCEIVER

PM4351 COMET

B8ZS and HDB3 decoding, line code violation detection, and loss of signal detection. It recovers the clock from the incoming RZ data pulses using a digital phase-locked-loop and reconstructs the NRZ data. Loss of signal is indicated after a programmable threshold of consecutive bit periods of the absence of pulses on both the positive and negative line pulse inputs and is cleared after the occurrence of a single line pulse. An alternate loss of signal indication is provided which is cleared upon meeting an 1-in-8 pulse density criteria for T1 and a 1-in-4 pulse density criteria for E1. If enabled, a microprocessor interrupt is generated when a loss of signal is detected and when the signal returns. A line code violation is defined as a bipolar violation (BPV) for AMI-coded signals, is defined as a BPV that is not part of a zero substitution code for B8ZS-coded signals, and is defined as a bipolar violation of the same polarity as the last bipolar violation for HDB3-coded signals.

In T1 mode, the input jitter tolerance of the COMET complies with the Bellcore Document TA-TSY-000170 and with the AT&T specification TR62411, as shown in Figure 6. The tolerance is measured with a QRSS sequence (220-1 with 14 zero restriction). The CDRC block provides two algorithms for clock recovery that result in differing jitter tolerance characteristics. The first algorithm (when the ALGSEL register bit is logic 0) provides good low frequency jitter tolerance, but the high frequency tolerance is close to the TR62411 limit. The second algorithm (when ALGSEL is logic 1) provides much better high frequency jitter tolerance at the expense of the low frequency tolerance; the low frequency tolerance of the second algorithm is approximately 80% that of the first algorithm.

PROPRIETARY AND CONFIDENTIAL

36

STANDARD PRODUCT

y

(kHz

)Log

DATA SHEET PMC-1970624 ISSUE 10 COMBINED E1/T1 TRANSCEIVER

PM4351 COMET

Figure 6 - T1 Jitter Tolerance

ALGSEL=1 at 772 kHz with 36 dB of attenuation

10

ALG SEL= 0 at 772 kHz with 36 dB of attenuation

Sine Wave

Jitter

Amplitude

P. to P. (UI)

Log Scale

1.0

0.3

0.2

0.1

0.310.30 Sine WaveJitter Frequenc

Bel lcore Spe c . AT &T Spec.

Scale

Acceptable Range

For E1 applications, the input jitter tolerance complies with the ITU-T Recommendation G.823 "The Control of Jitter and Wander Within Digital Networks Which are Based on the 2048 kbit/s Hierarchy." Figure 7 illustrates this specification and the performance of the phase-locked loop when the ALGSEL register bit is logic 0.

100101.0

PROPRIETARY AND CONFIDENTIAL

37

STANDARD PRODUCT

DATA SHEET PMC-1970624 ISSUE 10 COMBINED E1/T1 TRANSCEIVER

PM4351 COMET

Figure 7 - Compliance with ITU-T Specification G.823 for E1 Input Jitter

DPLL TOLERANCE

10

SINEWAVE

JITTER AMPLITUDE P. TO P. (UI) LOG SCALE

IN SPEC REGION

WITH AMI ENCODED

15

2 -1 PRBS

DPLL TOLERANCE WITH HDB3 ENCODED 2 -1 PRBS

15

1.5 1

0.2

0.1

9.3 T1 Framer

The T1 framing function is provided by the T1-FRMR block. This block searches for the framing bit position of SF, ESF, J1, T1DM or SLC®96 framing formats in the incoming recovered PCM stream. When searching for frame, the T1-FRMR examines each of the 193 (SF, T1DM or SLC®96) or each of 4*193 (ESF or J1) framing bit candidates concurrently.

The time required to find frame alignment to an error-free PCM stream containing randomly distributed channel data (i.e. each bit in the channel data has a 50% probability of being 1 or 0) is dependent upon the framing format. For standard superframe format (SF, also known as D4 format), the T1-FRMR block

REC. G823 JITTER TOLERANCE SPECIFICATION

34

2.4

1.8

10 10 10

SINEWAVE JITTER FREQUENCY, Hz - LOG SCALE

5

PROPRIETARY AND CONFIDENTIAL

38

STANDARD PRODUCT

DATA SHEET PMC-1970624 ISSUE 10 COMBINED E1/T1 TRANSCEIVER

PM4351 COMET

will determine frame alignment within 4.4 ms 99 times out of 100. For SLC®96 format, the T1-FRMR will determine frame alignment within 9.9 ms 99 times out of 100. For extended superframe format (ESF) and J1, the T1-FRMR will determine frame alignment within 15 ms 99 times out of 100. For T1DM format, the T1-FRMR will determine frame alignment within 1.125 ms 99 times out of

100. Once the T1-FRMR has found frame, the incoming PCM data is continuously

monitored for framing bit errors, bit error events (a framing bit error in SF or SLC®96, a framing bit error or sync bit error in T1DM, or a CRC-6 error in ESF and J1), and severe errored framing events. The T1-FRMR also detects loss of frame, based on a selectable ratio of framing bit errors.

The T1-FRMR extracts the Yellow alarm signal bits from the incoming PCM data stream in SF and SLC®96 framing formats, and extracts the Y-bit from the T1DM sync word in T1DM framing format. The T1-FRMR also extracts the SLC®96 data link in SLC®96 framing format (with external logic), extracts the facility data link bits in the ESF and J1 framing formats, and extracts the R-bit from the T1DM sync word in T1DM framing fo rmat.

The T1-FRMR can also be disabled to allow reception of unframed data.

9.4 E1 Framer

The E1 framing function is provided by the E1-FRMR block. The E1-FRMR block searches for basic frame alignment, CRC multiframe alignment, and channel associated signaling (CAS) multiframe alignment in the incoming recovered PCM stream.

Once the E1-FRMR has found basic (or FAS) frame alignment, the incoming PCM data stream is continuously monitored for FAS/NFAS framing bit errors. Framing bit errors are accumulated in the framing bit error counter contained in the PMON block. Once the E1-FRMR has found CRC multiframe alignment, the PCM data stream is continuously monitored for CRC multiframe alignment pattern errors, and CRC-4 errors. CRC-4 errors are accumulated in the CRC error counter of the PMON block. Once the E1-FRMR has found CAS multiframe alignment, the PCM data is continuously monitored for CAS multiframe alignment pattern errors. The E1-FRMR also detects and indicates loss of basic frame, loss of CRC multiframe, and loss of CAS multiframe, based on user-selectable criteria. The reframe operation can be initiated by software (via the E1-FRMR Frame Alignment Options Register), by excessive CRC errors, or when CRC multiframe alignment is not found within 400 ms. The E1-FRMR also identifies the position of the frame, the CAS multiframe, and the CRC multiframe.

PROPRIETARY AND CONFIDENTIAL

39

STANDARD PRODUCT

DATA SHEET PMC-1970624 ISSUE 10 COMBINED E1/T1 TRANSCEIVER

PM4351 COMET

The E1-FRMR extracts the contents of the International bits (from both the FAS frames and the NFAS frames), the National bits, and the Extra bits (from timeslot 16 of frame 0 of the CAS multiframe), and stores them in the E1-FRMR International/National Bits register and the E1-FRMR Extra Bits register. Moreover, the FRMR also extracts submultiframe-aligned 4-bit codewords from each of the National bit positions Sa4 to Sa8, and stores them in microprocessor-accessible registers that are updated every CRC submultiframe.

The E1-FRMR identifies the raw bit values for the Remote (or distant frame) Alarm (bit 3 in timeslot 0 of NFAS frames) and the Remote Signaling Multiframe (or distant multiframe) Alarm (bit 6 of timeslot 16 of frame 0 of the CAS multiframe) via the E1-FRMR International/National Bits Register, and the E1-FRMR Extra Bits Register respectively. Access is also provided to the "debounced" remote alarm and remote signaling multiframe alarm bits which are set when the corresponding signals have been a logic 1 for 2 or 3 consecutive occurrences, as per Recommendation O.162. Detection of AIS and timeslot 16 AIS are provided. AIS is also integrated, and an AIS Alarm is indicated if the AIS condition has persisted for at least 100 ms. The out of frame (OOF=1) condition is also integrated, indicating a Red Alarm if the OOF condition has persisted for at least 100 ms.

An interrupt may be generated to signal a change in the state of any status bits (OOF, OOSMF, OOCMF, AIS or RED), and to signal when any event (RAI, RMAI, AISD, COFA, FER, SMFER, CMFER, CRCE or FEBE) has occurred. Additionally, interrupts may be generated every frame, CRC submultiframe, CRC multiframe or signaling multiframe.

Basic Frame Alignment Procedure

The E1-FRMR searches for basic frame alignment using the algorithm defined in ITU-T Recommendation G.706 sections 4.1.2 and 4.2.

The algorithm finds frame alignment by using the following sequence:

1. Search for the presence of the correct 7-bit FAS (‘0011011’);

2. Check that the FAS is absent in the following frame by verifying that bit 2 of the assumed non-frame alignment sequence (NFAS) TS 0 byte is a logic 1;

3. Check that the correct 7-bit FAS is present in the assumed TS 0 byte of the next frame.

If either of the conditions in steps 2 or 3 are not met, a new search for frame alignment is initiated in the bit immediately following the second 7-bit FAS sequence check. This "hold-off" is done to ensure that new frame alignment

PROPRIETARY AND CONFIDENTIAL

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STANDARD PRODUCT

DATA SHEET PMC-1970624 ISSUE 10 COMBINED E1/T1 TRANSCEIVER

PM4351 COMET

searches are done in the next bit position, modulo 512. This facilitates the discovery of the correct frame alignment, even in the presence of fixed timeslot data imitating the FAS.

These algorithms provide robust framing operation even in the presence of random bit errors: framing with algorithm #1 or #2 provides a 99.98% probability of finding frame alignment within 1 ms in the presence of 10

-3

bit error rate and

no mimic patterns. Once frame alignment is found, the block sets the OOF indication low, indicates

a change of frame alignment (if it occurred), and monitors the frame alignment signal, indicating errors occurring in the 7-bit FAS pattern and in bit 2 of NFAS frames, and indicating the debounced value of the Remote Alarm bit (bit 3 of NFAS frames). Using debounce, the Remote Alarm bit has <0.00001% probability of being falsely indicated in the presence of a 10

-3

bit error rate. The block declares loss of frame alignment if 3 consecutive FASs have been received in error or, additionally, if bit 2 of NFAS frames has been in error for 3 consecutive occasions. In the presence of a random 10

-3

bit error rate the frame

loss criteria provides a mean time to falsely lose frame alignment of >12 minutes. The E1-FRMR can be forced to initiate a basic frame search at any time when

any of the following conditions are met:

• the software re-frame bit in the E1-FRMR Frame Alignment Options register

goes to logic 1;

• the CRC Frame Find Block is unable to find CRC multiframe alignment; or

• the CRC Frame Find Block accumulates excessive CRC evaluation errors

≥ 915 CRC errors in 1 second) and is enabled to force a re-frame under that

( condition.

CRC Multiframe Alignment Procedure

The E1-FRMR searches for CRC multiframe alignment by observing whether the International bits (bit 1 of TS 0) of NFAS frames follow the CRC multiframe alignment pattern. Multiframe alignment is declared if at least two valid CRC multiframe alignment signals are observed within 8 ms, with the time separating two alignment signals being a multiple of 2 ms

Once CRC multiframe alignment is found, the OOCMFV register bit is set to logic 0, and the E1-FRMR monitors the multiframe alignment signal, indicating errors occurring in the 6-bit MFAS pattern, errors occurring in the received CRC and the value of the FEBE bits (bit 1 of frames 13 and 15 of the multiframe). The E1-FRMR declares loss of CRC multifram e alignment if ba s ic frame

PROPRIETARY AND CONFIDENTIAL

41

STANDARD PRODUCT

DATA SHEET PMC-1970624 ISSUE 10 COMBINED E1/T1 TRANSCEIVER

PM4351 COMET

alignment is lost. However, once CRC multiframe alignment is found, it cannot be lost due to errors in the 6-bit MFAS pattern.

Under the CRC-to-non-CRC interworking algorithm, if the E1-FRMR can achieve basic frame alignment with respect to the incoming PCM data stream, but is unable to achieve CRC-4 multiframe alignment within the subsequent 400 ms, the distant end is assumed is assumed to be a non CRC-4 interface. The details of this algorithm are illustrated in the state diagram in Figure 8.

PROPRIETARY AND CONFIDENTIAL

42

STANDARD PRODUCT

(Op

g)

DATA SHEET PMC-1970624 ISSUE 10 COMBINED E1/T1 TRANSCEIVER

PM4351 COMET

Figure 8 - CRC Multiframe Alignment Algorithm

Out of Frame

3 consecutive FASor NF A S errors; manual refram e; or excessive CRC errors

FAS_Find_1

FAS found

NFAS_Find

NFAS found next frame

FAS_Find_2

FAS found next fra m e

CRCMFA

NFAS not found next fra m e

FAS not found next frame

Start 400ms timer and 8m s timer

BFA

8ms expire

8m s expire and NOT( 400m s expire)

Reset BFA to most recently found alignment

FAS_Find_1_Par

FAS found

NFAS_Find_Par

NFAS found next frame

FAS_Find_2_Par

FAS found next frame

BFA_Par

CRCMFA_Par

NFAS not found next frame

FAS not found next fra m e

Star t 8 ms ti mer

400m s expire

CRC to CRC Interworking

PROPRIETARY AND CONFIDENTIAL

CRCM FA_Par

tional settin

CRC to non-C RC Interworking

43

STANDARD PRODUCT

DATA SHEET PMC-1970624 ISSUE 10 COMBINED E1/T1 TRANSCEIVER

PM4351 COMET

Table 15 - E1-FRMR Framing States

State Out of Frame Out of Offline Frame

FAS_Find_1 Yes No NFAS_Find Yes No FAS_Find_2 Yes No BFA No No CRC to CRC Interworking No No FAS_Find_1_Par No Yes NFAS_Find_Par No Yes FAS_Find_2_Par No Yes BFA_Par No No CRC to non-CRC Interworking No No

The states of the primary basic framer and the parallel/offline framer in the E1-FRMR block at each stage of the CRC multiframe alignment algorithm are shown in Table 15.

From an out of frame state, the E1-FRMR attempts to find basic frame alignment in accordance with the FAS/NFAS/FAS G.706 Basic Frame Alignment procedure outlined above. Upon achieving basic frame alignment, a 400 ms timer is started, as well as an 8 ms timer. If two CRC multiframe alignment signals separated by a multiple of 2 ms are observed before the 8 ms timer has expired, CRC multiframe alignment is declared.

If the 8 ms timer expires without achieving multiframe alignment, a new offline search for basic frame alignment is initiated. This search is performed in accordance with the Basic Frame Alignment procedure outlined above. However, this search does not immediately change the actual basic frame alignment of the system (i.e., PCM data continues to be processed in accordance with the first basic frame alignment found after an out of frame state while this frame alignment search occurs as a parallel operation).

When a new basic frame alignment is found by this offline search, the 8 ms timer is restarted. If two CRC multifram e alignment signals separate d by a multiple of 2 ms are observed before the 8 ms timer has expired, CRC multiframe a lignment

PROPRIETARY AND CONFIDENTIAL

44

STANDARD PRODUCT

DATA SHEET PMC-1970624 ISSUE 10 COMBINED E1/T1 TRANSCEIVER

PM4351 COMET

is declared and the basic frame alignment is set accordingly (i.e., the basic frame alignment is set to correspond to the frame alignment found by the parallel offline search, which is also the basic frame alignment corresponding to the newly found CRC multiframe alignment).

Subsequent expirations of the 8 ms timer will likewise reinitiate a new search for basic frame alignment. If, however, the 400 ms timer expires at any time during this procedure, the E1-FRMR stops searching for CRC multiframe alignment and declares CRC-to-non-CRC interworking. In this mode, the E1-FRMR may be optionally set to either halt searchin g for CRC multiframe a lto gether, or may continue searching for CRC multiframe alignment using the established basic frame alignment. In either case, no further adjustments are made to the basic frame alignment, and no offline searches for basic frame alignment occur once CRC-to-non-CRC interworking is declared: it is assumed that the established basic frame alignment at this point is correct.

AIS Detection

When an unframed all-ones receive data stream is received, an AIS defect is indicated by setting the AISD bit to logic 1 when fewer than three zero bits are received in 512 consecutive bits or, optionally, in each of two consecutive periods of 512 bits. The AISD bit is reset to logic 0 when three or more zeros in 512 consecutive bits or in each of two consecutive periods of 512 bits. Finding frame alignment will also cause the AISD bit to be set to logic 0.

Signaling Frame Alignment

Once the basic frame alignment has been found, the E1-FRMR searches for Channel Associated Signaling (CAS) multiframe alignment using the following G.732 compliant algorithm: signaling multiframe alignment is declared when at least one non-zero time slot 16 bit is observed to precede a time slot 16 containing the correct CAS alignment pattern, namely four zeros (“0000”) in the first four bit positions of timeslot 16.

Once signaling multiframe alignment has been found, the E1-FRMR sets the OOSMFV bit of the E1-FRMR Framing Status register to logic 0, and monitors the signaling multiframe alignment signal, indicating errors occurring in the 4-bit pattern, and indicating the debounced value of the Remote Signaling Multiframe Alarm bit (bit 6 of timeslot 16 of frame 0 of the multiframe). Using debounce, the Remote Signaling Multiframe Alarm bit has < 0.00001% probability of being falsely indicated in the presence of a 10

-3

bit error rate.

The block declares loss of CAS multiframe alignment if two consecutive CAS multiframe alignment signals have been received in error, or additionally, if all the bits in time slot 16 are logic 0 for 1 or 2 (selectable) CAS multiframes. Loss of

PROPRIETARY AND CONFIDENTIAL

45

STANDARD PRODUCT

DATA SHEET PMC-1970624 ISSUE 10 COMBINED E1/T1 TRANSCEIVER

PM4351 COMET

CAS multiframe alignment is also declared if basic frame alignment has been lost.

National Bit Extraction

The E1-FRMR extracts and assembles the submultiframe-aligned National bit codewords Sa4[1:4] , Sa5[1:4] , Sa6[1:4] , Sa7[1:4] and Sa8[1:4]. The corresponding register values are updated upon generation of the CRC submultiframe interrupt.

This E1-FRMR also detects the V5.2 link ID signal, which is defined as the condition where 2 out of 3 Sa7 bits are zeroes. Upon reception of this Link ID signal, the V52LINKV bit of the E1-FRMR Framing Status register is set to logic 1. This bit is cleared to logic 0 when 2 out of 3 Sa7 bits are ones.

Alarm Integration

The OOF and the AIS defects are integrated, verifying that each condition has persisted for 104 ms (± 6 ms) before indicating the alarm condition. The alarm is removed when the condition has been absent for 104 ms (± 6 ms).

The AIS alarm algorithm accumulates the occurrences of AISD (AIS detection). The E1-FRMR counts the occurrences of AISD over a 4 ms interval and indicates a valid AIS is present when 13 or more AISD indications (of a possible

16) have been received. Each interval with a valid AIS presence indication increments an interval counter which declares AIS Alarm when 25 valid intervals have been accumulated. An interval with no valid AIS presence indication decrements the interval counter. The AIS Alarm declaration is removed when the counter reaches 0. This algorithm provides a 99.8% probability of declaring an AIS Alarm within 104 ms in the presence of a 10

-3

mean bit error rate.

The Red alarm algorithm monitors occurrences of OOF over a 4 ms interval, indicating a valid OOF interval when one or more OOF indications occurred during the interval, and indicating a valid in frame (INF) interval when no OOF indication occurred for the entire interval. Each interval with a valid OOF indication increments an interval counter which declares Red Alarm when 25 valid intervals have been accumulated. An interval with valid INF indication decrements the interval counter; the Red Alarm declaration is removed when the counter reaches 0. This algorithm biases OOF occurrences, leading to declaration of Red alarm when intermittent loss of frame alignment occurs.

PROPRIETARY AND CONFIDENTIAL

46

STANDARD PRODUCT

DATA SHEET PMC-1970624 ISSUE 10 COMBINED E1/T1 TRANSCEIVER

PM4351 COMET

9.5 T1 Inband Loopback Code Detector (IBCD)

The T1 Inband Loopback Code Detection function is provided by the IBCD block. This block detects the presence of either of two programmable INBAND LOOPBACK ACTIVATE and DEACTIVATE code sequences in either framed or unframed data streams. Each INBAND LOOPBACK code sequence is defined as the repetition of the programmed code in the PCM stream for at least 5.1 seconds. The code sequence detection and timing is compatible with the specifications defined in T1.403-1993, TA-TSY-000312, and TR-TSY-000303. LOOPBACK ACTIVATE and DEACTIVATE code indication is provided through internal register bits. An interrupt is generated to indicate when either code status has changed.

9.6 T1 Pulse Density Violation Detector (PDVD)

The Pulse Density Violation Detection function is provided by the PDVD block. The block detects pulse density violations of the requirement that there be N ones in each and every time window of 8(N+1) data bits (where N can equal 1 through 23). The PDVD also detects periods of 16 consecutive zeros in the incoming data. Pulse density violation detection is provided through an internal register bit. An interrupt is generated to signal a 16 consecutive zero event, and/or a change of state on the pulse density violation indication.

The PDVD block is available when the analog RXTIP and RXRING inputs are enabled (i.e., when the RUNI bit in the Receive Line Interface Configuration register is logic 0).

9.7 Performance Monitor Counters (PMON)

The Performance Monitor Counters function is provided by the PMON block. The block accumulates CRC error events, Frame Synchronization bit error events, Line Code Violation events, and Out Of Frame events, or optionally, Change of Frame Alignment (COFA) events with saturating counters over consecutive intervals as defined by the period of the supplied transfer clock signal (typically 1 second). When the transfer clock signal is applied, the PMON transfers the counter values into holding registers and resets the counters to begin accumulating events for the interval. The counters are reset in such a manner that error events occurring during the reset are not missed. If the holding registers are not read between successive transfer clocks, an OVERRUN register bit is asserted.

For T1, a line code violation is either a bipolar violation (only those not part of a zero substitution code for B8ZS-coded and HDB3 signals) or excessive zeros. Excessive zeros is a sequence of zeros greater than 15 bits long for an AMI-code

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signal and greater than 7 bits long for a B8ZS-coded signals. The inclusion of excessive zeros in the line code violation count can be disabled.

For E1, a line code violation is defined as a bipolar violation (BPV) for AMI-coded signals and is defined as a bipolar violation of the same polarity as the last bipolar violation for HDB3-coded signals.

Generation of the transfer clock within the COMET chip is performed by writing to any counter register location or by writing to the Global PMON Update register. The holding register addresses are contiguous to facilitate faster polling operations.

9.8 T1 Bit Oriented Code Dete ctor (RBOC)

The Bit Oriented Code detection function is provided by the RBOC block. This block detects the presence of 63 of the possible 64 bit oriented codes transmitted in the Facility Data Link channel in ESF framing format, as defined in

ANSI T1.403-1993 and in TR-TSY - 000194. The 64th code (111111) is similar to the DL FLAG sequence and is used by the RBOC to indicate no valid code received.

Bit oriented codes are received on the Facility Data Link channel as a 16-bit sequence consisting of 8 ones, a zero, 6 code bits, and a trailing zero (111111110xxxxxx0) which is repeated at least 10 times. The RBOC can be enabled to declare a received code valid if it has been observed for 8 out of 10 times or for 4 out of 5 times, as specified by the AVC bit in the control register.

Valid BOC are indicated through an internal status register. The BOC bits are set to all ones (111111 ) if no valid code has been detected. An interrupt is generated to signal when a detected code has been validated, or optionally, when a valid code goes away (i.e. the BOC bits go to all ones).

9.9 HDLC Receiver (RDLC)

The HDLC Receiver function is provided by the RDLC block. The RDLC is a microprocessor peripheral used to receive HDLC frames. Three RDLC blocks are provided for flexible extraction of standardized data links:

• T1 ESF facility data link

• T1DM data link

• ISDN D-channel

• E1 Common Channel Signaling data link

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• V5.1/V5.2 D-channel and C-channels.

• E1 Sa-bit data link

The RDLC detects the change from flag characters to the first byte of data, removes stuffed zeros on the incoming data stream, receives packet data, and calculates the CRC-CCITT frame check sequence (FCS).

In the address matching mode, only those packets whose first data byte matches one of two programmable bytes or the universal address (all ones) are stored in the FIFO. The two least significant bits of the address comparison can be masked for LAPD SAPI matching.

Received data is placed into a 128-byte FIFO buffer. An interrupt is generated when a programmable number of bytes are stored in the FIFO buffer. Other sources of interrupt are detection of the terminating flag sequence, abort sequence, or FIFO buffer overrun.

The Status Register contains bits which indicate the overrun or empty FIFO status, the interrupt status, and the occurrence of first flag or end of message bytes written into the FIFO. The Status Register also indicates the abort, flag, and end of message status of the data just read from the FIFO. On end of message, the Status Register indicates the FCS status and if the packet contained a non-integer number of bytes.

9.10 T1 Alarm Integrator (ALMI)

The T1 Alarm Integration function is provided by the ALMI block. This block detects the presence of Yellow, Red, and AIS Carrier Fail Alarms (CFA) in SF, T1DM, SLC®96, or ESF formats. The alarm detection and integration is compatible with the specifications defined in Bell Pub 43801, TA-TSY-000278, TR-TSY-000008, ANSI T1.403-1993, and TR-TSY-000191. Alarm detection and validation for SLC®96 is handled the same as SF framing format.

The ALMI block declares the presence of Yellow alarm when the Yellow pattern has been received for 425 ms (± 50 ms); the Yellow alarm is removed when the Yellow pattern has been absent for 425 ms (± 50 ms). The presence of Red alarm is declared when an out-of-frame condition has been present for 2.55 sec (± 40 ms); the Red alarm is removed when the out-of-frame condition has been absent for 16.6 sec (± 500 ms). In T1DM framing format the Red alarm declaration criteria can be selected to be either 400 ms (± 100 ms) or 2.55 sec (± 40 ms); removal of the Red alarm in T1DM can be selected to be either 100 ms (± 50 ms) or 16.6 sec (± 500 ms). The presence of AIS alarm is declared when an out-of-frame condition and all-ones in the PCM data stream

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have been present for 1.5 sec (± 100 ms); the AIS alarm is removed when the AIS condition has been absent for 16.8 sec (± 500 ms).

CFA alarm detection algorithms operate in the presence of a random 10 error rate.

The ALMI also indicates the presence or absence of the Yellow, Red, and AIS alarm signal conditions over 40 ms , 40 ms and 60 ms intervals, respectively, allowing an external microprocessor to integrate the alarm conditions via software with any user-specific algorithms. Alarm indication is provided through internal register bits.

9.11 Receive Elastic Store (RX-ELST)

The Receive Elastic Store (RX-ELST) synchronizes incoming PCM frames to the local backplane clock, BRCLK. The frame data is buffered in a two-frame circular data buffer. Input data is written to the buffer using a write pointer and output data is read from the buffer using a read pointer.

When the elastic store is being used, if the average frequency of the incoming data is greater than the average frequency of the backplane clock, the write pointer will catch up to the read pointer and the buffer will be filled. Under this condition a controlled slip will occur when the read pointer crosses the next frame boundary. The following frame of PCM data will be deleted.

-3

bit

If the average frequency of the incoming data is less than the average frequency of the backplane clock, the read pointer will catch up to the write pointer and the buffer will be empty. Under this condition a controlled slip will occur when the read pointer crosses the next frame boundary. The last frame which was read will be repeated.

A slip operation is always performed on a frame boundary. When the backplane timing is derived from the receive line data (i.e. BRCLK is

an output), the elastic store can be bypassed to eliminate the two frame delay. In this configuration the elastic store can be used to measure frequency differences between the recovered line clock and another 1.544 MHz or

2.048 MHz clock applied to the BRCLK input. A typical example might be to measure the difference in frequency between two received streams (i.e. EastWest frequency difference) by monitoring the number of SLIP occurrences of one direction with respect to the other.

To allow for the extraction of signaling information in the PCM data channels, superframe identification is also passed through the RX-ELST.

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For payload conditioning, the RX-ELST may optionally insert a programmable idle code into all channels when the framer is out of frame synchronization. This code is set to all 1's when the RX-ELST is reset.

9.12 Receive Jitter Attenuator (RJAT)

The Receive Jitter Attenuator (RJAT) digital PLL attenuates the jitter present on the RXTIP/RXRING or RDAT inputs. The attenuation is only performed when the RJATBYP register bit is a logic 0.

The jitter characteristics of the Receive Jitter Attenuator (RJAT) are the same as the Transmit Jitter Attenuator (TJAT).

9.13 Signaling Extractor (SIGX)

The Signaling Extraction (SIGX) block provides channel associated signaling (CAS) extraction from an E1 signaling multiframe or from SF and ESF T1 formats. With external logic the Signaling Extraction (SIGX) block extracts the nine bit signaling format from SLC®96 T1 formats.

The SIGX block provides signaling bit extraction from the received data stream for T1 ESF, SF, SLC®96 and E1 framing formats. It selectively debounces the bits, and serializes the results onto the BRSIG output. Debouncing is performed on individual signaling bits. This BRSIG output is channel aligned with BRPCM output, and the signaling bits are repeated for the entire superframe, allowing downstream logic to reinsert signaling into any frame, as determined by system timing. The signaling data stream contains the A,B,C,D bits in the lower 4 channel bit locations (bits 5, 6, 7 and 8) in T1 ESF and E1 framing formats; in SF and SLC®96 formats the A and B bits are repeated in locations C and D (i.e. the signaling stream contains the bits ABAB for each channel).

The SIGX block contains three superframes worth of signal buffering to ensure that there is a greater than 95% probability that the signaling bits are frozen in the correct state for a 50% ones density out-of-frame condition, as specified in TR-TSY-000170 and BELL PUB 43801. With signaling debounce enabled, the per-channel signaling state must be in the same state for 2 superframes before appearing on the serial output stream.

The SIGX block provides one superframe or signaling-multiframe of signal freezing on the occurrence of slips. When a slip event occurs, the SIGX freezes the output signaling for the entire superframe in which the slip occurred; the signaling is unfrozen when the next slip-free superframe occurs.

The SIGX also provides control over timeslot signaling bit fixing, data inversion and signaling debounce on a per-timeslot basis.

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The SIGX block also provides an interrupt to indicate a change of signaling state on a per channel basis.

9.14 Receive Per-channel Serial Controller (RPSC)

The Receive Per-channel Serial Controller (RPSC) function is provided by a PCSC block.

The RPSC allows data and signaling trunk conditioning to be applied independently on the receive stream on a per-channel basis.

9.15 T1 Signaling Aligner (SIGA)

The T1 Signaling Aligner can be positioned before the T1 basic transmitter to provide superframe alignment of the signaling bits between the backplane and the transmit DS-1 stream. The signaling alignment block maintains signaling bit integrity across superframe boundaries.

9.16 T1 Basic Transmitter (XBAS)

The T1 Basic Transmitter (XBAS) block generates the 1.544 Mbit/s T1 data stream according to SF, ESF, T1DM or SLC®96 formats.

In concert with the Transmit Per-Channel Serial Controller (TPSC), the XBAS block provides per channel control of idle code substitution, data inversion (either all 8 bits, sign bit only or magnitude only), digital milliwatt substitution, and zero code suppression. Three types of zero code suppression (GTE, Bell and DDS) are supported and selected on a per channel basis to provide minimum ones density control. Robbed bit signaling control and selection of the signaling source are also performed on a per-channel basis. All channels can be forced into a trunk conditioning state (idle code substitution and signaling conditioning) by use of the Master Trunk Conditioning bit in the T1 XBAS Configuration Register.

A data link is provided for ESF, T1DM and SLC®96 modes. The data link sources include bit oriented codes and HDLC messages. Support is provided for the transmission of framed or unframed Inband Code sequences and transmission of AIS or Yellow alarm signals for all formats.

PCM output signals may be selected to conform to B8ZS or AMI line coding. The transmitter can be disabled for framing via the FDIS bit in the Transmit

Framing and Bypass Options register. When transmitting ESF formatted data, the framing bit, datalink bit, or the CRC-6 bit from the input PCM stream can be by-passed to the output PCM stream.

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9.17 E1 Transmitter (E1-TRAN)

The E1 Transmitter (E1-TRAN) generates a 2048 kbit/s data stream according to ITU-T recommendations, providing individual enables for frame generation, CRC multiframe generation, and channel associated signaling (CAS) multiframe generation.

In concert with Transmit Per-Channel Serial Controller (TPSC), the E1-TRAN block provides per-timeslot control of idle code substitution, data inversion, digital milliwatt substitution, selection of the signaling source and CAS data. All timeslots can be forced into a trunk conditioning state (idle code substitution and signaling substitution) by use of the master trunk conditioning bit in the Configuration Register.

Common Channel Signaling (CCS) is supported in time slot 16 either through the internal HDLC Transmitter (TDPR) and the Transmit Channel Insertion (TXCI) block. Support is provided for the transmission of AIS and the transmission of remote alarm (RAI) and remote multiframe alarm signals.

The National Use bits (Sa-bits) can be sourced from the E1-TRAN National Bits Codeword registers as 4-bit codewords aligned to the submultiframe. Alternatively, the Sa-bits may individually carry data links sourced from the internal HDLC controllers, or may be passed transparently from the BTPCM input.

PCM output signals may be selected to conform to HDB3 or AMI line coding.

9.18 Transmit Elastic Store (TX-ELST)

The Transmit Elastic Store (TX-ELST) provides the ability to decouple the line timing from the backplane timing. The TX-ELST is required whenever the BTCLK and TCLKO clocks are not traceable to a common source. The elastic store function is in effect (with a nominal one frame delay) when:

1. BTCLK is an input (CMODE = 1) and the transmitter is loop timed to the

receive recovered clock (PLLREF[1:0] = ‘b10, OCLKSEL1 = 0, OCLKSEL0 =

0).

2. BTCLK is an input (CMODE = 1) and the transmitter is clocked by TCLKI

(OCLKSEL1 = 0, OCLKSEL0 = 1) or a jitter attenuated version of TCLKI (PLLREF[1:0] = ‘b11, OCLKSEL1 = 0, OCLKSEL0 = 0).

3. BTCLK is an output (CMODE = 0) referenced to the receive recovered clock

(PLLREF[1:0] = ‘b10) and the transmitter is clocked by TCLKI (OCLKSEL1 = 0, OCLKSEL0 = 1).

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When the elastic store is being used, if the average frequency of the backplane data is greater than the average frequency of the line clock, the buffer will fill. Under this condition a controlled slip will occur upon the next frame boundary. The following frame of PCM data will be dele ted.

If the average frequency of the backplane data is less than the average frequency of the line clock, the buffer empty. Under this condition a controlled slip will occur upon the next frame boundary. The latest frame will be repeated.

A slip operation is always performed on a frame boundary. The TX-ELST is upstream of the frame overhead insertion; therefore, frame slips do not corrupt the frame alignment signal.

When the line timing is derived from BTCLK or BTCLK is an output, the elastic store is bypassed to eliminate the two frame delay.

9.19 Transmit Per-Channel Serial Controller (TPSC)

The Transmit Per-channel Serial Controller allows data and signaling trunk conditioning or idle code to be applied on the transmit DS-1 stream on a perchannel basis. It also allows per-channel control of zero code suppression, data inversion, and application of digital milliwatt.

The Transmit Per-channel Serial Controller function is provided by a PerChannel Serial Controller (PCSC) block. The PCSC is a general purpose triple serializer. Data is sourced from three banks of thirty-two 8-bit registers, with each bank supporting a single serial output.

The TPSC interfaces directly to the E1-TRAN and T1-XBAS blocks to provide serial streams for signaling control, idle code data and PCM data control.

The registers are accessible from the µP interface in an indirect address mode. The BUSY indication signal can be polled from an internal status register to check for completion of the current operation.

9.20 T1 Inband Loopback Code Generator (XIBC)

The T1 Inband Loopback Code Generator (XIBC) block generates a stream of inband loopback codes (IBC) to be inserted into a T1 data stream. The IBC stream consists of continuous repetitions of a specific code and can be either framed or unframed. When the XIBC is enabled to generate framed IBC, the framing bit overwrites the inband code pattern. The contents of the code and its length are programmable from 3 to 8 bits. The XIBC interfaces directly to the XBAS Basic Transmitter block.

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9.21 T1 Bit Oriented Code Generator (XBOC)

The T1 Bit Oriented Code Generator function is provided by the XBOC block. This block transmits 63 of the possible 64 bit oriented codes in the Facility Data

Link channel in ESF framing format, as defined in ANSI T1.403-1989. The 64

th

code (111111) is similar to the HDLC Flag sequence and is used in the XBOC to disable transmission of any bit oriented codes.

Bit oriented codes are transmitted on the Facility Data Link channel as a 16-bit sequence consisting of 8 ones, a zero, 6 code bits, and a trailing zero (111111110xxxxxx0) which is repeated as long as the code is not 111111. The transmitted bit oriented codes have priority over any data transmitted on the FDL except for ESF Yellow Alarm. The code to be transmitted is programmed by writing the code register.

9.22 HDLC Transmitters

The HDLC Transmit function is provided by the TDPR block. Three TDPR blocks are provided for flexible insertion of standardized data links:

• T1 ESF facility data link

• T1DM data link

• ISDN D-channel

• E1 Common Channel Signaling data link

• V5.1/V5.2 D-channel and C-channels.

• E1 Sa-bit data link

The TDPR is a general purpose HDLC transmitter. The TDPR is used under microprocessor control to transmit HDLC data frames. The TDPR performs all of the data serialization, CRC generation, zero-bit stuffing, as well as flag, idle, and abort sequence insertion. Data to be transmitted is provided by writing to a transmit data register. Upon completion of the frames, a CRC-CCITT frame check sequence is transmitted, followed by flag sequences. If the transmit data register underflows, an abort sequence is automatically transmitted.

When enabled, the TDPR continuously transmits the flag sequence (01111110) until data is ready to be transmitted. Data bytes to be transmitted are written into the Transmit Data Register. The TDPR performs a parallel-to-serial conversion of each data byte and transmits it using one of two procedures.

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The default procedure provides automatic transmission of data once a complete packet is written. All complete packets of data will be transmitted. After the last data byte of a packet, the CRC word (if CRC insertion has been enabled) and a flag, or just a flag (if CRC insertion has not been enabled) is transmitted. The TDPR then returns to the transmission of flag characters until the next packet is available for transmission. While working in this mode, the user must only be careful to avoid overfilling the FIFO; underruns cannot occur unless the packet is greater than 128 bytes long. The TDPR will force transmission if the FIFO is filled up regardless of whether or not the packet has been completely written into the FIFO.

The second procedure transmits data only when the FIFO depth has reached a user configured upper threshold. The TDPR will continue to transmit data until the FIFO depth has fallen below the upper threshold and the transmission of the last packet with data above the upper threshold has completed. In this mode, the user must be careful to avoid overruns and underruns. An interrupt can be generated once the FIFO depth has fallen below a user configured lower threshold as an indicator for the user to write more data.

If there are more than five consecutive ones in the raw transmit data or in the CRC data, a zero is stuffed into the serial data outp ut. This prevents the unintentional transmission of flag or abort characters.

Abort characters can be continuously transmitted at any time by setting a control bit. During transmission, an underrun situation can occur if data is not written to the Transmit Data Register before the previous byte of a packet currently being transmitted has been depleted. In this case, an abort sequence is transmitted, and the controlling processor is notified via the UDR signal.

9.23 T1 Automatic Performance Report Generation

In compliance with the ANSI T1.231, T1.403 and T1.408 standards, a performance report is generated each second for T1 ESF applications. The report conforms to the HDLC protocol and is inserted into the ESF facility data link.

The performance report can only be transmitted if TDPR #1 is configured to insert the ESF Facility Data Link and the PREN bit of the TDPR #1 Configuration register is logic 1. The performance report takes precedence over incompletely written packets, but it does not pre-empt packets already being transmitted.

See the Operation section for details on the performance report encoding.

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9.24 Pulse Density Enforcer (XPDE)

The Pulse Density Enforcer function is provided by the XPDE block. Pulse density enforcement is enabled by a register bit within the XPDE.

This block monitors the digital output of the transmitter and detects when the stream is about to violate the ANSI T1.403 12.5% pulse density rule over a moving 192-bit window. If a density violation is detected, the block can be enabled to insert a logic 1 into the digital stream to ensure the resultant output no longer violates the pulse density requirement. When the XPDE is disabled from inserting logic 1s, the digital stream from the transmitter is passed through unaltered.

9.25 Pseudo Random Pattern Generation and Detection

The Pseudo Random Sequence Generator/Processor (PRGD) is a software programmable test pattern generator, receiver and analyzer. Two types of test patterns (pseudo random and repetitive) conform to ITU-T O.151, O.152 and O.153 standards.

The PRGD can be programmed to generate pseudo random patterns with lengths up to 32 bits or any user programmable bit pattern from 1 to 32 bits in length. In addition, the PRGD can insert single bit errors or a bit error rate between 10

-1

to 10-7.

The PRGD can be programmed to check for the generated pseudo random pattern. The PRGD can perform an auto synchronization to the expected pattern and accumulates the total number of bits received and the total number of bit errors in two 32-bit counters. The counters accumulate either over intervals defined by writes to the Pattern Detector registers or upon writes to the Global PMON Update Register. When an accumulation is forced, the holding registers are updated, and the counters reset to begin accumulating for the next interval. The counters are reset in such a way that no events are missed. The data is then available in the holding registers until the next accumulation.

9.26 Transmit Jitter Attenuator (TJAT)

The Transmit Jitter Attenuation function is provided by a digital phase lock loop and 80-bit deep FIFO. The TJAT receives jittery, dual-rail data in NRZ format on two separate inputs, which allows bipolar violations to pass through the block uncorrected. The incoming data streams are stored in a FIFO timed to the transmit clock (either BTCLK or the recovered clock). The respective input data emerges from the FIFO timed to the jitter attenuated clock (TCLKO) referenced to either TCLKI, BTCLK, or the recovered clock.

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The jitter attenuator generates the jitter-free 1.544 MHz or 2.048 MHz TCLKO output transmit clock by adjusting TCLKO's phase in 1/96 UI increments to minimize the phase difference between the generated TCLKO and input data clock to TJAT (either BTCLK or the recovered clock). Jitter fluctuations in the phase of the input data clock are attenuated by the phase-locked loop within TJAT so that the frequency of TCLKO is equal to the average frequency of the input data clock. For T1 applications, to best fit the jitter attenuation transfer function recommended by TR 62411, phase f luctuations with a jitter frequency above 5.7 Hz are attenuated by 6 dB per octave of jitter frequency. Wandering phase fluctuations with frequencies below 5.7 Hz are tracked by the generated TCLKO. In E1 applications, the corner frequency is 7.6 Hz. To provide a smooth flow of data out of TJAT, TCLKO is used to read data out of the FIFO.

If the FIFO read pointer (timed to TCLKO) comes within one bit of the write pointer (timed to the input data clock, BTCLK or RSYNC), TJAT will track the jitter of the input clock. This permits the phase jitter to pass through unattenuated, inhibiting the loss of data.

Jitter Characteristics

The TJAT Block provides excellent jitter tolerance and jitter attenuation while generating minimal residual jitter. It can accommodate up to 61 UIpp of input jitter at jitter frequencies above 5.7 Hz (7.6 Hz for E1). For jitter frequencies below 5.7 Hz (7.6 Hz for E1), more correctly called wander, the tolerance increases 20 dB per decade. In most applications the TJAT Block will limit jitter tolerance at lower jitter frequencies only. For high frequency jitter, above 10 kHz for example, other factors such as clock and data recovery circuitry may limit jitter tolerance and must be considered. For low frequency wander, below 10 Hz for example, other factors such as slip buffer hysteresis may limit wander tolerance and must be considered. The TJAT block meets the stringent low frequency jitter tolerance requirements of AT&T TR 62411 and thus allows compliance with this standard and the other less stringent jitter tolerance standards cited in the references.

The corner frequency in the jitter transfer response can be altered through programming.

TJAT exhibits negligible jitter gain for jitter frequencies below 5.7 Hz (7.6 Hz for E1), and attenuates jitter at frequencies above 5.7 Hz (7.6 Hz for E1) by 20 dB per decade. In most applications, the TJAT block will determine jitter attenuation for higher jitter frequencies only. Wander, below 10 Hz for example, will essentially be passed unattenuated through TJAT. Jitter, above 10 Hz for example, will be attenuated as specified, however, outgoing jitter may be dominated by the generated residual jitter in cases where incoming jitter is insignificant. This generated residual jitter is directly related to the use of a

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1/96 UI phase adjustment quantum. TJAT meets the jitter attenuation requirements of AT&T TR 62411. The block allows the implied jitter attenuation requirements for a TE or NT1 given in ANSI Standard T1.408, and the implied jitter attenuation requirements for a type II customer interface given in ANSI T1.403 to be met.

Jitter Tolerance

Jitter tolerance is the maximum input phase jitter at a given jitter frequency that a device can accept without exceeding its linear operating range, or corrupting data. For TJAT, the input jitter tolerance is 61 Unit Intervals peak-to-peak (UIpp) with a worst case frequency offset of 354 Hz. It is 80 UIpp with no frequency offset. The frequency offset is the difference between the frequency of XCLK and that of the input data clock. Values above 2 kHz in the below graph are based on simulation results.

Figure 9 - TJAT Jitter Tolerance

JITTER

AMPLITUDE,

UI pp

100

28

10

1.0

0.1

0.01

JAT MIN.TOLER ANCE

acceptable

unacceptable

1

10

100

1k 10k

61

0.4

100k

JITTER FREQUENCY, Hz

The accuracy of the XCLK frequency and that of the TJAT PLL reference input clock used to generate the jitter-free TCLKO output have an effect on the minimum jitter tolerance. Given that the TJAT PLL reference clock accuracy can

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be ±200 Hz and that the XCLK input accuracy can be ±100 ppm, the minimum jitter tolerance for various differences between the frequency of PLL reference clock and XCLK are shown in Figure 10.

Figure 10 - TJAT Minimum Jitter Tolerance vs. XCLK Accuracy

70

68

65

66

JAT MIN. JITTER TOLERANCE,

60

61

UI pp

55

MAX. FREQUENCY OFFSET

100

XCLK ACCURACY

200

0

250

32

300 354

100

Hz

,± ppm

Jitter Transfer

For T1 applications, the output jitter for jitter frequencies from 0 to 5.7 Hz (7.6 Hz for E1) is no more than 0.1 dB greater than the input jitter, excluding residual jitter. Jitter frequencies above 5.7 Hz (7.6 Hz for E1) are attenuated at a level of 6 dB per octave, as shown in Figure 11.

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Figure 11 - TJAT Jitter Transfer

0

-10

JITTER

GAIN

dB

-20

-30

62411 min

62411 max

JAT response

43802 max

-40

-50 1

10 100 1k 10k

5.7 JITTER FREQUENCY

Hz

T1

In the non-attenuating mode, when the FIFO is within one UI of overrunning or under running, the tracking range is 1.48 MHz to 1.608 MHz.

The guaranteed linear operating range for the jittered input clock is 1.544 MHz ± 200 Hz with worst case jitter (61 UIpp), and maximum system clock frequency offset (± 100 ppm). The nominal range is 1.544 MHz ± 963 Hz with no jitter or system clock frequency offset.

E1

In the non-attenuating mode, when the FIFO is within one UI of overrunning or under running, the tracking range is 2.13 MHz to 1.97 MHz.

The guaranteed linear operating range for the jittered input clock is 2.048 MHz ± 300 Hz with worst case jitter (61 UIpp), and maximum system clock frequency offset (± 100 ppm). The nominal range is 2.048 MHz ± 1277 Hz with no jitter or system clock frequency offset.

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Jitter Generation

In the absence of input jitter, the output jitter shall be less than 0.025 UIpp. This complies with the AT&T TR 62411 requirement of less than 0.025 UIpp of jitter generation.

9.27 Timing Options (TOPS)

The Timing Options block provides a means of selecting the source of the reference signal for the transmit digital PLL and the clock source used to derive the output TCLKO signal.

9.28 Line Transmitter

The line transmitter generates Alternate Mark Inversion (AMI) transmit pulses suitable for use in the DSX-1 (short haul T1), short haul E1, long haul T1 and long haul E1 environments. The voltage pulses are produced by applying a current to a known termination (termination resistor plus line impedance). The use of current (instead of a voltage driver) simplifies transmit Input Return Loss (IRL), transmit short circuit protection (none needed) and transmit tri-stating.

The output pulse shape is synthesized digitally with current digital-to-analog (DAC) converters which produce 24 samples per symbol. The current DAC’s produce differential bipolar outputs that directly drive the TXTIP[1:0] and TXRING[1:0] pins. The current output is applied to a terminating resistor (optional) and line-coupling transformer in a differential manner, which when viewed from the line side of the transformer produce the output pulses at the required levels and insures a small positive to negative pulse imbalance.

The pulse shape is user programmable. For T1 short haul, the cable length between the TLONG and the cross-connect (where the pulse template specifications are given) greatly affects the resulting pulse shapes. Hence, the data applied to the converter must account for different cable lengths. For CEPT E1 applications the pulse template is specified at the transmitter, thus only one setting is required. For T1 long haul with a LBO of 7.5 dB the previous bits effect what the transmitter must drive to compensate for inter-symbol interference; for LBO’s of 15 dB or 22.5 dB the previous 3 or 4 bits effect what the transmitter must send out.

Refer to the Operation section for details on creating the synthesized pulse shape.

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PM4351 COMET

9.29 Backplane Receive Interface (BRIF)

The Backplane Receive Interface allows data to be presented to a backplane in either a 1.544 Mbit/s, 2.048 Mbit/s, 4.096 Mbit/s, 8.192 Mbit/s or sub-rate NxDS0 serial stream.

All receive backplane signals are synchronous to BRCLK. BRCLK may be an output, in which case it is a jitter attenuated version of the recovered clock. If BRCLK is an input, it clocks the output of the frame slip buffer; therefore, it must be plesiochronous to the recovered clock.

When configured to provide a 1.544 Mbit/s data rate, the block generates the output data stream on the BRPCM pin containing 24 channel bytes of data followed by a single bit containing the framing bit or parity over the 24 channels. The BRSIG output pin contains 24 bytes of signaling nibble data located in the least significant nibble of each byte followed by a single bit position representing the "place holder" for the framing bit or parity over the 24 channels. The framing alignment indication on the BRFP pin indicates the first bit of the 193-bit frame (or, optionally, the f irst bit of every second frame, the first bit of the first frame of the superframe, or every second superframe). When BRFP is an input, the data read from the frame slip buffer is aligned to it.

In T1 mode, when configured to provide a 2.048 Mbit/s data rate, the block internally gaps the 2.048 MHz rate backplane clock to provide a serial PCM data on the BRPCM pin containing three channel bytes of data followed by one unused byte (can be logic 0 or logic 1). The signaling on the BRSIG pin is aligned to the least significant nibble of the associated channel on BRPCM. The frame alignment indication is provided on the BRFP pin, going high for one BRCLK cycle during the first bit of the unused byte, indicating the next data byte is the first channel of the frame, or the first channel of the first frame of the superframe. Alternatively, the PCM and signaling can be arranged in 24 contiguous timeslots, starting at the timeslot indicated by the BRFP pulse.

In E1 mode, the 2.048 Mbit/s data stream consumes all timeslots of BRPCM. The BRSIG output pin present 30 bytes of signaling nibble data located in the least significant nibble of each byte. The framing alignment indication on the BRFP output can be configured to indicate the first bit of each 256-bit frame, the first bit of every other 256-bit frame, the first bit of the first frame of the CRC multiframe, the first bit of the first frame of the signaling multiframe or all overhead bits. If BRFP is configured as an input, the BRPCM and BRSIG can be forced to an specific alignment provided the elastic store is used (the RXELSTBYP register bit is logic 0).

When configured for NxDS0 operation, no output clock edges are generated during the framing bit positions and idle channels.

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PM4351 COMET

As a programming option, the data stream bit and timeslot alignment relative to BRFP can be modified for Concentration Highway Interface (CHI) applications.

When configured for a multiplexed backplane, the two or four sets of PCM and signaling streams are byte-interleaved into a 4.096 Mbit/s or 8.192 Mbit/s serial stream.

9.30 Backplane Transmit Interface (BTIF)

The Backplane Transmit Interface allows data to be taken from a backplane in either a 1.544 Mbit/s, 2.048 Mbit/s, 4.096 Mbit/s, 8.192 Mbit/s or sub-rate NxDS0 serial stream.

When configured to receive a 1.544 Mbit/s data rate stream, the input data stream on the BTPCM pin to is expected to contain 24 channel bytes of data followed by a single bit location for the framing bit or optional parity over the previous 24 channels. The BTSIG input pin must contain 24 bytes of signaling nibble data located in the least significant nibble of each byte followed by a single bit position for the framing bit or optional parity over the previous frame. The framing alignment indication on the BTFP input must indicate the framing bit position of the 193-bit frame (or, optionally, the framing bit position of the first frame of the superframe).

In T1 mode, when configured to provide a 2.048 Mbit/s data rate, the block expects serial PCM data on the BTPCM pin to contain three channel bytes of data followed by one unused byte. The signaling on the BTSIG pin must be aligned to the least significant nibble of the associated channel on BTPCM. The frame alignment indication is expected on the BTFP pin, going to high during the first bit of the unused byte, indicating the next data byte is the first channel of the frame. Alternatively, the PCM and signaling can be arranged in 24 contiguous timeslots, starting at the timeslot indicated by the BTFP pulse.

In E1 mode, the 2.048 Mbit/s data stream consumes all timeslots of BRPCM. The BTSIG input presents 30 bytes of signaling nibble data located in the least significant nibble of each timeslot. The framing alignment indication on the BTFP pin can be configured to indicate the first bit of each 256-bit frame or the first bit of the first frame of the CRC mu ltiframe and signaling multiframes.

BTCLK can be configured as an output, in which case, BTCLK is generated from TCLKO. When configured for NxDS0 operation, no output clock edges are generated during the framing bit positions and idle channels.

BTFP can be configured as an output, in which case, the COMET dictates the frame alignment.

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PM4351 COMET

As a programming option, the data stream bit and timeslot alignment relative to BTFP can be modified for Concentration Highway Interface (CHI) applications.

When configured for a multiplexed backplane, one of two or four sets of PCM and signaling streams are extracted from the byte-interleaved 4.096 Mbit/s or

8.192 Mbit/s serial stream.

9.31 JTAG Test Access Port

The JTAG Test Access Port block provides JTAG support for boundary scan. The standard JTAG EXTEST, SAMPLE, BYPASS, IDCODE and STCTEST instructions are supported. The COMET revision E identification code is 443510CD hexadecimal. The revision F code is 543510CD.

9.32 Microprocessor Interface (MPIF)

The Microprocessor Interface allows the COMET to be configured, controlled and monitored via internal registers.

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PM4351 COMET

10 REGISTER DESCRIPTION

10.1 Normal Mode Register Memory Map

Table 16 - Normal Mode Register Memory Map

Addr Register

000H Global Configuration 001H Clock Monitor 002H Receive Options 003H Receive Line Interface Configuration 004H Transmit Line Interface Configuration 005H Transmit Framing and Bypass Options 006H Transmit Timing Options 007H Interrupt Source #1 008H Interrupt Source #2 009H Interrupt Source #3 00AH Master Diagnostics 00BH Master Test 00CH Analog Diagnostics 00DH Revision/Chip ID/Global PMON Update 00EH Reset 00FH PRGD Positioning/Control and HDLC Control 010H CDRC Configuration 011H CDRC Interrupt Enable 012H CDRC Interrupt Status 013H CDRC Alternate Loss of Signal 014H RJAT Interrupt Status 015H RJAT Reference Clock Divisor (N1) Control 016H RJAT Output Clock Divisor (N2) Control 017H RJAT Configuration

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PM4351 COMET

Addr Register

018H TJAT Interrupt Status 019H TJAT Reference Clock Divisor (N1) Control 01AH TJAT Output Clock Divisor (N2) Control 01BH TJAT Configuration 01CH RX-ELST Configuration 01DH RX-ELST Interrupt Enable/Status 01EH RX-ELST Idle Code 01FH RX-ELST Reserved 020H TX-ELST Configuration 021H TX-ELST Interrupt Enable/Status 022H-023H TX-ELST Reserved 024H-027H Reserved 028H RXCE Receive Data Link 1 Control 029H RXCE Receive Data Link 1 Bit Select 02AH RXCE Receive Data Link 2 Control 02BH RXCE Receive Data Link 2 Bit Select 02CH RXCE Receive Data Link 3 Control 02DH RXCE Receive Data Link 3 Bit Select 02EH-02FH RXCE Reserved 030H BRIF Receive Backplane Configuration 031H BRIF Receive Backplane Frame Pulse Configuration 032H BRIF Receive Backplane Parity/F-Bit Configuration 033H BRIF Receive Backplane Time Slot Offset 034H BRIF Receive Backplane Bit Offset 035H-037H BRIF Receive Backplane Reserved 038H TXCI Transmit Data Link 1 Control 039H TXCI Transmit Data Link 1 Bit Select 03AH TXCI Transmit Data Link 2 Control 03BH TXCI Transmit Data Link 2 Bit Select

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PM4351 COMET

Addr Register

03CH TXCI Transmit Data Link 3 Control 03DH TXCI Transmit Data Link 3 Bit Select 03EH-03FH TXCI Reserved 040H BTIF Transmit Backplane Configuration 041H BTIF Transmit Backplane Frame Pulse Configuration 042H BTIF Transmit Backplane Parity Configuration and Status 043H BTIF Transmit Backplane Time Slot Offset 044H BTIF Transmit Backplane Bit Offset Register 045H BTIF Transmit Backplane Reserved 046H BTIF Transmit Backplane Reserved 047H BTIF Transmit Backplane Reserved 048H T1 FRMR Configuration 049H T1 FRMR Interrupt Enable 04AH T1 FRMR Interrupt Status 04BH Reserved 04CH IBCD Configuration 04DH IBCD Interrupt Enable/Status 04EH IBCD Activate Code 04FH IBCD Deactivate Code 050H SIGX Configuration/Change of Signaling State 051H SIGX µP Access Status/Change of Signaling State 052H SIGX Channel Indirect Address/Control/ Change of Signaling

State 053H SIGX Channel Indirect Data Buffer/Change of Signaling State 054H T1 XBAS Configuration 055H T1 XBAS Alarm Transmit 056H T1 XIBC Control 057H T1 XIBC Loopback Code 058H PMON Interrupt Enable/Status

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PM4351 COMET

Addr Register

059H PMON Framing Bit Error Count 05AH PMON OOF/COFA/Far End Block Error Count (LSB) 05BH PMON OOF/COFA/Far End Block Error Count (MSB) 05CH PMON Bit Error/CRCE Count (LSB) 05DH PMON Bit Error/CRCE Count (MSB) 05EH PMON LCV Count (LSB) 05FH PMON LCV Count (MSB) 060H T1 ALMI Configuration 061H T1 ALMI Interrupt Enable 062H T1 ALMI Interrupt Status 063H T1 ALMI Alarm Detection Status 064H T1 PDVD Reserved 065H T1 PDVD Interrupt Enable/Status 066H T1 XBOC Reserved 067H T1 XBOC Code 068H T1 XPDE Reserved 069H T1 XPDE Interrupt Enable/Status 06AH T1 RBOC Enable 06BH T1 RBOC Code Status 06CH TPSC Configuration 06DH TPSC µP Access Status 06EH TPSC Channel Indirect Address/Control 06FH TPSC Channel Indirect Data Buffer 070H RPSC Configuration 071H RPSC µP Access Status 072H RPSC Channel Indirect Address/Control 073H RPSC Channel Indirect Data Buffer 074H-077H Reserved 078H T1 APRM Configuration/Control

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PM4351 COMET

Addr Register

079H T1 APRM Manual Load 07AH T1 APRM Interrupt Status 07BH T1 APRM One Second Content Octet 2 07CH T1 APRM One Second Content Octet 3 07DH T1 APRM One Second Content Octet 4 07EH T1 APRM One Second Content MSB (Octet 5) 07FH T1 APRM One Second Content LSB (Octet 6) 080H E1 TRAN Configuration 081H E1 TRAN Transmit Alarm/Diagnosti c Control 082H E1 TRAN International Control 083H E1 TRAN Extra Bits Control 084H E1 TRAN Interrupt Enable 085H E1 TRAN Interrupt Status 086H E1 TRAN National Bit Codeword Select 087H E1 TRAN National Bit Codeword 088H-08BH Reserved 08CH T1 FRMR Reserved 08DH T1 FRMR Reserved 08EH Reserved 08FH Reserved 090H E1 FRMR Frame Alignment Options 091H E1 FRMR Maintenance Mode Options 092H E1 FRMR Framing Status Interrupt Enable 093H E1 FRMR Maintenance/Alarm Status Interrupt Enable 094H E1 FRMR Framing Status Interrupt Indication 095H E1 FRMR Maintenance/Alarm Status Interrupt Indication 096H E1 FRMR Framing Status 097H E1 FRMR Maintenance/Alarm Status 098H E1 FRMR International/National Bits

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PM4351 COMET

Addr Register

099H E1 FRMR CRC Error Count - LSB 09AH E1 FRMR CRC Error Count - MSB 09BH E1 FRMR National Bit Codeword Interrupt Enables 09CH E1 FRMR National Bit Codeword Interrupts 09DH E1 FRMR National Bit Codewords 09EH E1 FRMR Frame Pulse/Alarm Interrupt Enables 09FH E1 FRMR Frame Pulse/Alarm Interrupt 0A0H-0A7H Reserved 0A8H TDPR #1 Configuration 0A9H TDPR #1 Upper Transmit Threshold 0AAH TDPR #1 Lower Transmit Threshold 0ABH TDPR #1 Interrupt Enable 0ACH TDPR #1 Interrupt Status/UDR Clear 0ADH TDPR #1 Transmit Data 0AEH Reserved 0AFH Reserved 0B0H TDPR #2 Configuration 0B1H TDPR #2 Upper Transmit Threshold 0B2H TDPR #2 Lower Transmit Threshold 0B3H TDPR #2 Interrupt Enable 0B4H TDP R # 2 Interrupt Status/UDR Clear 0B5H TDPR #2 Transmit Data 0B6H Reserved 0B7H Reserved 0B8H TDPR #3 Configuration 0B9H TDPR #3 Upper Transmit Threshold 0BAH TDPR #3 Lower Transmit Threshold 0BBH TDPR #3 Interrupt Enable 0BCH TDPR #3 Interrupt Status/UDR Clear

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PM4351 COMET

Addr Register

0BDH TDPR #3 Transmit Data 0BEH Reserved 0BFH Reserved 0C0H RDLC #1 Configuration 0C1H RDLC #1 Interrupt Control 0C2H RDLC #1 Status 0C3H RDLC #1 Data 0C4H RDLC #1 Primary Address Match 0C5H RDLC #1 Secondary Address Match 0C6H Reserved 0C7H Reserved 0C8H RDLC #2 Configuration 0C9H RDLC #2 Interrupt Control 0CAH RDLC #2 Status 0CBH RDLC #2 Data 0CCH RDLC #2 Primary Address Match 0CDH RDLC #2 Secondary Address Match 0CEH Reserved 0CFH Reserved 0D0H RDLC #3 Configuration 0D1H RDLC #3 Interrupt Control 0D2H RDLC #3 Status 0D3H RDLC #3 Data 0D4H RDLC #3 Primary Address Match 0D5H RDLC #3 Secondary Address Match 0D6H CSU Configuration 0D7H CSU Reserved 0D8H RLPS Indirect Data Register 0D9H RLPS Indirect Data Register

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PM4351 COMET

Addr Register

0DAH RLPS Indirect Data Register 0DBH RLPS Indirect Data Register 0DCH RLPS Equalizer Voltage Reference 0DDH-0DFH RLPS Rese rved 0E0H PRGD Control 0E1H PRGD Interrupt Enable/Status 0E2H PRGD Shift Register Length 0E3H PRGD Tap 0E4H PRGD Error Insertion 0E5H PRGD Reserved 0E6H PRGD Reserved 0E7H PRGD Reserved 0E8H PRGD Pattern Insertion #1 0E9H PRGD Pattern Insertion #2 0EAH PRGD Pattern Insertion #3 0EBH PRGD Pattern Insertion #4 0ECH PRGD Pattern Detector #1 0EDH PRGD Pattern Detector #2 0EEH PRGD Pattern Detector #3 0EFH PRGD Pattern Detector #4 0F0H XLPG Line Driver Configuration 0F1H XLPG Control/Status 0F2H XLPG Pulse Waveform Storage Write Address 0F3H XLPG Pulse Waveform Storage Data 0F4H XLPG Analog Test Positive Control 0F5H XLPG Analog Test Negative Control 0F6H XLPG Fuse Data Select 0F7H XLPG Reserved 0F8H RLPS Configuration and Status

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PM4351 COMET

Addr Register

0F9H RLPS ALOS Detection/Clearance Threshold 0FAH RLPS ALOS Detection Period 0FBH RLPS ALOS Clearance Period 0FCH RLPS Equalization Indirect Address 0FDH RLPS Equalization Read/WriteB Select 0FEH RLPS Equalizer Loop Status and Control 0FFH RLPS Equalizer Configuration 100H-1FFH Reserved for Test

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PM4351 COMET

11 NORMAL MODE REGISTER DESCRIPTION

Normal mode registers are used to configure and monitor the operation of the COMET. Normal mode registers (as opposed to test mode registers) are selected when A[8] is low.

Notes on Normal Mode Register Bits:

1. Writing values into unused register bits has no effect. Reading back unused bits can produce either a logic 1 or a logic 0; hence, unused register bits should be masked off by software when read.

2. All configuration bits that can be written into can also be read back. This allows the processor controlling the COMET to determine the pro gra mming state of the chip.

3. Writeable normal mode register bits are cleared to zero upon reset unless otherwise noted.

4. Writing into read-only normal mode register bit locations does not affect COMET operation unless otherwise noted.

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PM4351 COMET

Register 000H: Global Configuration

Bit Type Function Default

Bit 7 R/W PIO_OE 1 Bit 6 R/W PIO 0 Bit 5 R/W IBCD_IDLE 0 Bit 4 R/W RSYNC_ALOSB 0 Bit 3 R/W OOSMFAIS 0 Bit 2 R/W TRKEN 0 Bit 1 R/W RXMTKC 0 Bit 0 R/W E1/T1B 0

PIO_OE:

The programmable I/O output enable, PIO_OE, bit controls the PIO pin. When PIO_OE is logic 1, the PIO pin is configured as an output and driven by the COMET. When PIO_OE is logic 0, the PIO pin is configured as an input. Upon reset, the PIO pin is configured as an output.

PIO:

The programmable I/O, PIO, bit controls/reflects the state of the PIO pin. When the PIO pin is configured as an output, the PIO bit controls the state of the PIO pin. When the PIO pin is configured as an input, the PIO bit reflects the state of the PIO pin. Upon reset, the PIO pin has an output value of logic 0.

OOSMFAIS:

In E1 mode, this bit controls the receive backplane signaling trunk conditioning in an out of signaling multiframe condition. If OOSMFAIS is set to a logic 0, an OOSMF indication from the E1-FRMR does not affect the BRSIG output. When OOSMFAIS is a logic 1, an OOSMF indication from the E1-FRMR will cause the BRSIG output to be set to all 1's.

RSYNC_ALOSB:

The RSYNC_ALOSB bit controls the source of the loss of signal condition used to control the behaviour of the receive reference presented on the RSYNC. If RSYNC_ALOSB is a logic 0, analog loss of signal is used. If RSYNC_ALOSB is a logic 1, digital loss of signal is used. When COMET is in a loss of signal state, the RSYNC output is derived from XCLK. When

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Datasheet PM4351-NI, PM4351-RI, PM7366 Datasheet (PMC)

Specifications and Main Features

Frequently Asked Questions

User Manual

CONTENTS

LIST OF REGISTERS

LIST OF FIGURES

LIST OF TABLES

9.2 Clock and Data Recovery (CDRC)

9.5 T1 Inband Loopback Code Detector (IBCD)

9.6 T1 Pulse Density Violation Detector (PDVD)

9.7 Performance Monitor Counters (PMON)

9.8 T1 Bit Oriented Code Dete ctor (RBOC)

9.9 HDLC Receiver (RDLC)

11 NORMAL MODE REGISTER DESCRIPTION