Datasheet PM3351-RC, PM3351-SW Datasheet (PMC)

PM3351 ELAN 1X100

DATA SHEET
PMC-970113 ISSUE 3 SINGLE PORT FAST ETHERNET SWITCH

PM3351

ELAN 1X100

SINGLE PORT FAST ETHERNET

SWITCH

DATA SHEET

ISSUE 3: FEBRUARY 1998

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PM3351 ELAN 1X100

DATA SHEET
PMC-970113 ISSUE 3 SINGLE PORT FAST ETHERNET SWITCH

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PM3351 ELAN 1X100

DATA SHEET
PMC-970113 ISSUE 3 SINGLE PORT FAST ETHERNET SWITCH

CONTENTS

FEATURES............................................................................................................1

BLOCK DIAGRAM.................................................................................................3

DESCRIPTION ......................................................................................................4

Introduction....................................................................................................5

Switch Processor...........................................................................................5

Multi-channel DMA Processor........................................................................6

Ethernet/IEEE 802.3 MAC Interface..............................................................6

Expansion Port...............................................................................................6

Local Memory Controller................................................................................7

Clocking and Test..........................................................................................7

TYPICAL SYSTEM APPLICATION........................................................................8

Low-cost 10/100 Mbit/s Switching Hub..........................................................8

PRIMARY FEATURES AND BENEFITS ...............................................................9

Wire-speed frame switching...........................................................................9

Combined Input- and Output-buffered switch................................................9

Modular design. .............................................................................................9

Advanced switching features.........................................................................9

Spanning tree bridging capabilities..............................................................10

Management and monitoring support..........................................................10

Autoconfiguration via Local PROM/EEPROM..............................................10

PIN DIAGRAM.....................................................................................................12

208-Pin Quad Flat Pack Pin Diagram..........................................................12

PIN DESCRIPTION .............................................................................................13

Functional Grouping.....................................................................................15

PCI Expansion Bus Interface.......................................................................16

MII Interface Pins.........................................................................................17

Local Memory Interface ...............................................................................18

Clock Inputs and Outputs.............................................................................19

Miscellanous Inputs and Outputs.................................................................20

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PMC-970113 ISSUE 3 SINGLE PORT FAST ETHERNET SWITCH

DC CHARACTERISTICS.....................................................................................21

Absolute Maximum Ratings.........................................................................21

Recommended Operating Conditions..........................................................21

D.C. Characteristics.....................................................................................22

AC CHARACTERISTICS.....................................................................................23

PCI Bus Interface.........................................................................................24

MII Interface.................................................................................................25

Memory Interface.........................................................................................27

15 nS SRAM AC Timing.........................................................................27

150 ns EEPROM/EPROM AC Timing ....................................................28

60 ns EDO DRAM AC Timing.................................................................29

Clocking.......................................................................................................31

Miscellaneous..............................................................................................31

FUNCTIONAL DESCRIPTION.............................................................................32

Overview......................................................................................................32

System Components....................................................................................32

System Block Diagram...........................................................................33

System Memory Map..............................................................................34

Device Internal Blocks .................................................................................37

Switch Processor....................................................................................37

100Mbit/s Ethernet MAC Interface .........................................................38

Multichannel DMA Controller .......................................................................43

Memory Controller .......................................................................................46

PCI Expansion Port......................................................................................47

Watchdog Timer Facility.........................................................................51

Device Configuration..............................................................................52

System Bootstrap Image........................................................................54

Configuration Parameters.......................................................................60

Self Test and Error Reporting.................................................................61

Data Structures............................................................................................63

Switch Processor Operating Environment..............................................64

Packet Buffers........................................................................................68

Data Descriptors.....................................................................................71

Transfer Rings........................................................................................74

Local Port Descriptor and Port Descriptor Counters...............................76

Expansion Port Descriptor Table............................................................84

Address Hash Table...............................................................................86

Free Pools..............................................................................................94

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DATA SHEET
PMC-970113 ISSUE 3 SINGLE PORT FAST ETHERNET SWITCH

Spanning Tree Support Data Structures.................................................96

RTOS Requirements..............................................................................97

UDP/IP Protocol Stack Requirements....................................................97

SNMP Requirements..............................................................................97

Storage Requirements............................................................................97

Switching System Initialization...................................................................100

Frame Switching Process..........................................................................101

Address Learning and Aging......................................................................115

Local Address Learning........................................................................116

Remote Learning Process....................................................................117

Default Hash Bucket.............................................................................118

Buffer and Queue Management.................................................................122

Buffer Management..............................................................................123

Transmit FIFO Management ................................................................124

Broadcast Rate Limiting .......................................................................125

Statistics Collection....................................................................................126

Messaging Protocol ...................................................................................128

Spanning Tree Operation...........................................................................129

RTOS Operation........................................................................................129

UDP/IP Protocol Stack Operation..............................................................129

SNMP Operation........................................................................................129

Device Interface via PCI ............................................................................129

Frame Transfer to Non-ELAN Devices.................................................129

Participation in Address Learning.........................................................129

Participation in the Messaging Protocol................................................129

Accessing Variables and Statistics.......................................................129

Byte Ordering .......................................................................................129

Default Byte Ordering...........................................................................130

Alternate Byte Ordering........................................................................131

ELAN 1x100 / ELAN 8x10 Expansion Bus Data Transfer Rates..........131

PCI REGISTER/MEMORY ACCESS.................................................................137

PCI Configuration Space ...........................................................................137

PCI Configuration Registers.................................................................138

PCI Memory Space....................................................................................147

Local Memory Access...........................................................................148

Device Control/Status Registers...........................................................148

Device Configuration Registers............................................................150

Device Debug Registers.......................................................................155

Request and Acknowledge Counter Registers.....................................155

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DATA SHEET
PMC-970113 ISSUE 3 SINGLE PORT FAST ETHERNET SWITCH

PROGRAMMER'S MODEL................................................................................157

Local Memory ............................................................................................158

Register Map..............................................................................................158

General-Purpose Registers..................................................................158

Special-Purpose Registers...................................................................158

Control Registers..................................................................................159

Register Descriptions.................................................................................163

CPU Special Registers.........................................................................163

Device Control Registers......................................................................164

RPCIM Functional Block (PCI access DMA channel)................................173

DEBUG Functional Block...........................................................................182

DPI Functional Block (DMA transmit channel)...........................................187

TX_FIFO functional block: .................................................................................191

Major components of the TX_FIFO datapath.......................................191

TX_FIFO interrupts to Switch Processor..............................................192

Disposition of Frames:..........................................................................192

DPO funtional block (DMA transfer handshake channel)...........................199

HASH functional block...............................................................................215

Interrupts to Swtich Processor...................................................................226

GPI (Switch Processor General Purpose Inputs).......................................230

GPO (Switch Processor General Purpose Outputs)..................................231

Coprocessor Test Conditions.....................................................................235

OPERATION......................................................................................................237

Power Supply Sequencing.........................................................................237

MECHANICAL INFORMATION .........................................................................238

ORDERING AND THERMAL INFORMATION...................................................240

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DATA SHEET
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FEATURES

• Single-chip, 1-port, full duplex or half duplex, 10/100BaseT switching device for
low-cost unmanaged and managed networks.

• On-chip 50 MHz RISC CPU processor core, multi-channel DMA controller,
MAC-layer interface logic, FIFOs, PCI-based expansion port and a flexible
memory controller.

• CPU supports background applications running on local OS (e.g., SNMP or
RMON), and real-time data oriented applications (e.g., frame forwarding and
filtering decisions).

• Performs frame switching at a rate of 200 Mbit/s (full duplex), 100 Mbit/s (half
duplex).

• Fully compatible with the PM3350, 8-port 10 Mbit/s switch device; may be used
to create a compact and inexpensive mixed 10/100 Mbit/s switching hub.

• Store-and-forward operation with full error checking and filtering.

• Filtering and switching at wire rates (up to 148,800 packets per second),

supporting a mix of Ethernet and IEEE 802.3 protocols.

• Expansion port supports a peak system bandwidth of 1 Gbit/s, and is compatible
with industry-standard PCI bus (version 2.1).

• Performs all address learning, address table management and aging functions
for up to 32,768 MAC addresses (limited by external memory). Address
learning rate of up to 100,000 addresses per second.

• Maximum broadcast/multicast at wire rates with configurable broadcast storm
rate limiting.

• Low-latency operation in both unicast and broadcast modes.

• Implements the Link Partition function to isolate malfunctioning segments or

hosts.

• IEEE 802.1d compliant spanning-tree transparent bridging supported on-chip,
with configurable aging time and frame lifetime control.

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DATA SHEET
PMC-970113 ISSUE 3 SINGLE PORT FAST ETHERNET SWITCH

• Flow control supported for both full duplex and half duplex operation: supports
IEEE 802.3x PAUSE frame flow control in full-duplex mode, and supports user­enabled backpressure flow control in half-duplex mode with configurable buffer
thresholds and limits.

• Configuration, management, MIB statistics and diagnostics available in-band or
out-of-band.

• Maintains and collects per-port and per-host statistics at wire rates, allowing a
network switch comprised of PM3351 and PM3350 chips to implement RMON
statistics (EtherStats and HostStats) using supplied on-chip firmware.

• Interfaces directly to industry-standard 100 Mbit/s transceivers with no glue logic
via the built-in Medium Independent Interface (MII) port with full support for the
autonegotiation function implemented by the PHY devices.

• Fully static CMOS operation at 50 MHz clock rates.

• 3.3 Volt core, 5 Volt compatible I/O

• 208 pin PQFP package.

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DATA SHEET
PMC-970113 ISSUE 3 SINGLE PORT FAST ETHERNET SWITCH

BLOCK DIAGRAM

50 MHz

Embedded CPU

PCI

Expansion

Bus

PCI
Bus

Interface

Expansion

Registers

I

Cache

D

Cache

Transmit

Channel Logic

Receive

DMA Controller

External
memory

Interface

SRAM / EPROM

Tx

FIFO

Rx

FIFO

100BaseT

Transmit MAC

100BaseT

Transmit MAC

100BaseT

MII I/F

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PM3351 ELAN 1X100

DATA SHEET
PMC-970113 ISSUE 3 SINGLE PORT FAST ETHERNET SWITCH

DESCRIPTION

The PM3351 is a low-cost, highly integrated stand-alone single-chip switching device
for 10/100 Mbit/s Ethernet (IEEE 802.3u, IEEE 802.12) switching and bridging
applications. The device supports all processing required for switching Ethernet
packets between the on-chip Medium Independent Interface (MII) port and the built-in 1
Gbit/s expansion port, to which other PM3351 (ELAN 1x100) or PM3350 (ELAN 8x10)
devices may be attached.

The PM3351 is directly compatible with the PM3350, 8-port 10Mbit/s Ethernet switch
chip. The PM3351 can be used with the PM3350 to create non-blocking switches of the
configurations shown in the table below, with each 100 Mbit/s port configured for full­duplex and each 10 Mbit/s port configured for half-duplex

Switch Configuration # PM3350

Chips

# PM3351

Chips

4 x 100 Mbit/s 0 4
3 x 100 Mbit/s + 16 x 10Mbit/s 2 3
2 x 100 Mbit/s + 40 x 10 Mbit/s 5 2
1 x 100 Mbit/s + 56 x 10 Mbit/s 7 1
0 x 100 Mbit/s + 64 x 10 Mbit/s 8 0

A switch built using the PM3351 can be expanded to use up to 7 additional devices on
the PCI expansion bus; the limitation to 8 devices is a result of using dedicated internal
counters for implementing the ELAN switch protocol over the expansion bus. For details
on the expected expansion bus data traffic requirements for different combinations of
PM3350 and PM3351 chips please refer to section Expansion Bus Data Transfer
Rates.

All of the initialization, switching, interfacing, management and statistics gathering
functions are performed by the PM3351, minimizing the size and cost of a switching
hub with one or more 100 Mbit/s ports.

Switch configuration and management can be performed either remotely (in-band), via
the on-chip SNMP MIB, agent and integrated TCP/UDP/IP stack, or from a local CPU
interfaced to the expansion port. The ELAN 1x100 also collects per-port and per-host

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PM3351 ELAN 1X100

DATA SHEET
PMC-970113 ISSUE 3 SINGLE PORT FAST ETHERNET SWITCH

RMON statistics at wire rates on all ports. The PM3351 chip contains all the required
elements of a high-performance Ethernet switch: an MII interface for connection to
physical-layer transceivers, MAC-layer processing logic, buffer FIFOs, a high-speed
DMA engine for fast frame transfers, a local memory interface for up to 4 Mbytes of
external buffer memory, a compatible PCI bus master and slave unit for modular
expansion, and a switch processing unit that implements the switching and bridging
functions. The only additional components required for each 100 Mbit/s switch port are
an MII compliant transceiver (supports 100BaseTX/FX, 100BaseT4,100BaseT2, and
any future 802.3-compliant 100Mbit MII PHYs), passive line interface devices, a bank of
external memory and a system clock. The amount of external memory may range up to
4 Mbytes, depending on the amount of frame buffering required and the number of
MAC addresses to be supported, and may be implemented using standard
asynchronous SRAM devices with 15 nsec access times. Switch configuration
information is provided to the PM3351 using a single EPROM or EEPROM; only one
EPROM is required in a multiple PM3351/PM3350 system.

The ELAN 1x100 device is implemented in a high-density, low-voltage CMOS
technology for low cost and high performance. It is available in a 208-pin Quad Flat
Pack, and is ideally suited for compact, low-cost desktop, workgroup and departmental
Ethernet switching applications.

DEVICE DATA
Introduction

The ELAN 1x100 (PM3351) offers a complete system-level solution, integrating all
required elements (except frame/address memory and transceiver logic) in a single
high-density VLSI chip. It is a true single-chip switch; all the required functions,
including management, RMON-level statistics collection, spanning tree support and
self-configuration, are performed by the ELAN 1x100 without need for external CPUs or
logic. In addition, the functions required for expandability are also integrated into the
device.

The ELAN 1x100 is built around a RISC CPU based switching processor core which is
closely coupled with a multi-channel DMA controller, MAC-layer interface logic, FIFOs,
a PCI-based expansion port and a flexible memory controller.

Switch Processor

An on-chip Switch Processor is primarily responsible for performing the Ethernet / IEEE

802.3 frame routing functions, and can switch packets arriving simultaneously from the
single100BaseT port and the expansion port at full wire rates using address tables that
it creates and maintains in external local memory. Store-and-forward switching is

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PM3351 ELAN 1X100

DATA SHEET
PMC-970113 ISSUE 3 SINGLE PORT FAST ETHERNET SWITCH

performed, allowing the Switch Processor to detect CRC, length and alignment errors
and reject bad packets. The Switch Processor also supports IEEE 802.3
group/functional address handling. Address aging, topology change updates, and
statistics collection are performed by the Switch Processor as well.

The Switch Processor unit allows the device to support high-level capabilities. It
implements the full IEEE 802.1d spanning-tree transparent bridging protocol, which
allows the ELAN 1x100 to act as an expandable learning bridge, performing learning,
filtering and redirection at full speed. RMON statistics collection, plus a messaging
system to support master/slave communications in a multi-device switch, are also
implemented by the Switch Processor. When additional switch devices are connected
to the ELAN 1x100 expansion port, the Switch Processors in all PM3350 and PM3351
ELAN chips intercommunicate to transfer frames to each other and also transparently
support a distributed SNMP/RMON MIB.

Multi-channel DMA Processor

The on-chip DMA Controller contains four independent and concurrently operating
channels: one for receiving frames over the 100BaseT port; another for transmitting
frames over the same port; and two that are dedicated to the expansion port. The DMA
Controller operates under the control of the Switch Processor to transfer packets and
data at high speed between the 100BaseT port, the local memory and the expansion
port. It also computes 32-bit IEEE Frame Check Sequence (FCS) CRC remainders over
the transferred packets, allowing the Switch Processor to filter packets with errors and
generate CRCs for transmitted packets as required. Control logic is provided to support
full and half-duplex operation, as well as the handling of management traffic.

Ethernet/IEEE 802.3 MAC Interface

One Ethernet/IEEE 802.3u MAC-layer interface based on the Media Independent
Interface (MII) is built into the ELAN 1x100 chip. It connects directly to the external
100BaseT compatible PHY devices via the industry-standard MII interface, and
performs all of the MAC-layer processing tasks required for CSMA/CD networks. Both
full-duplex and half-duplex modes of operation are supported at 10 and 100 Mbit/s data
rates. The MAC interface includes independent receive and transmit FIFO buffers to
support sustained full wire rate operation.

Configuration and initialization of the attached 100Mbit/s PHY devices can be
performed using the MII management interface. This is accomplished by using the MII
pins MDIO and MDCLK to read, write and poll the management registers built into an
MII-compliant PHY device. This allows the PM3351 to support auto-negotiation, link
status, and other management operations on the attached PHY device(s), including the
Next Page functions. Serial management functions are implemented by the Switch
Processor for maximum flexibility and "standards-proofing".

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PM3351 ELAN 1X100

DATA SHEET
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Expansion Port

A 32-bit parity-checked PCI-based expansion port is provided to allow the ELAN 1x100
to communicate transparently with other PCI bus devices to implement switches that
have multiple 100Mbit/s and 10Mbit/s ports. The expansion port supports a maximum
throughput of over 1 Gbit/s, and requires only a single PAL or similar device serving as
a bus arbiter. A common protocol is used for inter-chip communication between the
ELAN 1x100 (PM3351) and ELAN 8x10 (PM3350). Packets received on an ELAN
1x100 MAC port that are destined for an external ELAN switch chip are transferred over
the expansion bus prior to transmission on the designated destination port. Broadcast
and multicast packets are handled using a two-level replication scheme, in which the
broadcast/multicast frame is first transferred to all of the external ELAN switch chips,
after which it is transmitted out the required destination ports without any further use of
the expansion bus. (In the case of an ELAN 1x100, only one port is present in each
destination device, and hence only one level of replication takes place.) In addition,
ELAN switch chips interconnected via the PCI bus exchange information to maintain the
distributed MIB.

The expansion port is compatible with the industry-standard Peripheral Component
Interconnect (PCI) specification version 2.1, which allows the ELAN 1x100 chip to be
directly interfaced to any host computer supporting the PCI bus. The host CPU can
then communicate with the ELAN 1x100 and control its functions, greatly expanding the
range of potential applications. The maximum PCI clock of 40 MHz is supported.

Local Memory Controller

The local memory is used for holding configuration information, MAC address tables
and statistics tables, node management data, packet buffers, and host communication
queues if a local host CPU is present. The ELAN 1x100 integrates a memory controller
that is capable of addressing and directly driving up to 16 MBytes of external memory,
divided into four banks of 4 MBytes each, with decoded selects for each bank.

1

Independent, software programmable access times may be set for each bank, allowing
a glueless interface to a mix of SRAM, , EEPROM, and EPROM in the same system.
An external memory timing generator may also be used if desired. The memory
controller accepts simultaneous requests from the Switch Processor, the DMA
processor, and the expansion port, and efficiently partitions the 100 MByte-per-second
memory port bandwidth among them.

The ELAN 1x100 is capable of auto-configuring after power-up via an 8-bit EPROM or
EEPROM connected to the memory port. Parameters (such as the MAC address, IP

1

When accessing SRAM and EEPROM devices, however, the actual limit is 1 Mbyte per bank, as the
upper bits of the internal address bus are not brought out to physical pins. The entire 4 Mbytes per bank is
only accessible when using DRAM memory types.

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PM3351 ELAN 1X100

DATA SHEET
PMC-970113 ISSUE 3 SINGLE PORT FAST ETHERNET SWITCH

address, configuration options, etc.) may be placed in this EPROM or EEPROM, and
will be loaded automatically by the ELAN 1x100.

1

Clocking and Test

The PM3351 is implemented in fully-static CMOS technology, and can operate at any
device clock frequency between 45 and 50 MHz (25 to 40 MHz for the expansion port
bus). The Switch Processor performs a comprehensive power on self test (POST), and
can report failure conditions and device status in a variety of ways (an 8-bit LED
interface register connected to local memory, writing to a host over the PCI bus, writing
to a serial port interface connected to local memory, etc).

1

The ELAN 1x100 follows the same configuration process as the ELAN 8x10 chip.

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PM3351 ELAN 1X100

M

DATA SHEET
PMC-970113 ISSUE 3 SINGLE PORT FAST ETHERNET SWITCH

TYPICAL SYSTEM APPLICATION
Low-cost 10/100 Mbit/s Switching Hub

The PM3351 chip can act as a high-speed server or backbone port in low-cost,
compact Ethernet switching hub applications. Such a hub can be created from one or
more PM3351 devices (one for every 100 Mbit/s port required), 1 to 7 PM3350 chips
(one for every eight 10 Mbit/s ports required), a bank of memory per device (60 nsec
DRAM for each PM3350, 15 ns SRAM for each PM3351) for holding frame buffers and
switching tables, a single 32k x 8-bit EEPROM device for configuration information, two
LXT944 10BaseT interface adapters per PM3350 chip, one LXT 970 100 Mbit/s PHY
device per PM3351, and suitable passive components (filters, transformers, crystal
oscillators, etc.). A block diagram of a typical 32-port 10BaseT stackable switching hub
with two 100 Mbit/s server/backbone ports is given in the following diagram. The
stacking connectors allow multiple switch assemblies to be seamlessly stacked.

8 x 10BaseT 10/100BaseT8 x 10BaseT

Quad

PHY

ELA N 8x10
8x10BaseT

Quad

PHY

PM 3350

EDO

DRAM

Quad

PHY

ELA N 8x10
8x10BaseT

PM 3350

PC I Backplane

ELA N 8x10

EEPRO

8x10BaseT

PM 3350

Quad

PHY

Quad

PHY

EDO

DRAM

8 x 10B aseT 8 x 10B aseT

Expandable 10/100 Mbit/s Ethernet Switch

Quad

PHY

ELA N 8x10

8 x 10BaseT

PM 3350

Quad

PHY

Quad

PHY

EDO

DRAM

10/100

PHY

ELA N 1x100

1x10/100

BaseT

PM 3351

EDO

DRAM

SRAM

ELA N 1x100

1x10/100

BaseT

PM 3351

10/100

PHY

10/100BaseT

SRAM

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PM3351 ELAN 1X100

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PRIMARY FEATURES AND BENEFITS

As an Ethernet switching/bridging solution, the PM3351 offers a number of benefits in a
low-cost switching hub:

Wire-speed frame switching.

Each PM3351 chip performs all of the functions required to implement a 10/100 Mbit/s
full/half duplex switch port at wire rates (ranging from 148,808 frames/sec for a frame
size of 64 bytes to 8130 frames/sec for a frame size of 1518 bytes). No additional logic,
microprocessors, etc. are necessary. In addition, the low cost and compact size
permitted by the single-chip PM3351 solution permits high-speed server or backbone
ports to be added to even entry-level switching hubs very simply.

Combined Input- and Output-buffered switch

The ELAN 1x100 implements a hybrid input-buffered/output-queued switching algorithm
which minimizes the possibility of frame lo ss, allows buffers to be allocate d on a
demand basis, and permits limits to be established to prevent any one memory
consumer from acquiring all system buffer memory. Frame buffer storage is allocated
within the external memory by the ELAN 1x100 from a central pool using an on-demand
method, employing linked lists of small, fixed-length buffers to hold variable sized
packets in order to maximize memory utilization.

Modular design.

Multiple PM3351 chips interconnect with no external glue logic (beyond a simple PCI
arbiter device), allowing a family of scalable switches to be built without redesign. When
used in conjunction with the PM3350 single-chip 8-port 10 Mbit/s Ethernet switch, a
10/100 Mbit/s switching hub can be realized at low cost. The 1 Gbit/s expansion port
bandwidth ensures that network capacity grows linearly as more chips from the ELAN
switch family are added.

Advanced switching features

The ELAN 1x100 implements per-frame lifetime control to ensure that transmit queues
are flushed properly in the event of bottlenecks at the output ports. Address aging is
handled on-chip, as is purging of the address table in the event of a network
reconfiguration. Broadcast storm rate limiting is implemented (with configurable rate
limits) to reduce the effects of high broadcast rates on the traffic flowing through the
switch. Two different methods of flow control are supported: backpressure for a half­duplex link and 802.3x Pause MAC Control frames for a full-duplex link. Flow control is
a user-selectable feature, with the thresholds and limits capable of being user­configured in order to minimize frame loss in heavily loaded networks. Backpressure is

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PM3351 ELAN 1X100

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performed by jamming (colliding with) incoming packets on the 100Mb port when the
port has no free receive buffers.

Spanning tree bridging capabilities

The ELAN 1x100 is capable of supporting the 802.1d spanning tree protocol, allowing it
to interoperate with IEEE-standard transparent bridges. The spanning tree protocol is
supported by the on-chip Switch Processor unit, and does not require an external CPU
for implementation, as the actual agent may be supported on the Switch Processor on
one of the PM3350 chips.

Management and monitoring support

The ELAN 1x100 (PM3351) maintains and collects RMON port and host statistics for all
learned MAC addresses at wire rates. These statistics may be retrieved either in-band
(via SNMP agent) or out-of-band (via the expansion bus). When multiple ELAN 1x100
and ELAN 8x10 chips are present in a system, they may be configured to
intercommunicate and create a distributed MIB in a transparent manner.

1

Status codes may be displayed on a set of LEDs (Light Emitting Diodes) during self-test
and operation at the system implementer's discretion. These status codes are output to
a register mapped into the ELAN 1x100 memory data bus at a specific address
location. Device failure during self-test, or specific operating conditions, may be
displayed using front-panel LEDs connected to the register.

An optional on-chip watchdog timer is provided by the ERST* output of the ELAN
1x100. The ERST* output of the device can be tied directly to the RST* input to provide
an optional system-wide watchdog reset. This facility permits the ELAN 1x100 to force
an automatic system restart whenever a fatal error is encountered during operation.

Autoconfiguration via Local PROM/EEPROM

The ELAN 1x100 automatically self-configures upon power-up using user-defined
parameters supplied in an external EPROM or EEPROM. The EPROM/EEPROM may
be connected to the memory bus and mapped to any address range; the ELAN 1x100
will automatically locate the EPROM or EEPROM and load the configuration
parameters from it. The ELAN 1x100 also contains hardware that enables it to write to
standard 3.3-volt EEPROM devices, thus permitting configuration information to be
changed dynamically.

1

The ELAN 8x10, if present in the system, can directly implement an optional on-chip SNMP agent on top
of an integral TCP/UDP/IP protocol stack, supporting SNMP and the RFC1493 bridge MIB, and supplying
SNMP access to the statistics gathered by the ELAN 1x100 (as well as the other devices in the system).
Alternatively, the system vendor may elect to disable the SNMP agent and access all chip statistics and
configuration variables directly from the expansion port.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 11

PM3351 ELAN 1X100

DATA SHEET
PMC-970113 ISSUE 3 SINGLE PORT FAST ETHERNET SWITCH

In a system with multiple ELAN devices, the master device (whether ELAN 1x100 or
ELAN 8x10) can load its configuration information and then configure the other ELAN
devices over the expansion bus, allowing configuration of the entire system with one
EPROM.

•

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 12

PM3351 ELAN 1X100

DATA SHEET
PMC-970113 ISSUE 3 SINGLE PORT FAST ETHERNET SWITCH

PIN DIAGRAM

The PM3351 is packaged in a 208-pin PQFP, with 135 signal pins, 36 VSS (gnd) pins,
31 VDD (3.3V) pins, and two 5V supply pins. The VSS and VDD pins are split between
internal (core) & i/o buffer pins (8 VSSI, 8 VDDI, 28 VSSO, & 23 VDDO pins). All pins
must be connected properly. Attention should be given to the 4 no-connect pins.

208-Pin Quad Flat Pack Pin Diagram

VSSI

VSSIncTST*

nc

VDDI

MINTR*

MDATA0

nc

MDATA1

VDDO

VSSO

MDATA3

MDATA2

MDATA4

VSSO

MDATA5

MDATA6

MDATA7

MDATA8

MDATA9

VDDO

VDDI

VSSO

MDATA10

MDATA11

MDATA12

VDDO

MDATA13

MDATA14

MDATA15

MDATA16

MDATA17

MDATA18

MDATA20

MDATA19

VSSO

VDDO

MDATA21

MDATA22

MDATA23

VSSO

MDATA24

MDATA25

MDATA26

MDATA27

MDATA28

VDDI

VSSI

MDATA29

MDATA30

MDATA31

BIAS5

VSSO

AD31

AD30

AD29

AD28

VDDO

VSSO

AD27

AD26

AD25

AD24

CBE3

VDDO

VSSO

FRAME*

DEVSEL*

IDSEL

TRDY*

IRDY*

VDDO

VSSO

AD23

AD22

AD21

AD20

AD19

AD18

VSSO
VDDO

VSSI

VDDI

AD17

AD16

CBE2

VSSO

REQ*

GNT*

INT*
VDDO
VSSO

AD15
AD14
AD13
AD12
AD11

VSSO

VDDO

AD10

AD9

AD8

CBE1

208

1

10

20

30

40

50

200

60

190

180

ELAN 1x100

PM3351

208 PQFP

70

80

100

160

150

140

130

120

110

VDDO
VSSO
MRAS*
MGWE
MWR0
MWR1
VDDO
VSSO
MWR2
MWR3
MRD*
MRDY*
MCS0*
VDDO
VSSO
MCS1*
MCS2*
MCS3*
MADDR0
MADDR1
MADDR2
MADDR3
VDDO
VDDI
VSSI
VSSO
MADDR4
MADDR5
MADDR6
MADDR7
MADDR8
MADDR9
VDDO
VSSO
MADDR10
MADDR11
MADDR12
MADDR13
VSSO
MADDR14
MADDR15
MADDR16
MADDR17
VDDO
VSSO
CRS
COL
TXD3
TXD2
TXD1
VSSI
VDDI

170

90

VSSO

VDDO

STOP*

PERR*

SERR*

PAR

AD7

AD6

AD5

AD4

AD3

AD1

AD0

AD2

VSSI

VSSO

VDDO

VDDI

VSSO

VDDO

CBE0

MEMCLK

VSSO

RST*

PCICLK

SYSCLK

VSSO

VDDO

nc

VSSI

MDC

VDDI

MDIO

VSSO

VDDO

CLK25

ERST*

VSSO

VDDO

RXD3

RXD2

RXD1

RXD0

RX_DV

RX_CLK

RX_ER

VDDO

TX_CLK

TXD0

TX_EN

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 13

BIAS5

VSSO

PM3351 ELAN 1X100

DATA SHEET
PMC-970113 ISSUE 3 SINGLE PORT FAST ETHERNET SWITCH

PIN DESCRIPTION

Pin Signal Pin Signal Pin Signal Pin Signal
1 BIAS5V 53 VDDO 105 VDDI 157 VDDI
2 VSSO 54 VSSO 106 VSSI 158 VSSI
3 AD31 55

4 AD30 56
5 AD29 57
6 AD28 58 PAR 110 COL 162 MDATA28

7 VDDO 59
8 VSSO 60 PCICLK 112 VSSO 164 MDATA27

9 AD27 61 VDDO 113 VDDO 165 MDATA26
10 AD26 62 VSSO 114 MADDR17 166 MDATA25
11 AD25 63 AD7 115 MADDR16 167 MDATA24
12 AD24 64 AD6 116 MADDR15 168 VSSO
13 CBE3 65 VDDI 117 MADDR14 169 VDDO
14 VDDO 66 VSSI 118 VSSO 170 MDATA23
15 VSSO 67 AD5 119 MADDR13 171 MDATA22
16

17
18 IDSEL 70 AD2 122 MADDR10 174 MDATA19

FRAME

DEVSEL

68 AD4 120 MADDR12 172 MDATA21

*

69 AD3 121 MADDR11 173 MDATA20

*

STOP
PERR
SERR

RST

*
*
*

*

107 TXD1 159 MDATA31
108 TXD2 160 MDATA30
109 TXD3 161 MDATA29

111 CRS 163 VSSO

19
20
21 VDDO 73 AD1 125 MADDR9 177 MDATA16

22 VSSO 74 AD0 126 MADDR8 178 MDATA15
23 AD23 75 CBE0 127 MADDR7 179 VSSO
24 AD22 76 MEMCLK 128 MADDR6 180 VDDO
25 AD21 77 VSSO 129 MADDR5 181 MDATA14
26 AD20 78 SYSCLK 130 MADDR4 182 MDATA13
27 AD19 79 VSSO 131 VSSO 183 VDDI
28 AD18 80 VDDO 132 VSSI 184 VSSI

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 14

TRDY

IRDY

*

*

71 VDDO 123 VSSO 175 MDATA18
72 VSSO 124 VDDO 176 MDATA17

PM3351 ELAN 1X100

DATA SHEET
PMC-970113 ISSUE 3 SINGLE PORT FAST ETHERNET SWITCH

Pin Signal Pin Signal Pin Signal Pin Signal
29 VSSO 81 CLK25 133 VDDI 185 MDATA12
30 VDDO 82 nc 134 VDDO 186 MDATA11
31 VSSI 83 MDIO 135 MADDR3 187 MDATA10
32 VDDI 84 VDDO 136 MADDR2 188 MDATA9
33 AD17 85 VSSO 137 MADDR1 189 MDATA8
34 AD16 86 VSSI 138 MADDR0 190 VSSO
35 CBE2 87 VDDI 139

36 VSSO 88 MDC 140
37
38
39
40 VDDO 92 RXD3 144
41 VSSO 93 RXD2 145 MRDY* 197 MDATA2

42 AD15 94 RXD1 146 MRD* 198 VSSO
43 AD14 95 RXD0 147

44 AD13 96 RX_DV 148
45 AD12 97 RX_CLK 149 VSSO 201 MDATA0

46 AD11 98 RX_ER 150 VDDO 202
47 VSSO 99 VDDO 151
48 VDDO 100 TX_CLK 152
49 AD10 101 TX_EN 153 MGWE* 205 nc

50 AD9 102 TXD0 154

REQ
GNT

INT

*
*

*

89 ERST* 141
90 VSSO 142 VSSO 194 MDATA5
91 VDDO 143 VDDO 195 MDATA4

MCS3
MCS2
MCS1

MCS0

MWR3
MWR2

MWR1
MWR0

MRAS

*
*
*

*

*

191 VDDO
192 MDATA7
193 MDATA6

196 MDATA3

199 VDDO

*

200 MDATA1

*

203 TST*

*

204 nc

*

206 nc

MINTR

*

51 AD8 103 BIAS5V 155 VSSO 207 VSSI
52 CBE1 104 VSSO 156 VDDO 208 VDDI

All VDD and VSS lines

•

be connected to the 3.3V supply and ground

must

respectively.

Standard decoupling practices should be followed for proper device operation.

•

The 4 pins marked as "nc" should be left as no-connects. They are intended

•

solely for factory use. Do not connect pins marked "nc" directly to either VDD or
VSS. If need be, the pins can be connected to either VDD or VSS through a
terminating resistor of value 1 k-ohm or greater.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 15

PM3351 ELAN 1X100

DATA SHEET
PMC-970113 ISSUE 3 SINGLE PORT FAST ETHERNET SWITCH

Functional Grouping

The following diagram shows the functional grouping of the PM3351 signal pins.

AD[31:0]

C/BE[3:0]*

PAR

FRAME*

TRDY*

IRDY*

STOP*

DEVSEL*

IDSEL

REQ*
GNT*

INT*
PERR*
SERR*

PCICLK

RST*

PM3351

PCI

ELAN 1x100

Local Memory Interface

ERST*

MD[31:0]

MA[17:0]

MCS[3:0]*

TXD[3:0]
TX_EN
TX_CLK
RXD[3:0]

RX_DV

MII

MRd*

MGWE*

MMWr[3:0]*

MRAS*

MRdy*

RX_CLK
RX_ER
CRS

COL
MDC
MDIO
SysClk
MemClk
Clk25
Mintr*
TST*

Pin description nomenclature:

• I input only

• O output only

• I/O bidirectional pin

• OD output only, open drain (requires external pull-up resistor to VDD).

The recommended pull-up resistance value for the open drain outputs is 2.7 k-ohm (this
is the recommended pull-up value suggested for PCI bus signals in the 5V signalling
environment).

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 16

PM3351 ELAN 1X100

DATA SHEET
PMC-970113 ISSUE 3 SINGLE PORT FAST ETHERNET SWITCH

PCI Expansion Bus Interface

Signal Name Size Type Description

AD[31:0] 32 I/O

CBE[3:0] 3 I/O

PAR 1 I/O

FRAME

DEVSEL

*

*

IRDY

*

TRDY

*

STOP

*

IDSEL 1 I

*

REQ

*

GNT

*

INT

*

PERR

*

SERR

PCICLK 1 I

1 I/O

1 I/O

1 I/O

1 I/O

1 I/O

1O

1I

1OD

1 I/O

1OD

Multiplexed PCI address/data bus, used by the PCI host or the PM3351 to
transfer addresses or data.

Command/Byte-Enable lines. These lines supply a command (during PCI
address phases) or byte enables (during data phases) for each bus transaction.

Address/data/command parity, supplies the even parity computed over the
AD[31:0] and CBE[3:0] lines during valid data phases; it is sampled (when the
PM3351 is acting as a target) or driven (when the PM3351 acts as an initiator)
one clock edge after the respective data phase.

Bus transaction delimiter (framing signal); a HIGH-to-LOW transition on this
signal indicates that a new transaction is beginning (with an address phase); a
LOW-to-HIGH transition indicates that the next valid data phase will end the
currently ongoing transaction.

Transaction Initiator (master) ready, used by the transaction initiator or bus
master to indicate that it is ready for a data transfer. A valid data phase ends

*

with data transfer when both IRDY
same clock edge.

Transaction Target ready, used by the transaction target or bus slave to indicate
that it is ready for a data transfer. A valid data phase ends with data transfer

*

when both IRDY
Transaction termination request, driven by the current target or slave to abort,

disconnect or retry the current transfer.
Device acknowledge: driven by a target to indicate to the initiator that the

address placed on the AD[31:0] lines (together with the command on the
CBE[3:0] lines) has been decoded and accepted as a valid reference to the
target's address space. Once asserted, it is held asserted until FRAME
deasserted; otherwise, it indicates (in conjunction with STOP
target-abort.

Device identification (slot) select. Assertion of IDSEL signals the PM3351 that it
is being selected for a configuration space access.

Bus request (to bus arbiter), asserted by the PM3351 to request control of the
PCI bus.

Bus grant (from bus arbiter); this indicates to the PM3351 that it has been
granted control of the PCI bus, and may begin driving the address/data and
control lines after the current transaction has ended (indicated by FRAME

*

and TRDY* all deasserted simultaneously).

IRDY
Interrupt request. This pin signals an interrupt request to the PCI host. The INT

pin should be tied to the INTA* line on the PCI bus.
Bus parity error signal, asserted by the PM3351 as a bus slave, or sampled by

the PM3351 as a bus master, to indicate a parity error on the AD[31:0] and
CBE[3:0] lines.

System error, used by the PM3351 to indicate to the PCI central resource that
there was a parity error on the AD[31:0] and CBE[3:0] lines during an address
phase.

PCI bus clock; supplies the PCI bus clock signal to the PM3351.

and TRDY* are sampled asserted on the same clock edge.

and TRDY* are sampled asserted on the

*

is

*

and TRDY*) a

*

,

*

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 17

PM3351 ELAN 1X100

DATA SHEET
PMC-970113 ISSUE 3 SINGLE PORT FAST ETHERNET SWITCH

RST

*

1I

PCI bus reset (system reset). Performs a hardware reset of the ELAN 1x100
and associated peripherals when asserted. The RST* input uses a Schmitt
trigger to accommodate slow rise and fall times, allowing a simple RC network
to be used to provide power-on reset capability.

MII Interface Pins

Signal Name Size Type Description

TXD[3:0] 4 O

TX_EN 1 O

TX_CLK 1 I

RX_DV 1 I

RXD[3:0] 4 I

RX_CLK 1 I

RX_ER 1 I

CRS 1 I

MII transmit data. TXD[3:0] is the nibble-wide MII transmit data bus. TXD[3:0]
transitions synchronously to the rising edge of TX_CLK. If TX_EN is asserted
then the TXD[3:0] bus has valid data which is to be accepted for transmission
by the PHY device.

MII transmit enable. Asserted by the PM3351 to indicate to the PHY device that
the TXD[3:0] bus has valid data. TX_EN is asserted with the first nibble of
preamble and remains continuously asserted throughout the frame. TX_EN is
negated prior to the first TX_CLK following the final nibble of the frame. TX_EN
is synchronous with respect to TX_CLK.

MII transmit clock. TX_CLK is a continuous clock that provides the timing
reference for the TX_EN and TXD[3:0] signals output from the PM3351.
TX_CLK is a nibble rate clock; an MII transceiver operating at 100Mbit/s must
provide a TX_CLK frequency of 25 Mhz.
For improved noise immunity this input buffer uses a Schmitt trigger.

MII receive data valid. RX_DV is an input that indicates that the PHY is
presenting recovered and decoded nibbles on the RXD[3:0] pins. In order for a
received frame to be accepted by the PM3351, RX_DV must be asserted prior
to or coincident to the first nibble of the Start of Frame Delimiter being driven on
RXD[3:0]; it must remain continuously asserted until after the rising edge of
RX_CLK when the last nibble fo the CRC is driven on RXD[3:0]. RX_DV is
synchronous with respect to RX_CLK.

MII receive data bus. RXD[3:0] is the nibble-wide MII receive data bus.
RXD[3:0] transitions synchronously to the rising edge of RX_CLK. The PM3351
samples RXD[3:0] on every rising edge of RX_CLK that RX_DV is asserted.
RXD[3:0] is ignored if RX_DV is deasserted.

MII receive clock. RX_CLK is a continuous clock that provides the timing
reference for the RX_DV, RX_ER, and RXD[3:0] signals input to the PM3351.
RX_CLK is a nibble rate clock; an MII transceiver operating at 100Mbit/s must
provide an RX_CLK frequency of 25 MHz during frame reception.
For improved noise immunity this input buffer uses a Schmitt trigger.

MII receive error. RX_ER is driven by the PHY for one or more RX_CLK periods
to indicate to the PM3351 that an error has occurred in the frame being
received. The PM3351 samples RX_ER on the rising edge of RX_CLK only if
RX_DV is asserted; all special code groups generated on RXD while RX_DV is
deasserted are ignored. RX_ER is synchronous with respect to RX_CLK.

MII carrier sense. CRS is an input that indicates that the physical media is non­idle, either because of transmit or receive activity. In full-duplex mode CRS is
ignored. The PHY is not required to have CRS transition synchronously to
either TX_CLK or RX_CLK.

The PM3351 samples CRS only on the rising edge of
the carrierSense variable in the MAC Deference process (see 802.3 spec
clauses 4.2.8 and 22.1.3.2).

TX_CLK

. It is used as

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 18

PM3351 ELAN 1X100

DATA SHEET
PMC-970113 ISSUE 3 SINGLE PORT FAST ETHERNET SWITCH

COL 8 I

MDIO 1 I/O

MDC 1 O

MII collision detect. COL is an input that indicates that a collision has occurred
on the physical media. In full-duplex mode COL is ignored. The PHY is not
required to have COL transition synchronously to either TX_CLK or RX_CLK.
The PM3351 only samples COL on the rising edge of TX_CLK.

MII management data input/output.MDIO is the bidirectional MII management
port data pin. MDIO is driven synchronously to MDCLK and is sampled on the
rising edge of MDCLK. When a management frame is not being transferred,
MDIO is not driven.

In order to implement the PHY detection feature via the MII mechanical
interface the MDIO pin should be externally pulled down to VSS through a 2.0­kohm +/-5% resistor.

MII management data clock. MDC is an aperiodic signal that is used as a
timing reference for the MDIO pin. MDC is continuously driven by the PM3351;
it is asserted only during management frame activity. MDC uses the SYSCLK
input as a timing reference.

Local Memory Interface

Although the on-chip local memory interface is designed to operate with various
memory types the memories intended to be used with the PM3351 are -15ns SRAM
and -150ns PROM/EPROM/EEPROM. EDO DRAM is supported for management and
custom applications, but is not intended to be used for standard switching.

Signal Name Size Type Description

MDATA[31:0] 32 I/O

MADDR[17:0] 18 O

MCS[3:0]

MRAS

*

*

4O

1O

Memory data bus. MDATA[31:0] carries the data driven to the external local
memory by the PM3351 during local memory writes, and the data sent back to
the PM3351 by the memory devices during local memory reads.

In addition, configuration information is latched from the MDATA[31:0] lines
during ELAN 1x100 reset and loaded into an internal configuration register;
either pullup-pulldown resistors or tristate buffers (enabled by the RST
drive configuration data on to the MDATA[31:0] lines during reset.

All MDATA[31:0] pins have internal pullups.
Memory address bus; supplies a word-aligned address to the external memory

devices (i.e., address bits 19 through 2 of the 24-bit byte address generated by
the internal PM3351 logic), and thus select a single 32-bit word to be read or
written. Up to 1 MB of memory may be directly addressed in each bank using
these address lines.

Memory bank chip selects. The MCS[3:0]
banks (each bank has maximum depth of 4 megabyte). They are decoded
directly from the most significant 2 bits (bits 23 and 22) of the 24-bit physical
byte address generated by the internal PM3351 logic, and are synchronous to
MEMCLK.

DRAM Row Address Strobe output; supplies the Row Address Strobe (RAS)
signal to one or more external DRAM banks. It is asserted to latch the row
address (supplied on the MADDR lines) into the DRAM array, and allow the
column address to be output one cycle later.
NOTE- can be left as a no-connect output if not using DRAM.

*

input)

*

outputs select one of four memory

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 19

PM3351 ELAN 1X100

DATA SHEET
PMC-970113 ISSUE 3 SINGLE PORT FAST ETHERNET SWITCH

*

MRD

MWR[3:0]

MGWE* 1 O

MRDY

MINTR

*

*

*

1O

4O

1I

1I

Memory read enable. This output signals the external memory banks that a
read is being performed and data should be output on the MDATA[31:0] lines
from the specified address. The MRD* output may be tied to the OE* inputs of
standard memory devices.

Memory write enables, used by the PM3351 to enable the data presented on
individual byte lanes of MDATA[31:0] to be individually written to memory.

*

MWR[0]
and so on. The MWR[3:0]* outputs should be connected to the appropriate
byte write enables.

Gobal memory write enable. This signal is used to signal that a write access is
occurring, and should be connected to the WE* inputs of dual CAS
asynchronous DRAM devices.
NOTE- can be left as a no-connect output if not using DRAM

Memory ready input. If an external memory timing generator is used, it can be
connected to the MRDY* input to force the PM3351 to insert wait states into
memory accesses. If the MRDY
MADDR[15:0], MCS[3:0]
(as well as MDATA[31:0] for memory writes).The MRDY* input is only sampled
by the PM3351 when performing an SRAM-type access; it is ignored for all
other memory types.

This feature is not tested as part of the fuctional test program of the device.
Therefore, MRDY* must be tied low (to logic 0) to ensure correct operation.

Local interrupt input. The MINTR* may be used to provide an interrupt input to
the ELAN 1x100 in special applications. If the MINTR* input is not used it
should be tied HIGH.
For improved noise immunity this input buffer uses a Schmitt trigger.

corresponds to MDATA[7:0], MWR[1]* corresponds to MDATA[15:8],

*

line is deasserted, the PM3351 will hold the

*

, MRD* and MWR[3:0]* lines at their present values

Clock Inputs and Outputs

Signal Name Size Type Description

SYSCLK 1 I

MEMCLK 1 O

CLK25 1 O

50 MHz master device clock input, This should be driven by a 50 MHz
symmetrical clock source with a duty cycle between 40% and 60%. It is re-timed
and driven out on the MEMCLK line, and is also used in the internal device
logic.
For improved noise immunity this input buffer uses a Schmitt trigger.

50 MHz clock derived from SYSCLK; supplies the re-timed 50 MHz clock (input
on the SYSCLK pin) to external devices.

25 MHz clock output. The 50 MHz input clock is internally divided by two and
output as a symmetrical 25 MHz clock on the CLK25 output; this clock may be
used as a clock reference input to an external PHY device.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 20

PM3351 ELAN 1X100

DATA SHEET
PMC-970113 ISSUE 3 SINGLE PORT FAST ETHERNET SWITCH

Miscellanous Inputs and Outputs

Signal Name Size Type Description

BIAS5V 1 I

TST* 1 I

ERST* 1 OD

The 5 volt bias pin must be connected to 5.0 volts for the input and bi-directional
pins to be 5 volt tolerant. This pin may be tied to VDD provided the maximum
static signal level is below VDD + 0.3V.

During power-up, the voltage on the BIAS5V pin must be kept equal to or
greater then the voltage on all input pins to avoid damage to the device. In
addition, the voltage on the BIAS5V pin is to be kept greater than or equal to
the voltage on the VDD pins.

Test select signal used for production testing. It must be tied HIGH for correct
operation.

External reset output. The ERST* pin is driven low by the ELAN 1x100 to reset
other components in the system. This output is asserted for a pre-set duration
(10 milliseconds) upon the detection of a falling edge on the RST* input, or
when the ELAN 1x100 senses a condition requiring a system hardware reset. It
is an open-drain output, and should be pulled up using a 2.7k-ohm resistor. The
ERST* output may be tied directly to the RST* input to implement a debounce
function in pushbutton reset applications. (Note that the ERST* output should be
left unconnected in host-based applications where the ELAN 1x100 must not be
allowed to reset the host CPU.)

Notes on Pin Description:

1. All inputs and bi-directionals present minimal capacitive loading and operate at
TTL logic levels.

2. All digital outputs and bi-directionals have 2 mA D.C. drive capability.

3. Pins MDATA[31:0], MINTR*, TST*, GNT*, and RST* have internal pull-up
resistors.

4. The VSSI and VSSO ground pins are not internally connected together. Failure
to connect these pins externally may cause malfunction or damage the part.

5. The VDDI and VDDO power pins are not internally connected together. Failure
to connect these pins externally may cause malfunction or damage the part.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 21

PM3351 ELAN 1X100

DATA SHEET
PMC-970113 ISSUE 3 SINGLE PORT FAST ETHERNET SWITCH

DC CHARACTERISTICS
Absolute Maximum Ratings

Maximum rating are the worst case limits that the device can withstand without
sustaining permanent damage. They are not indicative of normal mode operation
conditions.

Parameter Symbol Value Units

Supply Voltage Vdd -0.3 to +7.0 Vdc

BIAS5V pin voltage
with respect to Vss

Input Voltage Vin V
Input Current Iin +/-10 mAdc

Static Discharge

Voltage

Latch-Up Current ±80 mA

Lead Temperature +220 °C

Storage Temperature Tst -45 to +125 °C

Junction Temperature Tj +125 °C

Vbias5V Minimum: VDD – 0.3V

Maximum: 5.5V

+0.3 Vdc

bias5v

±1000 V

Vdc

Recommended Operating Conditions

Parameter Symbol Value Unit

s

Min Nom Max

Supply Voltage Vdd +3.13 +3.30 +3.47 Vdc

BIAS5V Voltage Vbias5v +4.75 +5.0 +5.25 Vdc

Operating Ambient Temp. Ta 0 +70 °C

NOTE: the PM3351 has been characterized over the industrial temperature range (Ta =

-40°C to +85°C). All DC and AC parametrics met the limits presented in the following
tables. In addition the package thermal characteristics of the 208 pin PQFP package
and power consumption of the device are such that the device can be operated without
any forced air (i.e. still air) over the full commercial tem perature range; however, if
operating over the industrial temperature range (which has a maximum ambient
temperature of +85 °C) a minimum airflow of 100 linear feet per minute is required.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 22

PM3351 ELAN 1X100

DATA SHEET
PMC-970113 ISSUE 3 SINGLE PORT FAST ETHERNET SWITCH

D.C. Characteristics

DC characteristics are specified over recommended operating conditions (TA = 0°C to
+70°C, VDD = 3.3 V ±5%, V

Parameter Description TTL I/Os PCI I/Os Units

Vih Input High Voltage 2.0 Vdd+0.52.0 Vdd+0.5Vdc

Vil Input Low Voltage -0.5 0.8 -0.5 0.8 Vdc

Voh Output High Voltage (Vdd = min, IOH =

Vol Output Low Voltage (Vdd = min, IOL =

lil Input Low Leakage Current, Note 3 -10 10 -10 10 µA

lih Input High Leakage Current, Note 3 -10 10 -10 10 µA

lilpu Input Low Current (Pull ups, VIL =

lihpu Input High Current (Pull ups, VIH = Vdd,

lddop Supply Current, Vdd = 3.47 MHz,

Outputs Unloaded, SYSCLK = 50MHz

= 5.0V ±5%).

BIAS

-2 mA, Note 2)

-2 mA, Note 2)

GND, Note 4)

Note 4)

Min Max Min Max

2.4 Vdd 2.4 Vdd Vdc

00.400.4Vdc

+100 +20 µA

-10 +10 µA

450 mA

Notes on D.C. Characteristics:

1. Negative currents flow into the device (sinking), positive currents flow out of the
device (sourcing).

2. Output pin or bidirectional pin. Voh not measured on Open Drain outputs.

3. Input pin or bidirectional pin without internal pull-up resistor.

4. Input pin or bidirectional pin with internal pull-up resistor.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 23

PM3351 ELAN 1X100

DATA SHEET
PMC-970113 ISSUE 3 SINGLE PORT FAST ETHERNET SWITCH

AC CHARACTERISTICS

AC characteristics are specified over recommended operating conditions (TA = 0°C to
+70°C, VDD = 3.3 V ±5%, V

= 5.0V ±5%).

BIAS

The PM3351 only supports a 5V signalling environment.

Notes on Input Timing:

1. When a set-up time is specified between an input and a clock, the set-up time is
the time in nanoseconds from the 1.4 Volt point of the input to the 1.4 Volt point
of the clock.

2. When a hold time is specified between an input and a clock, the hold time is the
time in nanoseconds from the 1.4 Volt point of the clock to the 1.4 Volt point of
the input.

Notes on Output Timing:

1. Output propagation delay time is the time in nanoseconds from the 1.4 Volt
point of the reference signal to the 1.4 Volt point of the output.

2. Maximum and minimum output propagation delays are specified with a 50 pF
load on the outputs, unless otherwise noted.

3. Output tristate delay is the time in nanoseconds from the 1.4 Volt point of the
reference signal to ±300mV of the termination voltage on the output. The test

load is 50Ω to 1.4V in parallel with 10 pf to GND.

Notes on Typical Values

AC parameters shown as Typical in the following tables are tested for functionality
under typical conditions. No guarantees are implied for maximum or minumum
performance.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 24

PM3351 ELAN 1X100

DATA SHEET
PMC-970113 ISSUE 3 SINGLE PORT FAST ETHERNET SWITCH

PCI Bus Interface

Parameter Description MIN Typ MAX Units

Tpsu Setup time of all PCI inputs from PCICLK rising 7 nsec

Tph Hold time of all PCI inputs from PCICLK rising 1 nsec

Tpon Minimum Float to active delay of all outputs from

PCICLK rising

Tpoff Maximum Active to float delay of all outputs from

PCICLK rising

Tpval Signal valid of all outputs from PCICLK rising 2 13 nsec

Trstoff RST* active to output float delay 40 nsec

2 nsec

28 nsec

PCICLK

Tpsu

PCI Inputs

Tph

PCI Outputs

Tpon

NOTES:
(1) PCI inputs are considered to be those signals that are driven
by an external PCI device, while PCI outputs are signals that
are driven by the PM3351. Note that many of the PCI signals
are treated as outputs in some cycles and inputs in others.

Tpoff

Tpval

PCI Bus Interface Timing

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 25

PM3351 ELAN 1X100

DATA SHEET
PMC-970113 ISSUE 3 SINGLE PORT FAST ETHERNET SWITCH

MII Interface

Parameter Description MIN MAX Units

Ftsc TX_CLK frequency 0 25 MHz

Ttch/Ttcl TX_CLK duty cycle (high/low) 35 65 Percent

Ttod Output delay from TX_CLK rising to TXD[3:0],

TX_EN

Ftsc

TX_CLK

Ttod

TXD[3:0],

TX_EN

020nsec

MII Interface Transmit Signals

Parameter Description MIN MAX Units

Frpc RX_CLK frequency 0 25 MHz

Trch/Trcl RX_CLK duty cycle (high/low) 35 65 Percent

Trpsu RXD[3:0], RX_DV, RX_ER setup to RX_CLK 8 nsec

Trph RXD[3:0], RX_DV, RX_ER hold to RX_CLK 8 nsec

Frpc

RX_CLK

Trpsu Trph

RXD[3:0]

RX_DV,

RX_ER

Trpsu Trph

MII Interface Receive Signals

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 26

PM3351 ELAN 1X100

DATA SHEET
PMC-970113 ISSUE 3 SINGLE PORT FAST ETHERNET SWITCH

Parameter Description MIN Typ MAX Units

Tmdch

Tmdcl
Tmdcp
Tmdo1

Min MDC high pulse width (Cload = 390 pF)

Min MDC low pulse width (Cload = 390 pF)

Min MDC period (Cload = 390 pF)

Min MDIO (output delay) to posedge MDC

1

1

1

1

160 nsec
160 nsec
400 nsec

20 nsec

Cload = 470 pF. Measured from Vil,max (0.8V)

or Vih,min(2.0V)

Tmdo2

Min MDIO (output delay) to posedge MDC

1

20 nsec

Cload = 470 pF. Measured from Vil,max (0.8V)

or Vih,min(2.0V)

Tmdisu Min MDIO (input) to MDC setup time 100 nsec

Tmdih Min MDIO (input) to MDC hold time 0 nsec

Notes:

1. Tested at 50 pF in production test and derated.

Tmdcp

Tmdch Tmdcl

MDC

Tmdo1

MDIO,

as output

Tmdo2

Tmdisu

MDIO,

as intput

Tmdih

MII Management Data Signals

MDIO is driven by
PM3351, sampled
by PHY

MDIO is driven by
PHY, sampled by
PM3351

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 27

PM3351 ELAN 1X100

]

DATA SHEET
PMC-970113 ISSUE 3 SINGLE PORT FAST ETHERNET SWITCH

Memory Interface

15 nS SRAM AC Timing

Parameter Description MIN Typ MAX Units

tCKP MCLK period 20 ns

tMAOD MADDR[17:0] delay from SYSCLK (read, first

cycle)
tCEW MCS*[3:0] pulse width 35 ns
tOEW MRD* pulse width 35 ns

tMDIS MDATA[31:0] setup to SYSCLK (read, second

4ns

cycle)

tRDH MDATA[31:0] hold from MRD* rise (read,

0ns

second cycle)

MDATA[31:0] hold from MCS*[3:0] rise (read,

second cycle)

tWAW MADDR[17:0] setup to MWE*[3:0] rise 20 ns

tWAH MADDR[17:0] hold from MWE*[3:0] rise 0 ns

tWP MWE*[3:0] pulse width (write, second cycle) 15 ns
tWDS MDATA[31:0] setup to MWE*[3:0] rise 8 ns
tWDH MDATA[31:0] hold to MWE*[3:0] rise 0 ns

21 ns

SR AM T im ing: Read/W rite cycle

Read
cycle 1

Y

LK

MCLK

MWE*[3:0
MCS[n]*

*

MRD

ADDR[17:0]

M D A TA [31:0]

*

MRDY

NO T ES: (1) T he functional w aveform s above are consistent w ith
no wa it states inserted. (that is, with MR D Y* being T TL low during
the read cycle). The M R D Y* tim in g w aveform is show n to highlig ht

p

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 28

tC K P

Read
cycle 2

tM D IS

tM R W

tRDH

Write
cycle 1

Write
cycle 2

tC E W

D2

tW D S

tW A H

tW D H

DON'T CARE

UNDEFINED

PM3351 ELAN 1X100

0

DATA SHEET
PMC-970113 ISSUE 3 SINGLE PORT FAST ETHERNET SWITCH

150 ns EEPROM/EPROM AC Timing

Parameter Description MIN Typ MAX Units

tCKP MCLK period 20 ns

tMAOD Max MADDR[17:0] delay from SYSCLK (read, first cycle) 21 ns

tCEW Min MCS*[3:0] pulse width 190 ns
tOEW Min MRD* pulse width 190 ns

tMDIS Min MDATA[31:0] setup to SYSCLK (read, 11th cycle) 10 ns

tRDH Min MDATA[31:0] hold from MRD* rise (read, 12th cycle)

(by design, data is latched internally in the cycle before

the rise of MRD*)

tWAW Min MADDR[17:0] setup to MWE*[3:0] rise 190 ns

tWAH Min MADDR[17:0] hold from MWE*[3:0] rise 40 ns

tWP Min MWE*[3:0] pulse width (write, second cycle) 190 ns
tWDS Min MDATA[31:0] setup to MWE*[3:0] rise 180 ns
tWDH Min MDATA[31:0] hold to MWE*[3:0] rise 15 ns

0 ns

EEPROM/EPROM WRITE CYCLE

0ns 100ns 200ns 3

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

SYSCLK

MCLK

M W E *[3 :0 ]

M C S *[3 :0 ]

MRD*

TMAOD TWAH

ADDR[17:0]

DATA[31:0]

TWAW

TWP

TWDS

TCEW

TWDH

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 29

PM3351 ELAN 1X100

DATA SHEET
PMC-970113 ISSUE 3 SINGLE PORT FAST ETHERNET SWITCH

EEPROM/EPROM READ CYCLE

0ns 100n 200n 3

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

SYSCL

MCL

MWE*[3:

MCS*[3:

MRD

TMAO

MADDR[17:

MDATA[31:

TCE

TOE

TRD

TMDI

EDO DRAM (not used in standard switching applications)
60 ns EDO DRAM AC Timing

Parameter Description MIN Typ MAX Units

tCKP MCLK period 20 nsec
tARD Min Row address stable to MRAS* fall delay 15 nsec

tRAW Min Row address width 35 nsec

tACD Min Column address stable to CAS* fall delay 15 nsec

tCAW Min Column address width 35 nsec

tCP Min CAS* period 35 nsec

tCPL Min CAS* low time 15 nsec
tWDS Min Write data setup to CAS* fall 15 nsec
tWDH Min Write data hold to CAS* fall 15 nsec

tRDS Min Read data setup to CAS* fall 20 nsec
tRDH Min Read data hold from CAS* fall 0 nsec
tREC Min Read data HiZ to write data drive 15 nsec

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 30

PM3351 ELAN 1X100

DATA SHEET
PMC-970113 ISSUE 3 SINGLE PORT FAST ETHERNET SWITCH

60 ns Single CAS EDO DRAM

tCKP

MCLK

MADDR[19:0]

MRAS*

MCS[n]*

MRD*

tRAW tCAW

ROW COL1 COL2 COL3 COL4

tARD tACD

tCP

tCPL

MDATA[31:0]

MCLK

MADDR[19:0]

MRAS*

MCS[n]*

MWR[3:0]*

MDATA[31:0]

MCLK

MADDR[19:0]

MRAS*

MCS[n]*

MWR[3:0]*

D1

tRDS

tRDH

4-Word Burst Read

tCKP

tRAW tCAW

ROW COL1 COL2 COL3

tARD tACD

tCP

tCPL

D1 D2 D3 D4

tWDS tWDH

4-Word Burst Write

tCKP

tRAW tCAW

ROW COL1 COL2

tARD tACD

tCP

tCPL

D2 D3 D4

COL4

MRD*

MDATA[31:0]

DRP / 12-96

D1

tREC

1-Word Read Followed by Write

D2

tWDS tWDH

DON'T CARE

UNDEFINED

Notes:
(1) Pin definitions shown above are for single CAS DRAM. Dual CAS DRAM is supported by selecting the

MDCAS bit in the memory configuration register. In this mode, the CAS signals are driven by
MWE*[3:0] and the RAS signals are driven by MCS*[3:0].

(2)

Asserting the MSLO bit in the memory configuration register extends the CAS low time to support 80

nS DRAM

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PM3351 ELAN 1X100

DATA SHEET
PMC-970113 ISSUE 3 SINGLE PORT FAST ETHERNET SWITCH

Clocking

Parameter Description MIN TYP MAX Units

Fck SYSCLK frequency
Tch SYSCLK High Pulse Width
Tcl SYCLK Low Pulse Width
Fpck PCICLK frequency
Tpch PCICLK High Pulse Width
Tpcl PCICLK Low Pulse W i dth
Fck25 CLK25 frequency
Trst RST* active time after PCICLK and SYSCLK

stable

1

2

3

5 50.0 50.5 MHz
8nsec
8nsec

0 40 40.5 MHz
11 nsec
11 nsec

Fck/2 MHz

10 usec

Notes:

1. The minimum clock frequency for production test is 5 MHz. In actual operation,
the minimum SYSCLK frequency is 1 MHz if DRAM present (this is to refresh
local DRAM memory); otherwise the minimum SYSCLK frequency is 0 MHz,
reflecting completely static operation. The nominal frequency of 50 MHz must
be provided for full throughput.

2. The minimum clock frequency for PCICLK reflects completely static operation.
The nominal frequency of 40 MHz must be provided for full throughput.
Minimum production test at 5.0 MHz

3. Guaranteed by design.

Miscellaneous

Parameter Description MIN MAX Units

Tmisu MINTR* setup to posedge SYSCLK 10 nsec

Tmih MINTR* hold to posedge SYSCLK 0 nsec

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 32

PM3351 ELAN 1X100

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PMC-970113 ISSUE 3 SINGLE PORT FAST ETHERNET SWITCH

FUNCTIONAL DESCRIPTION
Overview

This section will provide an overview of the PM3351 ELAN 1x100 components, the
device initialization and configuration process, the structures built and used by the
device to perform its functions, and a brief description of how packets are switched by
the device.

System Components

In order to describe the functions and operation of the ELAN 1x100 device, it is first
necessary to discuss the operating environment that is intended to be built around it. A
typical simple switching subsystem utilizing the ELAN 1x100 device consists of:

1. The ELAN 1x100 device itself. (Clearly, a complete system will include more
than a single ELAN 1x100 device, but this is not shown in the diagram below.)

2. A set of SRAM devices that provide the operating memory for the ELAN 1x100.
This memory should be mapped to the lowest bank of the ELAN 1x100 address
space (i.e., addresses starting at 0x000000 hex). The amount of SRAM
provided is a system-dependent parameter; a minimum system with about 150
kB of buffer space and around 1200 MAC addresses in the address table
requires 512kB of SRAM. SRAM requirements for this and other system
configurations may be computed using parameters supplied later in this
document.

3. An EPROM containing the bootstrap image for the ELAN 1x100 (i.e., the
operating firmware, operating parameters, and system initialization code) if this
ELAN device is designated as the system master. This EPROM is mapped to
the second lowest bank of the ELAN 1x100 memory address space (the 4 MB
address range starting at address 0x400000 hex.) The size of the EPROM is
highly dependent on the operating configuration of the ELAN 1x100, with the
minimum requirement being 32 kB.

4. External transceiver devices that implement the PHY layer functions required for
100BaseT Ethernet.

5. An LED register, connected to a bank of eight LEDs, that may be used to report
status information for diagnostic purposes if required. The LED register is
mapped into the third bank of ELAN 1x100 memory address space, starting at
0x800000 hex.

6. A system voltage monitor or other means of asserting a system reset for a
specified time after the power supply voltage has stabilized, plus, if desired, a
pushbutton switch for forcing a system reset after power-up.

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PM3351 ELAN 1X100

DATA SHEET
PMC-970113 ISSUE 3 SINGLE PORT FAST ETHERNET SWITCH

7. A set of pull-up and pull-down resistors that are connected to the ELAN 1x100
data bus in order to drive device configuration information on to the data bus
during system reset.

Note that the above subsystem description details a single ELAN 1x100 device in the
system. This subsystem is expected to work in tandem with similar ELAN 1x100 or
ELAN 8x10 subsystems to create an actual switch; however, the fundamental system
operation does not change as additional ELAN compatible devices are added.

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PM3351 ELAN 1X100

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PMC-970113 ISSUE 3 SINGLE PORT FAST ETHERNET SWITCH

System Block Diagram

The following diagram represents a high-level view of the simple switch subsystem
described above:

Power-On

Reset

RST* ERST*

TXD[3:0]
TX_EN
TX_CLK

50

MHz

Clock

PCI Bus

SYSCLK

ELAN 1x100

PM3351

MDATA[31:0]

MADDR[17:0]

MRD, MWR[3:0]

MCS[0]

MCS[1]

MCS[2]

RXD[3:0]
RX_DV
RX_CLK
RX_ER
CRS
COL
MDC
MDIO
COL[7:4]

MDATA[7:0]

Device
Config

Pull-up/

Pull-down

D A R/W CAS* D A OE* CS*

EPROM

SRAM

MDATA[7:0]

LED Register

Resistors

In the diagram above, the PHY device, the EPROM, the SRAM and the 50 MHz clock
oscillator are all implemented in a straightforward manner from off-the-shelf parts. The
device configuration resistors are merely resistor pull-ups and pull-downs that drive the

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PM3351 ELAN 1X100

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memory data bus lines to specific values during reset, as described later; the resistor
values used are not critical, and may range from 4.7k to 10k.

It is assumed that the minimum recommended configuration of 512 kilobyte of SRAM
and 32 kbytes of EPROM are used. A typical implementation would use four 128k x 8­bit 15 ns SRAM, together with a 256 kbit (32k x 8-bit) 150 ns EPROM. Larger memories
may also be used if more buffer space or MAC addresses are to be supported; if this is
done, the configuration parameters in the EPROM must be changed to reflect the
increased memory size. The SRAM and EPROM device types and speeds are defined
by the setting of the pull-up / pull-down resistors on the memory data bus during reset
time.

The power-on reset generator can be created either from discrete components, or from
a low-cost CPU monitor; the ERST* output from the ELAN 1x100 chip is strapped to the
reset signal to implement the watchdog capability of the ELAN device. Note that the
ERST* output may, as an alternative, used to signal some external processor that the
ELAN 1x100 device has encountered a fatal error condition requiring a software or
hardware reset; in this case, the ERST* output should be pulled up using a 2.7k
resistor.

The LED register is implemented using a simple 8-bit TTL register with a clock enable
that is tied to the indicated chip select output from the ELAN 1x100. Eight LEDs may be
connected to the outputs of this register to present the diagnostic status codes output
by the ELAN 1x100 firmware during self-test, system boot and operation. If a simple
TTL register is used, the LED register is effectively write-only; writes to this register will
modify the state of the LEDs, but reads from this register return invalid values. A read­back register can be used if this is a significant issue.

The first three chip select lines from the ELAN 1x100 (i.e., MCS[0]*, MCS[1]* and
MCS[2]*) are tied to the SRAM, the EPROM and the LED register, respectively; the
remaining chip select is unused. This maps the SRAM into the first bank of address
space, the EPROM into the second bank, and the LED register into the third bank. The
address map in the following subsection gives the 24-bit address ranges assigned to
each resource.

This system has only been presented to serve as a basis for the following discussion on
the device and system operation, and is not intended to serve as a complete example
or reference design. More details on actual system construction with the ELAN 1x100
may be found in the relevant application notes and reference design documents.

System Memory Map

The ELAN 1x100 device uses a single linear (flat) byte-addressable 16 MB address
space for accessing memory and memory-mapped devices. The external memory map
for the system described above is quite straightforward. From the point of view of the

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PM3351 ELAN 1X100

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local memory bus, it is as follows (note that the memory addresses shown increase
upwards):

0xffffff

0xc00000

0xbfffff

0x800004

0x800000

0x4fffff

0x420000

0x41ffff

Unused

Unused Bank 2

LED Register

Unused

Boot EPROM

(32 kB; occupies 128

kB)

Bank 3

Bank 1

0x400000

0x3fffff

Unused

0x100000

Bank 0

0x07ffff

System SRAM

(512 kB)

0x000000

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PM3351 ELAN 1X100

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Note that the 32 kB boot EPROM actually occupies 128 kB of address space. This is
because the EPROM is only 8 bits wide (i.e., a 32k x 8-bit configuration), and so is
connected to the least significant byte lane of the memory data bus. Hence each byte of
the EPROM takes up a full 32 bits worth of address space, leading to the 128 kB
requirement.

In a similar manner to the 8-bit wide EPROM, the LED register is mapped to the least
significant 8 bits of the data bus, but takes up a full 32 bits of address space. No other
device is shown as being mapped to the ELAN 1x100 address space in this simple and
minimal system; however, other devices (such as RS232-C serial ports) may be
interfaced as well, provided that firmware is developed to support them.

When viewed from the PCI bus, the ELAN 1x100 device appears to take up a 16 MB
block of contiguous addresses in the total 4 GB PCI address space. A virtually identical
memory map is presented to the PCI bus when accessing the ELAN 1x100 device as a
PCI slave (target), with the exception that a set of device control and communication
registers are implemented in the uppermost 64 kB of the 16 MB address space used by
the ELAN 1x100 device (note that the memory addresses shown increase upwards):

0xBBffffff

0xBBff0000

0xBBfeffff

0xBBc00000

0xBBbfffff

Rest of PCI Address

Space

Device Control

Registers

Unused

Unused Bank 2

Bank 3

0xBB800004

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LED Register

0xBB800000

0xBB4fffff

Unused

0xBB420000

0xBB41ffff

0xBB400000

0xBB3fffff

0xBB100000

0xBB07ffff

0xBB000000

Bank 1

Boot EPROM

(32 kB; occupies 128

kB)

Unused

Bank 0

System SRAM

(512 kB)

Rest of PCI Address

Space

The start address of the block occupied by the ELAN 1x100 is defined by the setting of
the memory base address register within the PCI configuration register space of the
ELAN 1x100 device, and is represented by the BB component of the addresses given
in the table above. The memory base address register may be set to any arbitrary value
via a PCI configuration write after system reset, provided that the base address is on a
16 MB boundary and that the ELAN 1x100 operating firmware parameters are set
consistently with the selected base address. Alternatively, the base address may be
set to a value between 0x00 and 0x0F, during reset, by the configuration registers

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PM3351 ELAN 1X100

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Device Internal Blocks

The ELAN 1x100 consists of the following major components: a Switch Processor, one
100Mbit/s full-duplex MAC interface, a DMA Controller, a memory controller and a PCI
expansion port.

Switch Processor

The Switch Processor is a 50 MHz proprietary RISC CPU that executes the firmware
required for carrying out all the frame switching and device control functions of the
ELAN 1x100. It is specifically designed to support LAN protocols at high speeds in a
closed embedded system environment. The Switch Processor contains various
hardware features that permit it to carry out all of its functions at maximum efficiency,
and is tightly coupled to the rest of the ELAN 1x100 device logic. The Switch Processor
interfaces to the rest of the ELAN 1x100 device via several dedicated hardware ports:

• It uses a special

control register access bus

to read or write any of up to 96 16­bit control registers that are implemented by the internal hardware units; these
registers are used to set configuration parameters in various ELAN 1x100 units,
read the unit status, set various operating parameters (such as address
pointers), and perform device self-test.

• It implements a set of thirteen level-sensitive

hardware interrupts

that are
connected to various blocks within the ELAN 1x100; these interrupts are the
primary task dispatching entity for the base switching code. Assertion of an
interrupt line causes the corresponding interrupt service routine (ISR) to begin
executing, and execution normally proceeds until the ISR has finished servicing
the unit that required attention.

• A set of 32

general-purpose outputs

and 15

general-purpose inputs

are
provided. These are connected to various low-level control and status signals
presented by various ELAN 1x100 internal logic blocks. The general-purpose
inputs and outputs considerably speed up the testing of the state of the logic
blocks and also the control of their functions, as multiple tests on inputs or
multiple modifications of outputs can be performed in a single instruction.

• A set of 16

coprocessor condition tests

are implemented by the Switch
Processor. These inputs are used to signal high-level device conditions
generated by various ELAN 1x100 functional units to the Switch Processor
firmware.

The internal and external registers implemented by the Switch Processor and the
associated ELAN 1x100 functional units, as well as the view of the debug registers from
the PCI bus interface, are presented in subsequent sections.

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The Switch Processor expects to locate its operating firmware as part of a

boot image

present in the external memory space. The format of the boot image is described later.

100Mbit/s Ethernet MAC Interface

A complete Ethernet/IEEE MAC-layer interface is built into the ELAN 1x100 chip,
communicating with external 100 Mbit/s transceivers via the on-chip MII port. The MAC­layer interface logic performs most of the processing tasks required by the IEEE
standard in hardware. In addition, the MAC interfaces contain FIFO buffers that
enhance throughput and reduce bandwidth loss due to frame delays. The MAC layer
interfaces also permits loopback testing of the external transceiver.

The PM3351 also supports the MII management interface to an MII compliant PHY
device. This is accomplished by using the MII serial management pins (MDIO and
MDCLK) in conjunction with firmware on the Switch Processor. This allows the PM3351
to support auto-negotiation, link status, and other management operations on the
attached PHY device(s). At system initialization time, the Switch Processor polls the
PHY device to determine the starting configuration resulting from the autonegotiation
process, prior to beginning normal operation; thereafter, the Switch Processor
periodically re-interrogates the PHY device to determine whether the configuration is
still valid, or whether a configuration change has occurred.

The ELAN 1x100 performs only the 802.3 MAC-sublayer functions and provides a
simple, inexpensive interconnection to an attached physical layer (PHY) device through
the Medium Independent Interface (MII) as described in 802.3u, clause 22. The
attached 100Mbit PHY device is responsible for performing the Physical Coding
Sublayer, Physical Medium Attachment, and Physical Medium Dependent sublayers;
that is, it is the interface between the actual Ethernet media on one side and the MII
interface on the other side.

The MAC interface unit consists of the following functional blocks:

• A signal interface compliant with the MII logical and electrical specifications. The
interface communicates with the PHY device using the TXD[3:0], TXEN and
TX_CLK signals for transmit data, and the RXD[3:0], RX_DV, RX_ER and
RX_CLK signals for receive data. In addition, the CRS and COL signals are
used for medial access during half-duplex operation. Note that the TX_ER
signal is not directly supported by the ELAN 1x100; the TX_ER input on the
PHY device, if present, should be tied LOW.1

1

The ELAN 1x100 does not provide a TX_ER signal as the device, being store-and-forward, will never
transmit an errored frame; in addition, the logical implementation is such that it is impossible to have a
data starvation condition occur during transmit.

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• A series of two unidirectional buffer FIFOs for receiving data from the MII media:
the first is a 32-deep nibble-wide FIFO that receives framed nibbles from the MII
receive channel pins; the second is the primary 64 byte receive FIFO that
assembles the nibbles into 32-bit data words and buffers them prior to transfer
to the external SRAM. Additional control logic is provided to strip off the
preamble and Start Frame Delimiter (SFD) from the receive data, to assemble
the framed data nibbles into octets, and to perform clock synchronization
between the MII receive clock and the internal system clock. The assembled
and buffered data words are then passed to the DMA Controller, which in turn
writes them out to local memory.

Note that the MAC interface unit can begin receiving the next incoming frame
while the DMA is still servicing the previous frame; control information is inserted
into the FIFOs to ensure that the two frames are properly separated before
transfer to memory.

• A 2048-byte transmit FIFO is provided to buffer transmit data received from
other ELAN devices over the PCI expansion bus interface prior to transmission
on the MAC transmit channel. This FIFO is large enough to hold more than one
maximum sized frame of 1518 bytes (plus an additional 512 bytes of the next
frame), or up to 32 minimum sized (64-byte) frames, allowing frames to be
stacked back-to-back for continuous transmission in the presence of PCI bus
latencies.

Frame transmission on the MII port only starts if an entire frame is present in the
transmit FIFO, and the Switch Processor has indicated that the frame is to be
transmitted. During transmission, data octets are read from the transmit FIFO
by the transmit MAC interface logic, synchronized to the MII transmit clock, and
then output on the MII transmit data nibble pins. Additional logic in the transmit
interface implements the lower-level frame transmission process described in
the 802.3 specification (preamble and SFD insertion, interframe gap timing,
collision detection and carrier deference for half-duplex, etc.).

• Control/status registers and logic that allows the Switch Processor to control the
MAC port and the attached PHY devices, and also to monitor status. The
control/status registers contain the timers required for the CSMA/CD algorithm.

MAC transmit sequence
During transmission, 8-bit data octets to be transmitted are passed from the transmit

FIFO to the link transmit interface where they are synchronized to the MII transmit clock
(TX_CLK). After any required deference or interframe gap time, the MII framing signal
TX_EN is asserted and the preamble and SFD are sent on the TXD[3:0] pins. After the
SFD, the data octets comprising the Ethernet frame header and payload are
disassembled into nibbles, which are then transmitted on the TXD[3:0] pins, followed

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ultimately by the Frame Check Sequence (FCS) word. The MAC interface unit will then
insert an interframe gap before proceeding to the next frame.

A 2-part interframe gap timing algorithm (functioning according to the IEEE 802.3
specification) is implemented. If a two-part interframe gap is not desired, it is possible to
set the Part 1 timing to zero, in which case the device will implement the Ethernet V2.0
(Blue Book) interframe gap behavior. The MAC logic also implements an internal
jabber counter to time out excessively long transmissions; thus the ELAN 1x100 does
not require the external PHY to provide jabber protection.

Half-duplex Normal Collision
In full-duplex mode, the MII signals COL (collision detect) and CRS (carrier sense) are

treated as don't cares, and have no affect on frame transmission and reception. In half­duplex mode, however, the COL and CRS signals are used by the MAC transmit logic
to implement the required collision sensing and deference processes as outlined in the

802.3 specification.
If a collision is detected (as reported by the external PHY on the COL pin) prior to the

first 512 bits of the frame being transmitted, a normal collision is declared. The MAC
port immediately ceases frame data transmission; instead, it forces transmission of a
32-bit (8-nibble) jam sequence, flushes the transmit data disassembly registers, and
signals to the Switch Processor that a collision ha s occurred, as well as an indication
that a normal collision was detected. The jam sequence used by the MAC is a series of
8 nibbles with TXD[3:0] of 5 hexadecimal (0101 binary).

In response to the collision indication, the Switch Processor will load an internal backoff
timer with the appropriate pseudorandom value that denotes the backoff time to be
counted out by the MAC transmit logic. When the backoff period is timed out, the MAC
logic will automatically re-attempt transmission of the frame, which will be retained in
the transmit FIFO. If sixteen transmission attempts of a single frame have ended in
collisions, however, the Switch Processor will discard the frame and clear it from the
transmit FIFO.

Half-Duplex Late Colsion
A late collision is declared if the collision was detected after 512 bits of the Ethernet

frame, including the preamble and SFD, had already been transmitted. In this case, the
MAC will abort the transmission of the frame and send the jam sequence as usual, but
the Switch Processor will (upon notification of a late collision) cause the frame to be
dropped from the transmit FIFO and not retried. This is required as a consequence of
the dynamic re-allocation of space within the transmit FIFO; once more than 64 bytes of
a frame have been transmitted (i.e., the late collision threshold has been crossed), the
space occupied by the transmitted p ortion of the frame in the transmit FIFO will begin to
be continuously deallocated and used to fetch and buffer the next frame. As a result, a

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late collision will usually preclude the retransmission of the original frame data, as it is
no longer present within the FIFO.

MAC Receive Sequence
Data nibbles are received from the MII receive data signal pins (RXD[3:0], in

conjunction with the clock, framing and error signals) and assembled into 8-bit data
bytes, which are then written to the receive FIFO. The data words in the receive FIFO is
subsequently read out by the DMA Controller as a stream of 32-bit words, and
transferred to buffers in the external memory.

At the end of frame reception, the MAC logic provides the DMA Controller with the
received frame status: frame too long (i.e., the received frame exceeded the
configurable maximum frame size), frame too short (i.e., the frame length was below
the configurable minimum frame size), misaligned frame (a framing error was detected
during nibble-to-byte conversion), or FIFO overrun (data was lost because the receive
FIFO was not drained at a sufficiently high rate). The DMA Controller combines this
status with its own internally generated error conditions when supplying the Switch
Processor with the general received frame status.

Oversize receive frames are truncated by the MAC logic to prevent buffer exhaustion
during the reception of a jabber. Assertion of the MII RX_ER signal while RX_DV is
asserted will force a CRC error if the data portion of the frame is being received, and
will cause the frame to be dropped if the preamble or SFD is being received.

The ELAN 1x100 MAC interface is configurable via a set of configuration registers that
are loaded at initialization time. The following parameters are configurable:

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Parameter Min Max Units Default

Numeric

Setting

Interframe spacing, Part 1 0 255 nibble

Interframe spacing, Part 2 0 255 nibble times 9 36 bit tmes

Preamble length (not including SFD) 0 255 bits 52 56 bits

Collision jam length 0 255 byte times 4 32 bits

Maximum receive/transmit frame

size

Minimum receive frame size 0 255 bytes 64 64 bytes

Late collision threshold 0 255 byte times 64 512 bit

Receiver blind time 0 255 nibble times 0 0 bit times

0 2048 bytes 1518 1518 bytes

times

1

15 60 bit times

Value

times

Frame Type Recognition
The MAC interface (in conjunction with the DMA Controller receive channel and the

Switch Processor) also allows selected frames to be received and specially handled by
the ELAN 1x100, based on the EtherType field within the frame. (Note that this
capability applies only to frames coded according to the Ethernet V2.0 standard, not the
IEEE 802.3 standard with LLC coding.) This facility can be used, for example, to
separate Address Resolution Protocol (ARP) frames from normal TCP/IP traffic, or for
recognizing and diverting MAC Control frames for flow control and other purposes.

The frame type recognition capability is implemented using a 16-bit register, referred to
as the ETYPE register, which is used to compare the EtherType fields of all received
frames to a predefined value. If a match is found, an indication is passed to the Switch
Processor by the DMA Controller at the time that the former is notified of the presence
of the received frame. The ETYPE register is normally set to 0x8808 hex after system
reset (i.e., the EtherType value corresponding to full-duplex MAC Control frames as per
IEEE 802.3x, clause 31); the Switch Processor may, however, modify this register if
some other type is to be recognized. Note that only one ETYPE register is provided,
and hence only one EtherType value may be checked for at any time. (Additional type
checking is performed by the Switch Processor firmware as required.)

Half-Duplex Flow Control: Backpressure
Flow control is supported as an option during half-duplex operation by means of a

backpressure mechanism, activated by the Switch Processor when an out-of-buffers
condition is detected during a high volume of received traffic. Backpressure is

1

A nibble time is one RX_CLK or TX_CLK period on the MII interface (nominally 40 ns).

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implemented by the MAC logic by continuously transmitting an extended jam sequence
(all-zeros) pattern, with gaps of one standard interframe spacing inserted periodically to
prevent the backpressure pattern from being interpreted as a jabber. Collisions
encountered during backpressure will not cause the MAC channel logic to back off in
the normal manner; instead, the MAC channel will send the standard jam pattern, time
out a normal interframe gap, and then resume the backpressure pattern.

If, during backpressure, the MAC channel detects that one or more frames are ready to
be transmitted over the channel by the ELAN 1x100 (e.g., a frame was received over
the PCI expansion bus and is destined for an end-station on the flow-controlled
channel), the MAC channel will cease transmitting the backpressure pattern, wait for a
normal interframe gap, and then transmit the desired frame(s). After all the pending
frames have been transmitted, the MAC logic will resume backpressuring the channel.

The backpressure mechanism described above is an optional feature: it should be
noted that this backpressure method will result in the complete shutdown of the MAC
channel (i.e., even local segment traffic will not be allowed to proceed), and so it is
recommended that backpressure be enabled only on ports that are connected to a
small number of end-stations.

Full-Duplex Flow Control: PAUSE MAC Control frames
Backpressure flow control relies on collisions to shut off frame reception, and hence

cannot be used during full duplex operation. PAUSE MAC Control frames, as specified
in IEEE 802.3x, annex 31B, are employed instead. PAUSE frame transmission is
controlled by the Switch Processor: if the Switch Processor determines that the amount
of available receive buffer space has fallen below a threshold, it will initiate the transmit
of a MAC Control frame that is formatted as a PAUSE frame according to the IEEE

802.3x standard, with a "pause_time" field set to a configurable number of slot times
(nominally 100). Additional PAUSE frames, with the same pause timer value, are
transmitted if the condition persists after the pause period ends.

The MAC logic also supports full duplex flow control attempts by downstream entities
when they are unable to accept data transmitted by the ELAN 1x100. In this case,
PAUSE frames are received with their EtherType fields set to 0x8808 hexadecimal,
indicating a MAC Control frame. The Switch Processor will then verify that the frame is
valid, shut off frame transmission at the next inter-frame boundary, and time out the
requested pause time (using a software-based method). If no more PAUSE frames are
received before the pause timer expires, transmission will recommence.

CLK25
The ELAN 1x100 provides a CLK25 output that can be tied directly to the 25 MHz input

clock used by most 100 Mbit/s Ethernet PHY devices.

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Multichannel DMA Controller

The on-chip DMA Controller contains four independent and concurrently operating
channels: two for the 100 Mbit/s MII port (one for receive and one for transmit) and two
dedicated to the 1 Gbit/s expansion port. The DMA Controller, operating under the
control of the switch processor, is responsible for performing all data block transfers
within the ELAN 1x100 made between the MII port, the local memory and the
expansion port. The DMA Controller also computes 32-bit IEEE Frame Check
Sequence (FCS) remainders over the received and transmitted frames, allowing the
Switch Processor to filter frames with CRC errors on receive, and also allowing CRCs to
be computed for injected management frames on transmit. In addition, the DMA
Controller implements an address lookup process that attempts to map the 48-bit MAC
addresses of received frames to entries in an address table maintained in local
memory. The DMA Controller provides sufficient bandwidth to guarantee that there will
be continuous and uninterrupted reception and transmission of frames at full wire rates.

A special feature of the DMA Controller is its ability to automatica lly alloca te buffer
storage from a central free pool (organized as a linked-list pointed to by a dedicated
device register) These allocatable data structures are called

packet buffers

; they are of
fixed (and configurable) length, and are chained together into linked-lists to hold
Ethernet frames of different lengths. The DMA channel associated with the receive path
is capable of creating these linked-lists of packet buffers automatically whenever
frames are received.

The four DMA Controller channels are dedicated to various functions as follows:

• One channel (referred to as the receive channel) is used to perform data
transfers between the MAC receive FIFO and the local memory, copying
received frame data from the FIFO to the local memory. As mentioned, the
receive channel generates a linked-list of packet buffers in external memory,
automatically allocating packet buffers as needed from a central free pool. A
32-bit CRC is computed on the receive data transfers, and the CRC result is
accessible to the Switch Processor f irmware in the form of a CRC error status
bit after a frame has been received.

• One channel (referred to as the transmit channel) is used to perform block
transfers over the external PCI expansion bus from external devices (other
ELAN 1x100s, ELAN 8x10s, or any other device implementing the same
protocol) to the 2048-byte transmit FIFO. This channel can follow a chain of
remote source packet buffers, reading data over the PCI bus. Only the required
frame data is written into the transmit FIFO; the headers of the packet buffers
are stripped off by the channel transfer logic.

The transmit channel implements special logic that allows the Switch Processor to
inspect the frame header and determine how the frame should be treated after it has

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been read into the transmit FIFO. This consists of a small 16-entry queue (referred to
as the disposition FIFO), that holds disposition commands generated by the Switch
Processor. After the header of each frame has been read over the PCI expansion bus,
the transmit channel notifies the Switch Processor via an interrupt; the Switch
Processor is then responsible for checking the header data and writing a disposition
command into the disposition FIFO. The disposition command instructs the transmit
channel logic as to how the frame should be handled. In all cases, a disposition
command applies only when a frame has been completely read into the transmit FIFO,
and the first byte of the frame reaches the head of the transmit FIFO.

The purpose of the disposition FIFO is to improve the efficiency of the switching
firmware when handling transmit frames. Each entry in the disposition FIFO
corresponds to a specific frame that has been placed into the main 2048-byte transmit
FIFO, and indicates how that frame is to be dealt with. Three possible actions may be
requested by the firmware, by setting entries in the disposition FIFO to various codes:

1. Send: the frame can be automatically sent over the MAC port when it reaches
the head of the transmit FIFO, i.e., the preceding frame, if any, has been
deleted from the FIFO. This is the normal mode of operation, used for dealing
with frames that should be transmitted without special processing.

2. Drop: the frame can be simply deleted from the transmit FIFO when it reaches
the head of the FIFO, without transmitting it over the MAC port. This is used
when the ELAN 1x100 decides to reject a particular frame that was queued for it
from an external device, or for special firmware-controlled frame processing.

3. Stop: when the first byte of the frame reaches the head of the transmit FIFO, the
DMA Controller should stop reading any more data out of the transmit FIFO,
and instead interrupt the Switch Processor. The Switch Processor firmware may
then choose to read data out of the transmit FIFO if required; when the firmware
processing is done, the disposition FIFO entry may be changed to a drop code
to delete the frame from the transmit FIFO, or to a send code to transmit the
frame over the MAC port in the normal manner.

The use of the disposition FIFO permits the firmware to make early decisions about
how the frame should be handled, even before the frame has been completely read into
the transmit FIFO. These decisions are expressed in the form of the disposition codes
(send, drop, and stop), which travel down the disposition FIFO in lockstep with the
stored frames travelling down the transmit FIFO. The DMA Cont roller ensures that one
entry is read from the disposition FIFO for each frame that is read out of (or dropped
from) the transmit FIFO.

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• One channel, referred to as the PCI access channel, is used to perform block
transfers under control of firmware running on the Switch Processor. This
channel is capable of performing PCI configuration read or write transactions as
well as standard PCI memory read or write operations. It is not intended to
handle frame data, but is generally used for control and inter-device
communication functions.

• The last channel (referred to as the transfer handshake channel) facilitates the
frame exchange handshake that takes place between multiple PM3350 and
PM3351 devices across the PCI expansion bus This channel can be set up to
perform up to seven writes in a single series of PCI transactions to special
request and acknowledge counters in up to seven external ELAN devices (or in
an external device that implements the ELAN frame transfer protocol). The
request and acknowledge counters are used to indicate the presence of a frame
being forwarded and to acknowledge receipt of the frame, respectively. This
channel also supports hardware that implements a ring of data descriptors that
are used for the seven transfer queues (discussed in more detail later).

DMA Controller operations performed by the receive channel take place largely
autonomously (after initial setup); the receive channel simply notifies the Switch
Processor upon the completion of reception of each incoming frame, and supplies the
necessary frame parameters to the Switch Processor via hardware registers. However,
the remaining channels perform their transfers completely under firmware control by the
Switch Processor. In operation, the Switch Processor loads the appropriate DMA
control registers with the desired transfer parameters and then enables the channel.
The hardware will then autonomously complete the transfer and notify the Switch
Processor upon completion via an interrupt.

Address Lookup Hardware
The DMA Controller contains internal hardware that performs an address lookup on the

source and destination MAC addresses in the headers of received Ethernet frames,
and attempts to match them against entries in an address table maintained in external
RAM.

During frame reception, the DMA receive channel extracts the 48-bit source and
destination MAC addresses from every incoming frame. These are then passed through
a hashing process that generates a 16-bit
index into a
point to zero or more

hash array

in external RAM. The entries in the hash array are expected to

hash buckets

, with each hash bucket being assigned to a unique

hash key

; the key, in turn, is used as an

MAC address. If multiple hash buckets are associated with a single hash array entry,
they are concatenated into a linked list, that is searched by the address lookup
hardware to locate the correct hash bucket for the given source or destination MAC
address. (The search is performed by comparing the actual MAC address against a 48­bit address field in the hash bucket.) If a match is found for either the source or the

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destination MAC addresses, or both, the pointers to the appropriate hash buckets are
passed to the Switch Processor along with the received frame.

A similar address lookup process is also performed by the transmit channel for a frame
that is being read over the PCI expansion bus from a remote device. This lookup is
restricted to the source MAC address only; further, the lookup is only done if required
by the Switch Processor. (This address lookup is used during the address learning
process, when it is desired to learn the source MAC addresses of frames that are being
read over the PCI expansion bus.)

Memory Controller

External RAM is required for packet buffers used to hold received Ethernet packets, as
well as data structures needed to perform switching and support system management.
The external memory may also contain patch or extension code for the on-chip Switch
Processor. The ELAN 1x100 therefore contains an integral memory controller unit
which supports a variety of standard memories without glue logic.

The memory controller is capable of addressing a total of 16 megabytes of row/column
multiplexed-address memories (i.e. DRAM), or a total of 4 megabytes of linear-address
memories (i.e. SRAM, EPROM and EEPROM), in any combination.1 The address
space is divided into four banks, each of which has an independently programmable
memory type and access time. This allows a mix of fast and slow devices to be used in
the system. Programming of EEPROM devices is done under control of Switch
Processor microcode. The memory controller is capable of performing up to 1 32-bit
transfer every 2 clock cycles (40 nsec at the nominal clock frequency of 50 MHz) to or
from an SRAM bank, for a maximum sustained throughput of 100 MB/s. Memory
device types or speeds cannot be mixed within a bank (i.e., a bank cannot consist of
part EEPROM and part SRAM, for example) without special logic that is outside the
scope of this document. In general, memory devices of different types must be
assigned to different banks, and selected with different chip selects.

The memory types used for standard switching by the PM3351 are summarized in the
table below:

1

The reduced space available for the non-multiplexed-address memories arises due to pin limitations:
only 18 memory address lines are driven to the pins driving the external memory bus (MADDR[17:0]),
whereas 20 address lines would actually be required (in conjunction with the four bank selects and the
four byte-enables) to span the entire 16 MB address space.

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Memory Type Spee

(nsec)

Standard SRAM 15 2 100 MB/s

Standard EPROM/EEPROM 150 12 17 MB/s

Latency
(cycles)

Peak

Bandwidth

The standard memory types that should be used with the ELAN 1x100 are 15 nsec
SRAM and 120/150 nsec EPROM or EEPROMA memory ready input pin (MRDY*) is
implemented for linear memory devices that have other speed requirements. This pin
is sampled by the ELAN 1x100 when accessing memories in standard asynchronous
SRAM mode; it may be driven inactive, prior to the end of any memory cycle by an
external memory timing generator to suitably lengthen the access cycle. The sampling
of the MRDY* input takes place at the end of the first clock cycle of a 2-cycle SRAM
access. Accesses to banks configured for memory types other than 2-cycle SRAM
cannot be controlled using MRDY*. The MRDY* pin should be tied LOW (i.e., logically
deasserted) if it is not used.

The ELAN 1x100 generates four separate write enables to enable individual bytes
within each addressed 32-bit word to be written to independently of the others. This
allows the ELAN 1x100 to perform byte (8-bit), halfword (16-bit), tribyte (24-bit) and
fullword (32-bit) memory accesses without using read-modify-write operations.

An interrupt input pin (MINTR*) is provided for special applications. A TTL logic LOW
level on this pin causes an interrupt to be generated to the internal Switch Processor,
the PCI bus (via the INT* output), or both. The use of this interrupt input is application
dependent and beyond the scope of this datasheet. The MINTR* pin should be tied
HIGH (i.e. logically deasserted) if it is not to be used.

PCI Expansion Port

The ELAN 1x100 includes a PCI v2.1 compatible bus master and slave interface, which
serves as an expansion port allowing multiple ELAN 1x100 and/or ELAN 8x10 chips to
be interconnected in the same system to create switches with larger numbers of ports.
The expansion port supports a maximum bus clock of 40 MHz (resulting in a >1 Gbit/s
peak transfer rate and a sustained throughput of 500 Mbit/s), and contains several
FIFOs to increase burst throughput and perform clock synchronization.

The PCI expansion port may be used for either expanding a switch built around ELAN
switch devices (to a maximum of eight PM3351 and PM3350 chips) or to allow the
ELAN 1x100 to be used in special applications requiring an intelligent 100 Mb/s
Ethernet interface. In these applications, the on-chip DMA Controller uses the PCI
expansion port master interface to notify other ELAN switch devices or the host CPU of
the presence of packets to be transferred, and to copy packets or data structures under
control of the Switch Processor from external ELAN switch devices to the local memory

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space via the PCI bus. Note that data are never transferred directly between the MAC
channels and the PCI bus.

The PCI bus master interface serves to allow the DMA controller as well as the CPU to
initiate transactions on the PCI bus. The bus master conforms to the requirements of
the PCI v2.1 specifications for standard transaction initiator devices, and can perform
configuration space as well as memory space read and write transfers. (Note that the
ELAN 1x100 does not support I/O space transactions.) The PCI bus master unit
contains a 64-byte write FIFO to buffer data being written by the ELAN 1x100 device to
an external target on the PCI bus, as well as a 128-byte read FIFO to hold data that has
been read from an external target. These FIFOs permit the bus master to operate using
long burst transactions for increasing the PCI bus bandwidth utilization. The bus master
interface also conforms to the PCI v2.1 latency timer requirements, and supports back­to-back transfers.

The PCI slave interface logic within the expansion port block responds to transfer
requests from external bus masters, performing the necessary accesses and
transferring the requested data. The slave interface logic acts as a responder during
frame transfers between devices belonging to the ELAN chipset, supplying Ethernet
frame data to requesters as necessary. An external processor can also use the PCI
slave interface to gain access to internal device registers and data structures in the
local memory space, or to download firmware or data to the ELAN 1x100 Switch
Processor. The slave interface unit contains a 32-byte write FIFO and a 128-byte read
FIFO to improve burst behavior during PCI reads and writes: the write FIFO buffers
data being written to the ELAN 1x100 by external devices, while the read FIFO holds
data read from local memory or internal registers in response to PCI memory read
commands from external requesters. Note that the slave interface only responds to
configuration space and memory space reads and writes; I/O space reads and writes
are not supported. The slave interface conforms to the access latency, access ordering
and disconnect rules of the PCI v2.1 standard. A set of special registers are provided in
the PCI configuration space that may be used to alter the access latency rules imposed
by the slave logic in order to improve PCI bus utilization if required.

The expansion port also contains hardware to speed up intercommunication between
ELAN 1x100 and ELAN 8x10 devices via the PCI bus. This hardware takes the form of
eigth request counters and eight acknowledge counters. Each request/ acknowledge
counter pair is dedicated to supporting communications with a specific external ELAN
device. An external ELAN 1x100 device will increment a request counter to signal that
a frame or message data is available to be read, and will increment an acknowledge
counter to acknowledge that it (the external ELAN 1x100) has read a message or frame
from the local ELAN 1x100. Standard PCI reads and writes can be used to increment
the request and acknowledge counters. More details on these counters are supplied
below.

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The expansion port is compatible with the "PCI Local Bus Specification", release 2.1.
To support the use of the ELAN 1x100 in standalone switch system applications, a
simple external bus arbiter (easily implemented in a single programmable logic device)
must be provided to arbitrate between PCI bus accesses of multiple ELAN devices.

The PCI bus interface within the expansion port runs synchronously to the PCI bus
clock, which must be supplied on the PCICLK input pin. This clock may range from 25
MHz to 40 MHz, with the duty cycle specified in the PCI Local Bus Specification. The
ELAN 1x100 PCI bus interface implements synchronization logic to transfer data
between the PCI bus clock domain and the internal device clock.

PCI Transactions Supported
The on-chip PCI interface is capable of initiating the following commands:

• memory read

• memory write

• configuration read

• configuration write

The on-chip PCI interface supports the following PCI commands as a target:

• memory read

• memory write

• configuration read

• configuration write

• memory read multiple

• memory read line

• memory write and invalidate

PCI Vendor ID and Device Number
The vendor ID assigned to the ELAN 1x100 device (in the PCI configuration register

space) is 11F8 hexadecimal, while the device number is 3351 hexadecimal. The class
code for the ELAN 1x100 is set to 0x020000 hexadecimal.

Slave Read Prefetching
As already mentioned, the PCI bus slave logic contains a 128-byte read FIFO buffer to

speed up reads made from this ELAN 1x100 device over the PCI bus. This FIFO has a
prefetch capability that is activated when accessing external memory space: it attempts
to read ahead and speculatively obtain more data words than have been actually
requested by the transaction master, thereby potentially increasing the efficiency of
burst transfers.

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The prefetch capability functions as follows. Initially, the PCI slave read FIFO is empty,
and remains so until the PCI slave is idle. When a read transaction is initiated by an
external bus master, the PCI slave logic will perform a disconnect with retry, after a
configurable amount of cycles, because the read FIFO is empty and no data can be
returned. The slave logic then decodes the target address of the read: if it corresponds
to external memory space, then the prefetch capability is activated. The slave logic
subsequently requests the memory controller to begin fetching from the target memory
address; the data returned are placed into the slave read FIFO, and the PCI slave logic
continues to fetch additional data words at consecutive addresses until the slave read
FIFO is full. Up to 128 bytes of data may be fetched in this way and placed into the
slave read FIFO.

At some point, the original PCI transaction initiator (bus master) is expected to retry the
access. (According to the rules of the PCI bus, it is an error for the bus master to
abandon an access that has been terminated with a disconnect-and-retry.) The PCI
slave logic will compare the address being requested by the PCI bus master for the
retried transaction to the address from which it began the prefetch; if a match occurs,
the slave logic will return the data present in the read FIFO in a continuous burst of
back-to-back data phases on the PCI bus. The burst of transfers on the PCI bus will
continue as long as (1) the read FIFO is not empty and (2) the bus master does not
terminate the access.

If the read FIFO empties during a transfer (possibly because the memory controller
cannot satisfy the requests from the PCI slave logic at a sufficient rate), the PCI slave
logic will issue another disconnect with retry, and continue to request the memory
controller for more data. The bus master is again expected to retry the access, and the
cycle continues.

If the bus master terminates the access in any way, the PCI slave logic will stop placing
data on the PCI bus and flush the read FIFO to discard any remaining unread data
words. It will then proceed to fulfill the next PCI read or write access.

The use of the PCI slave read FIFO enhances the ability of the PCI slave logic to
maintain the utilization of the PCI bus by transferring data in long bursts. If sufficient
delay is inserted by the bus master between the initial disconnected access and the
subsequent retry, the PCI slave will have time to read ahead by a substantial number of
words (up to 32) and can therefore transfer data in a long burst when the bus master
finally retries the access.

To further improve the efficiency of the PCI slave interface, the slave logic has the
capability of latching and holding up to two different target read addresses from two
different bus masters at a time. This allows the first bus master to make a read access,
which will be disconnected with retry by the PCI slave logic after the target address has
been latched; another bus master can then make another read access at a different
address, which will also be disconnected with retry by the slave logic after the address

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has been latched. (Only two such addresses can be latched by the slave; if yet a third
master makes another read access to another address, the slave logic will also
disconnect this master with a retry, but will not latch the address internally.) The
availability of the second read address means that the PCI slave logic can begin
immediately fetching data from the second location into the read FIFO after the first bus
master terminates its access, without waiting for the second bus master to retry the
access, and hence the PCI slave logic can improve its utilization of the available
memory and PCI bus bandwidth.

Note that writes are not allowed to be completed out-of-sequence with reads, and vice
versa.

Watchdog Timer Facility

The ELAN 1x100 device incorporates a simple internal watchdog timer that optionally
initiates an automatic system hardware reset if some catastrophic error occurs that
causes the Switch Processor to lock up or enter an undefined state. The watchdog
timer is built around the 16-bit WTIMER device control register (described in more detail
in a later section).

The WTIMER register principally acts as a down-counter, decrementing its value by 1
every millisecond until it reaches zero. Firmware running on the Switch Processor will,
under normal circumstances, periodically reload the WTIMER register with a non-zero
value before it reaches zero. If however, the Switch Processor firmware encounters
some serious system fault that prevents it from reloading the WTIMER register before it
has counted down to zero, the watchdog facility will assert the ERST* output LOW for
one millisecond. If the ERST* output is tied to the system reset line (this is made
possible by the fact that ERST* is an open-drain output), then the watchdog timer
facility will effectively reset the entire system. Alternatively, the ERST* output can tied to
a resistive pull-up and simply monitored by an external system processor; a hardware
or software reset of the ELAN 1x100 device should be performed if the ERST* output
goes LOW (logically asserted).

The value used by the Switch Processor firmware to reload the WTIMER register is a
configurable parameter, and should be chosen to ensure that false system resets do
not occur under high loads without simultaneously incurring an excessive system
recovery time. The maximum reload interval is approximately 65 seconds; the minimum
interval is about 2 milliseconds. A value of 1-2 seconds is recommended.

If the WTIMER register is loaded with all-ones (0xffff hex) the watchdog timer facility will
be disabled, and the WTIMER register will be prevented from counting down and
asserting the ERST* output. (The watchdog facility can hence be disabled by the
system implementer by setting the configurable reload value to 0xffff hex.) Note that the
WTIMER register rolls over to 0xffff after it has counted down to zero, thereby
automatically disabling itself after the 1 millisecond reset duration is over. If the

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WTIMER register is left untouched by the initialization process, then it will default to a
disabled state, i.e., it will remain loaded with 0xffff and, as a result, will not count down.

If the Switch Processor itself detects an unrecoverable fault that requires a general
system reset, then the Switch Processor firmware will write a value of zero to the
WTIMER register under program control. This will cause the ERST* pin to be
immediately asserted (driven LOW), potentially causing a hardware reset or notifying
the system processor that a fault has occurred.

Device Configuration

Basic device and system configuration (i.e., memory types and speeds for various
banks, the PCI base address for this ELAN 1x100 device, and auto-boot and
master/slave enable flags) are supplied by means of resistor pull-ups and pull-downs
connected to the 32-bit data bus. This configuration information is latched into internal
registers upon the second SYSCLK rising edge after the RST* input to the ELAN 1x100
transitions high, and sets up the ELAN 1x100 internal hardware. The 32 bits of
configuration data presented on the memory data bus are latched into the 16-bit
DCONFIG and MCONFIG registers internal to the ELAN 1x100; these registers may
also be accessed by the Switch Processor and by external devices via the PCI bus.

As an alternative to resistor pull-ups and pull-downs, a tristate buffer or tristatable
register may be used to drive configuration information on to the data bus during reset.
Care should be taken to remove the data by tristating the buffer or register no earlier
than 2 SYSCLK periods after the trailing edge of the RST* input, and no later than 10
SYSCLK periods after the latter (to prevent memory data bus contention).

The memory data bus is mapped to configuration bits as follows:

Device Pin Register Bit Description

MDATA[31] PCIRUN This input selects the default operating mode of the PCI

interface.
If logic 1:

• The on-chip PCI interface latches its slave memory base
address from the CHIPID configuration bits (MDATA[25:22]).

• The PCI Command Register bits for "Bus Master" and
"Memory Space" are set (1), thereby allowing the device to
respond to PCI memory space accesses and to be a bus
master.

If logic 0

• The PCI interface has a memory base address of 0.

• The PCI Command Register bits for "Bus Master" and
"Memory Space" are cleared (0); the device is disabled from
responding to PCI memory space accesses and will not be a
bus master.

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MDATA[30] RISCRUN A low on this signal halts the Switch Processor upon reset,

effectively placing the device into stand-by mode.
MDATA[29] RSTTM For test purposes only. Pull low for correct operation.
MDATA[28] IMDIS Internal memory disable: if high, the internal Switch Processor

ROM is disabled at initialization time.
MDATA[27] PCI3V If high, configures the PCI interface for the 3.3V signaling

environment. If low, configures the PCI interface for the 5V

signaling environment. Must be set to logic 0 since all AC

parametric testing done with the 5V signaling conditions.
MDATA[26] FIRM Reserved for use by Switch Processor firmware.
MDATA[25:22] CHIPID[3:0] These bits determine the PCI memory base address at

initialization time if the PCIRUN configuration bit is high. In this

case, the CHIPID[3:0] inputs are zero-extended to 8 bits and

loaded into the most significant byte of the Memory Base

Address register in the PCI configuration register space.
MDATA[21:16] RTCDIV[5:0] Real time clock divider: selects the divide ratio used for the

internal real-time clock prescaler. This field must be set

numerically equal to the frequency, in megahertz, of the clock

supplied on the SYSCLK input.
MDATA[15:14] MXSEL[1:0] Error! No index entries found.

MXSEL

00
01
10
11

Column Address

Bits

8

9
10
11

DRAM Configurations

Supported

64K x N & 128K x N

256K x N & 512K x N

1024K x N & 2048K x N

4 Meg x N & 8 Meg x N

MDATA[13] MSLO The MSLO bit extends read and write cycles to accommodate

slower DRAM devices in local memory devices. If MSLO is
high, 80ns DRAM is expected. If MSLO is low, 60ns DRAM is
expected. (MSLO must be a logic 0 if EDO DRAM is used with
the PM3351 since the device is intended to work with 60 ns
DRAM; as previously stated, DRAM, if used, is intended for non­switching applications).

MDATA[12] MDCAS This bit identifies the type of DRAM connected to the memory

interface. If MDCAS is high, the memory interface will generate
control signals for 2-CAS DRAMs; otherwise, it generates
signals for single CAS DRAMs. (Again, as DRAM is generally
not used for standard switching, these bits will usually be don’t­cares).

MDATA[11:9] MTYPE3[2:0] Indicates the type of memory connected to the MCS[3]* output:

MTYPE3[2:0]

000
001
010
011
100
101
110
111

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Selected memory type

Reserved
Reserved

15ns SRAM

Reserved
Reserved

150ns (E)EPROM

60ns EDO DRAM

Reserved

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MDATA[8:6] MTYPE2[2:0] Indicates the memory type associated with MCS[2]*. The

encoding is the same as for MTYPE3[2:0].

MDATA[5:3] MTYPE1[2:0] Indicates the memory type associated with MCS[1]*. The

encoding is the same as for MTYPE3[2:0].

MDATA[2:0] MTYPE0[2:0] Indicates the memory type associated with MCS[0]*. The

encoding is the same as for MTYPE3[2:0].

After the hardware configuration information has been latched from the data bus, it is
loaded into the DCONFIG and MCONFIG registers. The lower 16 bits of the
configuration word (i.e., bits 0 through 15, latched from MDATA[15:0]) are loaded into
the MCONFIG register, with MDATA[0] being loaded into the LSB of MCONFIG. The
upper 16 bits (i.e., corresponding to MDATA[31:16]) are loaded into the DCONFIG
register in a similar fashion.

System Bootstrap Image

The ELAN 1x100 is designed to self-initialize upon power-up, using information and
operating firmware supplied as a pre-determined image (referred to as the

boot image

)
in external memory (typically, EPROM or EEPROM). The boot image may be located
anywhere in the 16 MB address space,

and it must start on a 64 kB boundary

. The
ELAN 1x100 expects the boot image to be formatted in a predefined manner, as
described below. The boot image consists of a boot header and a set of boot data
blocks.

Boot Header
The boot image is distinguished by a special 32-bit signature followed by a predefined

configuration header. The ELAN 1x100 will, therefore, perform some basic initialization
indicated by the hardware configuration word loaded from the data bus after reset, and
then begin scanning the entire memory space at 64 kB boundaries for the boot image
signature. It expects to find the four bytes of the signature aligned on four consecutive
32-bit boundaries, as indicated in the following table:

Offset from 64kB

Boundary

Expected Contents

(hex)

+0 XXXXXXC7
+4 XXXXXXA8
+8 XXXXXX37

+12 XXXXXX59

The use of a signature to locate the boot image, rather than an explicit address, implies
that it is not necessary to indicate the exact location of the configuration image to the

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ELAN 1x100. Instead, the boot image may be located anywhere throughout the 16 MB
address space. In addition, a boot image need not even be supplied using an EPROM
or EEPROM; it may also be downloaded to RAM by an external device or host
processor.

The ELAN 1x100 expects to find executable firmware code within the boot image that
will perform the actual initialization process. However, the boot image is generally only 8
bits wide, and thus the firmware code supplied within it cannot be directly executed by
the ELAN 1x100 Switch Processor, which uses 32-bit instructions located on 32-bit
boundaries. It is thus necessary for the ELAN 1x100 to copy the boot image to a block
of RAM that is set aside for the purpose, and to convert the 8-bit boot image to a 32-bit
version so that the boot firmware code can be directly executed.

When a proper boot image signature is found, therefore, the ELAN 1x100 will
automatically go on to read a preformatted header within the boot image. This header
should supply information required to copy the boot image to a pre-allocated block of
RAM, and is formatted as follows:

Field Size,

Bytes

1 +16 HDRFLAGS Boot image processing flags
3 +20,+24,+28 CPYTARGET Target RAM block to copy 8-bit

2 +32,+36 CPYSIZE Amount of data to copy in 64-

3 +40,+44,+48 CPYFROM Source of copy data within boot

3 +52,+56,+60 BOOTSTART Address to begin execution at

4 +64,+68,+72,+76 CHECKSUM 32-bit checksum, computed over

4 +80,+84,+88,+92 SPACER Must be set to 0x00000000

Byte Offsets from

Start

Mnemonic Description

boot image to

byte blocks

image

after copy is complete

entire boot image (including

checksum field)

hexadecimal

The HDRFLAGS field supplies some control bits that determine how the ELAN 1x100
will handle the boot image, and is formatted as follows:

7654 0

EightBit CpyInt JmpInt reserved

EightBit:

If set, indicates that the boot image is formatted as an eight-bit-wide memory

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block; otherwise, indicates a 32-bit boot image in memory. If this bit is not set
(indicating a 32-bit-wide boot image), the CpyInt and JmpInt flags must also
be cleared.

CpyInt:

If this bit is set, the contents of the boot image should be copied to the
internal instruction RAM of the Switch Processor rather than a block of
external memory. This bit should be set only if the EightBit flag is also set
(i.e., for a standard 8-bit-wide boot image). As a 32-bit-wide boot image, can
be executed directly, no copy is done, internal or otherwise.

JmpInt:

The JmpInt bit signifies, if set, that the BOOTSTART address indicates an
address present in the instruction RAM of the Switch Processor, rather than
an address in a block of external memory. This bit should be set only if the
EightBit flag is also set (i.e., for a standard 8-bit-wide boot image). It is
assumed that a 32-bit-wide boot image will be executed directly from it’s
external memory location.

If the EightBit flag is set, the ELAN 1x100 will copy data bytes from the EPROM or
EEPROM boot image to consecutive byte addresses in a block of 32-bit wide RAM,
thereby converting the 8-bit boot image to a 32-bit boot image that can be executed.
The target RAM may be either external (SRAM or DRAM) or the internal instruction
RAM within the Switch Processor, according to whether the CpyInt flag is set.

The CPYTARGET, CPYSIZE and CPYFROM fields of the header define a block
transfer that must be performed from the boot image to an area of external SRAM or
internal instruction RAM in order to convert the 8-bit boot image to an executable 32-bit
image. After the copy and conversion has been done, the BOOTSTART field denotes a
24-bit address from which the ELAN 1x100 Switch Processor will begin executing code,
either inside the internal instruction RAM (as is generally the case), or external RAM.
The code at this location is responsible for initializing the ELAN 1x100 system and
environment. The JmpInt bit signals whether BOOTSTART refers to internal or external
RAM.

The CHECKSUM field contains a 32-bit checksum computed over the entire boot
image. The bootstrap firmware will recompute this checksum and compare it with the
value in the CHECKSUM field. If a mismatch occurs, the ELAN 1x100 will consider the
boot image as invalid, and will terminate the system initialization and startup process
and report an error.

Note that the boot image header above is described as it would appear from the switch
processor. In the view from the 8-bit image contained within an EPROM or EEPROM,
the addresses would be divided by 4. This is because the 8 bit wide memory is
connected to the least-significant byte lane of the memory data bus. Each byte within

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the EPROM or EEPROM, therefore, will start on a 32-bit boundary and occupy the
least-significant 8 bits of a memory word; the upper 24 bits of the word will be ignored
by the ELAN 1x100. Note that this header only uses the least significant byte even if a
32 bit boot memory is being used. An alternative view of the boot header, giving the
components of the header as they would appear inside the 8-bit-wide ROM, is given
below:

0x59 0x37 0xa8 0xc7 0

CPYTARGET[23:0] HDRFLAGS[7:0] 4

CPYFROM[15:0] CPYSIZE[15:0] 8

BOOTSTART[23:0] CPYFROM[23:16] 12

CHECKSUM[31:0] 16

SPACER[31:0] 20

Typical Usage
In the standard EPROM or EEPROM bootstrap image, the HDRFLAGS field is set to

0xE0 hex, indicating an 8-bit-wide boot image that must be copied into the Switch
Processor's internal instruction RAM, and then executed. The boot image that is copied
into the internal RAM includes the normal frame switching firmware, as well as a small
bootstrap loader routine. The bootstrap loader (which will be pointed to by
BOOTSTART) will then copy the remainder of the 8-bit-wide boot ROM into external
memory, and finally jump to an entry point in the code copied into external memory that
will configure the rest of the device and the system if necessary.

A 32-bit-wide boot image must always set the HDRFLAGS field to 0x00, or else the
bootstrap process will fail. In this case, the CPYTARGET, CPYSIZE, and CPYFROM
fields are ignored, as no copying is done. It is expected that the BOOTSTART value
will be a valid address in the 32-bit-wide memory containing the boot image where
execution must begin in order to initialize and start the system.

Boot Data
In addition to the signature, header and bootstrap firmware code, the boot image is

expected to contain configuration information such as the sizes of memory buffer pools,
buffer limits defined on a per-port basis, predetermined MAC addresses to be placed in
the routing tables, the location of external ELAN devices, the MAC address and IP
address assigned to this ELAN 1x100, and so on. The boot image must also supply the
operating firmware that is required by the ELAN 1x100 for frame switching and
management. The general layout of the standard boot image supplied by PMC is
shown below (note that the memory addresses increase downwards):

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0 Boot Image Signature

Boot Image Header

ELAN 1x100 Switching Firmware

Bootstrap Loader Routine

System Table

ELAN 8x10 Switching Firmware

Boot Tag Space

32

Boot Tag Processing Code

kbytes

RTOS Firmware Code (optional)

UDP/IP Stack Firmware Code

(optional)

256

kbytes

The bootstrap firmware code performs a brief self-test, testing external memory and
verifying the boot image checksum. The status of each stage of the self-test is output
as writes of binary codes to the (configurable) memory location at which the optional
LED register may be located. After the self-test completes, the ELAN 1x100 uses the
information read from the boot image to set up the fixed and dynamic data structures in
external and internal RAM, and then initiates normal operation.

The actual bootstrap firmware is divided into two portions, referred to as the
and the

boot tag processing code

parameter blocks that define various data structures or hardware entities that must be
initialized in a particular way, as well as the data values required for the initialization.
The boot tag processing code scans over the array of boot tags; for each class of boot
tag, an associated routine is invoked to actually perform the required initialization. This
approach permits the initialization process to be extended very simply to cover new
types of structures or new hardware features: additional boot tags (together with their
associated routines) can be included in order to perform new types of initialization in a
well-structured manner, without having to be concerned about interactions between
different portions of the bootstrap firmware.

SNMP Agent/MIB Firmware Code

(optional)

boot tags

. The boot tags essentially comprise a set of

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As shown, the basic bootstrap code and the master switch operating firmware occupy
32 kbytes of EPROM/EEPROM space; if an SNMP agent is required (with the
associated UDP/IP stack and RTOS firmware), then the boot image size requirements
rise to 256 kbytes.

Contact the factory for more information on the boot image, and the means of creating
one.

Master/Slave System Initialization
In a multiple-ELAN 1x100 and ELAN 8x10 system, a single ELAN 8x10 or ELAN 1x100

device may be designated as a master and possess a boot image in an EPROM or
EEPROM. This ELAN 1x100 is then responsible for initializing and configuring all the
other ELAN 1x100s in the system via the expansion port interface. This is facilitated by
the RISCRUN configuration bit supplied on the memory data buses of all of the ELAN
1x100s in the system. In this application, the master ELAN 1x100 should have its
RISCRUN bit pulled HIGH during reset, and all of the other slaves should have the
corresponding bits pulled LOW, ensuring that they enter standby mode The master
ELAN 1x100 can then configure itself, download boot information to the RAM interfaced
to the remaining ELAN 1x100s, and finally enable all of the slave ELAN 1x100s to start
running. The slave devices can then initialize themselves using the downloaded
information.

Note that the firmware images for both the ELAN 1x100 and ELAN 8x10 devices are
present in the boot image. This is done to permit a single boot image (and
consequently EPROM or EEPROM) to be used to initialize an entire system of ELAN
devices of either type. The System Table is used for this purpose: it contains
information regarding the initialization and operating code requirements of every device
in the system, and the bootstrap firmware running on the system master device uses
this table to properly initialize and start the slave devices. Slave initialization is carried
out by the master device after the master has loaded its boot image, set up its private
environment, and determined that it is indeed the master; at this time, it copies the
bootstrap firmware, the appropriate block of switching firmware (depending on whether
the target slave device is an ELAN 1x100 or an ELAN 8x10) and the appropriate set of
boot tags into the slave device's local RAM space across the PCI bus. The master then
causes the slave to begin executing the bootstrap firmware and initialize itself. Once
initialization is complete, the slaves notify the master, and the system is ready for frame
processing.

Host-Controlled System Boot
In a host-controlled system, it is expected that all of the ELAN 1x100 devices are

configured as slaves, i.e., they do not possess EPROMs or EEPROMs containing boot
images that permit them to self-configure at power-up. Instead, they enter a halt state
after system reset and wait for the host (i.e., system master processor) to download the

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required boot image and enable them to begin executing it. This can be done by
converting the bootstrap firmware to run on the host system. The bootstrap firmware
should then perform the same general functions (reading each boot tag and
implementing the required initialization function) to pass the appropriate information to
the ELAN devices. Contact the factory for more information and sample code.

Stand-Alone System Boot
Typically an ELAN 1x100 device will be part of a multiple ELAN device system, where

the master device is responsible for controlling the initialization of the slaves; or work in
conjunction with a host processor, in which case the host is required to take over these
initialization and start-up functions. However, it is possible for a system to be designed
where each ELAN device has its own EPROM or EEPROM containing a private boot
image, and it is not necessary for a master entity to initialize other devices. In such a
system, some elements of the multi-device boot ROM are unnecessary; the resulting
boot image would be laid out as follows:

0 Boot Image Signature

Boot Image Header

ELAN Switching Firmware

Bootstrap Loader Routine

Boot Tag Space

32

Boot Tag Processing Code

kbytes

RTOS Firmware Code (optional)

UDP/IP Stack Firmware Code

(optional)

256

kbytes

Contact the factory for further information and sample boot images.

Configuration Parameters

SNMP Agent/MIB Firmware Code

(optional)

A number of configuration parameters can be adjusted by the system implementer to
create a boot image for various types of target systems. The configuration parameters
are located in a single header file that is read automatically whenever a boot image is

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created using the development kit. The following table gives the user-accessible
configuration parameters:

General System Parameters

MstrChipNum Chip number assigned to master device (generally 0)

HashMask Mask setting size of hash table array (0x1fff max)

NumChips Total number of ELAN 1x100 and ELAN 8x10 devices
ChipBase0 Upper 8 bits of base address of device 0 on PCI bus
ChipBase1 Upper 8 bits of base address of device 1 on PCI bus
ChipBase2 Upper 8 bits of base address of device 2 on PCI bus

Error! No index

Upper 8 bits of base address of device 3 on PCI bus

entries found.

ChipBase4 Upper 8 bits of base address of device 4 on PCI bus
ChipBase5 Upper 8 bits of base address of device 5 on PCI bus
ChipBase6 Upper 8 bits of base address of device 6 on PCI bus
ChipBase7 Upper 8 bits of base address of device 7 on PCI bus

Boot Image Header Parameters

BOOT_START Target area reserved for copying boot image from ROM

BOOT_ENTRY Entry point of bootstrap loader/firmware in copied image

BOOT_SIZE Size of boot image in 64-byte blocks (i.e., ROM copy size)

LED_START Address of LED status register for signaling status codes

ROM_LOC Boot image EPROM/EEPROM base address (copy source)

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Parameters Specific to ELAN 1x100

BIGSTRUCTst Start of pool of free packet buffers

nBIGSTRUCTs Number of free packet buffers in pool

HASHSTRUCTst Start of pool of free hash bucket structures

nHASHSTRUCTs Number of free hash bucket structures in pool

SMALLSTRUCTst Start of pool of free forwarding tag structures

nSMALLSTRUCTs Number of free forwarding tags in pool

DISPSTRUCTst Start of pool of free data descriptor structures for messages

nDISPSTRUCTs Number of free message descriptors in pool

DDRINGst Start of transfer ring structures

nDDsPERRING Number of elements per transfer ring

nDDsPERRINGshift Log2 of number of elements per transfer ring

Parameters Specific to ELAN 8x10

XPD_DD Address of first data descriptor attached to transfer queues

FreeHB Start of pool of free hash bucket structures
FreePB Start of pool of free packet buffer structures

FreeDD Start of pool of free data descriptor structures

num_FreePBs Number of free hash bucket structures in pool

LclPBLim Buffer limit per port

Note that further information on ELAN 1x100 data structures can be found later in this
document.

Self Test and Error Reporting

The bootstrap firmware code is expected to implement any required power-on self-test
(POST) functions that are required by the system of which the ELAN 1x100 is a part. If
any of the POST routines detects an error, it is expected to halt the bootstrap process
and write a special code to the (optional) LED register that is mapped into the ELAN
1x100 memory address space. If the LED register is implemented, then the failure
indication can be obtained for diagnostic purposes.

Currently, two primary types of self-test routines are implemented:

1. A checksum is computed over the complete boot image and compared to the
precomputed checksum in the boot image header. If a mismatch is detected,
then the boot image is considered to be corrupted, and cannot be used for
system initialization.

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2. A destructive RAM test is performed over the entire RAM space with the
exception of the space occupied by the boot image itself. The RAM test is quite
simple, and consists of writing a known pseudorandom value to each location in
the RAM and then reading the data back. If the data read is not equal to that
written, then the RAM is considered to be defective, and the system cannot
begin operation. (The RAM self-test is not intended to be an exhaustive device
test aimed at unconditionally detecting a faulty RAM, but merely a fast and
simple test for a gross go/no-go check.)

Additional self-test routines will be implemented in the bootstrap firmware code as
developed.

In addition to the self-test functions performed upon system start-up, the ELAN 1x100
operating firmware also performs numerous checks of its internal state during normal
system operation. If an unrecoverable error is detected, the ELAN 1x100 will output a
status code to the LED register, and then attempt to restart itself (and possibly the
entire system) via the internal watchdog reset facility. If the internal watchdog reset
output (as driven onto the ERST* pin) is connected to the global system reset, then the
ELAN 1x100 will reset the entire system; otherwise, the ERST* pin should be monitored
by an external system master to determine when the ELAN 1x100 is halted due to
some fatal error, and must be reset in order to continue.

In general, LEDs 6 and 7 (i.e., the most significant bits of the LED register) are intended
to be used to provide a general failure indication; LED 5 indicates whether the failure
occurred at self-test and initialization time, or whether the failure occurred during normal
operation; and the rest of the LEDs supply a diagnostic code that can be used to
identify the cause of the failure.

The LEDs also serve to output special codes during system initialization and during
normal operation. In this case, LEDs 6 and 7 will not be lighted. LED 5 indicates
whether the status pertains to system initialization or normal operation. Codes output
during system initialization indicate the index of the bootstrap tag being processed
during the initialization process, and range from 0 to the maximum number of bootstrap
tags in the boot image.

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The codes written out to the LED register are defined below:

Description LED7 LED6 LED5 LED4 LED3 LED2 LED1 LED0

Bootstrap Tag Index Off Off Off Tag[4] Tag[3] Tag[2] Tag[1] Tag[0]

Operational Status

Indication

Boot Checksum

Failure

RAM Self-test

Failure

Operational Failure Blinking On On Code[4] Code[3] Code[2] Code[1] Code[0]

Off Off On Info[4] Info[3] Info[2] Info[1] Info[0]

Blinking On Off Off Off Off Off On

Blinking On Off Off Off Off On Of f

If a failure is detected at any time that causes the ELAN 1x100 to halt normal operation,
the most significant LED (connected to bit 7 of the LED register) will be made to blink
on and off at a 0.5 second rate. The next-most-significant LED (i.e., bit 6 of the LED
register) will be turned ON by writing a zero to this bit position of the LED register; this
serves as a global failure indication, and may alternatively be polled by system
hardware to determine whether a failure has occurred. LED number 5 indicates whether
the failure occurred during system boot-up or normal operation: if it is lit, the system
encountered an unrecoverable error during operation. The remaining five LEDs are
used to signal an error-specific code that can be used for diagnostic purposes. The
codes signalling tag processing information, operational information and operational
errors during operation are TBD.

Data Structures

It is assumed that an earlier bootstrap initialization and configuration phase will have set
up some predefined data structures in ELAN 1x100 local memory. These are the
Switch Processor operating environment (stacks, memory pool, local variables, etc.),
Transfer rings, free pools (containing Packet Buffers, Data Descriptors for messages,
Hash Buckets and Forwarding Tags), the Port Descriptor Table (with the associated
per-port section of the Management Information Base), the MAC address hash table
(which also contains the per-host section of the Management Information Base), and
data associated with the IEEE 802.1d spanning tree bridge configuration algorithm.

The data structures, their function, and the operations performed on them are
described below. In addition, the memory requirements for each type of structure, as
well as the general memory map expected by the Switch Processor operating firmware,
are provided in this section.

The general layout of the various data structures in RAM is shown below. Note that
addresses increase downwards. The actual addresses delimiting various regions of
memory are implementation-specific, and not provided here; instead, the names of the

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parameters supplied during the generation of a boot image that control these addresses
is given next to the memory regions. A description of how these addresses may be
computed, as well as a sample memory map for a typical system configuration, is
provided later in this section.

0x000000

Switch Processor Operating Environment

BIGSTRUCTst

Packet Buffers

DDRINGst

Transfer rings

DISPSTRUCTst

Message Data Descriptors

HASHSTRUCTst

Hash Buckets

SMALLSTRUCTst

Forwarding Tags

BOOT_START

Boot Image Copy Area

Top of RAM

Switch Processor Operating Environment

The Switch Processor requires a small operating environment (i.e., data structures and
variables) for performing basic frame switching functions. This environment is set up in
the external RAM during the bootstrap initialization and configuration phase. The entire
operating environment occupies about 43 kbytes of space, and must be located starting
at address 0x000000 hex in the external memory. The operating environment excludes
the space used by Ethernet frame buffers and the queueing structures used to track
them, and also does not include the code, data or stack spaces that are needed by the
(optional) RTOS, UDP/IP stack, or SNMP agent firmware. The general layout of the
operating environment is as follows:

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0x000000

Reserved for switching firmware
0x001FFF
0x002000

Frequently used variables and parameters (cached)

0x00207f

0x002080

Save space for switching firmware (cached)

0x0020bf

0x0020c0

Local Port Descriptor (cached)

0x0020ff

0x002100

Background Queues (cached)

0x0021ff

0x002200

Random Number Generator Table (cached)

0x0022ff

0x002300

Expansion Port Descriptors (cached)

0x0023ff

0x002400

Dispatch Table

0x0024ff

0x002500

Miscellaneous variables and tables

0x0025ff

0x002600

Port Descriptor Error Counters

0x00267f

0x002680

Transmit Distribution FIFO

0x0028ff

0x002900

Hash Table

0x00a8ff

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The components of the operating environment are as follows:

1. The first 8192 bytes of space are reserved for holding switching firmware code.
This space is intended to serve as a backup for the internal 8192 byte
instruction RAM present in the ELAN 1x100.

2. The next 128 bytes are used to hold various frequently referenced, global
variables, such as the exception masks, broadcast counters, etc. These
variables normally reside in the Switch Processor data cache, and hence their
memory image may be inconsistent until the cache is flushed to memory.

3. A block of 64 bytes is reserved for use by the switching firmware as a register
save space during interrupts. This area is also cached.

4. A Local Port Descriptor is placed in the next 64 bytes. The Local Port
Descriptor also resides in the Switch Processor data cache, and this region of
memory will thus contain out-of-date values until the data cache is flushed. The
Local Port Descriptor contains statistics and control information used during
frame switching, and is described in further detail below.

5. A set of 16 Background Queues are placed in the next 256 bytes. These
queues are used to transfer frames and messages from the foreground
switching tasks to background and management tasks. The Background
Queues reside in the cached memory area.

6. The next 256 bytes are reserved for the Random Number Generation Table.
This table contains an array of seed values that are used to generate pseudo­random numbers during the computation of backoff timer values for half-duplex
collision handling.

7. A set of eight Expansion Port Descriptors occupies another 256 bytes. These
data structures hold information pertaining to the devices accessible via the PCI
expansion bus. As in the case of the Local Port Descriptors, the Expansion Port
Descriptors are normally cached and the memory region will not be updated
until a data cache flush. The Expansion Port Descriptors are discussed in more
detail below.

8. A Dispatch Table, consisting of an array of pointers to firmware routines that
acta as handlers for special situations or for error recovery purposes. A block of
256 bytes is reserved for the Dispatch Table. Note that the Dispatch Table is
located immediately following the cached region of the Switch Processor
operating environment; this and all subsequent data structures are not cached.

9. The next 256 bytes are reserved for miscellaneous variables utilized on an
infrequent basis by the switching firmware. This includes things such as a
generic hash bucket structure and debug variables.

10. A Port Descriptor Error Counter structure is provided to hold error and collision
statistics for the local (MAC) port. The counter block requires 96 bytes of

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storage; the remaining 32 bytes being reserved for future applications. These
counters are also described in more detail below.

11. The next 640 bytes are used for a firmware-maintained Transmit Distribution
FIFO. This FIFO holds flags and address table information for frames that are
queued for transmit in the internal 2048-byte transmit FIFO, and is used by the
Switch Processor for post-transmit processing.

12. The remaining 32768 bytes of space are reserved for the Hash Pointer Array.
This array forms the base of the MAC address hash table; each 4-byte entry in
the array contains a pointer to a chain of hash buckets that hold the actual per­MAC information required for frame switching. The entire array is cleared to zero
(NULL) during the initialization process. The Hash Pointer Array contains a total
of 8192 pointers.

The first 1024 bytes of the operating environment (ranging from 0x2000 through 0x23ff
hex, in the memory map above) are normally cached by the Switch Processor in the
data cache. As the data cache uses a write-back policy, the actual memory locations
corresponding to the cached structures may be out-of-date (i.e., not reflect the most
recent information written to the locations by the firmware). For instance, the per-port
SNMP counters contained within the Local Port Descriptors are cached, and hence the
memory images of the per-port counters may not be up-to-date. Thus the Switch
Processor must be forced to flush the data cache to update the external memory
locations prior to reading them from an external CPU via the PCI bus. This can be
accomplished via the messaging interface described further within this section.

It is the responsibility of the bootstrap and initialization firmware contained within the
boot image to set up and initialize the entire operating environment described above.

Variables and Tables in Operating Environment
The Switch Processor operating environment contains a number of variables and tables

used during normal operation. Some of these memory locations (i.e., those located
between addresses 0x2000 and 0x20c0 hex in the memory map above) are normally
expected to be cached in the Switch Processor data cache, while the remainder are
never loaded into the data cache by the operating firmware. The following is a brief
listing of the significant variables in the operating environment:

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Variable Name Width

Description

(bits)

cdHStruct 24 Pointer to head of linked-list of free hash buckets
cdSStruct 24 Pointer to head of linked-list of forwarding tags

cdDFIFOwr 24 Pointer to head entry in Distribution FIFO

Error! No index

entries found.

Error!

No index

Error! No index entries found.

entries

found.

cdTotCollide 32 Total number of collisions encountered on MAC port

cdDStruct 24 Pointer to head of free data descriptor pool reserved for holding

messages

cdCurrentXPD 24 Temporary storage: holds address of expansion port descriptor

currently in use

cdLNR 32 Temporary save space for LNR register in Switch Processor

cdFirstHash 24 Temporary storage: holds the address of the first hash bucket

or forwarding tag in a chain of address table entries

cdHashIdxMask 16 Bitmask used to restrict the range of the hash key computed as

an index into the hash array

cdRefMask 16 Global bitmask restricting devices and ports to which multicasts

and broadcasts may be directed
* 8 LSBs are unused, set to zero

* 8 MSBs correspond to the eight possible devices in a system

cdChipNum 8 Logical chip number assigned to this ELAN 1x100

cdNumChips 8 Total number of ELAN chips in system (both ELAN 1x100 and

others)

cdPCIRefCount 8 Reference count to use during broadcasts

cdAgeTick 8 Aging task trigger flag

cdAgeEnable 8 Aging task enable flag

cdDDsInRingShift 16 Log2 of number of elements in each transfer ring structure

cdFPullTl 24 Pointer to tail of management frame being extracted from

internal transmit FIFO by firmware

cdFPullHd 24 Pointer to head of management frame being extracted from

internal transmit FIFO by firmware

cdFPullBytes 16 Number of bytes remaining for management frame being read

out of internal transmit FIFO by firmware

cdDispatchPCI 24 Pointer to next free message data descriptor to use for

queueing messages for background processing

cdFPush 24 Pointer to management frame being written into internal

transmit FIFO by firmware

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Packet Buffers

Ethernet frames are stored in the external SRAM by the ELAN 1x100 chip in small,
fixed length

packet buffers

; with multiple packet buffers being chained in a linked list to
hold a complete Ethernet frame. The size of every packet buffers is determined at
configuration time, and may range from 64 to 240 bytes; the default is 80 bytes.

Each packet buffer contains an 8-byte header holding various control information fields,
and from 0 to at most (N - 8) bytes of payload comprising Ethernet frame data. (In this
context 'N' denotes the total size of each packet buffer: the default 80-byte packet
buffers will contain at most 72 bytes of payload.) The Ethernet data stored in the packet
buffers includes the Ethernet header and CRC fields.

A MAC channel byte-swap control bit is implemented in the LWCTRL device control
register (see register descriptions below). If the byte swap control is set to the default of
zero, indicating no byte swap, the packet buffers have the following format (where 'N' is
the total size of the packet buffer in bytes):

31 24 23 16 15 8 7 0 Byte Offset

Size NextPB 0

Last Size RefCount unused, reserved 4

PayloadByte0 PayloadByte1 PayloadByte2 PayloadByte3 8
PayloadByte4 PayloadByte5 PayloadByte6 PayloadByte7 12

. . . .

PayloadByte(n-4) PayloadByte(n-3) PayloadByte(n-2) PayloadByte(n-1) (N-4)

If the MAC channel is set up to swap the incoming frame bytes, then the payload field
of the packet buffers will be byte-swapped, but the headers will be left unchanged, as
shown below:

Byte

31 24 23 16 15 8 7 0

Size NextPB 0

LastSize RefCount unused, reserved 4

PayloadByte3 PayloadByte2 PayloadByte1 PayloadByte0 8
PayloadByte7 PayloadByte6 PayloadByte5 PayloadByte4 12

. . . .

PayloadByte(n-1) PayloadByte(n-2) PayloadByte(n-3) PayloadByte(n-4) (N-4)

Offset

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NextPB:

24-bit pointer to next packet buffer in linked-list of packet buffers constituting
a frame. If no next packet buffer exists (i.e., this is the tail of the linked-list),
then this field is NULL (all-zeros).

Size:

8-bit size of packet buffer payload (excludes the 8-byte header), in bytes.

RefCount:

8-bit reference count associated with frame: gives the number of Data
Descriptor Ring queues that are pointing to this packet buffer.

LastSize:

8-bit count of total number of valid payload bytes (not including the 8-byte
header) in the last packet buffer in the linked-list of buffers. Only valid if this is
the first packet buffer in the linked-list, and there is more than one packet
buffer in the linked-list.

PayloadByte0 - PayloadByte(n-4):

8-bit packet buffer payload bytes: contains Ethernet frame data for the frame
contained within the linked-list of packet buffers.

The NextPB field in the packet buffer header contains a pointer to the next packet
buffer in a the chain of buffers that holds the entire Ethernet frame. If this is the last (or
only) buffer in the chain, then this field is set to zero to indicate a NULL pointer and
hence the end of the linked list. The Size field holds the number of valid payload bytes
(i.e., excluding the 8 packet buffer header bytes) in the packet buffer payload field; for
an 80-byte packet buffer, the value in this byte can range between 0 and 72. A value of
zero indicates a completely empty packet bu ffer with no data, which will simply be
skipped over by the hardware or firmware with no ill effects.

The RefCount field holds a reference count indicating the number of ports or devices to
which the packet buffer contents must be transmitted, and is used to determine when
the packet buffer may be freed. The reference count is normally 1 for unicast frames,
and equals the sum of the number of destination ports and devices for broadcasts; it is
only valid for the last packet buffer in a chain (i.e., when the next packet buffer pointer
is NULL), and is ignored in other buffers.

The LastSize field in the header holds the total number of valid bytes, not including the
header, in the last packet buffer in a linked list of buffers. It should be placed in the first
packet buffer in the chain, and is principally used to optimize processing of packet
buffers by the hardware. This field is ignored if there is only one packet buffer in the
chain, or if the buffer under consideration is not the first one in the chain.

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The remaining bytes in the packet buffer contain the payload, consisting of Ethernet
frame bytes received by the MAC channel of the ELAN 1x100 (or created via software).
The bytes are placed into the packet buffer in the order depicted above, depending on
the setting of the byte swap hardware configuration bit. Note that 'PayloadByte0' in the
above diagrams refers to the first byte received from the medium for the payload of the
given packet buffer; in the case of the first packet buffer in a chain, this byte will contain
the LSB of the 48-bit MAC destination address in the Ethernet frame header.

Packet buffer chains may also be used by the various chips in the system to contain
message data that is to be exchanged between devices interfaced to the PCI bus. If a
packet buffer holds message data rather than Ethernet frame data, then the format of
the header is unchanged, but the payload field is formatted in a message-specific
manner.

Data contained within packet buffers is never cached by the Switch Processor, and
hence the contents of any packet buffer may be read at any time via the PCI expansion
port. In normal operation, packet buffers are primarily manipulated by the DMA
hardware; the Switch Processor usually writes only the RefCount and LastSize fields.

Data Descriptors

Ethernet frames, messages and other pieces of data being transferred between devices
within an ELAN 1x100 system, or between tasks on a single ELAN 1x100, are tracked
by means of 16-byte

data descriptors

. (When a data descriptor refers to an Ethernet
frame that contains management data to be processed by the ELAN 1x100 system
itself, or to buffers holding control and status data that are exchanged for messaging
purposes within the ELAN 1x100 system, then it is sometimes referred to as a

descriptor

.)

message

Data descriptors form the primary queueing elements in the ELAN 1x100 device: in
addition to forming the individual elements of transfer rings (see below), they are used
to hold message information and to create special frame handling queues for
management functions. All data descriptors have the same general format, and contain
pointers to the first and last packet buffer of a packet buffer chain holding an Ethernet
frame or a control/status message, flags fields that indicate the processing to be
performed on the frame or message, and other information required for processing the
payload.

In general, data descriptors are formatted as follows:

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Byte

31 24 23 16 15 8 7 0

Flags NextDD 0

NumPBs FirstPB 4

SrcPort LastPB 8

SrcChip HashBkt 12

Offset

NextDD:

24-bit pointer to next data descriptor in linked-list of data descriptors forming
message queue or transfer ring.

Flags:

8-bit data descriptor flags field, formatted as below.

FirstPB:

24-bit pointer to first packet buffer in linked-list of packet buffers containing
frame or message data. If NULL (zero), no packet buffer chain exists for this
data descriptor; this is only valid for special message data descriptors where
all message data can be contained within the 16-byte descriptor structure
itself.

NumPBs:

8-bit count of packet buffers in chain pointed to by FirstPB. If FirstPB is NULL
(zero), then this field can be used for message-specific purposes.

LastPB:

24-bit pointer to last packet buffer in linked-list of packet buffers pointed to by
FirstPB. If FirstPB is NULL (zero), then this field can be used for message­specific purposes.

SrcPort:

8-bit source port index within device: indicates the MAC channel upon which
the frame was received. For the ELAN 1x100, this field wil be 0 since the
device only has one port. Only valid if the descriptor points to an Ethernet
frame that was actually received on a MAC channel; otherwise, can be used
for message-specific purposes.

HashBkt:

24-bit pointer to source or destination hash bucket. Only valid for Ethernet
frames; if the descriptor indicates a message, then this field can be used for
message-specific purposes.

SrcChip:

8-bit index of source device that received frame. For the ELAN 1x100 system,

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this must range from 0 through 7. Only valid for Ethernet frames; if the
descriptor indicates a message, then this field can be used for message­specific purposes.

The NextDD field in the data descriptor contains a pointer to the next data descriptor in
a chain of descriptors that constitutes a queue of Ethernet frames or messages. If this
is the last (or only) element in the queue or chain, then this field is set to zero to
indicate a NULL pointer and hence the end of the linked-list.

The Flags field holds a set of flag bits and bitfields that provide type and control
information for the data descriptor, and is formatted as follows:

765 43 0

Learn Special Type MsgCode

Learn:

If set, indicates that the source address (SA) field of the Ethernet frame
pointed to by this descriptor contains a new MAC address that must be
learned by the device. Only valid for Ethernet frames received by the ELAN
1x100 from the PCI expansion port; should not be set if the data descriptor
points to a message.

Special:

Type:

If set, indicates that the data contained within the packet buffer chain pointed
to by this data descriptor requires special processing by the firmware, and
should not be treated as a normal Ethernet frame. This bit is typically set to
indicate a message that is being passed between devices on the PCI
expansion port, or between firmware tasks on an ELAN 1x100.

This 2-bit field contains the type of frame pointed to by the data descriptor
FirstPB field, and is interpreted as follows:

Type Interpretation

00 Unicast frame from remote device
01 Unicast frame from local MAC channel
10 Broadcast frame from remote device
11 Broadcast frame from local MAC channel

The above definitions of the Type field are only valid if the Special bit is clear,
indicating that this data descriptor points to a normal Ethernet frame.

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MsgCode:

The 4-bit MsgCode field is only valid if the Special bit is set; in this case, it is
used to carry a message code that identifies the type of message carried by
the packet buffers to which this data descriptor points.

Msgcode Interpretation

0000 reserved
0001 reserved
0010 reserved
0011 reserved
0100 Topology change notification message
0101 Forwarding tag deletion request message
0110 reserved
0111 ARP broadcast frame message
1000 reserved
1001 reserved
1010 reserved
1011 reserved
1100 reserved
1101 reserved
1110 reserved
1111 reserved

The FirstPB and LastPB fields contain the 24-bit addresses of the head and tail,
respectively, of the linked-list of packet buffers that are associated with this data
descriptor. If only one packet buffer is present in the linked-list, then the FirstPB and
LastPB pointers contain the same value. It is an error for the FirstPB field to be zero in
any valid data descriptor that points to an Ethernet frame; however, message data
descriptors (i.e., those used for exchanging messages between ELAN 1x100 devices)
may optionally have the FirstPB field set to zero, if the entire content of the message
can be placed in unused fields of the data descriptor. The NumPBs field contains the
count of the number of packet buffers contained within the linked-list of packet buffers,
and may range between 1 and 255.

The SrcPort and SrcChip fields indicate the source port index and the source device
index, respectively, on which the Ethernet frame entered the system. The value in the
SrcPort field will be always be a constant 0 as the ELAN 1x100 only has one MAC
channel; the value placed in the SrcChip field by any ELAN 1x100 device is assigned
as a system parameter during the device boot-up and initialization process, using data
obtained from the boot image. If the Learn bit is set in the data descriptor Flags field,

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then both of these fields are used to associate the source MAC address within the
Ethernet frame with a particular device and physical port. These fields are generally not
valid for message descriptors, in which case they contain message-specific information.

The HashBkt field holds the 24-bit local memory address of the address hash bucket
associated with either the source or destination MAC address in the Ethernet frame
header. If the Ethernet frame is to be broadcast (or the Learn bit is set, and the frame
must be flooded), the HashBkt field holds the memory address of the hash bucket
corresponding to the source MAC address in the source device's address space; if, on
the other hand, the frame is a unicast, then the HashBkt field contains the memory
address of the hash bucket for the destination MAC address in the destination device's
address space. The HashBkt field has a dual purpose: it is used to learn the memory
address of a source hash bucket during broadcasts and floods, and is also used to
indicate a target destination hash bucket to use in switching unicast frames once
address learning is complete. More details on the use of the HashBkt field in various
situations will be provided in subsequent sections. Note that the HashBkt field is not
used when the data descriptor does not point to an Ethernet frame (i.e., is a message
descriptor); in this case, it contains message-specific information.

Data descriptors are never cached by the Switch Processor, and hence the contents of
any data descriptor that is not actually being processed by the Switch Processor or ring
hardware may be read at any time via the PCI expansion port.

Transfer Rings

A set of fixed-size data structures, called

transfer rings

, are used to control the transfer
of Ethernet frames and control/status messages to other devices interfaced to the
ELAN 1x100 via the PCI expansion bus. Each transfer ring is dedicated to a particular
external device, and points to frame or message data that must be sequentially
transferred to that device across the PCI bus. Transfer rings thus operate under a FIFO
queueing discipline. The general structure of the transfer rings is given below:

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DDRINGst Element 0

Element 1
Element 2

Transfer Ring 0 Element 3

.
.

Element (N-1)

DDRINGst + 16*N Element 0

Element 1
Element 2

Transfer Ring 1 Element 3

.
.

Element (N-1)

DDRINGst + 32*N

DDRINGst + 112*N Element 0

Transfer Ring 7 Element 3

.
.
.
.

Element 1
Element 2

.
.

Element (N-1)

Each transfer ring consists of N elements, where N is a power of 2. (The actual value of

is an implementation parameter, and is determined at system initialization time by

N

configuration parameters in the boot image.) Each element in a transfer ring is
formatted as a data descriptor structure; the NextDD field in each data descriptor is set
up by the bootstrap firmware to point to the next consecutive element in the same
transfer ring, with the last element in a transfer ring being set up to point back to the
first. The elements in a given transfer ring therefore create a closed linked-list; if the
NextDD pointers are followed starting from any element in the ring, the path followed
will eventually return to the starting point. The remainder of the fields in each element
(beyond the NextDD pointer) are left uninitialized at system startup.

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When an Ethernet frame or a control/status message is to be transferred to another
device in the system, the first free element in the transfer ring corresponding to that
device is set up appropriately to point to the frame or message. (If the message is
sufficiently small, then the message data may simply be written into fields within the
element instead.) Additional frames or control messages are queued for the same
device by simply setting up consecutive elements in the transfer ring as required; when
the last element in a ring has been assigned to a frame or message, the index of the
next free element is wrapped back to the start of the ring. The transfer rings are hence
used as a true ring buffer.

The receiving entity (i.e., external device on the PCI bus) is expected to retrieve
messages from the appropriate transfer ring when notified to do so. Message retrieval
is performed in the same order that the messages were placed on the ring. Since each
element is formatted as a data descriptor structure, the receiving entity can obtain all of
the information necessary to retrieve the Ethernet frame or control/status message
payload by simply reading the contents of the element. After a given element has been
read by the receiving entity, it is expected to notify the ELAN 1x100 that the element is
now available to hold another Ethernet frame or control/status message.

The actual notification process whereby the ELAN 1x100 signals a remote device that
one or more elements contain information about Ethernet frames or messages that are
ready for transfer is supported by special communication hardware described later.
Similarly, the notification of retrieved elements by remote devices to the ELAN 1x100 is
also performed with hardware support described in a later section. The ELAN 1x100
also implements hardware that allows the Switch Processor to efficiently queue frames
and messages to multiple transfer rings, for use during broadcasts and multicasts.

Note that a unicast message or frame (i.e., information that is directed towards only one
external device on the PCI expansion bus by the ELAN 1x100) results in only one data
descriptor being allocated and formatted on a single transfer ring. A multicast message
or frame, however, requires multiple elements to be set up in as many transfer rings as
there are recipients of the message.

The sizes of the various transfer rings determine the maximum number of frames or
messages that can be queued at any one time for the corresponding devices. The
selection of these sizes therefore has a substantial impact on the efficiency and
performance of the system. The number of elements within each transfer rign may
range from 32 to 65,536, in powers of 2 (representing actual memory sizes of 512 to
1,048,576 bytes). Criteria for selecting the sizes of the transfer rings are given later in
this section.

None of the elements in any transfer ring is cached by the Switch Processor, and hence
they can be read safely at any time over the PCI bus.

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Local Port Descriptor and Port Descriptor Counters

A data structure, called the

Local Port Descriptor,

is associated with the MAC interface
within the ELAN 1x100. The local port descriptor contains various control/status and
frame statistics fields, and is updated whenever a frame is received or transmitted by
that MAC interface.

Associated with the local port descriptor is another structure, referred to as the

Descriptor Counter Structure

, that contains a set of frame error statistics fields which

Port

track various error counts updated on an infrequent basis during normal operation. Both
of these structures are under the sole control of the Switch Processor, and never
modified or read by the rest of the ELAN 1x100 hardware.

Both the local port descriptor and the port descriptor counter structure are located in the
Switch Processor operating environment, and are indicated in the previously supplied
memory map. Note that both structures are completely under the control of the Switch
Processor firmware, and are never read or modified by the ELAN 1x100 hardware.

Local Port Descriptor Structure
The local port descriptor structure occupies 64 bytes, and is formatted as follows:

Byte
31 24 23 16 15 8 7 0
NumCollide reserved 0

0x00 reserved 4

MulticastMask MaxBuffers 8

PortFlags reserved BackoffMask 12

TXFrames 16

TXOctets 20

TXFirstDefer 24

reserved 28

RXUcstFrames 32

RXValidOctets 36

RXFrames64 40

RXFrames65-127 44
RXFrames128-255 48
RXFrames256-511 52

RXFrames512-1023 56

RXFrames1024-1518 60

Offset

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NumCollide:

8-bit count of collisions experienced so far while attempting to transmit the
frame at the head of the transmit FIFO cleared to zero before starting the first
transmission attempt for each frame. Note that this field is only used in half­duplex operation.

MaxBuffers:

16-bit count of packet buffers that remain available to hold incoming received
frames; flow control or frame discard will be initiated when this count goes to
zero.

MulticastMask:

16-bit mask used to restrict broadcasts and multicasts received on the ELAN
1x100 MAC channel to a subset of the external devices in the system (that is,
to restrict frame forwarding over the PCI expansion bus). The lower 8 bits of
this mask are always zero.

BackoffMask:

16-bit mask used to limit the range of collision backoff values generated by
the truncated binary exponential backoff algorithm for this port. Note that only
the lower 10 bits are significant; the upper 6 bits of this field should always be
set to zero.

PortFlags:

8-bit control flags used for controlling switching of frames received over the
ELAN 1x100 MAC port, or transmitted over the port.

TXFrames:

32-bit count of frames (unicast, multicast or broadcast) successfully
transmitted on this port without errors.

TXOctets:

32-bit count of total number of bytes successfully transmitted on this port
without errors.

TXFirstDefer:

32-bit count of total number of frames that were forced to defer to incoming
(receive) traffic during their first transmission attempt. This counter will
always be zero if the MAC port is configured for full-duplex operation.

RXUcstFrames:

32-bit count of valid unicast frames received on this port.

RXValidOctets:

32-bit count of non-errored bytes received on this port.

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RXFrames64:

32-bit count of frames received on this port, whether errored or non-errored,
that were 64 bytes in size.

RXFrames65-127:

32-bit count of frames received on this port, whether errored or non-errored,
that ranged between 65 and 127 bytes in size, inclusive.

RXFrames128-255:

32-bit count of frames received on this port, whether errored or non-errored,
that ranged between 128 and 255 bytes in size, inclusive.

RXFrames256-511:

32-bit count of frames received on this port, whether errored or non-errored,
that ranged between 256 and 511 bytes in size, inclusive.

RXFrames512-1023:

32-bit count of frames received on this port, whether errored or non-errored,
that ranged between 512 and 1023 bytes in size, inclusive.

RXFrames1024-1518:

32-bit count of frames received on this port, whether errored or non-errored,
that ranged between 1024 and 1518 bytes in size, inclusive.

The NumCollide field is used to track the number of consecutive collisions encountered
when attempting to transmit a given frame in half-duplex mode. It is cleared to zero
prior to starting the transmit of every frame. If a collision terminates the frame
transmission attempt, this field is incremented by one; if the count of collisions for this
frame exceeds the pre-defined maximum (generally, a default value of 16, according to
the IEEE 802.3 standard), then the frame is discarded and an error is reported. The
NumCollide field will always be zero if the MAC port is in full-duplex mode.

MaxBuffers is expected to be initialized (during the system boot-up process) with the
maximum number of packet buffers that may be allocated to hold Ethernet frames by
the ELAN 1x100 during reception. This field is decremented by the number of packet
buffers used to store each received Ethernet frame; when it becomes less than or equal
to zero, the switching firmware will refuse to accept any more frames, and will discard
frames if received. MaxBuffers is incremented whenever an Ethernet frame that was
received on this MAC port has been completely transferred to all external ELAN devices
over the PCI expansion bus, and its packet buffers are freed. If backpressure (for a
half-duplex link) or PAUSE flow control (for a full-duplex link) is enabled, then a
globally-configurable threshold is defined; if the value of the MaxBuffers field falls below
this threshold, then the MAC channel will start the appropriate flow control mechanism,
which will consist of either channel jamming in half-duplex mode, or transmission of a
PAUSE control frame to the upstream station in full-duplex mode.

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The 16-bit MulticastMask field is used to restrict broadcasts, multicasts and floods of
packets received on the MAC channel with which this local port descriptor is
associated. The 8 LSBs of this mask are always set to zero on the ELAN 1x100, while
the upper 8 bits of the mask correspond on a one-to-one basis to the eight possible
devices in the system. A device is permitted to be part of a multicast if its corresponding
bit in the MulticastMask field is set to a '1'. (Note that the bit in the MulticastMask
corresponding to the ELAN 1x100 device itself is always set to zero at initialization
time.) The MulticastMask field is logically ANDed with the global restriction mask
managed by the spanning tree protocol entity to permit broadcasts to be further
restricted to remove loops in the broadcast topology.

A 16-bit BackoffMask field is provided to allow the range of collision backoff values to
be adjusted via management access. The BackoffMask field contents are logically
ANDed with the standard pseudorandom backoff value generated according to the
IEEE 802.3 backoff timer computation algorithm. The uppermost 6 bits of the
BackoffMask must be set to zero. The lower 10 bits should normally be set to all-ones,
if the IEEE 802.3 standard backoff algorithm (which specifies a range of 0 to 1023 slot
times, inclusive) is to be adhered to; however, smaller ranges of backoff values may be
generated by reducing the number of '1' bits set in this mask.

The PortFlags field supplies several port-specific control bits that are used to determine
the operating mode of the switching firmware when handling Ethernet frames that are
received from or transmitted to this port. This field is formatted as:

76 5 43210

BackPEn Special Type reserved TXBlkd RXBlkd BackPRn

BackPEn:

If set, indicates that backpressure flow control is enabled for this port. This bit
is normally set via a configuration parameter at system initialization time.

Special:

If set, indicates that the data descriptors created for Ethernet frames received
on this MAC channel should have the Special flag bits set in their Flags fields,
causing them to be specially handled by the switching firmware. Normally set
to zero.

Type:

This 2-bit field is used to initialize the 2-bit frame Type subfield in the Flags
fields of data descriptors corresponding to Ethernet frames received on this
MAC channel. Normally set to 01 binary, corresponding to unicast frames
received on a local MAC channel.

TXBlkd:

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If set, indicates that the MAC channel is blocked to transmit; i.e., no frames

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can be transmitted out this MAC channel. Normally used by the spanning tree
algorithm.

RXBlkd:

If set, indicates that the MAC channel is blocked to received; i.e., frames
received on this MAC channel must be discarded. Normally used by the
spanning tree algorithm.

BackPRn:

If set, indicates that backpressure flow control is running for this port.

The remainder of the local port descriptor holds per-port counters that are maintained
and updated by the switching firmware in order to support the SNMP and RMON MIB
statistics. A total of 11 32-bit counters are implemented.

The Switch Processor caches the local port descriptor during normal operation. The in­memory copy of the local port descriptor, therefore, is likely to be 'stale' (i.e., outdated
by information in the Switch Processor's data cache). The local port descriptor should
preferably be read, if desired, by using the message interface maintained by the Switch
Processor. If the contents of the local port descriptor must be directly read over the PCI
bus, the Switch Processor data cache must be flushed prior to the read, again via the
message interface, which is described later.

Port Descriptor Counter Structure
The 96-byte port descriptor counter structure is considered to be an auxiliary data

structure to the local port descriptor. This structure contains various error and collision
counters that are infrequently updated during normal operation. The purpose of
separating these counters from the local port descriptor structures is to reduce the
amount of data that must be cached in the Switch Processor data cache: the port
descriptor counter structures are not cached by the Switch Processor.

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Each port descriptor counter structure is formatted as follows:

Byte

31 24 23 16 15 8 7 0

SingleCollide 0

MultCollide 4
LateCollide 8

CollideAbort 12

RXErrorOctets 16

AlignErrors 20
CRCErrors 24

DribbleFrames 28

OVFErrors 32

OversizeErrors 36

JabberErrors 40

ShortErrors 44

FragErrors 48
LimitErrors 52

TXErrors 56

reserved 60

RXBcstFrames 64

RXBcstOctets 68

RXFloodFrames 72

RXFloodOctets 76

RXMcastFrames 80

RXMcastOctets 84

reserved 88
reserved 92

Offset

SingleCollide:

32-bit count of single collisions encountered when attempting to transmit
frames out this MAC port. Only valid in half-duplex mode.

MultCollide:

32-bit count of multiple collisions encountered when attempting to transmit
frames out this MAC port. Only valid in half-duplex mode.

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LateCollide:

32-bit count of late collisions encountered when attempting to transmit frames
out this MAC port. Only valid in half-duplex mode.

CollideAbort:

32-bit count of transmit frames that were discarded due to excessive
collisions for this MAC port. Only valid in half-duplex mode.

RXErrorOctets:

32-bit count of total number of octets for received frames that exhibited an
error: this includes frames having alignment, CRC, FIFO overflow, oversize,
jabber, short, collision fragment or buffer limit errors.

AlignErrors:

32-bit count of frames received on this MAC port with alignment errors. A
frame is deemed to have an alignment error if it is of valid length, and had an
incorrect CRC together with an odd number of framed data nibbles received
on the MII interface. In this context, "valid length" means an actual frame
length, excluding the preamble and SFD, between 64 and 1518 octets,
inclusive.

CRCErrors:

32-bit count of frames received on this MAC port with CRC errors. A CRC
error is declared if a received frame is of valid length, had an even number of
framed data nibbles as received on the MII interface, and failed the FCS
check.

DribbleFrames:

32-bit count of the number of frames that were received with dribble errors. A
frame is considered to have a dribble error if it has an odd number of framed
data nibbles as received on the MII interface, but was otherwise non-errored
(including the FCS check). Note that frames with dribble errors will still be
accepted and forwarded by the switching firmware, and will hence cause the
RXValidOctets counter to be incremented.

OVFErrors:

32-bit count of frames received on this MAC port that were otherwise valid,
but dropped due to receive FIFO overflow.

OversizeErrors:

32-bit count of frames received on this MAC port that passed the FCS check
but exceeded the preset maximum frame length limit (nominally1518 octets).

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JabberErrors:

32-bit count of frames received on this MAC port that failed the FCS check
and was longer than the preset maximum frame length.

ShortErrors:

32-bit count of frames received on this MAC port that passed the FCS check
but were below the preset minimum frame length (nominally 64 octets).

FragErrors:

32-bit count of frames received on this MAC port that failed the FCS check
and were below the preset minimum frame length. These frames are typically
collision fragments.

LimitErrors:

32-bit count of frames received on this MAC port that were dropped due to
lack of buffer space to hold them (i.e., as a result of congestion).

LengthErrors:

32-bit count of frames received on this MAC port that failed the IEEE 802.3
length check (i.e., the Length field within the frame was between 45 and 1499
inclusive, but did not match the actual frame length).

TXErrors:

32-bit count of frames that were dropped while being transmitted out this
MAC port. This counter is always zero during full-duplex operation; in half­duplex mode, it is incremented whenever a valid frame is dropped from the
transmit FIFO due to late collision, excessive collisions, or excessive carrier
deference.

RxBcstFrames:

32-bit count of valid broadcast frames received on this port (that is, the
destination address of the received frame is all-ones, corresponding to the
IEEE 802.3 broadcast address).

RXBcastOctets:

32-bit count of octets in valid broadcast frames received on this port.

RxFloodFrames:

32-bit count of valid frames received on this port that were flooded to all ports
on the spanning tree. A frame is flooded if the 48-bit destination address is
not an IEEE 802.3 Group/Functional address (i.e., the LSB of the address is
zero, indicating a unicast destination) and an entry for the destination address
is not present in the address table.

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RXFloodOctets:

32-bit count of octets in valid flood frames received on this port.

RxMcstFrames:

32-bit count of valid multicast frames received on this port (i.e., the 48-bit
destination addresses of the counted frames are IEEE 802.3
Group/Functional addresses, but not the broadcast address of all-ones).

RXMcastOctets:

32-bit count of octets in valid multicast frames received on this port.

The counters maintained within the port descriptor counter structure correspond to
those required by the RMON and SNMP MIBs.

The port descriptor counter structure occupies the memory locations described in the
address map previously given. As the port descriptor counter structure is not cached, it
may be read at any time via PCI bus accesses.

Expansion Port Descriptor Table

A set of data structures, collectively referred to as the

Expansion Port Descriptor Table

is associated with the PCI expansion port. The Expansion Port Descriptor Table
consists of eight 16-byte

expansion port descriptors

, each representing one of the (at
most) eight ELAN 1x100 devices (or compatible devices, such as the ELAN 8x10) in the
system. The expansion port descriptor table is used in conjunction with the transfer
rings by the switching firmware to transfer frames and messages to other devices within
the system.

A single expansion port descriptor and the corresponding frame transfer queue is
assigned to each device present on the PCI bus; as there can be at most seven
external devices (i.e., excluding the ELAN 1x100 itself), only seven of the eight
expansion port descriptors are used, and the eighth descriptor is left untouched. Each
expansion port descriptor is hence effectively assigned to a logical device, with indices
ranging from 0 through 7. The expansion port descriptor structures are mapped into the
memory locations as given in the foregoing address map, with the structure
corresponding to logical device index zero being mapped into the lowest memory
address, and so on.

Note that the use of the expansion port descriptors is not limited to communicating with
ELAN 1x100 devices. Any device that implements the same transfer protocol can be
interfaced to the ELAN 1x100 PCI bus interface and assigned an expansion port
descriptor (with the associated frame transfer queue), and the ELAN 1x100 device will
transfer frames to this device without any special considerations. A detailed description
of the frame transfer protocol, and the use of the expansion port descriptor and transfer

,

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ring structures to sequence the transfer of data across the PCI bus, is given in a
subsequent section.

An expansion port descriptor occupies 16 bytes, and is formatted as follows:

31 24 23 16 15 8 7 0 Byte

Offset

ChipNum RingBase 0

CtrMask reserved 4

reserved reserved 8

RemDD 12

RingBase:

24-bit pointer to first data descriptor in the transfer ring corresponding to this
expansion port descriptor. This field is initialized with the base address fo the
appropriate transfer ring during system boot, and remains unchanged
thereafter.

ChipNum:

8-bit index assigned to remote chip corresponding to this expansion port
descriptor. This field is set up at initialization time to contain a '0' for the first
expansion port descriptor (i.e., with index 0), a '1' for the second expansion
port descriptor, and so on.

CtrMask:

8-bit mask that must be passed to the DMA Controller increment channel
hardware when attempting to increment a request or acknowledge counter in
the remote device.

RemDD:

32-bit PCI address of next data descriptor pointing to frame to be transferred
from remote device. Generally, the uppermost 8 bits of this field remain
constant, and give the upper 8 bits of the PCI base address set for the
remote device; the lower 24 bits vary, and give the offset of the data
descriptor with reference to the PCI base address.

The ChipNum and CtrMask fields are statically configured during initialization time.
ChipNum should be loaded with the index of the remote device, and is used by the
firmware during consistency checks. The CtrMask field contains an 8-bit mask with the
bit corresponding to the numeric index of the remote device set, and all of the other bits
cleared. For example, CtrMask in expansion port descriptor zero (the first descriptor)
will be set to 00000001 binary; that in the second expansion port descriptor will be set
to 00000010 binary; and so on. The contents of CtrMask are loaded into the DMA
Controller increment channel parameter registers when the switching firmware desires

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to increment either the request or acknowledge counter in the remote device during
expansion port frame transfers.

The RemDD field holds the 32-bit PCI address of the data descriptor at the head of the
transfer queue or ring assigned to this ELAN 1x100 in the remote device. This field is
set up at system initialization time: the uppermost 8 bits are set to the 8 MSBs of the
PCI base address of the remote device, while the lower 24 bits are set up to be equal to
the value loaded into the RingBase field of the expansion port descriptor in the remote
device (i.e., the address of the first data descriptor in the remote device's transfer
queue or ring). After frame transfer from the remote device begins, the uppermost 8 bits
of the RemDD field remain the same, but the lower 24 bits are progressively updated by
the firmware as frames are copied from the remote device. The frame transfer queue
discipline described above makes the updating of this field simple: the NextDD field of
the last data descriptor to be copied from the remote device is simply loaded into the
lower 24 bits of the RemDD field.

As already noted, the expansion port descriptor corresponding to the index assigned to
the ELAN 1x100 device itself (i.e., the device implementing the expansion port
descriptor) is not used. Thus expansion port descriptor 0 in device 0 is not used,
expansion port descriptor 1 in device 1 is not used, and so on. (Obviously, it is
meaningless for a device to transfer frames to

itself

across the PCI bus.)

Unlike local port descriptors, the data queued on an expansion port descriptor need not
be restricted to Ethernet frames. Inter-device messages are exchanged by formatting
them into packet buffers and then placing them on the expansion port descriptor
transfer queues corresponding to the target devices. The data descriptor flags should
be set up properly to ensure that the messages are handled specially by the remote
devices, and not treated as normal Ethernet frames. If the message is sufficiently
compact, the packet buffers may be dispensed with and the entire message can be
packed into the data descriptor; in this case, the FirstPB field of the data descriptor
should be set to a NULL.

The expansion port descriptor structures are all cached by the Switch Processor in its
data cache during normal operation; hence the in-memory copies of the expansion port
descriptors may be out-of-date, and cannot be read directly from the PCI bus interface
in a reliable manner unless a data cache flush is performed first via the message
interface.

Address Hash Table

The ELAN 1x100 stores all learned or pre-configured Ethernet addresses using a

table

approach. Each entry in the address hash table is associated with a particular 48-

hash

bit IEEE MAC address. The table contains all of the information required to accept,
process and switch packets to known (i.e., previously learned or set up) addresses. (In
consonance with standard bridging practice, packets destined for unknown, i.e., not

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DATA SHEET
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previously seen or set up destinations must be flooded to all ports, or those determined
using the standard IEEE 802.1d spanning tree.) The hash table also serves to hold per­host statistics information.

Note that when multiple ELAN 1x100 devices are present in a system the hash table
becomes a distributed data structure, with a separate table being maintained by each
device and kept consistent by exchanging information among the different ELAN 1x100
devices according to a predefined protocol.

The hash table consists of three types of data structures: an array, referred to as the

hash pointer array

called

hash buckets

hosts; and a set of 16-byte

, of between 256 and 8192 pointers; a set of 64-byte data structures

, that hold the actual per-MAC information for locally reachable

forwarding tags

that hold abbreviated per-MAC information

for hosts reachable via external devices.
Each pointer in the hash array points to a linked-list of zero or more hash buckets

and/or forwarding tags. Each hash bucket or forwarding tag corresponds to a particular
MAC address; only one hash bucket or forwarding tag may be present for a given MAC
address in any device. In addition, only one hash bucket may be present for a given
MAC address in a complete system; however, multiple forwarding tags may be present
in the various devices that point to this hash bucket.

To access the hash bucket for a specific MAC address, the hash lookup engine in the
DMA Controller first creates a

hash key

and uses it to generate an index into the hash
pointer array. The hash key is obtained by dividing the 48-bit MAC address into three
16-bit blocks:

47 32 31 16 15 0

Block 2 Block 1 Block 0

The three blocks are logically XORed together to create a single 16-bit value, which is
then logically ANDed with a configurable 16-bit bitmask to obtain the index into the hash
pointer array. The purpose of the bitmask is to limit the range of the indices to the
actual size of the hash pointer array: if there are 8,192 entries in the array, the bitmask
should be defined such that the 13 LSBs are set to '1', and the 3 MSBs are set to '0'.

The hash lookup engine uses the computed index to locate the corresponding pointer
within the hash pointer array, and reads the pointer to obtain the first element of the
linked-list of hash buckets and/or forwarding tags that must be searched. It then scans
the linked-list, comparing the complete 48-bit MAC address to be resolved with the
MAC address fields within the hash buckets or forwarding tags, until the required hash
bucket or forwarding tag is found (or no more entries are present in the linked-list). If a
match is found, then the search is declared successful, and the memory address of the
hash bucket or forwarding tag is passed to the Switch Processor; if the complete linked-

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