Datasheet PLUS173BA, PLUS173BN, PLUS173DA, PLUS173DN Datasheet (Philips)

Philips Semiconductors Programmable Logic Devices Product specification

PLUS173B/D

Programmable logic arrays
(22 × 42 × 10)

33

October 22, 1993 853–1298 11164

DESCRIPTION

The PLUS173 PLDs are high speed,
combinatorial Programmable Logic Arrays.
The Philips Semiconductors state-of-the-art
Oxide Isolated Bipolar fabrication process is
employed to produce propagation delays as
short as 12ns.

The 24-pin PLUS173 devices have a
programmable AND array and a
programmable OR array. Unlike PAL 
devices, 100% product term sharing is
supported. Any of the 32 logic product terms
can be connected to any or all of the 10
output OR gates. Most PAL ICs are limited to
7 AND terms per OR function; the PLUS173
devices can support up to 32 input wide OR
functions.

The polarity of each output is user­programmable as either Active-High or
Active-Low, thus allowing AND-OR or
AND-NOR logic implementation. This feature
adds an element of design flexibility,
particularly when implementing complex
decoding functions.

The PLUS173 devices are user­programmable using one of several
commercially available, industry standard
PLD programmers.

FEATURES

•I/O propagation delays (worst case)

– PLUS173B – 15ns max.
– PLUS173D – 12ns max.

•Functional superset of 20L10 and most

other 24-pin combinatorial PAL devices

•Two programmable arrays

– Supports 32 input wide OR functions

•12 inputs

•10 bi-directional I/O

•42 AND gates

– 32 logic product terms
– 10 direction control terms

•Programmable output polarity

– Active-High or Active-Low

•Security fuse

•3-State outputs

•Power dissipation: 750mW (typ.)

•TTL Compatible

APPLICATIONS

•Random logic

•Code converters

•Fault detectors

•Function generators

•Address mapping

•Multiplexing

PIN CONFIGURATIONS

1234
5
6
7
8
9

10
11

12 13 14 15 16 17 18

19

20

21

22

23

24

25

262728

1
2
3
4
5
6
7
8

9
10
11
12 13

14

15

16

17

18

19

20

21

22

23

24

N Package

I0
I1
I2
I3
I4
I5
I6

I7
I8
I9

I10

V

CC

B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
I11

GND

A Package

N = Plastic Dual In-Line (300mil-wide)

I0I1I2I3

V

CC

B9 B8

NC

I4
I5
I6
I7
I8

NC

I9 I10 GND I11 B0 B1 B2

NC

B3

B7
B6
B5
B4

NC

A = Plastic Leaded Chip Carrier

ORDERING INFORMATION

DESCRIPTION tPD (MAX) ORDER CODE DRAWING NUMBER

24-Pin Plastic Dual In-Line 300mil-wide 15ns PLUS173BN 0410D
24-Pin Plastic Dual In-Line 300mil-wide 12ns PLUS173DN 0410D
28-Pin Plastic Leaded Chip Carrier 15ns PLUS173BA 0401F
28-Pin Plastic Leaded Chip Carrier 12ns PLUS173DA 0401F

PAL is a registered trademark of Advanced Micro Devices Corporation.

Philips Semiconductors Programmable Logic Devices Product specification

PLUS173B/D

Programmable logic arrays
(22 × 42 × 10)

October 22, 1993

34

LOGIC DIAGRAM

NOTES:

1. All programmed ‘AND’ gate locations are pulled to logic “1”.

2. All programmed ‘OR’ gate locations are pulled to logic “0”.

3. Programmable connection.

(LOGIC TERMS–P) (CONTROL TERMS)

1

2

3

4

5

6

7

8

9

10

11

13

14

15

16

17

18

19

20

21

22

23

I0

I1

I2

I3

I4

I5

I6

I7

I8

I9

I10

I11

B9

B8

B7

B6

B5

B4

B3

B2

B1

B0

31 24 23 16 15 8 7 0

D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

S9

S8

S7

S6

S5

S4

S3

S2

S1

S0

X9

X8

X7

X6

X5

X4

X3

X2

X1

X0

B9

B8

B7

B6

B5

B4

B3

B2

B1

B0

Philips Semiconductors Programmable Logic Devices Product specification

PLUS173B/D

Programmable logic arrays
(22 × 42 × 10)

October 22, 1993

35

FUNCTIONAL DIAGRAM

P31 P0 D0 D9

I0

I11

B0

B9

B9

B0

S0

S9

X9

X0

ABSOLUTE MAXIMUM RATINGS

1

THERMAL RATINGS

RATING

SYMBOL PARAMETER MIN MAX UNIT

V

CC

Supply voltage +7 V

DC

V

IN

Input voltage +5.5 V

DC

V

OUT

Output voltage +5.5 V

DC

I

IN

Input currents –30 +30 mA

I

OUT

Output currents +100 mA

T

amb

Operating free-air temperature range 0 +75 °C

T

stg

Storage temperature range –65 +150 °C

NOTES:

1. Stresses above those listed may cause malfunction or permanent damage to the device. This
is a stress rating only. Functional operation at these or any other condition above those
indicated in the operational and programming specification of the device is not implied.

TEMPERATURE

Maximum junction 150°C
Maximum ambient 75

°C

Allowable thermal rise 75

°C

ambient to junction

Philips Semiconductors Programmable Logic Devices Product specification

PLUS173B/D

Programmable logic arrays
(22 × 42 × 10)

October 22, 1993

36

DC ELECTRICAL CHARACTERISTICS

0°C ≤ T

amb

≤ +75°C, 4.75 ≤ VCC ≤ 5.25V

LIMITS

SYMBOL PARAMETER TEST CONDITIONS MIN TYP

1

MAX UNIT

Input voltage

2

V

IL

Low VCC = MIN 0.8 V

V

IH

High VCC = MAX 2.0 V

V

IC

Clamp VCC = MIN, IIN = –12mA –0.8 –1.2 V

Output voltage

2

VCC = MIN

V

OL

Low

4

IOL = 15mA 0.5 V

V

OH

High

5

IOH = –2mA 2.4 V

Input current

9

VCC = MAX

I

IL

Low VIN = 0.45V –100 µA

I

IH

High VIN = V

CC

40 µA

Output current

VCC = MAX

I

O(OFF)

Hi-Z state

8

V

OUT

= 2.7V 80 µA

V

OUT

= 0.45V –140

I

OS

Short circuit

3, 5, 6

V

OUT

= 0V –15 –70 mA

I

CC

VCC supply current

7

VCC = MAX 150 200 mA

Capacitance

VCC = 5V

I

IN

Input VIN = 2.0V 8 pF

C

B

I/O VB = 2.0V 15 pF

NOTES:

1. All typical values are at VCC = 5V, T

amb

= +25°C.

2. All voltage values are with respect to network ground terminal.

3. Test one at a time.

4. Measured with inputs I0 – I4 = 0V, inputs I5 – I9 = 4.5V, I11 = 4.5V and I19 = 10V. For outputs B0 – B4 and for outputs B5 – B9 apply the
same conditions except I11 = 0V.

5. Same conditions as Note 4 except input I11 = +10V.

6. Duration of short circuit should not exceed 1 second.

7. I

CC

is measured with inputs I0 – I11 and B0 – B9 = 0V. Part in Virgin State.

8. Leakage values are a combination of input and output leakage.

9. I

IL

and IIH limits are for dedicated inputs only (I0 – I11).

Philips Semiconductors Programmable Logic Devices Product specification

PLUS173B/D

Programmable logic arrays
(22 × 42 × 10)

October 22, 1993

37

AC ELECTRICAL CHARACTERISTICS

0°C ≤ T

amb

≤ +75°C, 4.75 ≤ VCC ≤ 5.25V, R1 = 300Ω, R2 = 390Ω

LIMITS

SYMBOL PARAMETER FROM TO TEST PLUS173B PLUS173D UNIT

CONDITION MIN TYP MAX MIN TYP MAX

t

PD

Propagation Delay

2

Input +/– Output +/– CL = 30pF 11 15 10 12 ns

t

OE

Output Enable

1

Input +/– Output – CL = 30pF 11 15 10 12 ns

t

OD

Output Disable

1

Input +/– Output + CL = 5pF 11 15 10 12 ns

NOTES:

1. For 3-State outputs; output enable times are tested with C

L

= 30pF to the 1.5V level, and S1 is open for high-impedance to High tests and
closed for high-impedance to Low tests. Output disable times are tested with CL = 5pF. High-to-High impedance tests are made to an output
voltage of V

T

= (VOH – 0.5V) with S1 open, and Low-to-High impedance tests are made to the VT = (VOL + 0.5V) level with S1 closed.

2. All propagation delays are measured and specified under worst case conditions.

VOLTAGE WAVEFORM

MEASUREMENTS:

All circuit delays are measured at the +1.5V level
of inputs and outputs, unless otherwise specified.

90%

10%

5ns5ns

5ns 5ns

90%

10%

+3.0V

+3.0V

0V

0V

t

RtF

Input Pulses

TIMING DEFINITIONS

SYMBOL PARAMETER

t

PD

Propagation delay between
input and output.

t

OD

Delay between input change
and when output is off (Hi-Z
or High).

t

OE

Delay between input change
and when output reflects
specified output level.

TEST LOAD CIRCUIT

TIMING DIAGRAM

Test Load Circuit

+5V

C

L

R

1

R

2

S

1

GND

B

Z

B

Z

INPUTS

I

n

I

n

B

M

B

M

OUTPUTS

C

2

C

1

DUT

NOTE:

C

1

and C2 are to bypass VCC to GND.

V

CC

+3V

0V

V

OH

V

OL

I, B

B

t

PD

1.5V 1.5V 1.5V

1.5V 1.5V

t

OD

t

OE

V

T

Philips Semiconductors Programmable Logic Devices Product specification

PLUS173B/D

Programmable logic arrays
(22 × 42 × 10)

October 22, 1993

38

LOGIC PROGRAMMING

The PLUS173 series is fully supported by
industry standard (JEDEC compatible) PLD
CAD tools, including Philips Semiconductors
SNAP design software package. ABEL and
CUPL design software packages also
support the PLUS173 architecture.

All packages allow Boolean and state
equation entry formats. SNAP, ABEL and
CUPL also accept, as input, schematic
capture format.

PLUS173 logic designs can also be
generated using the program table entry
format, which is detailed on the following
page. This program table entry format is
supported by SNAP only.

To implement the desired logic functions, the
state of each logic variable from logic
equations (I, B, O, P, etc.) is assigned a
symbol. The symbols for TRUE,
COMPLEMENT, INACTIVE, PRESET, etc.,
are defined below.

PROGRAMMING AND SOFTWARE SUPPORT

Refer to Section 9

(Development Software)

and Section 10

(Third-Party Programmer/

Software Support)

of this data handbook for

additional information.

AND ARRAY – (I, B)

CODE

O

STATE

INACTIVE

1, 2

CODESTATE CODESTATE CODESTATE

I, B

H

L –

P, D

I, B

I

, B

I, B

I, B

P, D

I, B

I

, B

I, B

P, D

I, B

I

, B

I, B

P, D

I, B

I

, B

I, B

DON’T CARE

OR ARRAY – (B) VIRGIN STATE

A factory shipped virgin device contains all
fusible links intact, such that:

1. All outputs are at “H” polarity.

2. All P

n

terms are disabled.

3. All P

n

terms are active on all outputs.

NOTES:

1. This is the initial unprogrammed state of all link pairs. It is normally associated with all unused
(inactive) AND gates P

n

, Dn.

2. Any gate Pn, Dn will be unconditionally inhibited if both the true and complement of any input
(I, B) are left intact.

ABEL is a trademark of Data I/O Corp.
CUPL is a trademark of Logical Devices, Inc.

CODEACTIVE LEVEL

LOW

(INVERTING)

L

CODEACTIVE LEVEL

HIGH

1

(NON-INVERTING)

H

S

X

B

S

X

B

OUTPUT POLARITY – (B)

CODE

INACTIVE

A

CODE

P

n

STATUS

ACTIVE

1

•

P

S

P

n

STATUS

P

S

Philips Semiconductors Programmable Logic Devices Product specification

PLUS173B/D

Programmable logic arrays
(22 × 42 × 10)

October 22, 1993

39

PROGRAM TABLE

POLARITY

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0

PIN

T

E

R
M

AND OR

ACTIVE

INACTIVE

CONTROL

HIGH

LOW

A

INACTIVE

H

L

B(0)

(POL)

DON’T CARE

I, B

I, B

I, B(I)

CUSTOMER NAME

PHILIPS DEVICE #

PROGRAM TABLE # REV DATE

0HL

—

VARIABLE

NAME

AND OR

B(0)

11 10 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0

B(I)

13 11 10 9 8 7 6 5 4 3 2 1 23 22 21 20 19 18 17 16 15 14 23 22 21 20 19 18 17 16 15 14

NOTES

1.

2.

3.

The PLA is shipped with all links intact. Thus a background

(Shown BLANK for clarity.)

Unused I and B bits in the AND array must be programmed

Unused product terms can be left blank.

Don’t Care (—).

of entries corresponding to states of virgin links exists in the

table.

0

I

Philips Semiconductors Programmable Logic Devices Product specification

PLUS173B/D

Programmable logic arrays
(22 × 42 × 10)

October 22, 1993

40

SNAP RESOURCE SUMMARY DESIGNATIONS

CANDAND

P

31

P

0

D

0

D

9

I

0

I

11

B

0

B

9

B

9

B

0

S

0

S

9

X

9

X

0

OR

DIN173
NIN173

EXOR173

TOUT173

DIN173
NIN173