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PLS159AA
Datasheet (Philips)
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Datasheet PLS159AA, PLS159AN Datasheet (Philips)

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Page 1
Philips Semiconductors Programmable Logic Devices Product specification
PLS159A
Programmable logic sequencer (16 × 45 × 12)
25
October 22, 1993 853–1159 11164

DESCRIPTION

C
. It features 8 registered I/O outputs (F) in conjunction with 4 bidirectional I/O lines (B). These yield variable I/O gate and register configurations via control gates (D, L) ranging from 16 inputs to 12 outputs.
The AND/OR arrays consist of 32 logic AND gates, 13 control AND gates, and 21 OR gates with fusible link connections for programming I/O polarity and direction. All AND gates are linked to 4 inputs (I), bidirectional I/O lines (B), internal flip-flop outputs (Q), and Complement Array output (C
). The Complement Array consists of a NOR gate optionally linked to all AND gates for generating and propagating complementary AND terms.
On-chip T/C buffers couple either True (I, B, Q) or Complement (I
, B, Q, C) input polarities to all AND gates, whose outputs can be optionally linked to all OR gates. Any of the 32 AND gates can drive bidirectional I/O lines (B), whose output polarity is individually programmable through a set of Ex-OR gates for implementing AND-OR or AND-NOR logic functions. Similarly, any of the 32 AND gates can drive the J-K inputs of all flip-flops. There are 4 AND gates for the Asynchronous Preset/Reset functions.
All flip-flops are positive edge-triggered and can be used as input, output or I/O (for interfacing with a bidirectional data bus) in conjunction with load control gates (L), steering inputs (I), (B), (Q) and programmable output select lines (E).
The PLS159A is field-programmable, enabling the user to quickly generate custom patterns using standard programming equipment.

FEATURES

•High-speed version of PLS159
•f
MAX
= 18MHz
– 25MHz clock rate
•Field-Programmable (Ni-Cr link)
•4 dedicated inputs
•13 control gates
•32 AND gates
•21 OR gates
•45 product terms:
– 32 logic terms – 13 control terms
•4 bidirectional I/O lines
•8 bidirectional registers
•J-K, T, or D-type flip-flops
•Power-on reset feature on all flip-flops
(F
n
= 1)
•Asynchronous Preset/Reset
•Complement Array
•Active-High or -Low outputs
•Programmable OE control
•Positive edge-triggered clock
•Input loading: –100µA (max.)
•Power dissipation: 750mW (typ.)
•TTL compatible
•3-State outputs

APPLICATIONS

•Random sequential logic
•Synchronous up/down counters
•Shift registers
•Bidirectional data buffers
•Timing function generators
•System controllers/synchronizers
•Priority encoder/registers

PIN CONFIGURATIONS

1 2 3 4 5 6 7 8 9
10 11
12
13
14
15
16
17
18
19
20
N Package
CLK
I0 I1 I2
I3 B0 B1 B2 B3 F0
GND
F1
F2
F3
F4
F5
F6
F7
V
CC
OE
123 4 5 6 7 8
9 10 11 12 13
14
15
16
17
18
1920
A Package
F0 F1
F2
F3
F4
F5
F6
F7
V
CC
OE
CLK
I0I1
I2
I3 B0 B1 B2
B3
GND
N = Plastic Dual In-Line Package (300mil-wide)
A = Plastic Leaded Chip Carrier

ORDERING INFORMATION

DESCRIPTION ORDER CODE DRAWING NUMBER
20-Pin Plastic Dual In-Line Package (300mil-wide) PLS159AN 0408D 20-Pin Plastic Leaded Chip Carrier PLS159AA 0400E
Page 2
Philips Semiconductors Programmable Logic Devices Product specification
PLS159A
Programmable logic sequencer (16 × 45 × 12)
October 22, 1993
26

LOGIC DIAGRAM

(LOGIC TERMS-T) (CONTROL TERMS)
NOTES:
1. All OR gate inputs with a blown link float to logic “0”.
2. All other gates and control inputs with a blown link float to logic “1”.
3. ⊕ denotes WIRE-OR.
4. Programmable connection.
2 3 4 5
19
6
7
8
9
I0 I1 I2 I3
B3
B2
B1
B0
F7
31 24 23 16 15 8 7 0
P
BRBPARALBLA
D3 D2 D1 D0
X3
X2
X1
X0
B3
B2
B1
B0
F7
F6
F5
F4
F3
F2
C
C
F1
F0
S3
S2
S1
S0
J Q K
EAE
B
CK’
18
F6
J Q K
CK’
17
F5
J Q K
CK’
16
F4
J Q K
CK’
15
F3
J Q K
CK’
14
F2
J Q K
CK’
13
F1
J Q K
CK’
12
F0
J Q K
CK’
1
CLK
CK
F
C
11
OE
M7
M6
M5
M4
M3
M2
M1
M0
P R
P R
Page 3
Philips Semiconductors Programmable Logic Devices Product specification
PLS159A
Programmable logic sequencer (16 × 45 × 12)
October 22, 1993
27

FUNCTIONAL DIAGRAM

C
a
b
S
Q Q
C
a
b
a
b
X
CK
P R
JKQ
M
(LOGIC TERMS) (CONTROL TERMS)
P
B
D
E
A
B
F
T
31
T0F
C
(4)
OE
E
B
CK
P R
JKQ
M
(4)
F
RBPAR
A
LBL
A
CLK
CK
0 1 0
0 0 1
STATE REGISTER
S
R
S
n + 1
PRESENT STATE
A
⋅ B ⋅ C ⋅ . . .
NEXT STATE
Q2 Q1 Q0
SET Q
0
: J0 = (Q
3
⋅ Q
2
⋅ Q1 ⋅ Q0) ⋅ A ⋅ B ⋅ C . . .
K
0
= 0
RESET Q
1
: J1 = 0
K
1
= (Q
3
⋅ Q
2
⋅ Q1 ⋅ Q0) ⋅ A ⋅ B ⋅ C . . .
HOLD Q
2
: J2 = 0
K
2
= 0
1
0
Q3
TOGGLE Q3: J3 = (Q
3
⋅ Q2 ⋅ Q1 ⋅ Q0) ⋅ A ⋅ B ⋅ C . . .
K3 = (Q
3
⋅ Q
2
⋅ Q1 ⋅ Q0) ⋅ A ⋅ B ⋅ C . . .
NOTE:
Similar logic functions are applicable for D and T mode flip-flops.

FLIP-FLOP TRUTH TABLE

OE L CK P R J K Q F
H Hi-Z
L X X L X X X L H L X X H L X X H L L X X L H X X L H L L ↑ L L L L Q Q L L ↑ L L L H L H L L ↑ L L H L H L
L L ↑ L L H H Q Q H H ↑ L L L H L H* H H ↑ L L H L H L*
+10V X ↑ X X L H L H* *
X ↑ X X H L H L* *
NOTES:
1. Positive Logic: J-K = T
0
+ T1 + T2 ……………… T
31
Tn = C⋅ (I0 ⋅ I1 ⋅ I2 …) ⋅ (Q0 ⋅ Q1 …) ⋅ (B0 ⋅ B1 ⋅ …)
2. ↑ denotes transition from Low to High level.
3. X = Don’t care
4. * = Forced at F
n
pin for loading the J-K flip-flop in the Input mode. The load control term, L
n
must be enabled (HIGH) and the p-terms that are connected to the associated flip-flop must be forced LOW (disabled) during Preload.
5. At P = R = H, Q = H. The final state of Q depends on which is released first.
6. * * = Forced at F
n
pin to load J-K flip-flop independent of program code (Diagnostic mode), 3-State B outputs.

LOGIC FUNCTION

Page 4
Philips Semiconductors Programmable Logic Devices Product specification
PLS159A
Programmable logic sequencer (16 × 45 × 12)
October 22, 1993
28

VIRGIN STATE

The factory shipped virgin device contains all fusible links intact, such that:
1. OE
is always enabled.
2. Preset and Reset are always disabled.
3. All transition terms are disabled.
4. All flip-flops are in D-mode unless otherwise programmed to J-K only or J-K or D (controlled).
5. All B pins are inputs and all F pins are outputs unless otherwise programmed.

CAUTION: PLS159A PROGRAMMING ALGORITHM

The programming voltage required to program the PLS159A is higher (17.5V) than that required to program the PLS159 (14.5V). Consequently, the PLS159 programming algorithm will not program the PLS159A. Please exercise caution when accessing programmer device codes to insure that the correct algorithm is used.

THERMAL RATINGS

TEMPERATURE
Maximum junction 150°C Maximum ambient 75°C Allowable thermal rise
ambient to junction
75°C

ABSOLUTE MAXIMUM RATINGS

1
RATINGS
SYMBOL PARAMETER MIN MAX UNIT
V
CC
Supply voltage +7 V
DC
V
IN
Input voltage +5.5 V
DC
V
OUT
Output voltage +5.5 V
DC
I
IN
Input currents –30 +30 mA
I
OUT
Output currents +100 mA
T
amb
Operating temperature range 0 +75 °C
T
stg
Storage temperature range –65 +150 °C
NOTES:
1. Stresses above those listed may cause malfunction or permanent damage to the device. This is a stress rating only. Functional operation at these or any other condition above those indicated in the operational and programming specification of the device is not implied.
Page 5
Philips Semiconductors Programmable Logic Devices Product specification
PLS159A
Programmable logic sequencer (16 × 45 × 12)
October 22, 1993
29

DC ELECTRICAL CHARACTERISTICS

0°C ≤ T
amb
≤ +75°C, 4.75V ≤ VCC ≤ 5.25V
LIMITS
SYMBOL PARAMETER TEST CONDITION MIN TYP
1
MAX UNIT
Input voltage
2
V
IH
High VCC = MAX 2.0 V
V
IL
Low VCC = MIN 0.8 V
V
IC
Clamp VCC = MIN, IIN = –12mA –0.8 –1.2 V
Output voltage
2
V
OH
High VCC = MIN, IOH = –2mA 2.4 V
V
OL
Low IOL = 10mA 0.35 0.5 V
Input current
I
IH
High
VCC = MAX, V
IN
= 5.5V
<1 80
µA
I
IL
Low VIN = 0.45V –10 –100
µA
Output current
I
O(OFF)
Hi-Z state
4, 7
VCC = MAX, V
OUT
= 5.5V 1 80
µA
V
OUT
= 0.45V –1 –140
µA
I
OS
Short circuit
3, 5
V
OUT
= 0V
–15 –70
mA
I
CC
VCC supply current
6
VCC = MAX 150 190 mA
Capacitance
C
IN
Input VCC = 5.0V, VIN = 2.0V 8 pF
C
OUT
Output V
OUT
= 2.0V 15 pF
NOTES:
1. All typical values are at V
CC
= 5V, T
amb
= +25°C.
2. All voltage values are with respect to network ground terminal.
3. Test one at a time.
4. Measured with V
IH
applied to OE.
5. Duration of short circuit should not exceed 1 second.
6. I
CC
is measured with the OE input grounded, all other inputs at 4.5V and the outputs open.
7. Leakage values are a combination of input and output leakage.
Page 6
Philips Semiconductors Programmable Logic Devices Product specification
PLS159A
Programmable logic sequencer (16 × 45 × 12)
October 22, 1993
30

AC ELECTRICAL CHARACTERISTICS

0°C ≤ T
amb
≤ +75°C, 4.75V ≤ VCC ≤ 5.25V, R1 =470Ω, R2 = 1kΩ
LIMITS
SYMBOL PARAMETER FROM TO TEST CONDITION MIN TYP
1
MAX UNIT
Pulse width
t
CKH
Clock2 High CK + CK – CL = 30pF 20 15 ns
t
CKL
Clock Low CK – CK + CL = 30pF 20 15 ns
t
CKP
Period CK + CK + CL = 30pF 55 45 ns
t
PRH
Preset/Reset pulse (I,B) – (I,B) + CL = 30pF 35 30 ns
Setup time
5
t
IS1
Input (I,B) ± CK + CL = 30pF 35 30 ns
t
IS2
Input (through Fn) F ± CK + CL = 30pF 15 10 ns
t
IS3
Input (through Complement Array)
4
(I,B) ± CK + CL = 30pF 55 45 ns
Hold time
t
IH1
Input (I,B) ± CK + CL = 30pF 0 –5 ns
t
IH2
Input (through Fn) F ± CK + CL = 30pF 15 10 ns
Propagation delay
t
CKO
Clock CK + F ± CL = 30pF 15 20 ns
t
OE1
Output enable
3
OE – F – CL = 30pF 20 30 ns
t
OD1
Output disable
3
OE + F + CL = 5pF 20 30 ns
t
PD
Output (I,B) ± B ± CL = 30pF 25 35 ns
t
OE2
Output enable
3
(I,B) + B ± CL = 30pF 20 30 ns
t
OD2
Output disable
3
(I,B) – B + CL = 5pF 20 30 ns
t
PRO
Preset/Reset (I,B) + F ± CL = 30pF 35 45 ns
t
PPR
Power-on/preset VCC + F – CL = 30pF 0 10 ns
NOTES:
1. All typical values are at V
CC
= 5V, T
amb
= +25°C.
2. To prevent spurious clocking, clock rise time (10% – 90%) ≤ 10ns.
3. For 3-State output; output enable times are tested with C
L
= 30pF to the 1.5V level, and S1 is open for high-impedance to High tests and
closed for high-impedance to Low tests. Output disable times are tested with C
L
= 5pF. High-to-High impedance tests are made to an output
voltage of VT = (VOH – 0.5V) with S1 open, and Low-to-High impedance tests are made to the VT = (VOL + 0.5V) level with S1 closed.
4. When using the Complement Array t
CKP
= 75ns (min).
5. Limits are guaranteed with 12 product terms maximum connected to each sum term line.

VOLTAGE WAVEFORMS

MEASUREMENTS:
All circuit delays are measured at the +1.5V level of inputs and outputs, unless otherwise specified.
90%
10%
5ns5ns
5ns 5ns
90%
10%
+3.0V
+3.0V
0V
0V
t
RtF
Input Pulses

TEST LOAD CIRCUIT

+5V
C
L
R
1
R
2
S
1
GND
B
Z
B
Y
INPUTS
I
0
I
n
B
W
B
X
OUTPUTS
C
2
C
1
DUT
NOTE:
C
1
and C2 are to bypass VCC to GND.
V
CC
OE
CLK
Page 7

1.5V 1.5V
1.5V1.5V1.5V
1.5V
V
T
1.5V1.5V
+3V
0V
+3V
0V
V
OH
V
OL
+3V
0V
I, B
(INPUTS)
CLK
F
(OUTPUTS)
OE
t
IH1
t
IS1
t
IS1
t
CKH
t
CKL
t
CKP
t
CKO
t
OD1
t
OE1
Flip-Flop Outputs
I, B
(INPUTS)
B
(OUTPUTS)
I, B (OUTPUT ENABLE)
t
PD
t
OE2
t
OD2
1.5V
1.5V
+1.5V+1.5V
V
T
+3V
0V
V
OH
V
OL
+3V
0V
Gate Outputs
Power-On Reset
+5V
0V
V
OH
V
OL
+3V
0V
4.5V
+3V
0V
t
PPR
t
CKO
1.5V 1.5V
1.5V
1.5V
1.5V 1.5V 1.5V
F
(OUTPUTS)
I, B
(INPUTS)
CLK
V
CC
t
IS1
t
IS1
t
CKH
t
CKL
t
CKP
Philips Semiconductors Programmable Logic Devices Product specification
PLS159A
Programmable logic sequencer (16 × 45 × 12)
October 22, 1993
31

TIMING DIAGRAMS TIMING DEFINITIONS

SYMBOL PARAMETER
t
CKH
Width of input clock pulse.
t
CKL
Interval between clock pulses.
t
CKP
Clock period.
t
PRH
Width of preset input pulse.
t
IS1
Required delay between beginning of valid input and positive transition of clock.
t
IS2
Required delay between beginning of valid input forced at flip-flop output pins, and positive transition of clock.
t
IH1
Required delay between positive transition of clock and end of valid input data.
t
IH2
Required delay between positive transition of clock and end of valid input data forced at flip-flop output pins.
t
CKO
Delay between positive transition of clock and when outputs become valid (with OE
Low).
t
OE1
Delay between beginning of Output Enable Low and when outputs become valid.
t
OD1
Delay between beginning of Output Enable High and when outputs are in the OFF-State.
t
PPR
Delay between VCC (after power-on) and when flip-flop outputs become preset at “1” (internal Q outputs at “0”).
t
PD
Propagation delay between combinational inputs and outputs.
t
OE2
Delay between predefined Output Enable High, and when combinational outputs become valid.
t
OD2
Delay between predefined Output Enable Low and when combinational outputs are in the OFF-State.
t
PRO
Delay between positive transition of predefined Preset/Reset input, and when flip-flop outputs become valid.
t
IH1
Page 8
Philips Semiconductors Programmable Logic Devices Product specification
PLS159A
Programmable logic sequencer (16 × 45 × 12)
October 22, 1993
32
TIMING DIAGRAMS (Continued)
+3V
0V
+3V
0V
+3V
0V
V
OH
V
OL
t
IS1
* t
IS1
t
CKO
t
PRH
t
PRO
1.5V
1.5V
1.5V
1.5V
1.5V
1.5V
(PRESET)
(RESET)
(PRESET)
(RESET)
I,B
(INPUTS)
CLK
PRESET/RESET
(I, B INPUTS)
Q
F
(OUTPUTS)
* Preset and Reset functions override Clock. However, F outputs may glitch with the first positive Clock Edge if t
IS1
cannot be guaranteed by the user.
Asynchronous Preset/Reset
Flip-Flop Input Mode
I, B
(LOAD SELECT)
OE
L
F
(INPUTS)
CLK
Q
(D
IN
)
1.5V 1.5V
1.5V 1.5V
1.5V
V
T
(FORCED DIN)
+3V
0V
+3V
0V
+3V
0V
+3V
0V
V
OH
V
OL
t
OE1
t
OD1
t
IS2
t
IH2
t
CKH
t
IH1
Page 9

Philips Semiconductors Programmable Logic Devices Product specification
PLS159A
Programmable logic sequencer (16 × 45 × 12)
October 22, 1993
33

LOGIC PROGRAMMING

The PLS159A is fully supported by industry standard (JEDEC compatible) PLD CAD tools, including Philips Semiconductors’ SNAP, Data I/O Corporation’s ABEL and Logical Devices Inc.’s CUPL design software packages.
All packages allow Boolean and state equation entry formats. SNAP, ABEL and CUPL also accept, as input, schematic capture format.
PLS159A logic designs can also be generated using the program table entry format detailed on the following pages. This program table entry format is supported by the Philips Semiconductors SNAP PLD design software package.
To implement the desired logic functions, the state of each logic variable from logic equations (I, B, O, P, etc.) is assigned a symbol. The symbols for TRUE,
COMPLEMENT, INACTIVE, PRESET, etc., are defined below.

PROGRAMMING AND SOFTWARE SUPPORT

Refer to Section 9
(Development Software)
and Section 10
(Third-party Programmer/
Software Support)
of this data handbook for
additional information.

“AND” ARRAY – (I), (B), (Qp)

STATE
DON’T CARE
CODE
STATE
I, B, Q
CODE
L
STATE
I, B, Q
CODE
STATE
INACTIVE
1, 2
CODE
O –H
(T, FC, L, P, R, D)
n
I, B, Q
I, B, Q
I, B, Q
(T, FC, L, P, R, D)
n
I, B, Q
I, B, Q
I, B, Q
(T, FC, L, P, R, D)
n
I, B, Q
I, B, Q
I, B, Q
(T, FC, L, P, R, D)
n
I, B, Q
I, B, Q
I, B, Q

“COMPLEMENT” ARRAY – (C)

ACTION
TRANSPARENT
CODE
ACTION
PROPAGATE
CODE
•
ACTION
GENERATE
5
CODE
ACTION
INACTIVE
1, 3, 5
CODE
O –A
C
C
(Tn, FC)
C
C
(T
n
, FC)
C
C
(T
n
, FC)
C
C
(T
n
, FC)

“OR” ARRAY – (F-F CONTROL MODE) “OR” ARRAY – (Qn = D-Type)

QJ
K
•
QJ
K
F
C
ACTION J–K OR D
(CONTROLLED)
1
CODE
A
F
C
MM
ACTION
J–K ONLY
CODE
QJ
K
•
QJ
K
T
n
Tn STATUS
ACTIVE (Set)
1
CODE
A
T
n
M = ENABLED
INACTIVE (Reset)
CODE
M = ENABLED
T
n
STATUS
ENABLED DISABLED
CAUTION:
THE PLS159A Programming Algorithm is different from the PLS159.
Notes on following page.
Page 10

Philips Semiconductors Programmable Logic Devices Product specification
PLS159A
Programmable logic sequencer (16 × 45 × 12)
October 22, 1993
34

“OR” ARRAY – (Qn = J-K Type)

QJ
K
T
n
M = DISABLED
ACTION
HOLD
CODE
QJ
K
T
n
M = DISABLED
ACTION
RESET
CODE
L
QJ
K
T
n
M = DISABLED
ACTION
SET
CODE
QJ
K
T
n
ACTION
TOGGLE
CODE
O –H
M = DISABLED

“OR” ARRAY – (S or B) “EX-OR” ARRAY – (B)

Tn STATUS
INACTIVE
CODE
•
Tn STATUS
ACTIVE
1
CODE
A
T
n
S, B
T
n
POLARITY
LOW
1
CODE
L
POLARITY
HIGH
CODE
H
S
B
S
B
S, B

“OE” ARRAY – (E)

ACTION
DISABLE
CODE
ACTION
ENABLE
4
CODE
ACTION
CONTROL
CODE
ACTION IDLE
1, 4
CODE
O –A
E
n
OE
E
n
OE
E
n
OE
E
n
OE
•
NOTES:
1. This is the initial unprogrammed state of all link pairs. It is normally associated with all unused (inactive) AND gates.
2. Any gate (T, F
C
, L, P, R, D)n will be unconditionally inhibited if both of the I, B, or Q links are left intact.
3. To prevent oscillations, this state is not allowed for C link pairs coupled to active gates T
n
, FC.
4. E
n
= O and En = • are logically equivalent states, since both cause Fn outputs to be unconditionally enabled.
5. These states are not allowed for control gates (L, P, R, D)n due to their lack of “OR” array links.
Page 11
Philips Semiconductors Programmable Logic Devices Product specification
PLS159A
Programmable logic sequencer (16 × 45 × 12)
October 22, 1993
35

PROGRAM TABLE

J/K J/K or D A
(controlled)
HIGH H LOW L
012301234567
(OR)
Q(N) B(O)
POLARITY
E
A
E
B
F/F MODE
0123456701230123
0 1 2 3 4 5 6 7 8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
T
E R M
F
C
C
AND
I B(I) Q(P)
P
B
R
B
D3 D2 D1 D0
PIN 5 4 3 2 9 8 7 6 19 18 17 16 15 14 13 12
CUSTOMER NAME
PURCHASE ORDER #
PHILIPS DEVICE #
TOTAL NUMBER OF PARTS
PROGRAM TABLE # REV DATE
THIS PORTION TO BE COMPLETED BY SIGNETICS
CF (XXXX)
CUSTOMER SYMBOLIZED PART #
DATE RECEIVED
COMMENTS
AND OR CONTROL
NOTES
1. The device is shipped with all links intact. Thus a back­ground of entries corresponding to states of virgin links exists in the table, shown BLANK for clarity.
2. Program unused C, I, B, and Q bits in the AND array as (–). Program unused Q, B, P, and R bits in the OR array as (–) or (A), as applicable.
3. Unused Terms can be left blank.
4. Q (P) and Q (N) are respectively the present and next states of flip-flops Q.
INACTIVE O I, B, Q H I
, B, Q L
DON’T CARE –
INACTIVE O GENERATE A PROPAGATE
TRANSPARENT
–
I, B(I), Q(P)
C
ACTIVE A INACTIVE
P, R, B(O) (Q = D)
TOGGLE O SET H RESET L HOLD –
(Q = J/K)
IDLE O CONTROL A ENABLE DISABLE –
E
A, B
(POL)
F/F MODE
L
A
R
A
P
A
L
B
Page 12
Philips Semiconductors Programmable Logic Devices Product specification
PLS159A
Programmable logic sequencer (16 × 45 × 12)
October 22, 1993
36

SNAP RESOURCE SUMMARY DESIGNATIONS

CK159
C
a
b
S
Q Q
C
a
b
a
b
X
CK
P R
JKQ
M
(LOGIC TERMS) (CONTROL TERMS)
P
B
D
E
A
B
F
T
31
T0F
C
(4)
OE
E
B
CK
P R
JKQ
M
(4)
F
RBPAR
A
LBL
A
CLK
CK
TNOUT159
JKFF159
OEA159
OEB159
CAND AND
ANDFC
NOR
DIN159 NIN159
DIN159 NIN159
LNIN159 LDIN159
EXOR159
OR
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