Page 1
)
0
(
RED
YELLOW
HIGH EFFICIENCY RED
GREEN
HIGH EFFICIENCY GREEN
PLCD5580
PLCD5581
PLCD5582
PLCD5583
PLCD5584
Low Power 0.145” 8-Character, 5x5 Dot Matrix
Parallel Input Alphanumeric Intelligent Display
Package Dimensions in inches (mm)
.145
3.68)
1.680 (42.67) max.
0.210
(5.34)
Pin 1 Indicator
Part Number
PLCD558X
SIEMENS
WW
EIA Date
Code
Z
0.105
(2.67)
0.771
(19.58)
0.386
(9.8)
0.012 (0.30) typ.
Intensity Code
Color Bin
(For Yellow Only)
1
0.209 (5.31)
0.086
(2.19)
0.600
(15.24
FEATURES
•
Eight 0.145” (3.68 mm) High 5 x 5 Dot Matrix Characters in Red, Yellow, High Efficiency Red, Green,
or High Efficiency Green
Built-in 2 Page, 256 Character ROM. Both Pages
•
Mask Programmable for Custom Fonts
•
Built-in Decoders, Multiplexers and Drivers
Wide Viewing Angle, X Axis ± 50 ° , Y Axis ± 65 °
•
•
Programmable Features:
– Individual Flashing Character
– Full Display Blinking
– Multi-Level Dimming and Blanking
– Clear Function
– Lamp Test
•
Internal or External Clock
•
End Stackable Dual-In-Line Plastic Package
Low Power: 20% Less Power Consumption Than
•
5 X 7 Format
0.189
(4.79)
DESCRIPTION
The PLCD5580 (Red), PLCD5581 (Yellow), PLCD5582 (High Efficiency Red), PLCD5583 (Green), and PLCD5584 (High Efficiency
Green) are eight digit, 5x5 dot matrix, alphanumeric Programmable Displays. The 0.145 inch high digits are packaged in a rugged, high quality, optically transparent, standard 0.6 inch 28 pin
plastic DIP.
The on-board CMOS has a built-in two page, 256 character ROM.
Both pages are mask programmable for 256 custom characters.
The first page of ROM of the standard product contains 128 characters including ASCII, selected European and Scientific symbols. The second page contains Katakana Japanese characters,
more European characters, Avionics, and other graphic symbols.
The PLCD558X is designed for standard microprocessor interface techniques and is fully TTL compatible. The Clock I/O and
Clock Select pins allow the user to synchronize multiple display
modules.
0.018 typ.
(.46)
0.100
(2.54) typ.
0.160±.020
(4.06±.50)
2–131
Page 2
)
.
Maximum Rating
DC Supply Voltage ........................................–0.5 to +7.0 Vdc
Input Voltage Levels Relative
to Ground...............................................–0.5 to V
Operating Temperature .................................–40 °
Storage Temperature....................................–40 °
+0.5 Vdc
CC
C to +85 ° C
C to +100 ° C
Maximum Solder Temperature 0.063"
below Seating Plane, t<5 sec...................................... 260 °
Relative Humidity at 85 °
Note: Maximum voltage is with no LEDs illuminated.
C.................................................85%
C
Enlarged Character Font
0.033
(0.84)
typ.
0.011
(0.28)
typ.
0.100
(2.54)
C0 C1 C2 C3 C4
0.022
(0.56) typ.
R0
R1
R2
R3
R4
0.145
(3.68)
Dimensions in inches (mm)
Tolerance: .XXX= ±
.010 (.25)
Switching Specifications
(over operating temperature range and V
=4.5 V).
CC
Symbol Description Min. Units
Tbw Time Between Writes 30 ns
(2)
Tacc
Display Access Time 130 ns
Tas Address Setup Time 10 ns
Tces Chip Enable Hold Time 0 ns
Tah Address Hold Time 20 ns
Tceh Chip Enable Hold Time 0 ns
Tw Write Active Time 100 ns
Tds Data Valid Prior to
50 ns
Rising Edge of Write
Tdh Data Hold Time 20 ns
(1)
Trc
Tclr
(3)
Reset Active Time 300 ns
Clear Cycle Time 3
µ s
1. Wait 300 ns min. after the reset function is turned off.
2. Tacc=Tas + Tw + Tah
3. The Clear Cycle Time may be shortened by writing a
second Control Word with the Clear Bit disabled, 160 ns
after the first control word that enabled the Clear Bit.
Write Cycle Timing Diagram
Tas
FL, A3-A0
CE
Tces
WR
D7-D0
Tacc
Tw
Tds
Tah
Tdh
Tceh
Tbw
data wait data
write control
word-clear bit
enabled
wait 130 ns write control
word-clear bit
enabled
The Flash RAM and Character RAM may not be accessed
until the Clear Cycle is complete.
see Notes
see Notes
see Notes
Notes
see Notes
1. All input voltages are (VIL=0.8 V, VIH=2.0 V
2. These wave forms are not edge triggered
3. Tbw=Tas + Tah
2–132
PLCD5580/1/2/3/4
Page 3
Optical Characteristics at 25 ° C
V
=5.0 V at Full Brightness
CC
Red PLCD5580
Description Symbol Min. Typ. Units
Peak Luminous Intensity
Peak Wavelength
Dominant Wavelength
(1)
I
V
peak
λ
(peak) 660 nm
λ
(d) 639 nm
70 90
Yellow PLCD5581
Description Symbol Min. Typ. Units
Peak Luminous Intensity
Peak Wavelength
Dominant Wavelength
(1)
I
V
peak
λ
(peak) 583 nm
λ
(d) 585 nm
130 210
High Efficiency Red PLCD5582
Description Symbol Min. Typ. Units
Peak Luminous Intensity
Peak Wavelength
Dominant Wavelength
(1)
I
V
peak
λ
(peak) 630 nm
λ
(d) 626 nm
150 330
Green PLCD5583
Description Symbol Min. Typ. Units
µ cd/dot
µ cd/dot
µ cd/dot
Peak Luminous Intensity
Peak Wavelength
Dominant Wavelength
(1)
I
V
peak
λ
(peak) 565 nm
λ
(d) 570 nm
150 260
High Efficiency Green PLCD5584
Description Symbol Min. Typ. Units
Peak Luminous Intensity
Peak Wavelength
Dominant Wavelength
Note
1. Peak luminous intensity is meaaured at T
(1)
I
V
peak
λ
(peak) 568 nm
λ
(d) 574 nm
=T
=25 ° C. No time is allowed for the device to warm up prior to measurement.
A
J
200 510
µ cd/dot
µ cd/dot
2–133
PLCD5580/1/2/3/4
Page 4
Electrical Characteristics at 25 ° C
Parameters
Limits
Min. Typ. Max. Units
Conditions
V
CC
I
Blank 0.5 1.0 mA V
CC
I
8 digits
CC
I
Current
IP
(1)
, 16 dots/character 240 290 mA V
4.5 5.0 5.5 V
11 18
µ AV
(with pull-up)
I
Input leakage current
I
± 1
µ AV
(without pull-up)
V
Input Voltage High 2.0 V
IH
CC
VV
+0.3
V
Input Voltage Low GND
IL
0.8 V V
–0.3
V
Output Voltage Low
OL
0.4 V V
(Clock Pin)
V
Output Voltage High
OH
2.4 V VCC=4.5 V to 5.5 V,
(Clock Pin)
I
Output Current High
OH
–0.9 mA VCC=4.5 V, VOH=2.4 V
(Clock I/O)
I
Output Current Low
OL
1.6 2 mA VCC=4.5 V, VOL=0.4 V
(Clock I/O)
=5 V, V
CC
=5 V, “#” displayed in all
CC
IN
=5 V
eight digits
=5 V, V
CC
(WR
, CE, FL, RST, ClkSel)
=5 V, V
CC
=0 V to V
IN
=0 V to V
IN
CC
CC
(Clk I/O, A0–A3, D0–D7)
=4.5 V to 5.5 V
CC
=4.5 V to 5.5 V
CC
=4.5 V to 5.5 V,
CC
I
=1.6 mA
OL
I
=40 µA
OH
,
,
θ
Thermal Resistance,
JC
25 °C/W
Junction to Case
F
External Clock,
ext
Input Frequency
F
Internal Clock,
osc
Output Frequency
(2)
(2)
28 81.14 KHz VCC=5.0 V, CLKSEL=0
28 81.14 KHz VCC=5.0 V, CLKSEL=1
Clock I/O Buss Loading 240 pF
Clock Out Rise Time 500 ns V
Clock Out Fall Time 500 ns V
FM, Digit Multiplex Frequency 125 256 362.5 Hz
Blinking Rate 0.98 2 2.83 Hz
Notes:
1. Average I
2. Internal/external frequency duty factor is 50%.
measured at full brightness. Peak I
CC
CC
5
=
⁄
8
x I
I
(# displayed).
AVG
CC
=4.5 V, VOH=2.4 V
CC
=4.5 V, VOL=0.4 V
CC
2–134
PLCD5580/1/2/3/4
Page 5
T op View
28 15
TOP VIEW
Pin Function Definition
1 RST
2FL
3 A0 Address input LSB
4 A1 Address input
5 A2 Address input MSB
114
Pin Assignment
6 A3 Mode selector
7 Substr. bias Optional connection to V
8 Substr. bias See Definition 7
9 Substr. bias See Definition 7
Pin Function Pin Function
1 RST 28 D7
2FL
27 D6
3A0 26D5
4A1 25D4
5A2 24D3
6A3 23D2
10 No connect
11 CLKSEL
12 CLK I/O Outputs master clock or inputs external
13 WR
14 V
CC
15 GND Analog Ground for LED drivers
16 GND Digital Ground for internal drivers
17 CE
18 No connect
19 D0 Data input LSB
20 D1 Data input
7 Substr. bias 22 No Pin
8 Substr. bias 21 No Pin
9 Substr. bias 20 D1
10 No Connect 19 D0
21 No pin
22 No pin
23 D2 Data input
24 D3 Data input
25 D4 Data input
26 D5 Data input
27 D6 Data input
11 CLKSEL
18 No Connect
28 D7 Data input MSB, selects ROM, page 1
12 CLK I/O 17 CE
Used to initialize a display and synchronize blinking for multiple displays
Low input accesses the Flash RAM
. Can’t be
CC
used to supply power to display.
Selects internal/external clock source
clock
A low will write data into the display if CE
is low
Positive power supply input
Enables access to the display
or 2
13 WR 16 GND (logic)
14 V
CC
15 GND (supply)
Cascading the PLCD558X Displays
WR
FL
RST
V
WR FL RST CLK I/O CLKSEL
Display
D0-D7 A0-A4 CE
Data I/O
Address
A6
A7
A8
A9
Address
Decoder
0
Address Decode Chip 1 to 14
15
CC
WR FL RST CLK I/O CLKSEL
Up to14 More Displays
in between
2–135
D0-D7 A0-A4 CE
Display
PLCD5580/1/2/3/4
Page 6
Character Set–ROM Page 1
D0
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
D1
ASCII
Code
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
D2
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
D3
D6 D5 D4 Hex 0 1 2 3 4 5 6 7 8 9 A B C D E F
0 0 0 0
0 0 1 1
0 1 0 2
0 1 1 3
1 0 0 4
1 0 1 5
1 1 0 6
1 1 1 7
Notes
1. D7=0
2. High=1 level. Low=0 level.
2–136
PLCD5580/1/2/3/4
Page 7
Character Set–ROM Page 2
D0
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
D1
ASCII
Code
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
D2
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
D3
D6 D5 D4 Hex 0 1 2 3 4 5 6 7 8 9 A B C D E F
0 0 0 0
0 0 1 1
0 1 0 2
0 1 1 3
1 0 0 4
1 0 1 5
1 1 0 6
1 1 1 7
Notes
1. D7=1
2. High=1 level. Low=0 level.
2–137
PLCD5580/1/2/3/4
Page 8
Block Diagram
Rows 0 to 9
0 1 2 3 4 5 6 7
Row Control Logic
& Row Drivers
RST
CLK I/O
CLKSEL
D7
D6
D5
D4
D3
D2
D1
D0
+ 32
OSC
Counter
Display
Memory
8 x 8 Bits
Address
Lines
Address Decoder
A0 A1 A2 A3 WR CE FL
Control Word
Decode Logic
Control Word
Flash RAM
(8 x 1 Bit)
+ 7
Counter
7 Bit ASCII
Code
Mux
Rate
+ 128
Counter
Latches
Blink
Rate
Row Decoder
ROM 1 ROM 2
128x7 Bit
ASCII
Character
Decode
(4.48K Bits)
Column De coder
Functional Description
The PLCD558X block diagram is comprised of the following
major blocks and registers.
Display Memory consists of a 8x8 bit RAM block. Each of
the eight 8-bit words holds the 7-bit ASCII data (bit D0-D6).
The 8th bit, D7 selects 1 of the 2 pages of character ROM.
D7=0 selects Page 1 of the ROM and D7=1 selects Page 2 of
the ROM. A3=1.
RST
can be used to initialize display operation upon power
up or during normal operation. When activated, RST
will clear
the Flash RAM and Control Word Register (00H) and reset the
internal counter. All eight display memory locations will be set
to 20H to show blanks in all digits.
FL
pin enables access to the Flash RAM. The Flash RAM will
set (D0=1)or reset (D0=0) flashing of the character
addressed by A0–A2.
The 1x8 bit Control W ord RAM is loaded with attribute data
if A3=0.
The Control W ord Logic decodes attribute data for proper
implementation.
Character ROM is designed for two pages of 128 characters
each. Both pages of the ROM are Mask Programmable for
custom fonts. On the standard product page one contains
standard ASCII, selected European characters and some scientific symbols. Page two contains Katakana characters,
more European characters, avionics, and other graphic symbols.
DISPLAY
Columns 0 to 19
Timing and
Control Logic
128x7 Bit
ASCII
Character
Decode
(4.48K Bits)
Column
Data
Master
Slave
Latches
Digit
0 to 8
Column
Drivers for
Digit 0 to 8
The Clock Source could either be the internal oscillator
(CLKSEL
=1) of the device or an external clock (CLKSEL=0)
could be an input from another PLCD211X display for the
synchronization of blinking for multiple displays.
The Display Multiplexer controls the Row Drivers so no
additional logic is required for a display system.
The Display has eight digits. Each digit has 25 LEDs clustered into a 5x5 dot matrix.
Theory of Operation
The PLCD558X Programmable display is designed to work
with all major microprocessors. Data entry is via an eight bit
parallel bus. Three bits of address route the data to the
proper digit location in the RAM. Standard control signals like
WR
and CE allow the data to be written into the display.
D0–D7 data bits are used for both ASCII and control word
data input. A3 acts as the mode selector. If A3=0, D0–D7
load the RAM with control word data. If A3=1, D0–D7 will
load the RAM with ASCII and page select data. In the later
mode, D7=0 selects Page 1 of Character ROM and D7=1
selects Page 2 of Character ROM.
For normal operation FL
pin should be held high. When FL is
held low, Flash RAM is accessed to set character blinking.
The seven bit ASCII code is decoded by the Character ROM
to generate Column data. Twenty columns worth of data is
sent out each display cycle and it takes fourteen display
cycles to write into eight digits.
The rows are being multiplexed in two sets of five rows each.
The internal timing and control logic synchronizes the turning
on of rows and presentation of column data to assure proper
display operation.
2–138
PLCD5580/1/2/3/4
Page 9
Data Input Commands
Signals
Operation
CE WR FL A3 A2 A1 A0
1
x
x
x
x
x
x
X
1
x
x
x
x
x
No operation
No operation
0010000Write Control Register
Digit 0 (left)
0
0
0
1
1
0
0
Digit 1
1
0
0
1
1
0
0
Digit 2
0
1
0
1
1
0
0
Digit 3
1
1
0
1
1
0
0
Digit 4
0
0
1
1
1
0
0
Digit 5
1
0
1
1
1
0
0
Digit 6
0
1
1
1
1
0
0
Digit 7 (right)
1
1
1
1
1
0
0
Digit 0 (left)
0
0
0
X
0
0
0
Digit 1
1
0
0
X
0
0
0
Digit 2
0
1
0
X
0
0
0
Digit 3
1
1
1
X
0
0
0
Digit 4
0
0
1
X
0
0
0
Digit 5
1
0
1
X
0
0
0
Digit 6
0
1
1
X
0
0
0
Digit 7 (right)
1
1
1
X
0
0
0
X=don’t care
Write display data to user RAM
and Page Select Register
D0–D6=ASCII Data
D7=0 Select ROM1
D7=1 Select ROM 2
Write Flash RAM Register
D0=0 Flashing Character off
D0=1 Flashing Character on
D1–D7=X
Power up Sequence
Upon power up display will come on at random. Thus the
display should be reset on power-up. The reset will clear the
Flash RAM, Control Word Register and reset the internal
counter . All the digits will show blanks and display brightness
level will be 100%.
Microprocessor Interface
The interface to a microprocessor is through the 8-bit data
bus (D0-D7), the 4-bit address bus (A0–A3) and control lines
FL
, CE and WR.
To write data (ASCII/ Control Word) into the display CE
should be held low, address and data signals stable and WR
should be brought low.
The Control Word is decoded by the Control Word Decode
Logic. Each code has a different function. The code for display brightness changes the duty cycle for the column drivers. The peak LED current stays the same but the average
LED current diminishes depending on the intensity level.
The character Flash Enable causes 2 Hz coming out of the
counter to be ANDED with column drive signal and makes
the column driver to cycle at 2 Hz. Thus the character flashes
at 2 Hz.
The display Blink works the same way as the Flash Enable
but causes all twenty column drivers to cycle at 2 Hz thereby
making all eight digits to blink at 2 Hz.
The Lamp Test causes the column drivers to run at
cycle thus all the LEDs in all eight digits turn on at 50% intensity.
Clear bit clears the character RAM and writes a blank into
the display memory. It however does not clear the control
word.
ASCII Data or Control Word Data can be written into the display at this point. For multiple display operation, CLK I/O
must be properly selected. CLK I/O will output the internal
clock if CLKSEL
if CLKSEL
=1, or will allow input from an external clock
=0.
1
/2 duty
2–139
PLCD5580/1/2/3/4
Page 10
Control W ord Format
Display Brightness
The display can be programmed to vary between blank, 13%, 20%, 27%, 40%, 53%, 80%, and
full brightness. Bits D0, D1 and D2 control the display brightness.
CE WR FL A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 Display Brightness
0
0
1
0
X
X
X
0
0
X
X
X
0
0
0
0
0
1
0
X
X
X
0
0
X
X
X
0
0
0
1
0
X
X
X
0
0
X
X
0
0
1
0
X
X
X
0
0
0
0
1
0
X
X
X
0
0
1
0
X
0
0
1
0
0
0
1
0
X
X
X
X
X
0
X
0
X
0
X
0
X
0
X
0
X
0
X
0
X
X
X
X
X
X
X
X
X
X
X
X
0
0
1
0
1
1
0
1
0
1
1
1
1
1
0
1
0
1
0
1
100% Brightness
80% Brightness
53% Brightness
40% Brightness
27% Brightness
20% Brightness
13% Brightness
Blank Display
X= Don’t care
Flash RAM Function
Character Flash is controlled by FL
of FL
being low, proper digit address and D0 being high will write a flash bit into the
pin, bit D0 and control word bit D3. Combination
Flash RAM Register. In the control word mode when D3 is brought high, the above
mentioned character will flash.
Setting the Flash Bit
CE WR FL A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 Operation
0
0
0
X
A
A
A
X
X
X
X
X
X
X
0
0
0
0
X
A
A
A
X
X
X
X
X
X
X
Flash RAM disabled
1
Flash RAM enabled
X=Don’t care A=Selected address
Character Flash Control Word
CE WR FL A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 Operation
0
0
1
0
X
X
X
0
0
X
0
0
B
B
B
0
0
1
0
X
X
X
0
0
X
0
1
B
B
Disable Flashing Char.
B
Enabled Flashing Char.
X=Don’t care B=Selected brightness
Display Blinking
Blinking function is independent of Flash function. When D4 is held high, entire display blinks at 2 Hz.
CE WR FL A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 Operation
0
0
1
0
X
X
X
0
0
X
0
0
B
B
B
0
0
1
0
X
X
X
0
0
X
1
0
B
B
Display Blinking disabled
B
Display Blinking enabled
X=Don’t care B=Selected brightness
Lamp Test
Bit D6 when brought high will cause all the LEDs in all eight digits to light up at 53% brightness.
Selecting or de-selecting Lamp Test has no effect on the display memory.
CE WR FL A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 Operation
0
0
0
0
X=Don’t care
1
0
X
X
X
0
0
X
0
X
X
X
X
1
0
X
X
X
0
0
X
0
0
X
X
2–140
Lamp Test disabled
X
Lamp Test enabled
PLCD5580/1/2/3/4
Page 11
Clear Function
Clear function will clear the display. The Flash RAM will be set to all zeros. An ASCII blank code (20H) will be written into the
display memory. The user must 3 µs or write a new control word to the display with control wor d bit D7=0 to disable clear
before writing any data to the display memory , otherwise all new data to the display memory will remain clear ed. See Switching
Specifications for clear function timing.
CE WR FL A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 Operation
0
0
1
0
X
X
X
0
X
X
X
X
X
X
X
0
0
1
0
X
X
X
1
X
X
X
X
X
X
Clear disabled
X
Clear user RAM, page
RAM, flash RAM and display
X=Don’t care
Control W ord Format
D7 D6 D5 D4 D3 D2 D1 D0
CLEAR
ENABLE
LAMP
TEST
NOT
USED
BLINK
ENABLE
FLASH
ENABLE
BRIGHTNESS
CONTROL
D2 D1 D0 BRIGHTNESS
0 0 0 100%
0 0 1 80%
0 1 0 53%
0 1 1 40%
1 0 0 27%
1 0 1 20%
1 1 0 13%
1 1 1 0% Blank
D3 FLASH ENABLE
0 Disable Flashing Character
1 Enable Blinking Character
D4 BLINKING DISPLAY
0 Disable Blinking Character
1 Enable Blinking Character
D6 LAMP TEST
0 Disable Lamp Test
1 Enable Lamp Test (all dots on at 53% brightness)
D7 CLEAR ENABLE
0 Disable Clear
1 Enable Clear (Clear Data RAM, Page RAM, Flash RAM)
2–141
PLCD5580/1/2/3/4
Page 12
Electrical and Mechanical Considerations
V oltage Transient Suppression
For best results power the display and the components that
interface with the display to avoid logic inputs higher than
V
. Additionally, the LEDs may cause transients in the
CC
power supply line while they change display states. The common practice is to place a parallel combination of a .01 µF
and a 22 µF capacitor between V
packages.
ESD Protection
The input protection structure of the PLCD5580/1/2/3/4 provides significant protection against ESD damage. It is capable of withstanding discharges greater than 2 KV. T ake all the
standard precautions, normal for CMOS components. These
include properly grounding personnel, tools, tables, and
transport carriers that come in contact with unshielded parts.
If these conditions are not, or cannot be met, keep the leads
of the device shorted together or the parts in anti-static packaging.
Soldering
Considerations
THE PLCD5580/1/2/3/4 can be hand soldered with SN63 solder using a grounded iron set to 260°C.
Wave soldering is also possible following these conditions:
Preheat that does not exceed 93°C on the solder side of the
PC board or a package surface temperature of 85°C. Water
soluble organic acid flux (except carboxylic acid) or resinbased RMA flux without alcohol can be used.
Wave temperature of 245°C ±5°C with a dwell between 1.5
sec. to 3.0 sec. Exposure to the wave should not exceed temperatures above 260°C for five seconds at 0.063" below the
seating plane. The packages should not be immersed in the
wave.
Post Solder Cleaning Procedures
The least offensive cleaning solution is hot D.I. water (60°C)
for less than 15 minutes. Addition of mild saponifiers is
acceptable. Do not use commercial dishwasher detergents.
For faster cleaning, solvents may be used. Exercise care in
choosing solvents as some may chemically attack the nylon
package. Maximum exposure should not exceed two minutes
at elevated temperatures. Acceptable solvents are TF (trichorotrifluorethane), TA, 111 Trichloroethane, and unheated
acetone.
(1)
Note: 1. Acceptable commercial solvents are: Basic TF, Ark-
lone, P. Genesolv, D. Genesolv DA, Blaco-Tron TF,
Blaco-Tron TA, and Freon TA.
Unacceptable solvents contain alcohol, methanol, methylene
chloride, ethanol, TP35, TCM, TMC, TMS+, TE, or TES. Since
many commercial mixtures exist, contact a solvent vendor for
chemical composition information. Some major solvent manufacturers are: Allied Chemical Corporation, Specialty Chemical Division, Morristown, NJ; Baron-Blakeslee, Chicago, IL;
Dow Chemical, Midland, MI; E.I. DuPont de Nemours & Co.,
Wilmington, DE.
For further information refer to Appnotes 18 and 19 in the current Siemens Optoelectronic Data Book.
and GND for all display
CC
An alternative to soldering and cleaning the display modules
is to use sockets. Naturally, 28 pin DIP sockets .600" wide
with .100" centers work well for single displays. Multiple display assemblies are best handled by longer SIP sockets or
DIP sockets when available for uniform package alignment.
Socket manufacturers are Aries Electronics, Inc., Frenchtown, NJ; Garry Manufacturing, New Brunswick, NJ; Robinson-Nugent, New Albany, IN; and Samtec Electronic
Hardward, New Albany, IN.
For further information refer to Appnote 22 in the current Siemens Optoelectronic Data Book.
Optical
Considerations
The .200" high character of the PLCD588X gives readability
up to eight feet. Proper filter selection enhances readability
over this distance.
Using filters emphasizes the contrast ratio between a lit LED
and the character background. This will increase the discrimination of different characters. The only limitation is cost. Take
into consideration the ambient lighting environment for the
best cost/benefit ratio for filters.
Incandescent (with almost no green) or fluorescent (with
almost no red) lights do not have the flat spectral response of
sunlight. Plastic band-pass filters are an inexpensive and
effective way to strengthen contrast ratios. The PLCD5880/
5882 are red/high efficiency red displays and should be
matched with long wavelength pass filter in the 570 nm to
590 nm range. The PLCD5881/5883/5884 should be
matched with a yellow-green band-pass filter that peaks at
565 nm. For displays of multiple colors, neutral density grey
filters offer the best compromise.
Additional contrast enhancement is gained by shading the
displays. Plastic band-pass filters with built-in louvers offer
the next step up in contrast improvement. Plastic filters can
be improved further with anti-reflective coatings to reduce
glare. The trade-off is fuzzy characters. Mounting the filters
close to the display reduces this effect. Take care not to overheat the plastic filter by allowing for proper air flow.
Optimal filter enhancements are gained by using circular
polarized, anti-reflective, band-pass filters. The circular polar izing further enhances contrast by reducing the light that
travels through the filter and reflects back off the display to
less than 1%. Selecting the proper intensity of the displays
allows 10,000 foot candle sunlight viewability.
Several filter manufacturers supply quality filter materials.
Some of them are: Panelgraphic Corporation, W. Caldwell,
NJ; SGL Homalite, Wilmington, DE; 3M Company, Visual
Products Division, St. Paul, MN; Polaroid Corporation, Polarizer Division, Cambridge, MA; Marks Polarized Corporation,
Deer Park, NY, Hoya Optics, Inc., Fremont, CA.
One last note on mounting filters: recessing displays and
bezel assemblies is an inexpensive way to provide a shading
effect in overhead lighting situations. Several bezel manufacturers are: R.M.F. Products, Batavia, IL; Nobex Components,
Griffith Plastic Corp., Burlingame, CA; Photo Chemical Products of California, Santa Monica, CA; I.E.E.-Atlas, Van Nuys,
CA.
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PLCD5580/1/2/3/4
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