Page 1
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Philips Semiconductors Product Specification
Logic level TOPFET PIP3102-R
DESCRIPTION QUICK REFERENCE DATA
Monolithic logic level protected SYMBOL PARAMETER MAX. UNIT
power MOSFET using TOPFET2
technology assembled in a 5 pin V
surface mounting plastic package. I
APPLICATIONS T
General purpose switch for driving
D
P
R
DS
tot
j
DS(ON)
lamps SYMBOL PARAMETER NOM. UNIT motors solenoids V
PS
heaters
FEATURES FUNCTIONAL BLOCK DIAGRAM
TrenchMOS output stage with
low on-state resistance
Separate input pin for higher
frequency drive
5 V logic compatible input
Separate supply pin for logic
and protection circuits with low
operating current
Overtemperature protection
Drain current limiting
Short circuit load protection
Latched overload trip state reset
by the protection pin
Diagnostic flag pin indicates
protection supply connected,
overtemperature condition,overload
tripped state, or open circuit load
(detected in the off-state)
ESD protection on all pins
Overvoltage clamping
PROTECTION SUPPLY
FLAG
INPUT
Continuous drain source voltage 50 V
Continuous drain current 30 A
Total power dissipation 90 W
Continuous junction temperature 150 ˚C
Drain-source on-state resistance 28 mΩ
Protection supply voltage 5 V
DRAIN
OC LOAD
DETECT
RIG
LOGIC AND
PROTECTION
O/V
CLAMP
POWER
MOSFET
SOURCE
Fig.1. Elements of the TOPFET.
PINNING - SOT426 PIN CONFIGURATION SYMBOL
PIN DESCRIPTION
1 input
2 flag
3 (connected to mb)
4 protection supply
5 source
3
12 45
mb
TOPFET
P
F
I
Fig. 2. Fig. 3.
mb drain
October 2002 1 Rev 1.000
D
P
S
Page 2
Philips Semiconductors Product Specification
Logic level TOPFET PIP3102-R
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum Rating System (IEC 134)
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
Continuous voltage
V
DS
Drain source voltage
Continuous currents
I
D
I
I
I
F
I
P
Drain current VPS = 5 V; T
Input current -5 5 mA
Flag current -5 5 mA
Protection supply current -5 5 mA
Thermal
P
tot
T
stg
T
j
T
sold
Total power dissipation Tmb = 25˚C - 90 W
Storage temperature -55 175 ˚C
Junction temperature
Mounting base temperature during soldering - 260 ˚C
1
2
VIS = 0 V - 50 V
25˚C - self - A
VPS = 0 V; T
mb =
85˚C - 30 A
mb =
limited
continuous - 150 ˚C
ESD LIMITING VALUE
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
V
C
Electrostatic discharge capacitor Human body model; - 2 kV
voltage C = 250 pF; R = 1.5 kΩ
OVERLOAD PROTECTION LIMITING VALUE
With an adequate protection supply For overload conditions an n-MOS The drain current is limited to
connected, TOPFET can protect transistor turns on between the reduce dissipation in case of short
itself from two types of overload - input and source to quickly circuit load. Refer to OVERLOAD
overtemperature and short circuit discharge the power MOSFET CHARACTERISTICS.
load. gate capacitance.
SYMBOL PARAMETER REQUIRED CONDITION MIN. MAX. UNIT
Overload protection
V
DS
Drain source voltage VPS ≥ 4 V 0 35 V
3
protection supply
OVERVOLTAGE CLAMPING LIMITING VALUES
At a drain source voltage above 50 V the power MOSFET is actively turned on to clamp overvoltage transients.
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
Inductive load turn off IDM = 20 A; VDD ≤ 20 V
E
DSM
E
DRM
Non-repetitive clamping energy Tmb = 25˚C - 350 mJ
Repetitive clamping energy Tmb ≤ 95˚C; f = 250 Hz - 45 mJ
1 Prior to the onset of overvoltage clamping. For voltages above this value, safe operation is limited by the overvoltage clamping energy.
2 A higher Tj is allowed as an overload condition but at the threshold T
3 All control logic and protection functions are disabled during conduction of the source drain diode. If the protection circuit was previously
latched, it would be reset by this condition.
the over temperature trip operates to protect the switch.
j(TO)
October 2002 2 Rev 1.000
Page 3
Philips Semiconductors Product Specification
Logic level TOPFET PIP3102-R
THERMAL CHARACTERISTIC
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Thermal resistance
R
th j-mb
OUTPUT CHARACTERISTICS
Limits are for -40˚C ≤ Tmb ≤ 150˚C; typicals are for Tmb = 25˚C unless otherwise specified.
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
V
(CL)DSS
I
DSS
Junction to mounting base - - 1.2 1.39 K/W
Off-state VIS = 0 V
Drain-source clamping voltage ID = 10 mA 50 - 70 V
= 4 A; tp ≤ 300 µs; δ ≤ 0.01 50 60 70 V
I
DM
Drain source leakage current1VPS = 0 V; VDS = 40 V - - 100 µA
Tmb = 25˚C - 0.1 10 µA
On-state tp ≤ 300 µs; δ ≤ 0.01; VPS ≥ 4 V
R
DS(ON)
Drain-source resistance IDM = 10 A; VIS ≥ 4.4 V - - 50 mΩ
Tmb = 25˚C - 21 28 mΩ
INPUT CHARACTERISTICS
Limits are for -40˚C ≤ Tmb ≤ 150˚C; typicals are for Tmb = 25˚C unless otherwise specified.
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Normal operation
V
I
IS
V
R
I
ISL
IS(TO)
(CL)IS
IG
Input threshold voltage
Input current VIS = 5 V - 16 100 µA
Input clamping voltage II = 1 mA 5.5 6.4 8.5 V
Internal series resistance
Overload protection latched VPS ≥ 4 V
Input current VIS = 5 V 1 2.7 4 mA
2
ID = 1 mA 0.6 - 2.6 V
Tmb = 25˚C 1.1 1.6 2.1 V
3
to gate of power MOSFET - 1.7 - kΩ
1 The drain current required for open circuit load detection is switched off when there is no protection supply, in order to ensure a low off-state
2 The measurement method is simplified if VPS = 0 V, in order to distinguish ID from I
3 This is not a directly measurable parameter.
quiescent current. Refer to OPEN CIRCUIT LOAD DETECTION CHARACTERISTICS.
. Refer to OPEN CIRCUIT LOAD DETECTION
CHARACTERISTICS.
DSP
October 2002 3 Rev 1.000
Page 4
Philips Semiconductors Product Specification
Logic level TOPFET PIP3102-R
PROTECTION SUPPLY CHARACTERISTICS
Limits are for -40˚C ≤ Tmb ≤ 150˚C; typicals are for Tmb = 25˚C.
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Protection & detection
V
I
PS
V
PSF
, I
(CL)PS
PSL
Threshold voltage
Normal operation or
protection latched
Supply current VPS = 4.5 V - 210 450 µA
Clamping voltage IP = 1.5 mA 5.5 6.5 8.5 V
Overload protection latched
1
IF = 100 µA; VDS = 5 V 2.5 3.45 4 V
V
PSR
t
pr
Reset voltage 1 1.8 3 V
Reset time VPS ≤ 1 V 10 45 120 µs
OPEN CIRCUIT LOAD DETECTION CHARACTERISTICS
An open circuit load condition can be detected while the TOPFET is in the off-state. Refer to TRUTH TABLE.
VPS = 5 V. Limits are for -40˚C ≤ Tmb ≤ 150˚C and typicals are for Tmb = 25˚C.
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
I
V
V
DSP
DSF
ISF
Off-state drain current
Drain threshold voltage
Input threshold voltage
2
3
4
VIS = 0 V; 2 V ≤ VDS ≤ 40 V 0.9 1.8 2.7 mA
VIS = 0 V 0.2 1 2 V
ID = 100 µA 0.3 0.8 1.1 V
OVERLOAD CHARACTERISTICS
Tmb = 25˚C unless otherwise specified.
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Short circuit load VPS > 4 V
I
P
T
D
D(TO)
DSC
Drain current limiting VIS = 5 V; -40˚C ≤ Tmb ≤ 150˚C 28.5 44 60 A
Overload protection VPS > 4 V
Overload power threshold device trips if PD > P
D(TO)
Characteristic time which determines trip time
5
75 185 250 W
250 380 600 µs
Overtemperature protection VPS = 5 V
T
j(TO)
1 When VPS is less than V
2 The drain source current which flows in a normal load when the protection supply is high and the input is low.
3 If VDS < V
4 For open circuit load detection, VIS must be less than V
5 Trip time t
Threshold temperature from ID ≥ 4 A or VDS > 0.2 V 150 170 - ˚C
the flag pin indicates low protection supply voltage. Refer to TRUTH TABLE.
PSF
then the flag indicates open circuit load.
DSF
.
ISF
varies with overload dissipation PD according to the formula t
d sc
d sc
≈ T
/ ln[ PD / P
DSC
D(TO)
].
October 2002 4 Rev 1.000
Page 5
Philips Semiconductors Product Specification
Logic level TOPFET PIP3102-R
TRUTH TABLE
For normal, open-circuit load and overload conditions or inadequate protection supply voltage.
Assumes proper external pull-up for flag pin. Refer to
CONDITION PROTECTION INPUT FLAG OUTPUT
Normal on-state 1 1 0 ON
Normal off-state 1 0 0 OFF
Open circuit load 1 1 0 ON
Open circuit load 1 0 1 OFF
Short circuit load
1
Over temperature 1 X 1 OFF
Low protection supply voltage 0 1 1 ON
Low protection supply voltage 0 0 1 OFF
FLAG CHARACTERISTICS.
1 1 1 OFF
KEY ‘0’ equals low
‘1’ equals high
‘X’ equals don’t care.
FLAG CHARACTERISTICS
The flag is an open drain transistor which requires an external pull-up circuit.
Limits are for -40˚C ≤ Tmb ≤ 150˚C; typicals are for Tmb = 25˚C.
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Flag ‘low’ normal operation; VPS = 5 V
V
I
FSF
FSF
Flag voltage IF = 100 µA - 0.8 1 V
Flag saturation current VFS = 5 V - 10 - mA
Flag ‘high’ overload or fault
I
V
FSO
(CL)FS
Flag leakage current VFS = 5 V - 0.1 10 µA
Flag clamping voltage IF = 100 µA 5.5 6.2 8.5 V
Application information
R
F
Suitable external pull-up VFF = 5 V - 47 - kΩ
resistance
SWITCHING CHARACTERISTICS
Tmb = 25˚C; RI = 50 Ω; RIS = 50 Ω; VDD = 15 V; resistive load RL = 10 Ω.
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
t
t
t
t
d on
r
d off
f
Turn-on delay time VIS: 0 V ⇒ 5 V - 1.8 5 µs
Rise time - 3.5 8 µs
Turn-off delay time VIS: 5 V ⇒ 0 V - 11 30 µs
Fall time - 5 12 µs
1 In this condition the protection circuit is latched. To reset the latch the protection pin must be taken low. Refer to PROTECTION SUPPLY
CHARACTERISTICS.
October 2002 5 Rev 1.000
Page 6
Philips Semiconductors Product Specification
Logic level TOPFET PIP3102-R
CAPACITANCES
Tmb = 25 ˚C; f = 1 MHz
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
C
iss
C
oss
C
rss
C
pso
C
fso
Input capacitance VDS = 25 V; VIS = 0 V - 710 1050 pF
Output capacitance VDS = 25 V; VIS = 0 V - 370 550 pF
Reverse transfer capacitance VDS = 25 V; VIS = 0 V - 26 40 pF
Protection supply pin VPS = 5 V - 22 - pF
capacitance
Flag pin capacitance VFS = 5 V; VPS = 0 V - 12 - pF
PD%
120
100
80
60
40
20
0
0 20 40 60 80 100 120 140
Normalise Power Derating
T
/ OC
mb
Fig.4. Normalised limiting power dissipation.
PD% = 100⋅PD/PD(25˚C) = f(Tmb)
ID / A
40
30
20
10
0
0 20 40 60 80 100 120 140
/ OC
T
mb
Fig.5. Continuous drain current.
ID = f(T
); condition: VIS = 5 V
amb
ID / A
80
70
60
50
40
30
20
10
0
0246810121416
VIS / V =
7
6
5
4
3
VDS / V
Fig.6. Typical output characteristics, Tj = 25˚C.
ID = f(VDS); parameter VIS; tp = 300 µs & tp < td
I
/ A
D
80
70
60
50
40
30
20
10
0
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2
y
VIS / V =
VDS / V
sc
7
6
5
4
3
2
Fig.7. Typical on-state characteristics, Tj = 25˚C.
ID = f(VDS); parameter VIS; tp = 300 µs
October 2002 6 Rev 1.000
Page 7
Philips Semiconductors Product Specification
Logic level TOPFET PIP3102-R
T
OC
j (TO)
200
Data below 4V is for
190
180
170
160
150
345678
T
= f(VPS); conditions: VIS = 5 V
j(TO)
I
/ A
DSS
100E-6
information only. All
spec. values are for
normal operation at
4V and above.
VPS / V
T
/ OC
j
Normalised R
a
2
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
-50 0 50 100 150
DS(ON)
= f(Tj)
Fig.8. Normalised drain-source on-state resistance.
a = R
50
R
DS(ON)/RDS(ON)
/ mOhm
DS(ON)
25˚C = f(Tj); ID = 10 A; VIS = 4.4 V
Fig.11. Typical overtemperature protection threshold.
40
30
20
10
0
012345678
Fig.9. Typical on-state resistance, Tj = 25˚C. R
= f(VIS); conditions: ID = 10 A; VPS = 4 V; tp = 300 µs
I
/ A
D
80
70
60
50
40
30
20
10
0
012345678
max.
typ.
VIS / V
DS(ON)
y
VDS = 13V
VIS / V
Fig.10. Typical transfer characteristics, Tj = 25˚C.
ID = f(VIS); conditions: VPS ≥ 4 V tp = 300 µs
10E-6
1E-6
100E-9
10E-9
1E-9
-50 0 50 100 150
Fig.12. Typical drain source leakage current.
I
= f(Tj); conditions: VDS = 40 V; VPS = VIS = 0 V
DSS
/ mA
I
IS
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
01234567
T
/ OC
j
Latched
V
/ V
IS
max.
typ.
Unlatched
Fig.13. Typical DC input characteristics, Tj = 25˚C.
IIS & I
= f(VIS); normal operation & protection latched
ISL
October 2002 7 Rev 1.000
Page 8
Philips Semiconductors Product Specification
Logic level TOPFET PIP3102-R
IIS & I
10E-3
1E-3
ISL
I
ISL
2.5
2.0
1.5
I
DSP
/ mA
00E-6
I
IS
10E-6
-50 0 50 100 150
Fig.14. Typical DC input currents. IIS & I
normal & latched; conditions: VIS = 5 V; VPS = 5 V
V
/ V
IS(TO)
3.0
2.5
2.0
1.5
1.0
0.5
0.0
-50 0 50 100 150
Tj / OC
/ OC
T
j
max
typ.
min.
= f(Tj);
ISL
.
Fig.15. Input threshold voltage.
V
= f(Tj); conditions: ID = 1 mA; VDS = 5 V
IS(TO)
1.0
I
is constant from Vds = 2V to 40V
DSP
0.5
0
012345
V
/ V
DS
Fig.17. Off state drain current characteristic.
I
= f(VDS); conditions: Tj = 25˚C; VPS = 5 V; VIS = 0 V
DSP
I
/ mA
DSP
2.5
2.0
1.5
1.0
0.5
0
012345678
VPS / V
Fig.18. Off state drain current vs protection supply.
I
= f(VPS); Tj = 25˚C; VDS = 13 V; VIS = 0 V
DSP
/ mA
10
IIS / mA
2.5
I
DSP
8
6
2.0
4
2
0
02468
V
/ V
IS
Fig.16. Typical input clamping characteristic.
II = f(VIS); normal operation, Tj = 25˚C
1.5
-50 0 50 100 150
Fig.19. Typical off state drain current I
conditions: VDS = 13 V; VPS = 5 V; VIS = 0 V
Tj / OC
DSP
= f(Tj);
October 2002 8 Rev 1.000
Page 9
Philips Semiconductors Product Specification
Logic level TOPFET PIP3102-R
V
/ V
V
/ V
DSF
2
Normal load
typ.
1
Open circuit load
0
-50 0 50 100 150
Tj / OC
Fig.20. Open circuit detection threshold voltage.
V
= f(Tj); VPS ≥ 4 V ; VIS = 0 V
DSF
V
/ V
ISF
1.0
PSR
3.0
2.8
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
-50 0 50 100 150
Tj / OC
Fig.23. Typical protection reset voltage.
V
= f(Tj); tlr = 100 µs
PSR
I
/ A
FS
10E-6
Normal operation
typ.
0.5
Open circuit detection
0
-50 0 50 100 150
Tj / OC
Fig.21. Open circuit input threshold voltage.
V
= f(Tj); VPS ≥ 4 V ; ID = 100 µA
ISF
IPS / mA
2
1
VPS = 0 or 5V
1E-6
00E-9
10E-9
-50 0 50 100 150
Tj / OC
max.
typ.
Fig.24. Typical flag characteristics. IFS = f(Tj);
fault & overload operation; VIS = 5 V; VFS = 5 V
V
/ V
PSF
4.0
3.8
3.6
3.4
3.2
0
012345678
/ V
V
PS
Fig.22. Typical DC protection supply characteristics.
IPS = f(VPS); normal or overload operation; Tj = 25 ˚C
3.0
-50 0 50 100 150
Tj / OC
Fig.25. Typical protection threshold voltage.
V
= f(Tj); VDS = 5 V ; IF = 100 µA
PSF
October 2002 9 Rev 1.000
Page 10
Philips Semiconductors Product Specification
Logic level TOPFET PIP3102-R
VDS
0
ID
0
VIS
0
RI = RIS
Fig.26. Clamping energy test circuit, RIS = 100 Ω.
E
DSM
E
/ J
DSM
1.2
1.0
0.8
0.6
0.4
0.2
0
0.1 1 10 100
V(CL)DSR
VDD
RF
= 0.5 ⋅LI
VDD
+
L
D
TOPFET
S
(CL)DSR
L / mH
VDS
D.U.T.
/(V
(CL)DSR−VDD
-
-ID/100
R 01
shunt
)
25OC
150OC
VPS
+
P
P
F
I
2
⋅V
D
Fig.27. Typical non-repetitive clamping energy.
E
= f(L); conditions: VIS = 0 V
DSM
VII
RI
RIS
VIS
TOPFET
P
F
I
D
P
S
Fig.29. Test circuit for resistive load switching times.
VIS = 5 V
V
& V
/ V
IS
16
14
12
10
DS
V
DS
8
6
4
2
0
0 5 10 15 20 25 30 35 40 45 50
V
IS
Time / µs
Fig.30. Typical switching waveforms, resistive load.
RL = 10 Ω; adjust VDD to obtain ID = 1.5 A; Tj = 25˚C
ID / A
4
V
/ V
DSS
65
ID =
3
4A
2
10mA
1
0
50 60 70
V
/ V
DS
Fig.28. Typical clamping characteristic, 25˚C.
ID = f(VDS); conditions: VIS = 0 V; tp ≤ 300 µs
60
-50 0 50 100 150
Tj / OC
Fig.31. Overvoltage clamping characteristic.
VDS = f(Tj); conditions: VIS = 0 V; tp ≤ 300 µs
October 2002 10 Rev 1.000
Page 11
Philips Semiconductors Product Specification
Logic level TOPFET PIP3102-R
/ A
I
D
80
70
60
50
40
30
20
10
0
-50 0 50 100 150
Tj / OC
max.
typ.
min.
Fig.32. Typical overload current, VDS = 5 V.
ID = f(Tj); conditions: VIS = 5 V; VPS = 4 V; tp = 300 µs
IS / A
15
10
5
Capacitance / pF
10000
, C
C
iss
C
oss
C
rss
, C
oss
rss
t
p
T
1000
100
10
0 1020304050
Fig.34. Typical capacitances, C
C = f(VDS); conditions: VIS = 0 V; f = 1 MHz
Zth / ( K / W )
0.5
0.2
0.1
0.05
0.02
0
V
/ V
DS
iss
P
D
D =
t
p
T
.
1E+01
1E+00
1E-01
1E-02
0
0 0.5 1
VSD / V
Fig.33. Typical reverse diode current, Tj = 25 ˚C.
IS = f(V
); conditions: VIS = 0 V; tp = 300 µs
SDS
1E-06 1E-05 1E-04 1E-03 1E-02 1E-01 1E+00 1E+01
t / s
Fig.35. Transient thermal impedance.
Zth
= f(t); parameter D = tp/T
j-mb
1E-03
October 2002 11 Rev 1.000
Page 12
Philips Semiconductors Product Specification
Logic level TOPFET PIP3102-R
MECHANICAL DATA
Plastic single-ended surface mounted package (Philips version of D2-PAK); 5 leads
(one lead cropped)
E
D
1
mounting
base
D
H
D
3
1
24 5
b
e e ee
A
1
L
p
c
Q
SOT426
A
0 2.5 5 mm
scale
DIMENSIONS (mm are the original dimensions)
0.64
0.46
D
max.
11
D
1
10.30
1.60
1.20
REFERENCES
9.70
L
H
15.80
14.80
Q
D
2.60
2.20
EUROPEAN
PROJECTION
ISSUE DATE
98-12-14
99-06-25
e
E
1.70
2.90
2.10
p
UNIT
mm
A
4.50
4.10
OUTLINE
VERSION
SOT426
A
bc
1
1.40
0.85
1.27
0.60
IEC JEDEC EIAJ
Fig.36. SOT426 surface mounting package1, centre pin connected to mounting base.
1 Epoxy meets UL94 V0 at 1/8". Net mass: 1.5 g.
For soldering guidelines and SMD footprint design, please refer to Data Handbook SC18.
October 2002 12 Rev 1.000
Page 13
Philips Semiconductors Product Specification
Logic level TOPFET PIP3102-R
DEFINITIONS
DATA SHEET STATUS
DATA SHEET PRODUCT DEFINITIONS
STATUS
Objective data Development This data sheet contains data from the objective specification for
Preliminary data Qualification This data sheet contains data from the preliminary specification.
Product data Production This data sheet contains data from the product specification. Philips
Limiting values
Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and
operation of the device at these or at any other conditions above those given in the Characteristics sections of
this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
Philips Electronics N.V. 2002
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the
copyright owner.
The information presented in this document does not form part of any quotation or contract, it is believed to be
accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under patent or other
industrial or intellectual property rights.
1
STATUS
2
product development. Philips Semiconductors reserves the right to
change the specification in any manner without notice
Supplementary data will be published at a later date. Philips
Semiconductors reserves the right to change the specification without
notice, in order to improve the design and supply the best possible
product
Semiconductors reserves the right to make changes at any time in
order to improve the design, manufacturing and supply. Changes will
be communicated according to the Customer Product/Process
Change Notification (CPCN) procedure SNW-SQ-650A
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices or systems where malfunction of these
products can be reasonably expected to result in personal injury. Philips customers using or selling these products
for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting
from such improper use or sale.
1 Please consult the most recently issued datasheet before initiating or completing a design.
2 The product status of the device(s) described in this datasheet may have changed since this datasheet was published. The latest information is
October 2002 13 Rev 1.000
available on the Internet at URL http://www.semiconductors.philips.com.
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